05349feaa2
Bring over camera driver changes as of msm-4.19 commit 5a5551a7 (Merge "msm: camera: reqmgr: Fix CRM shift one req issue"). Change-Id: Ic0c2b2d74d1b3470c1c51d98228e312fb13c501a Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
254 lines
6.4 KiB
C
254 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _CAM_CDM_H_
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#define _CAM_CDM_H_
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/random.h>
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#include <linux/spinlock_types.h>
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#include <linux/mutex.h>
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#include <linux/workqueue.h>
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#include <linux/bug.h>
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#include "cam_cdm_intf_api.h"
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#include "cam_soc_util.h"
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#include "cam_cpas_api.h"
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#include "cam_hw_intf.h"
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#include "cam_hw.h"
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#include "cam_debug_util.h"
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#define CAM_MAX_SW_CDM_VERSION_SUPPORTED 1
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#define CAM_SW_CDM_INDEX 0
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#define CAM_CDM_INFLIGHT_WORKS 5
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#define CAM_CDM_HW_RESET_TIMEOUT 300
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#define CAM_CDM_HW_ID_MASK 0xF
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#define CAM_CDM_HW_ID_SHIFT 0x5
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#define CAM_CDM_CLIENTS_ID_MASK 0x1F
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#define CAM_CDM_GET_HW_IDX(x) (((x) >> CAM_CDM_HW_ID_SHIFT) & \
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CAM_CDM_HW_ID_MASK)
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#define CAM_CDM_CREATE_CLIENT_HANDLE(hw_idx, client_idx) \
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((((hw_idx) & CAM_CDM_HW_ID_MASK) << CAM_CDM_HW_ID_SHIFT) | \
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((client_idx) & CAM_CDM_CLIENTS_ID_MASK))
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#define CAM_CDM_GET_CLIENT_IDX(x) ((x) & CAM_CDM_CLIENTS_ID_MASK)
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#define CAM_PER_CDM_MAX_REGISTERED_CLIENTS (CAM_CDM_CLIENTS_ID_MASK + 1)
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#define CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM (CAM_CDM_HW_ID_MASK + 1)
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/* enum cam_cdm_reg_attr - read, write, read and write permissions.*/
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enum cam_cdm_reg_attr {
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CAM_REG_ATTR_READ,
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CAM_REG_ATTR_WRITE,
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CAM_REG_ATTR_READ_WRITE,
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};
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/* enum cam_cdm_hw_process_intf_cmd - interface commands.*/
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enum cam_cdm_hw_process_intf_cmd {
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CAM_CDM_HW_INTF_CMD_ACQUIRE,
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CAM_CDM_HW_INTF_CMD_RELEASE,
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CAM_CDM_HW_INTF_CMD_SUBMIT_BL,
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CAM_CDM_HW_INTF_CMD_RESET_HW,
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CAM_CDM_HW_INTF_CMD_INVALID,
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};
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/* enum cam_cdm_regs - CDM driver offset enums.*/
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enum cam_cdm_regs {
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/*cfg_offsets 0*/
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CDM_CFG_HW_VERSION,
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CDM_CFG_TITAN_VERSION,
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CDM_CFG_RST_CMD,
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CDM_CFG_CGC_CFG,
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CDM_CFG_CORE_CFG,
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CDM_CFG_CORE_EN,
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CDM_CFG_FE_CFG,
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/*irq_offsets 7*/
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CDM_IRQ_MASK,
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CDM_IRQ_CLEAR,
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CDM_IRQ_CLEAR_CMD,
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CDM_IRQ_SET,
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CDM_IRQ_SET_CMD,
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CDM_IRQ_STATUS,
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CDM_IRQ_USR_DATA,
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/*BL FIFO Registers 14*/
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CDM_BL_FIFO_BASE_REG,
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CDM_BL_FIFO_LEN_REG,
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CDM_BL_FIFO_STORE_REG,
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CDM_BL_FIFO_CFG,
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CDM_BL_FIFO_RB,
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CDM_BL_FIFO_BASE_RB,
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CDM_BL_FIFO_LEN_RB,
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CDM_BL_FIFO_PENDING_REQ_RB,
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/*CDM System Debug Registers 22*/
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CDM_DBG_WAIT_STATUS,
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CDM_DBG_SCRATCH_0_REG,
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CDM_DBG_SCRATCH_1_REG,
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CDM_DBG_SCRATCH_2_REG,
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CDM_DBG_SCRATCH_3_REG,
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CDM_DBG_SCRATCH_4_REG,
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CDM_DBG_SCRATCH_5_REG,
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CDM_DBG_SCRATCH_6_REG,
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CDM_DBG_SCRATCH_7_REG,
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CDM_DBG_LAST_AHB_ADDR,
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CDM_DBG_LAST_AHB_DATA,
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CDM_DBG_CORE_DBUG,
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CDM_DBG_LAST_AHB_ERR_ADDR,
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CDM_DBG_LAST_AHB_ERR_DATA,
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CDM_DBG_CURRENT_BL_BASE,
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CDM_DBG_CURRENT_BL_LEN,
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CDM_DBG_CURRENT_USED_AHB_BASE,
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CDM_DBG_DEBUG_STATUS,
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/*FE Bus Miser Registers 40*/
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CDM_BUS_MISR_CFG_0,
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CDM_BUS_MISR_CFG_1,
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CDM_BUS_MISR_RD_VAL,
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/*Performance Counter registers 43*/
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CDM_PERF_MON_CTRL,
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CDM_PERF_MON_0,
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CDM_PERF_MON_1,
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CDM_PERF_MON_2,
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/*Spare registers 47*/
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CDM_SPARE,
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};
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/* struct cam_cdm_reg_offset - struct for offset with attribute.*/
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struct cam_cdm_reg_offset {
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uint32_t offset;
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enum cam_cdm_reg_attr attribute;
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};
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/* struct cam_cdm_reg_offset_table - struct for whole offset table.*/
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struct cam_cdm_reg_offset_table {
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uint32_t first_offset;
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uint32_t last_offset;
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uint32_t reg_count;
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const struct cam_cdm_reg_offset *offsets;
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uint32_t offset_max_size;
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};
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/* enum cam_cdm_flags - Bit fields for CDM flags used */
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enum cam_cdm_flags {
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CAM_CDM_FLAG_SHARED_CDM,
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CAM_CDM_FLAG_PRIVATE_CDM,
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};
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/* enum cam_cdm_type - Enum for possible CAM CDM types */
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enum cam_cdm_type {
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CAM_VIRTUAL_CDM,
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CAM_HW_CDM,
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};
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/* enum cam_cdm_mem_base_index - Enum for possible CAM CDM types */
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enum cam_cdm_mem_base_index {
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CAM_HW_CDM_BASE_INDEX,
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CAM_HW_CDM_MAX_INDEX = CAM_SOC_MAX_BLOCK,
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};
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/* struct cam_cdm_client - struct for cdm clients data.*/
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struct cam_cdm_client {
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struct cam_cdm_acquire_data data;
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void __iomem *changebase_addr;
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uint32_t stream_on;
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uint32_t refcount;
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struct mutex lock;
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uint32_t handle;
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};
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/* struct cam_cdm_work_payload - struct for cdm work payload data.*/
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struct cam_cdm_work_payload {
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struct cam_hw_info *hw;
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uint32_t irq_status;
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uint32_t irq_data;
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struct work_struct work;
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};
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/* enum cam_cdm_bl_cb_type - Enum for possible CAM CDM cb request types */
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enum cam_cdm_bl_cb_type {
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CAM_HW_CDM_BL_CB_CLIENT = 1,
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CAM_HW_CDM_BL_CB_INTERNAL,
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};
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/* struct cam_cdm_bl_cb_request_entry - callback entry for work to process.*/
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struct cam_cdm_bl_cb_request_entry {
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uint8_t bl_tag;
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enum cam_cdm_bl_cb_type request_type;
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uint32_t client_hdl;
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void *userdata;
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uint32_t cookie;
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struct list_head entry;
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};
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/* struct cam_cdm_hw_intf_cmd_submit_bl - cdm interface submit command.*/
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struct cam_cdm_hw_intf_cmd_submit_bl {
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uint32_t handle;
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struct cam_cdm_bl_request *data;
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};
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/* struct cam_cdm_hw_mem - CDM hw memory struct */
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struct cam_cdm_hw_mem {
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int32_t handle;
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uint32_t vaddr;
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uintptr_t kmdvaddr;
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size_t size;
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};
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/* struct cam_cdm - CDM hw device struct */
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struct cam_cdm {
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uint32_t index;
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char name[128];
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enum cam_cdm_id id;
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enum cam_cdm_flags flags;
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struct completion reset_complete;
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struct completion bl_complete;
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struct workqueue_struct *work_queue;
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struct list_head bl_request_list;
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struct cam_hw_version version;
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uint32_t hw_version;
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uint32_t hw_family_version;
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struct cam_iommu_handle iommu_hdl;
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struct cam_cdm_reg_offset_table *offset_tbl;
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struct cam_cdm_utils_ops *ops;
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struct cam_cdm_client *clients[CAM_PER_CDM_MAX_REGISTERED_CLIENTS];
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uint8_t bl_tag;
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atomic_t error;
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atomic_t bl_done;
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struct cam_cdm_hw_mem gen_irq;
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uint32_t cpas_handle;
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};
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/* struct cam_cdm_private_dt_data - CDM hw custom dt data */
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struct cam_cdm_private_dt_data {
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bool dt_cdm_shared;
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uint32_t dt_num_supported_clients;
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const char *dt_cdm_client_name[CAM_PER_CDM_MAX_REGISTERED_CLIENTS];
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};
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/* struct cam_cdm_intf_devices - CDM mgr interface devices */
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struct cam_cdm_intf_devices {
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struct mutex lock;
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uint32_t refcount;
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struct cam_hw_intf *device;
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struct cam_cdm_private_dt_data *data;
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};
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/* struct cam_cdm_intf_mgr - CDM mgr interface device struct */
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struct cam_cdm_intf_mgr {
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bool probe_done;
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struct cam_cdm_intf_devices nodes[CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM];
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uint32_t cdm_count;
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uint32_t dt_supported_hw_cdm;
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int32_t refcount;
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};
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int cam_cdm_intf_register_hw_cdm(struct cam_hw_intf *hw,
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struct cam_cdm_private_dt_data *data, enum cam_cdm_type type,
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uint32_t *index);
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int cam_cdm_intf_deregister_hw_cdm(struct cam_hw_intf *hw,
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struct cam_cdm_private_dt_data *data, enum cam_cdm_type type,
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uint32_t index);
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#endif /* _CAM_CDM_H_ */
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