a9d924743a
If Device boots up in secure mode, CNSS defers PCI enumeration, calibration and host driver registration. When secure mode exits host driver gets notified from CTRL_PARAM and calls PLD API to perform previously deferred operations and enable WLAN HW. This can take some seconds and by the time again Secure mode can enter, disable WLAN and access controlled by TZ. Now Calibration completes and CNSS receives CAL_DONE indication. As part of CAL_DONE when CNSS try to power off WLAN access WLAN_EN it results in NOC error. One more scenario, where CNSS can access WLAN_EN when WLAN HW is disabled by TZ, could be when QMI message times out. Consider secure mode is entering as part of CNSS will to IDLE shutdown. During IDLE shutdown while sending MODE_OFF QMI message to FW it might wait for 10 seconds if FW does not respond. But TZ has timeout of 5 sec if framework does not respond in 5 Sec TZ will disable WLAN_EN and access control it. Now when after QMI timedout when try to access WLAN_EN it results in NOC error. Check secure peripheral state before updating WLAN_EN and maintain correct driver state in such scenario. Change-Id: I4a0892f02edb42496b9633d2d33ded26cbc08707 CRs-Fixed: 3247847
1058 lines
28 KiB
C
1058 lines
28 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
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/* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */
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#include <linux/err.h>
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#include <linux/seq_file.h>
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#include <linux/debugfs.h>
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#include "main.h"
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#include "bus.h"
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#include "debug.h"
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#include "pci.h"
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#define MMIO_REG_ACCESS_MEM_TYPE 0xFF
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#define MMIO_REG_RAW_ACCESS_MEM_TYPE 0xFE
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#if IS_ENABLED(CONFIG_IPC_LOGGING)
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void *cnss_ipc_log_context;
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void *cnss_ipc_log_long_context;
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#endif
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static int cnss_pin_connect_show(struct seq_file *s, void *data)
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{
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struct cnss_plat_data *cnss_priv = s->private;
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seq_puts(s, "Pin connect results\n");
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seq_printf(s, "FW power pin result: %04x\n",
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cnss_priv->pin_result.fw_pwr_pin_result);
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seq_printf(s, "FW PHY IO pin result: %04x\n",
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cnss_priv->pin_result.fw_phy_io_pin_result);
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seq_printf(s, "FW RF pin result: %04x\n",
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cnss_priv->pin_result.fw_rf_pin_result);
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seq_printf(s, "Host pin result: %04x\n",
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cnss_priv->pin_result.host_pin_result);
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seq_puts(s, "\n");
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return 0;
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}
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static int cnss_pin_connect_open(struct inode *inode, struct file *file)
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{
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return single_open(file, cnss_pin_connect_show, inode->i_private);
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}
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static const struct file_operations cnss_pin_connect_fops = {
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.read = seq_read,
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.release = single_release,
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.open = cnss_pin_connect_open,
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.owner = THIS_MODULE,
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.llseek = seq_lseek,
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};
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static int cnss_stats_show_state(struct seq_file *s,
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struct cnss_plat_data *plat_priv)
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{
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enum cnss_driver_state i;
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int skip = 0;
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unsigned long state;
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seq_printf(s, "\nState: 0x%lx(", plat_priv->driver_state);
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for (i = 0, state = plat_priv->driver_state; state != 0;
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state >>= 1, i++) {
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if (!(state & 0x1))
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continue;
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if (skip++)
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seq_puts(s, " | ");
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switch (i) {
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case CNSS_QMI_WLFW_CONNECTED:
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seq_puts(s, "QMI_WLFW_CONNECTED");
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continue;
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case CNSS_FW_MEM_READY:
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seq_puts(s, "FW_MEM_READY");
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continue;
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case CNSS_FW_READY:
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seq_puts(s, "FW_READY");
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continue;
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case CNSS_IN_COLD_BOOT_CAL:
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seq_puts(s, "IN_COLD_BOOT_CAL");
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continue;
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case CNSS_DRIVER_LOADING:
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seq_puts(s, "DRIVER_LOADING");
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continue;
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case CNSS_DRIVER_UNLOADING:
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seq_puts(s, "DRIVER_UNLOADING");
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continue;
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case CNSS_DRIVER_IDLE_RESTART:
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seq_puts(s, "IDLE_RESTART");
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continue;
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case CNSS_DRIVER_IDLE_SHUTDOWN:
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seq_puts(s, "IDLE_SHUTDOWN");
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continue;
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case CNSS_DRIVER_PROBED:
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seq_puts(s, "DRIVER_PROBED");
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continue;
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case CNSS_DRIVER_RECOVERY:
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seq_puts(s, "DRIVER_RECOVERY");
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continue;
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case CNSS_FW_BOOT_RECOVERY:
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seq_puts(s, "FW_BOOT_RECOVERY");
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continue;
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case CNSS_DEV_ERR_NOTIFY:
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seq_puts(s, "DEV_ERR");
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continue;
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case CNSS_DRIVER_DEBUG:
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seq_puts(s, "DRIVER_DEBUG");
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continue;
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case CNSS_COEX_CONNECTED:
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seq_puts(s, "COEX_CONNECTED");
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continue;
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case CNSS_IMS_CONNECTED:
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seq_puts(s, "IMS_CONNECTED");
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continue;
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case CNSS_IN_SUSPEND_RESUME:
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seq_puts(s, "IN_SUSPEND_RESUME");
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continue;
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case CNSS_IN_REBOOT:
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seq_puts(s, "IN_REBOOT");
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continue;
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case CNSS_COLD_BOOT_CAL_DONE:
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seq_puts(s, "COLD_BOOT_CAL_DONE");
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continue;
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case CNSS_IN_PANIC:
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seq_puts(s, "IN_PANIC");
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continue;
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case CNSS_QMI_DEL_SERVER:
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seq_puts(s, "DEL_SERVER_IN_PROGRESS");
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continue;
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case CNSS_QMI_DMS_CONNECTED:
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seq_puts(s, "DMS_CONNECTED");
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continue;
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case CNSS_DAEMON_CONNECTED:
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seq_puts(s, "DAEMON_CONNECTED");
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continue;
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case CNSS_PCI_PROBE_DONE:
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seq_puts(s, "PCI PROBE DONE");
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continue;
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case CNSS_DRIVER_REGISTER:
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seq_puts(s, "DRIVER REGISTERED");
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continue;
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case CNSS_WLAN_HW_DISABLED:
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seq_puts(s, "WLAN HW DISABLED");
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continue;
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case CNSS_FS_READY:
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seq_puts(s, "FS READY");
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continue;
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case CNSS_DRIVER_REGISTERED:
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seq_puts(s, "DRIVER REGISTERED");
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continue;
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}
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seq_printf(s, "UNKNOWN-%d", i);
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}
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seq_puts(s, ")\n");
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return 0;
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}
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static int cnss_stats_show_gpio_state(struct seq_file *s,
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struct cnss_plat_data *plat_priv)
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{
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seq_printf(s, "\nHost SOL: %d", cnss_get_host_sol_value(plat_priv));
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seq_printf(s, "\nDev SOL: %d", cnss_get_dev_sol_value(plat_priv));
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return 0;
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}
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static int cnss_stats_show(struct seq_file *s, void *data)
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{
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struct cnss_plat_data *plat_priv = s->private;
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cnss_stats_show_state(s, plat_priv);
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cnss_stats_show_gpio_state(s, plat_priv);
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return 0;
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}
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static int cnss_stats_open(struct inode *inode, struct file *file)
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{
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return single_open(file, cnss_stats_show, inode->i_private);
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}
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static const struct file_operations cnss_stats_fops = {
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.read = seq_read,
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.release = single_release,
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.open = cnss_stats_open,
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.owner = THIS_MODULE,
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.llseek = seq_lseek,
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};
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static ssize_t cnss_dev_boot_debug_write(struct file *fp,
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const char __user *user_buf,
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size_t count, loff_t *off)
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{
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struct cnss_plat_data *plat_priv =
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((struct seq_file *)fp->private_data)->private;
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struct cnss_pci_data *pci_priv;
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char buf[64];
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char *cmd;
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unsigned int len = 0;
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char *sptr, *token;
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const char *delim = " ";
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int ret = 0;
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if (!plat_priv)
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return -ENODEV;
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len = min(count, sizeof(buf) - 1);
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if (copy_from_user(buf, user_buf, len))
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return -EFAULT;
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buf[len] = '\0';
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sptr = buf;
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token = strsep(&sptr, delim);
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if (!token)
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return -EINVAL;
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cmd = token;
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cnss_pr_dbg("Received dev_boot debug command: %s\n", cmd);
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if (sysfs_streq(cmd, "on")) {
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ret = cnss_power_on_device(plat_priv);
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} else if (sysfs_streq(cmd, "off")) {
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cnss_power_off_device(plat_priv);
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} else if (sysfs_streq(cmd, "enumerate")) {
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ret = cnss_pci_init(plat_priv);
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} else if (sysfs_streq(cmd, "powerup")) {
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set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
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ret = cnss_driver_event_post(plat_priv,
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CNSS_DRIVER_EVENT_POWER_UP,
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CNSS_EVENT_SYNC, NULL);
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} else if (sysfs_streq(cmd, "shutdown")) {
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ret = cnss_driver_event_post(plat_priv,
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CNSS_DRIVER_EVENT_POWER_DOWN,
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0, NULL);
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clear_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
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} else if (sysfs_streq(cmd, "assert_host_sol")) {
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ret = cnss_set_host_sol_value(plat_priv, 1);
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} else if (sysfs_streq(cmd, "deassert_host_sol")) {
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ret = cnss_set_host_sol_value(plat_priv, 0);
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} else if (sysfs_streq(cmd, "pdc_update")) {
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if (!sptr)
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return -EINVAL;
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ret = cnss_aop_send_msg(plat_priv, sptr);
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} else if (sysfs_streq(cmd, "dev_check")) {
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cnss_wlan_hw_disable_check(plat_priv);
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} else if (sysfs_streq(cmd, "dev_enable")) {
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cnss_wlan_hw_enable();
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} else {
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pci_priv = plat_priv->bus_priv;
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if (!pci_priv)
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return -ENODEV;
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if (sysfs_streq(cmd, "download")) {
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set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
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ret = cnss_pci_start_mhi(pci_priv);
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} else if (sysfs_streq(cmd, "linkup")) {
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ret = cnss_resume_pci_link(pci_priv);
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} else if (sysfs_streq(cmd, "linkdown")) {
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ret = cnss_suspend_pci_link(pci_priv);
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} else if (sysfs_streq(cmd, "assert")) {
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cnss_pr_info("FW Assert triggered for debug\n");
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ret = cnss_force_fw_assert(&pci_priv->pci_dev->dev);
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} else if (sysfs_streq(cmd, "set_cbc_done")) {
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cnss_pr_dbg("Force set cold boot cal done status\n");
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set_bit(CNSS_COLD_BOOT_CAL_DONE,
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&plat_priv->driver_state);
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} else {
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cnss_pr_err("Device boot debugfs command is invalid\n");
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ret = -EINVAL;
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}
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}
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if (ret < 0)
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return ret;
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return count;
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}
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static int cnss_dev_boot_debug_show(struct seq_file *s, void *data)
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{
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seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/dev_boot\n");
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seq_puts(s, "<action> can be one of below:\n");
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seq_puts(s, "on: turn on device power, assert WLAN_EN\n");
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seq_puts(s, "off: de-assert WLAN_EN, turn off device power\n");
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seq_puts(s, "enumerate: de-assert PERST, enumerate PCIe\n");
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seq_puts(s, "download: download FW and do QMI handshake with FW\n");
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seq_puts(s, "linkup: bring up PCIe link\n");
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seq_puts(s, "linkdown: bring down PCIe link\n");
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seq_puts(s, "powerup: full power on sequence to boot device, download FW and do QMI handshake with FW\n");
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seq_puts(s, "shutdown: full power off sequence to shutdown device\n");
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seq_puts(s, "assert: trigger firmware assert\n");
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seq_puts(s, "set_cbc_done: Set cold boot calibration done status\n");
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seq_puts(s, "\npdc_update usage:");
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seq_puts(s, "1. echo pdc_update {class: wlan_pdc ss: <pdc_ss>, res: <vreg>.<mode>, <seq>: <val>} > <debugfs_path>/cnss/dev_boot\n");
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seq_puts(s, "2. echo pdc_update {class: wlan_pdc ss: <pdc_ss>, res: pdc, enable: <val>} > <debugfs_path>/cnss/dev_boot\n");
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return 0;
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}
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static int cnss_dev_boot_debug_open(struct inode *inode, struct file *file)
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{
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return single_open(file, cnss_dev_boot_debug_show, inode->i_private);
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}
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static const struct file_operations cnss_dev_boot_debug_fops = {
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.read = seq_read,
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.write = cnss_dev_boot_debug_write,
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.release = single_release,
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.open = cnss_dev_boot_debug_open,
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.owner = THIS_MODULE,
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.llseek = seq_lseek,
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};
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static int cnss_reg_read_debug_show(struct seq_file *s, void *data)
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{
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struct cnss_plat_data *plat_priv = s->private;
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mutex_lock(&plat_priv->dev_lock);
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if (!plat_priv->diag_reg_read_buf) {
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seq_puts(s, "\nUsage: echo <mem_type> <offset> <data_len> > <debugfs_path>/cnss/reg_read\n");
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seq_puts(s, "Use mem_type = 0xff for register read by IO access, data_len will be ignored\n");
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seq_puts(s, "Use mem_type = 0xfe for register read by raw IO access which skips sanity checks, data_len will be ignored\n");
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seq_puts(s, "Use other mem_type for register read by QMI\n");
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mutex_unlock(&plat_priv->dev_lock);
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return 0;
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}
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seq_printf(s, "\nRegister read, address: 0x%x memory type: 0x%x length: 0x%x\n\n",
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plat_priv->diag_reg_read_addr,
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plat_priv->diag_reg_read_mem_type,
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plat_priv->diag_reg_read_len);
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seq_hex_dump(s, "", DUMP_PREFIX_OFFSET, 32, 4,
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plat_priv->diag_reg_read_buf,
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plat_priv->diag_reg_read_len, false);
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plat_priv->diag_reg_read_len = 0;
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kfree(plat_priv->diag_reg_read_buf);
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plat_priv->diag_reg_read_buf = NULL;
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mutex_unlock(&plat_priv->dev_lock);
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return 0;
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}
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static ssize_t cnss_reg_read_debug_write(struct file *fp,
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const char __user *user_buf,
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size_t count, loff_t *off)
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{
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struct cnss_plat_data *plat_priv =
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((struct seq_file *)fp->private_data)->private;
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char buf[64];
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char *sptr, *token;
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unsigned int len = 0;
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u32 reg_offset, mem_type;
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u32 data_len = 0, reg_val = 0;
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u8 *reg_buf = NULL;
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const char *delim = " ";
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int ret = 0;
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len = min(count, sizeof(buf) - 1);
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if (copy_from_user(buf, user_buf, len))
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return -EFAULT;
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buf[len] = '\0';
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sptr = buf;
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token = strsep(&sptr, delim);
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if (!token)
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return -EINVAL;
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if (!sptr)
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return -EINVAL;
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if (kstrtou32(token, 0, &mem_type))
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return -EINVAL;
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token = strsep(&sptr, delim);
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if (!token)
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return -EINVAL;
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if (!sptr)
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return -EINVAL;
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if (kstrtou32(token, 0, ®_offset))
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return -EINVAL;
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token = strsep(&sptr, delim);
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if (!token)
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return -EINVAL;
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if (kstrtou32(token, 0, &data_len))
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return -EINVAL;
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if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
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mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
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ret = cnss_bus_debug_reg_read(plat_priv, reg_offset, ®_val,
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mem_type ==
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MMIO_REG_RAW_ACCESS_MEM_TYPE);
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if (ret)
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return ret;
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cnss_pr_dbg("Read 0x%x from register offset 0x%x\n", reg_val,
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reg_offset);
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return count;
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}
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if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
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cnss_pr_err("Firmware is not ready yet\n");
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return -EINVAL;
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}
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mutex_lock(&plat_priv->dev_lock);
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kfree(plat_priv->diag_reg_read_buf);
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plat_priv->diag_reg_read_buf = NULL;
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reg_buf = kzalloc(data_len, GFP_KERNEL);
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if (!reg_buf) {
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mutex_unlock(&plat_priv->dev_lock);
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return -ENOMEM;
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}
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ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, reg_offset,
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mem_type, data_len,
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reg_buf);
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if (ret) {
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kfree(reg_buf);
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mutex_unlock(&plat_priv->dev_lock);
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return ret;
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}
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plat_priv->diag_reg_read_addr = reg_offset;
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plat_priv->diag_reg_read_mem_type = mem_type;
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plat_priv->diag_reg_read_len = data_len;
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plat_priv->diag_reg_read_buf = reg_buf;
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mutex_unlock(&plat_priv->dev_lock);
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return count;
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}
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static int cnss_reg_read_debug_open(struct inode *inode, struct file *file)
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{
|
|
return single_open(file, cnss_reg_read_debug_show, inode->i_private);
|
|
}
|
|
|
|
static const struct file_operations cnss_reg_read_debug_fops = {
|
|
.read = seq_read,
|
|
.write = cnss_reg_read_debug_write,
|
|
.open = cnss_reg_read_debug_open,
|
|
.owner = THIS_MODULE,
|
|
.llseek = seq_lseek,
|
|
};
|
|
|
|
static int cnss_reg_write_debug_show(struct seq_file *s, void *data)
|
|
{
|
|
seq_puts(s, "\nUsage: echo <mem_type> <offset> <reg_val> > <debugfs_path>/cnss/reg_write\n");
|
|
seq_puts(s, "Use mem_type = 0xff for register write by IO access\n");
|
|
seq_puts(s, "Use mem_type = 0xfe for register write by raw IO access which skips sanity checks\n");
|
|
seq_puts(s, "Use other mem_type for register write by QMI\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t cnss_reg_write_debug_write(struct file *fp,
|
|
const char __user *user_buf,
|
|
size_t count, loff_t *off)
|
|
{
|
|
struct cnss_plat_data *plat_priv =
|
|
((struct seq_file *)fp->private_data)->private;
|
|
char buf[64];
|
|
char *sptr, *token;
|
|
unsigned int len = 0;
|
|
u32 reg_offset, mem_type, reg_val;
|
|
const char *delim = " ";
|
|
int ret = 0;
|
|
|
|
len = min(count, sizeof(buf) - 1);
|
|
if (copy_from_user(buf, user_buf, len))
|
|
return -EFAULT;
|
|
|
|
buf[len] = '\0';
|
|
sptr = buf;
|
|
|
|
token = strsep(&sptr, delim);
|
|
if (!token)
|
|
return -EINVAL;
|
|
|
|
if (!sptr)
|
|
return -EINVAL;
|
|
|
|
if (kstrtou32(token, 0, &mem_type))
|
|
return -EINVAL;
|
|
|
|
token = strsep(&sptr, delim);
|
|
if (!token)
|
|
return -EINVAL;
|
|
|
|
if (!sptr)
|
|
return -EINVAL;
|
|
|
|
if (kstrtou32(token, 0, ®_offset))
|
|
return -EINVAL;
|
|
|
|
token = strsep(&sptr, delim);
|
|
if (!token)
|
|
return -EINVAL;
|
|
|
|
if (kstrtou32(token, 0, ®_val))
|
|
return -EINVAL;
|
|
|
|
if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
|
|
mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
|
|
ret = cnss_bus_debug_reg_write(plat_priv, reg_offset, reg_val,
|
|
mem_type ==
|
|
MMIO_REG_RAW_ACCESS_MEM_TYPE);
|
|
if (ret)
|
|
return ret;
|
|
cnss_pr_dbg("Wrote 0x%x to register offset 0x%x\n", reg_val,
|
|
reg_offset);
|
|
return count;
|
|
}
|
|
|
|
if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
|
|
cnss_pr_err("Firmware is not ready yet\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, reg_offset, mem_type,
|
|
sizeof(u32),
|
|
(u8 *)®_val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return count;
|
|
}
|
|
|
|
static int cnss_reg_write_debug_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, cnss_reg_write_debug_show, inode->i_private);
|
|
}
|
|
|
|
static const struct file_operations cnss_reg_write_debug_fops = {
|
|
.read = seq_read,
|
|
.write = cnss_reg_write_debug_write,
|
|
.open = cnss_reg_write_debug_open,
|
|
.owner = THIS_MODULE,
|
|
.llseek = seq_lseek,
|
|
};
|
|
|
|
static ssize_t cnss_runtime_pm_debug_write(struct file *fp,
|
|
const char __user *user_buf,
|
|
size_t count, loff_t *off)
|
|
{
|
|
struct cnss_plat_data *plat_priv =
|
|
((struct seq_file *)fp->private_data)->private;
|
|
struct cnss_pci_data *pci_priv;
|
|
char buf[64];
|
|
char *cmd;
|
|
unsigned int len = 0;
|
|
int ret = 0;
|
|
|
|
if (!plat_priv)
|
|
return -ENODEV;
|
|
|
|
pci_priv = plat_priv->bus_priv;
|
|
if (!pci_priv)
|
|
return -ENODEV;
|
|
|
|
len = min(count, sizeof(buf) - 1);
|
|
if (copy_from_user(buf, user_buf, len))
|
|
return -EFAULT;
|
|
|
|
buf[len] = '\0';
|
|
cmd = buf;
|
|
|
|
if (sysfs_streq(cmd, "usage_count")) {
|
|
cnss_pci_pm_runtime_show_usage_count(pci_priv);
|
|
} else if (sysfs_streq(cmd, "request_resume")) {
|
|
ret = cnss_pci_pm_request_resume(pci_priv);
|
|
} else if (sysfs_streq(cmd, "resume")) {
|
|
ret = cnss_pci_pm_runtime_resume(pci_priv);
|
|
} else if (sysfs_streq(cmd, "get")) {
|
|
ret = cnss_pci_pm_runtime_get(pci_priv, RTPM_ID_CNSS);
|
|
} else if (sysfs_streq(cmd, "get_noresume")) {
|
|
cnss_pci_pm_runtime_get_noresume(pci_priv, RTPM_ID_CNSS);
|
|
} else if (sysfs_streq(cmd, "put_autosuspend")) {
|
|
ret = cnss_pci_pm_runtime_put_autosuspend(pci_priv,
|
|
RTPM_ID_CNSS);
|
|
} else if (sysfs_streq(cmd, "put_noidle")) {
|
|
cnss_pci_pm_runtime_put_noidle(pci_priv, RTPM_ID_CNSS);
|
|
} else if (sysfs_streq(cmd, "mark_last_busy")) {
|
|
cnss_pci_pm_runtime_mark_last_busy(pci_priv);
|
|
} else if (sysfs_streq(cmd, "resume_bus")) {
|
|
cnss_pci_resume_bus(pci_priv);
|
|
} else if (sysfs_streq(cmd, "suspend_bus")) {
|
|
cnss_pci_suspend_bus(pci_priv);
|
|
} else {
|
|
cnss_pr_err("Runtime PM debugfs command is invalid\n");
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return count;
|
|
}
|
|
|
|
static int cnss_runtime_pm_debug_show(struct seq_file *s, void *data)
|
|
{
|
|
struct cnss_plat_data *plat_priv = s->private;
|
|
struct cnss_pci_data *pci_priv;
|
|
int i;
|
|
|
|
if (!plat_priv)
|
|
return -ENODEV;
|
|
|
|
pci_priv = plat_priv->bus_priv;
|
|
if (!pci_priv)
|
|
return -ENODEV;
|
|
|
|
seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/runtime_pm\n");
|
|
seq_puts(s, "<action> can be one of below:\n");
|
|
seq_puts(s, "usage_count: get runtime PM usage count\n");
|
|
seq_puts(s, "reques_resume: do async runtime PM resume\n");
|
|
seq_puts(s, "resume: do sync runtime PM resume\n");
|
|
seq_puts(s, "get: do runtime PM get\n");
|
|
seq_puts(s, "get_noresume: do runtime PM get noresume\n");
|
|
seq_puts(s, "put_noidle: do runtime PM put noidle\n");
|
|
seq_puts(s, "put_autosuspend: do runtime PM put autosuspend\n");
|
|
seq_puts(s, "mark_last_busy: do runtime PM mark last busy\n");
|
|
seq_puts(s, "resume_bus: do bus resume only\n");
|
|
seq_puts(s, "suspend_bus: do bus suspend only\n");
|
|
|
|
seq_puts(s, "\nStats:\n");
|
|
seq_printf(s, "%s: %u\n", "get count",
|
|
atomic_read(&pci_priv->pm_stats.runtime_get));
|
|
seq_printf(s, "%s: %u\n", "put count",
|
|
atomic_read(&pci_priv->pm_stats.runtime_put));
|
|
seq_printf(s, "%-10s%-10s%-10s%-15s%-15s\n",
|
|
"id:", "get", "put", "get time(us)", "put time(us)");
|
|
for (i = 0; i < RTPM_ID_MAX; i++) {
|
|
seq_printf(s, "%d%-9s", i, ":");
|
|
seq_printf(s, "%-10d",
|
|
atomic_read(&pci_priv->pm_stats.runtime_get_id[i]));
|
|
seq_printf(s, "%-10d",
|
|
atomic_read(&pci_priv->pm_stats.runtime_put_id[i]));
|
|
seq_printf(s, "%-15llu",
|
|
pci_priv->pm_stats.runtime_get_timestamp_id[i]);
|
|
seq_printf(s, "%-15llu\n",
|
|
pci_priv->pm_stats.runtime_put_timestamp_id[i]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cnss_runtime_pm_debug_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, cnss_runtime_pm_debug_show, inode->i_private);
|
|
}
|
|
|
|
static const struct file_operations cnss_runtime_pm_debug_fops = {
|
|
.read = seq_read,
|
|
.write = cnss_runtime_pm_debug_write,
|
|
.open = cnss_runtime_pm_debug_open,
|
|
.owner = THIS_MODULE,
|
|
.llseek = seq_lseek,
|
|
};
|
|
|
|
static int process_drv(struct cnss_plat_data *plat_priv, bool enabled)
|
|
{
|
|
if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
|
|
cnss_pr_err("DRV cmd must be used before QMI ready\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
enabled ? cnss_set_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01) :
|
|
cnss_clear_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01);
|
|
|
|
cnss_pr_info("%s DRV suspend\n", enabled ? "enable" : "disable");
|
|
return 0;
|
|
}
|
|
|
|
static int process_quirks(struct cnss_plat_data *plat_priv, u32 val)
|
|
{
|
|
enum cnss_debug_quirks i;
|
|
int ret = 0;
|
|
unsigned long state;
|
|
unsigned long quirks = 0;
|
|
|
|
for (i = 0, state = val; i < QUIRK_MAX_VALUE; state >>= 1, i++) {
|
|
switch (i) {
|
|
case DISABLE_DRV:
|
|
ret = process_drv(plat_priv, !(state & 0x1));
|
|
if (!ret)
|
|
quirks |= (state & 0x1) << i;
|
|
continue;
|
|
default:
|
|
quirks |= (state & 0x1) << i;
|
|
continue;
|
|
}
|
|
}
|
|
|
|
plat_priv->ctrl_params.quirks = quirks;
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t cnss_control_params_debug_write(struct file *fp,
|
|
const char __user *user_buf,
|
|
size_t count, loff_t *off)
|
|
{
|
|
struct cnss_plat_data *plat_priv =
|
|
((struct seq_file *)fp->private_data)->private;
|
|
char buf[64];
|
|
char *sptr, *token;
|
|
char *cmd;
|
|
u32 val;
|
|
unsigned int len = 0;
|
|
const char *delim = " ";
|
|
|
|
if (!plat_priv)
|
|
return -ENODEV;
|
|
|
|
len = min(count, sizeof(buf) - 1);
|
|
if (copy_from_user(buf, user_buf, len))
|
|
return -EFAULT;
|
|
|
|
buf[len] = '\0';
|
|
sptr = buf;
|
|
|
|
token = strsep(&sptr, delim);
|
|
if (!token)
|
|
return -EINVAL;
|
|
if (!sptr)
|
|
return -EINVAL;
|
|
cmd = token;
|
|
|
|
token = strsep(&sptr, delim);
|
|
if (!token)
|
|
return -EINVAL;
|
|
if (kstrtou32(token, 0, &val))
|
|
return -EINVAL;
|
|
|
|
if (strcmp(cmd, "quirks") == 0)
|
|
process_quirks(plat_priv, val);
|
|
else if (strcmp(cmd, "mhi_timeout") == 0)
|
|
plat_priv->ctrl_params.mhi_timeout = val;
|
|
else if (strcmp(cmd, "mhi_m2_timeout") == 0)
|
|
plat_priv->ctrl_params.mhi_m2_timeout = val;
|
|
else if (strcmp(cmd, "qmi_timeout") == 0)
|
|
plat_priv->ctrl_params.qmi_timeout = val;
|
|
else if (strcmp(cmd, "bdf_type") == 0)
|
|
plat_priv->ctrl_params.bdf_type = val;
|
|
else if (strcmp(cmd, "time_sync_period") == 0)
|
|
plat_priv->ctrl_params.time_sync_period = val;
|
|
else
|
|
return -EINVAL;
|
|
|
|
return count;
|
|
}
|
|
|
|
static int cnss_show_quirks_state(struct seq_file *s,
|
|
struct cnss_plat_data *plat_priv)
|
|
{
|
|
enum cnss_debug_quirks i;
|
|
int skip = 0;
|
|
unsigned long state;
|
|
|
|
seq_printf(s, "quirks: 0x%lx (", plat_priv->ctrl_params.quirks);
|
|
for (i = 0, state = plat_priv->ctrl_params.quirks;
|
|
state != 0; state >>= 1, i++) {
|
|
if (!(state & 0x1))
|
|
continue;
|
|
if (skip++)
|
|
seq_puts(s, " | ");
|
|
|
|
switch (i) {
|
|
case LINK_DOWN_SELF_RECOVERY:
|
|
seq_puts(s, "LINK_DOWN_SELF_RECOVERY");
|
|
continue;
|
|
case SKIP_DEVICE_BOOT:
|
|
seq_puts(s, "SKIP_DEVICE_BOOT");
|
|
continue;
|
|
case USE_CORE_ONLY_FW:
|
|
seq_puts(s, "USE_CORE_ONLY_FW");
|
|
continue;
|
|
case SKIP_RECOVERY:
|
|
seq_puts(s, "SKIP_RECOVERY");
|
|
continue;
|
|
case QMI_BYPASS:
|
|
seq_puts(s, "QMI_BYPASS");
|
|
continue;
|
|
case ENABLE_WALTEST:
|
|
seq_puts(s, "WALTEST");
|
|
continue;
|
|
case ENABLE_PCI_LINK_DOWN_PANIC:
|
|
seq_puts(s, "PCI_LINK_DOWN_PANIC");
|
|
continue;
|
|
case FBC_BYPASS:
|
|
seq_puts(s, "FBC_BYPASS");
|
|
continue;
|
|
case ENABLE_DAEMON_SUPPORT:
|
|
seq_puts(s, "DAEMON_SUPPORT");
|
|
continue;
|
|
case DISABLE_DRV:
|
|
seq_puts(s, "DISABLE_DRV");
|
|
continue;
|
|
case DISABLE_IO_COHERENCY:
|
|
seq_puts(s, "DISABLE_IO_COHERENCY");
|
|
continue;
|
|
case IGNORE_PCI_LINK_FAILURE:
|
|
seq_puts(s, "IGNORE_PCI_LINK_FAILURE");
|
|
continue;
|
|
case DISABLE_TIME_SYNC:
|
|
seq_puts(s, "DISABLE_TIME_SYNC");
|
|
continue;
|
|
default:
|
|
continue;
|
|
}
|
|
}
|
|
seq_puts(s, ")\n");
|
|
return 0;
|
|
}
|
|
|
|
static int cnss_control_params_debug_show(struct seq_file *s, void *data)
|
|
{
|
|
struct cnss_plat_data *cnss_priv = s->private;
|
|
|
|
seq_puts(s, "\nUsage: echo <params_name> <value> > <debugfs_path>/cnss/control_params\n");
|
|
seq_puts(s, "<params_name> can be one of below:\n");
|
|
seq_puts(s, "quirks: Debug quirks for driver\n");
|
|
seq_puts(s, "mhi_timeout: Timeout for MHI operation in milliseconds\n");
|
|
seq_puts(s, "qmi_timeout: Timeout for QMI message in milliseconds\n");
|
|
seq_puts(s, "bdf_type: Type of board data file to be downloaded\n");
|
|
seq_puts(s, "time_sync_period: Time period to do time sync with device in milliseconds\n");
|
|
|
|
seq_puts(s, "\nCurrent value:\n");
|
|
cnss_show_quirks_state(s, cnss_priv);
|
|
seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout);
|
|
seq_printf(s, "mhi_m2_timeout: %u\n",
|
|
cnss_priv->ctrl_params.mhi_m2_timeout);
|
|
seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout);
|
|
seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type);
|
|
seq_printf(s, "time_sync_period: %u\n",
|
|
cnss_priv->ctrl_params.time_sync_period);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cnss_control_params_debug_open(struct inode *inode,
|
|
struct file *file)
|
|
{
|
|
return single_open(file, cnss_control_params_debug_show,
|
|
inode->i_private);
|
|
}
|
|
|
|
static const struct file_operations cnss_control_params_debug_fops = {
|
|
.read = seq_read,
|
|
.write = cnss_control_params_debug_write,
|
|
.open = cnss_control_params_debug_open,
|
|
.owner = THIS_MODULE,
|
|
.llseek = seq_lseek,
|
|
};
|
|
|
|
static ssize_t cnss_dynamic_feature_write(struct file *fp,
|
|
const char __user *user_buf,
|
|
size_t count, loff_t *off)
|
|
{
|
|
struct cnss_plat_data *plat_priv =
|
|
((struct seq_file *)fp->private_data)->private;
|
|
int ret = 0;
|
|
u64 val;
|
|
|
|
ret = kstrtou64_from_user(user_buf, count, 0, &val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
plat_priv->dynamic_feature = val;
|
|
ret = cnss_wlfw_dynamic_feature_mask_send_sync(plat_priv);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return count;
|
|
}
|
|
|
|
static int cnss_dynamic_feature_show(struct seq_file *s, void *data)
|
|
{
|
|
struct cnss_plat_data *cnss_priv = s->private;
|
|
|
|
seq_printf(s, "dynamic_feature: 0x%llx\n", cnss_priv->dynamic_feature);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cnss_dynamic_feature_open(struct inode *inode,
|
|
struct file *file)
|
|
{
|
|
return single_open(file, cnss_dynamic_feature_show,
|
|
inode->i_private);
|
|
}
|
|
|
|
static const struct file_operations cnss_dynamic_feature_fops = {
|
|
.read = seq_read,
|
|
.write = cnss_dynamic_feature_write,
|
|
.open = cnss_dynamic_feature_open,
|
|
.owner = THIS_MODULE,
|
|
.llseek = seq_lseek,
|
|
};
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
#ifdef CONFIG_CNSS2_DEBUG
|
|
static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
|
|
{
|
|
struct dentry *root_dentry = plat_priv->root_dentry;
|
|
|
|
debugfs_create_file("dev_boot", 0600, root_dentry, plat_priv,
|
|
&cnss_dev_boot_debug_fops);
|
|
debugfs_create_file("reg_read", 0600, root_dentry, plat_priv,
|
|
&cnss_reg_read_debug_fops);
|
|
debugfs_create_file("reg_write", 0600, root_dentry, plat_priv,
|
|
&cnss_reg_write_debug_fops);
|
|
debugfs_create_file("runtime_pm", 0600, root_dentry, plat_priv,
|
|
&cnss_runtime_pm_debug_fops);
|
|
debugfs_create_file("control_params", 0600, root_dentry, plat_priv,
|
|
&cnss_control_params_debug_fops);
|
|
debugfs_create_file("dynamic_feature", 0600, root_dentry, plat_priv,
|
|
&cnss_dynamic_feature_fops);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
|
|
{
|
|
int ret = 0;
|
|
struct dentry *root_dentry;
|
|
|
|
root_dentry = debugfs_create_dir("cnss", 0);
|
|
if (IS_ERR(root_dentry)) {
|
|
ret = PTR_ERR(root_dentry);
|
|
cnss_pr_err("Unable to create debugfs %d\n", ret);
|
|
goto out;
|
|
}
|
|
|
|
plat_priv->root_dentry = root_dentry;
|
|
|
|
debugfs_create_file("pin_connect_result", 0644, root_dentry, plat_priv,
|
|
&cnss_pin_connect_fops);
|
|
debugfs_create_file("stats", 0644, root_dentry, plat_priv,
|
|
&cnss_stats_fops);
|
|
|
|
cnss_create_debug_only_node(plat_priv);
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
|
|
{
|
|
debugfs_remove_recursive(plat_priv->root_dentry);
|
|
}
|
|
#else
|
|
int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
|
|
{
|
|
plat_priv->root_dentry = NULL;
|
|
return 0;
|
|
}
|
|
|
|
void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#if IS_ENABLED(CONFIG_IPC_LOGGING)
|
|
void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
|
|
const char *log_level, char *fmt, ...)
|
|
{
|
|
struct va_format vaf;
|
|
va_list va_args;
|
|
|
|
va_start(va_args, fmt);
|
|
vaf.fmt = fmt;
|
|
vaf.va = &va_args;
|
|
|
|
if (log_level)
|
|
printk("%scnss: %pV", log_level, &vaf);
|
|
|
|
ipc_log_string(log_ctx, "[%s] %s: %pV", process, fn, &vaf);
|
|
|
|
va_end(va_args);
|
|
}
|
|
|
|
static int cnss_ipc_logging_init(void)
|
|
{
|
|
cnss_ipc_log_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
|
|
"cnss", 0);
|
|
if (!cnss_ipc_log_context) {
|
|
cnss_pr_err("Unable to create IPC log context\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
cnss_ipc_log_long_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
|
|
"cnss-long", 0);
|
|
if (!cnss_ipc_log_long_context) {
|
|
cnss_pr_err("Unable to create IPC long log context\n");
|
|
ipc_log_context_destroy(cnss_ipc_log_context);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void cnss_ipc_logging_deinit(void)
|
|
{
|
|
if (cnss_ipc_log_long_context) {
|
|
ipc_log_context_destroy(cnss_ipc_log_long_context);
|
|
cnss_ipc_log_long_context = NULL;
|
|
}
|
|
|
|
if (cnss_ipc_log_context) {
|
|
ipc_log_context_destroy(cnss_ipc_log_context);
|
|
cnss_ipc_log_context = NULL;
|
|
}
|
|
}
|
|
#else
|
|
static int cnss_ipc_logging_init(void) { return 0; }
|
|
static void cnss_ipc_logging_deinit(void) {}
|
|
void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
|
|
const char *log_level, char *fmt, ...)
|
|
{
|
|
struct va_format vaf;
|
|
va_list va_args;
|
|
|
|
va_start(va_args, fmt);
|
|
vaf.fmt = fmt;
|
|
vaf.va = &va_args;
|
|
|
|
if (log_level)
|
|
printk("%scnss: %pV", log_level, &vaf);
|
|
|
|
va_end(va_args);
|
|
}
|
|
#endif
|
|
|
|
int cnss_debug_init(void)
|
|
{
|
|
return cnss_ipc_logging_init();
|
|
}
|
|
|
|
void cnss_debug_deinit(void)
|
|
{
|
|
cnss_ipc_logging_deinit();
|
|
}
|