3709853456
This change brings msm display driver including sde, dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel project. It is first source code snapshot from base kernel project. Change-Id: Iec864c064ce5ea04e170f24414c728684002f284 Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
593 lines
15 KiB
C
593 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/workqueue.h>
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#include "pll_drv.h"
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#include "dsi_pll.h"
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#include "dsi_pll_14nm.h"
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#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
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#define VCO_DELAY_USEC 1
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static struct dsi_pll_db pll_db[DSI_PLL_NUM];
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static struct regmap_config dsi_pll_14nm_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x588,
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};
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static struct regmap_bus post_n1_div_regmap_bus = {
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.reg_write = post_n1_div_set_div,
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.reg_read = post_n1_div_get_div,
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};
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static struct regmap_bus n2_div_regmap_bus = {
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.reg_write = n2_div_set_div,
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.reg_read = n2_div_get_div,
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};
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static struct regmap_bus shadow_n2_div_regmap_bus = {
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.reg_write = shadow_n2_div_set_div,
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.reg_read = n2_div_get_div,
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};
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static struct regmap_bus dsi_mux_regmap_bus = {
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.reg_write = dsi_mux_set_parent_14nm,
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.reg_read = dsi_mux_get_parent_14nm,
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};
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/* Op structures */
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static const struct clk_ops clk_ops_dsi_vco = {
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.recalc_rate = pll_vco_recalc_rate_14nm,
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.set_rate = pll_vco_set_rate_14nm,
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.round_rate = pll_vco_round_rate_14nm,
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.prepare = pll_vco_prepare_14nm,
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.unprepare = pll_vco_unprepare_14nm,
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};
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/* Shadow ops for dynamic refresh */
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static const struct clk_ops clk_ops_shadow_dsi_vco = {
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.recalc_rate = pll_vco_recalc_rate_14nm,
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.set_rate = shadow_pll_vco_set_rate_14nm,
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.round_rate = pll_vco_round_rate_14nm,
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};
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static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
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.ref_clk_rate = 19200000UL,
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.min_rate = 1300000000UL,
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.max_rate = 2600000000UL,
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.pll_en_seq_cnt = 1,
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.pll_enable_seqs[0] = dsi_pll_enable_seq_14nm,
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_vco_clk_14nm",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_ops_dsi_vco,
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},
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};
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static struct dsi_pll_vco_clk dsi0pll_shadow_vco_clk = {
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.ref_clk_rate = 19200000u,
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.min_rate = 1300000000u,
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.max_rate = 2600000000u,
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_shadow_vco_clk_14nm",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_ops_shadow_dsi_vco,
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},
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};
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static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
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.ref_clk_rate = 19200000UL,
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.min_rate = 1300000000UL,
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.max_rate = 2600000000UL,
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.pll_en_seq_cnt = 1,
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.pll_enable_seqs[0] = dsi_pll_enable_seq_14nm,
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_vco_clk_14nm",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_ops_dsi_vco,
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},
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};
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static struct dsi_pll_vco_clk dsi1pll_shadow_vco_clk = {
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.ref_clk_rate = 19200000u,
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.min_rate = 1300000000u,
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.max_rate = 2600000000u,
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.pll_en_seq_cnt = 1,
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.pll_enable_seqs[0] = dsi_pll_enable_seq_14nm,
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_shadow_vco_clk_14nm",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_ops_shadow_dsi_vco,
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},
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};
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static struct clk_regmap_div dsi0pll_post_n1_div_clk = {
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.reg = 0x48,
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.shift = 0,
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.width = 4,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_post_n1_div_clk",
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.parent_names =
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(const char *[]){ "dsi0pll_vco_clk_14nm" },
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_regmap_div dsi0pll_shadow_post_n1_div_clk = {
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.reg = 0x48,
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.shift = 0,
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.width = 4,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_shadow_post_n1_div_clk",
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.parent_names =
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(const char *[]){"dsi0pll_shadow_vco_clk_14nm"},
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_regmap_div dsi1pll_post_n1_div_clk = {
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.reg = 0x48,
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.shift = 0,
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.width = 4,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_post_n1_div_clk",
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.parent_names =
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(const char *[]){ "dsi1pll_vco_clk_14nm" },
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_regmap_div dsi1pll_shadow_post_n1_div_clk = {
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.reg = 0x48,
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.shift = 0,
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.width = 4,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_shadow_post_n1_div_clk",
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.parent_names =
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(const char *[]){"dsi1pll_shadow_vco_clk_14nm"},
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_regmap_div dsi0pll_n2_div_clk = {
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.reg = 0x48,
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.shift = 0,
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.width = 4,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_n2_div_clk",
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.parent_names =
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(const char *[]){ "dsi0pll_post_n1_div_clk" },
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_regmap_div dsi0pll_shadow_n2_div_clk = {
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.reg = 0x48,
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.shift = 0,
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.width = 4,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_shadow_n2_div_clk",
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.parent_names =
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(const char *[]){ "dsi0pll_shadow_post_n1_div_clk" },
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_regmap_div dsi1pll_n2_div_clk = {
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.reg = 0x48,
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.shift = 0,
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.width = 4,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_n2_div_clk",
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.parent_names =
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(const char *[]){ "dsi1pll_post_n1_div_clk" },
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_regmap_div dsi1pll_shadow_n2_div_clk = {
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.reg = 0x48,
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.shift = 0,
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.width = 4,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_shadow_n2_div_clk",
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.parent_names =
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(const char *[]){ "dsi1pll_shadow_post_n1_div_clk" },
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_fixed_factor dsi0pll_pixel_clk_src = {
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.div = 2,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_pixel_clk_src",
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.parent_names = (const char *[]){ "dsi0pll_n2_div_clk" },
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_fixed_factor dsi0pll_shadow_pixel_clk_src = {
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.div = 2,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_shadow_pixel_clk_src",
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.parent_names = (const char *[]){ "dsi0pll_shadow_n2_div_clk" },
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_fixed_factor dsi1pll_pixel_clk_src = {
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.div = 2,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_pixel_clk_src",
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.parent_names = (const char *[]){ "dsi1pll_n2_div_clk" },
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_fixed_factor dsi1pll_shadow_pixel_clk_src = {
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.div = 2,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_shadow_pixel_clk_src",
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.parent_names = (const char *[]){ "dsi1pll_shadow_n2_div_clk" },
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_regmap_mux dsi0pll_pixel_clk_mux = {
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.reg = 0x48,
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.shift = 0,
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.width = 1,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi0_phy_pll_out_dsiclk",
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.parent_names =
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(const char *[]){ "dsi0pll_pixel_clk_src",
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"dsi0pll_shadow_pixel_clk_src"},
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.num_parents = 2,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_regmap_mux_closest_ops,
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},
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},
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};
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static struct clk_regmap_mux dsi1pll_pixel_clk_mux = {
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.reg = 0x48,
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.shift = 0,
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.width = 1,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_pixel_clk_mux",
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.parent_names =
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(const char *[]){ "dsi1pll_pixel_clk_src",
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"dsi1pll_shadow_pixel_clk_src"},
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.num_parents = 2,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_regmap_mux_closest_ops,
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},
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},
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};
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static struct clk_fixed_factor dsi0pll_byte_clk_src = {
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.div = 8,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_byte_clk_src",
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.parent_names = (const char *[]){ "dsi0pll_post_n1_div_clk" },
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.num_parents = 1,
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.flags = (CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_fixed_factor dsi0pll_shadow_byte_clk_src = {
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.div = 8,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_shadow_byte_clk_src",
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.parent_names =
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(const char *[]){ "dsi0pll_shadow_post_n1_div_clk" },
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.num_parents = 1,
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.flags = (CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_fixed_factor dsi1pll_byte_clk_src = {
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.div = 8,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_byte_clk_src",
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.parent_names = (const char *[]){ "dsi1pll_post_n1_div_clk" },
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.num_parents = 1,
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.flags = (CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_fixed_factor dsi1pll_shadow_byte_clk_src = {
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.div = 8,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_shadow_byte_clk_src",
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.parent_names =
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(const char *[]){ "dsi1pll_shadow_post_n1_div_clk" },
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.num_parents = 1,
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.flags = (CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_regmap_mux dsi0pll_byte_clk_mux = {
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.reg = 0x48,
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.shift = 0,
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.width = 1,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi0_phy_pll_out_byteclk",
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.parent_names =
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(const char *[]){"dsi0pll_byte_clk_src",
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"dsi0pll_shadow_byte_clk_src"},
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.num_parents = 2,
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.ops = &clk_regmap_mux_closest_ops,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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},
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},
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};
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static struct clk_regmap_mux dsi1pll_byte_clk_mux = {
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.reg = 0x48,
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.shift = 0,
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.width = 1,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_byte_clk_mux",
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.parent_names =
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(const char *[]){"dsi1pll_byte_clk_src",
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"dsi1pll_shadow_byte_clk_src"},
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.num_parents = 2,
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.ops = &clk_regmap_mux_closest_ops,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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},
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},
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};
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static struct clk_hw *mdss_dsi_pllcc_14nm[] = {
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[BYTE0_MUX_CLK] = &dsi0pll_byte_clk_mux.clkr.hw,
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[BYTE0_SRC_CLK] = &dsi0pll_byte_clk_src.hw,
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[PIX0_MUX_CLK] = &dsi0pll_pixel_clk_mux.clkr.hw,
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[PIX0_SRC_CLK] = &dsi0pll_pixel_clk_src.hw,
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[N2_DIV_0_CLK] = &dsi0pll_n2_div_clk.clkr.hw,
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[POST_N1_DIV_0_CLK] = &dsi0pll_post_n1_div_clk.clkr.hw,
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[VCO_CLK_0_CLK] = &dsi0pll_vco_clk.hw,
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[SHADOW_BYTE0_SRC_CLK] = &dsi0pll_shadow_byte_clk_src.hw,
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[SHADOW_PIX0_SRC_CLK] = &dsi0pll_shadow_pixel_clk_src.hw,
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[SHADOW_N2_DIV_0_CLK] = &dsi0pll_shadow_n2_div_clk.clkr.hw,
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[SHADOW_POST_N1_DIV_0_CLK] = &dsi0pll_shadow_post_n1_div_clk.clkr.hw,
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[SHADOW_VCO_CLK_0_CLK] = &dsi0pll_shadow_vco_clk.hw,
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[BYTE1_MUX_CLK] = &dsi1pll_byte_clk_mux.clkr.hw,
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[BYTE1_SRC_CLK] = &dsi1pll_byte_clk_src.hw,
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[PIX1_MUX_CLK] = &dsi1pll_pixel_clk_mux.clkr.hw,
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[PIX1_SRC_CLK] = &dsi1pll_pixel_clk_src.hw,
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[N2_DIV_1_CLK] = &dsi1pll_n2_div_clk.clkr.hw,
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[POST_N1_DIV_1_CLK] = &dsi1pll_post_n1_div_clk.clkr.hw,
|
|
[VCO_CLK_1_CLK] = &dsi1pll_vco_clk.hw,
|
|
[SHADOW_BYTE1_SRC_CLK] = &dsi1pll_shadow_byte_clk_src.hw,
|
|
[SHADOW_PIX1_SRC_CLK] = &dsi1pll_shadow_pixel_clk_src.hw,
|
|
[SHADOW_N2_DIV_1_CLK] = &dsi1pll_shadow_n2_div_clk.clkr.hw,
|
|
[SHADOW_POST_N1_DIV_1_CLK] = &dsi1pll_shadow_post_n1_div_clk.clkr.hw,
|
|
[SHADOW_VCO_CLK_1_CLK] = &dsi1pll_shadow_vco_clk.hw,
|
|
};
|
|
|
|
int dsi_pll_clock_register_14nm(struct platform_device *pdev,
|
|
struct mdss_pll_resources *pll_res)
|
|
{
|
|
int rc = 0, ndx, i;
|
|
int const ssc_freq_default = 31500; /* default h/w recommended value */
|
|
int const ssc_ppm_default = 5000; /* default h/w recommended value */
|
|
struct dsi_pll_db *pdb;
|
|
struct clk_onecell_data *clk_data;
|
|
struct clk *clk;
|
|
struct regmap *regmap;
|
|
int num_clks = ARRAY_SIZE(mdss_dsi_pllcc_14nm);
|
|
|
|
if (pll_res->index >= DSI_PLL_NUM) {
|
|
pr_err("pll ndx=%d is NOT supported\n", pll_res->index);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ndx = pll_res->index;
|
|
pdb = &pll_db[ndx];
|
|
pll_res->priv = pdb;
|
|
pdb->pll = pll_res;
|
|
ndx++;
|
|
ndx %= DSI_PLL_NUM;
|
|
pdb->next = &pll_db[ndx];
|
|
|
|
if (pll_res->ssc_en) {
|
|
if (!pll_res->ssc_freq)
|
|
pll_res->ssc_freq = ssc_freq_default;
|
|
if (!pll_res->ssc_ppm)
|
|
pll_res->ssc_ppm = ssc_ppm_default;
|
|
}
|
|
|
|
clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL);
|
|
if (!clk_data)
|
|
return -ENOMEM;
|
|
|
|
clk_data->clks = devm_kcalloc(&pdev->dev, num_clks,
|
|
sizeof(struct clk *), GFP_KERNEL);
|
|
if (!clk_data->clks)
|
|
return -ENOMEM;
|
|
|
|
clk_data->clk_num = num_clks;
|
|
|
|
/* Set client data to mux, div and vco clocks. */
|
|
if (pll_res->index == DSI_PLL_1) {
|
|
regmap = devm_regmap_init(&pdev->dev, &post_n1_div_regmap_bus,
|
|
pll_res, &dsi_pll_14nm_config);
|
|
dsi1pll_post_n1_div_clk.clkr.regmap = regmap;
|
|
dsi1pll_shadow_post_n1_div_clk.clkr.regmap = regmap;
|
|
|
|
regmap = devm_regmap_init(&pdev->dev, &n2_div_regmap_bus,
|
|
pll_res, &dsi_pll_14nm_config);
|
|
dsi1pll_n2_div_clk.clkr.regmap = regmap;
|
|
|
|
regmap = devm_regmap_init(&pdev->dev, &shadow_n2_div_regmap_bus,
|
|
pll_res, &dsi_pll_14nm_config);
|
|
dsi1pll_shadow_n2_div_clk.clkr.regmap = regmap;
|
|
|
|
regmap = devm_regmap_init(&pdev->dev, &dsi_mux_regmap_bus,
|
|
pll_res, &dsi_pll_14nm_config);
|
|
dsi1pll_byte_clk_mux.clkr.regmap = regmap;
|
|
dsi1pll_pixel_clk_mux.clkr.regmap = regmap;
|
|
|
|
dsi1pll_vco_clk.priv = pll_res;
|
|
dsi1pll_shadow_vco_clk.priv = pll_res;
|
|
|
|
pll_res->vco_delay = VCO_DELAY_USEC;
|
|
|
|
for (i = BYTE1_MUX_CLK; i <= SHADOW_VCO_CLK_1_CLK; i++) {
|
|
pr_debug("register clk: %d index: %d\n",
|
|
i, pll_res->index);
|
|
clk = devm_clk_register(&pdev->dev,
|
|
mdss_dsi_pllcc_14nm[i]);
|
|
if (IS_ERR(clk)) {
|
|
pr_err("clk registration failed for DSI: %d\n",
|
|
pll_res->index);
|
|
rc = -EINVAL;
|
|
goto clk_reg_fail;
|
|
}
|
|
clk_data->clks[i] = clk;
|
|
}
|
|
|
|
rc = of_clk_add_provider(pdev->dev.of_node,
|
|
of_clk_src_onecell_get, clk_data);
|
|
} else {
|
|
regmap = devm_regmap_init(&pdev->dev, &post_n1_div_regmap_bus,
|
|
pll_res, &dsi_pll_14nm_config);
|
|
dsi0pll_post_n1_div_clk.clkr.regmap = regmap;
|
|
dsi0pll_shadow_post_n1_div_clk.clkr.regmap = regmap;
|
|
|
|
regmap = devm_regmap_init(&pdev->dev, &n2_div_regmap_bus,
|
|
pll_res, &dsi_pll_14nm_config);
|
|
dsi0pll_n2_div_clk.clkr.regmap = regmap;
|
|
|
|
regmap = devm_regmap_init(&pdev->dev, &shadow_n2_div_regmap_bus,
|
|
pll_res, &dsi_pll_14nm_config);
|
|
dsi0pll_shadow_n2_div_clk.clkr.regmap = regmap;
|
|
|
|
regmap = devm_regmap_init(&pdev->dev, &dsi_mux_regmap_bus,
|
|
pll_res, &dsi_pll_14nm_config);
|
|
dsi0pll_byte_clk_mux.clkr.regmap = regmap;
|
|
dsi0pll_pixel_clk_mux.clkr.regmap = regmap;
|
|
|
|
dsi0pll_vco_clk.priv = pll_res;
|
|
dsi0pll_shadow_vco_clk.priv = pll_res;
|
|
pll_res->vco_delay = VCO_DELAY_USEC;
|
|
|
|
for (i = BYTE0_MUX_CLK; i <= SHADOW_VCO_CLK_0_CLK; i++) {
|
|
pr_debug("reg clk: %d index: %d\n", i, pll_res->index);
|
|
clk = devm_clk_register(&pdev->dev,
|
|
mdss_dsi_pllcc_14nm[i]);
|
|
if (IS_ERR(clk)) {
|
|
pr_err("clk registration failed for DSI: %d\n",
|
|
pll_res->index);
|
|
rc = -EINVAL;
|
|
goto clk_reg_fail;
|
|
}
|
|
clk_data->clks[i] = clk;
|
|
}
|
|
|
|
rc = of_clk_add_provider(pdev->dev.of_node,
|
|
of_clk_src_onecell_get, clk_data);
|
|
}
|
|
|
|
if (!rc) {
|
|
pr_info("Registered DSI PLL ndx=%d clocks successfully\n",
|
|
pll_res->index);
|
|
return rc;
|
|
}
|
|
|
|
clk_reg_fail:
|
|
return rc;
|
|
}
|