587685c687
git-subtree-dir: qcom/opensource/securemsm-kernel git-subtree-mainline:46e9caf0d0git-subtree-split:a6005ceed2Change-Id: repo: https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/securemsm-kernel tag: LA.VENDOR.14.3.0.r1-17300-lanai.QSSI15.0
137 lines
3.0 KiB
C
137 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* QTI crypto Driver
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*
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* Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __CRYPTO_MSM_QCEDEVI_H
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#define __CRYPTO_MSM_QCEDEVI_H
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#include <linux/interrupt.h>
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#include <linux/cdev.h>
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#include <crypto/hash.h>
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#include "qcom_crypto_device.h"
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#include "fips_status.h"
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#include "qce.h"
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#include "qcedev_smmu.h"
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#define CACHE_LINE_SIZE 64
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#define CE_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE
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enum qcedev_crypto_oper_type {
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QCEDEV_CRYPTO_OPER_CIPHER = 0,
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QCEDEV_CRYPTO_OPER_SHA = 1,
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QCEDEV_CRYPTO_OPER_OFFLOAD_CIPHER = 2,
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QCEDEV_CRYPTO_OPER_LAST
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};
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struct qcedev_handle;
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struct qcedev_cipher_req {
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struct skcipher_request creq;
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void *cookie;
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};
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struct qcedev_sha_req {
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struct ahash_request sreq;
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void *cookie;
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};
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struct qcedev_sha_ctxt {
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uint32_t auth_data[4];
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uint8_t digest[QCEDEV_MAX_SHA_DIGEST];
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uint32_t diglen;
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uint8_t trailing_buf[64];
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uint32_t trailing_buf_len;
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uint8_t first_blk;
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uint8_t last_blk;
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uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE];
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bool init_done;
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};
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struct qcedev_async_req {
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struct list_head list;
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struct completion complete;
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enum qcedev_crypto_oper_type op_type;
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union {
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struct qcedev_cipher_op_req cipher_op_req;
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struct qcedev_sha_op_req sha_op_req;
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struct qcedev_offload_cipher_op_req offload_cipher_op_req;
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};
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union {
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struct qcedev_cipher_req cipher_req;
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struct qcedev_sha_req sha_req;
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};
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struct qcedev_handle *handle;
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int err;
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wait_queue_head_t wait_q;
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uint16_t state;
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bool timed_out;
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};
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/**********************************************************************
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* Register ourselves as a char device to be able to access the dev driver
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* from userspace.
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*/
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#define QCEDEV_DEV "qce"
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struct qcedev_control {
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/* CE features supported by platform */
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struct msm_ce_hw_support platform_support;
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uint32_t ce_lock_count;
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uint32_t high_bw_req_count;
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/* CE features/algorithms supported by HW engine*/
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struct ce_hw_support ce_support;
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/* replaced msm_bus with interconnect path */
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struct icc_path *icc_path;
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/* average and peak bw values for interconnect */
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uint32_t icc_avg_bw;
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uint32_t icc_peak_bw;
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/* char device */
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struct cdev cdev;
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int minor;
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/* qce handle */
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void *qce;
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/* platform device */
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struct platform_device *pdev;
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unsigned int magic;
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struct list_head ready_commands;
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struct qcedev_async_req *active_command;
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spinlock_t lock;
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struct tasklet_struct done_tasklet;
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struct list_head context_banks;
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struct qcedev_mem_client *mem_client;
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};
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struct qcedev_handle {
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/* qcedev control handle */
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struct qcedev_control *cntl;
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/* qce internal sha context*/
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struct qcedev_sha_ctxt sha_ctxt;
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/* qcedev mapped buffer list */
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struct qcedev_buffer_list registeredbufs;
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};
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void qcedev_cipher_req_cb(void *cookie, unsigned char *icv,
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unsigned char *iv, int ret);
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void qcedev_sha_req_cb(void *cookie, unsigned char *digest,
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unsigned char *authdata, int ret);
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#endif /* __CRYPTO_MSM_QCEDEVI_H */
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