d4846129c1
Add qcn9224 v2 HW headers and move v1 headers to qca9224/v1 dir. Change-Id: Ieba3f50dd1160e8fe3017eb8656f993456ca410a CRs-Fixed: 3247610
125 lines
5.4 KiB
C
125 lines
5.4 KiB
C
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/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _RX_PPDU_START_H_
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#define _RX_PPDU_START_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_RX_PPDU_START 6
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#define NUM_OF_QWORDS_RX_PPDU_START 3
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struct rx_ppdu_start {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t phy_ppdu_id : 16,
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preamble_time_to_rxframe : 8,
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reserved_0a : 8;
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uint32_t sw_phy_meta_data : 32;
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uint32_t ppdu_start_timestamp_31_0 : 32;
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uint32_t ppdu_start_timestamp_63_32 : 32;
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uint32_t rxframe_assert_timestamp : 32;
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uint32_t tlv64_padding : 32;
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#else
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uint32_t reserved_0a : 8,
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preamble_time_to_rxframe : 8,
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phy_ppdu_id : 16;
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uint32_t sw_phy_meta_data : 32;
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uint32_t ppdu_start_timestamp_31_0 : 32;
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uint32_t ppdu_start_timestamp_63_32 : 32;
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uint32_t rxframe_assert_timestamp : 32;
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uint32_t tlv64_padding : 32;
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#endif
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};
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#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000
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#define RX_PPDU_START_PHY_PPDU_ID_LSB 0
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#define RX_PPDU_START_PHY_PPDU_ID_MSB 15
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#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff
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#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000
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#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16
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#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23
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#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000
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#define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000
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#define RX_PPDU_START_RESERVED_0A_LSB 24
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#define RX_PPDU_START_RESERVED_0A_MSB 31
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#define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000
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#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000
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#define RX_PPDU_START_SW_PHY_META_DATA_LSB 32
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#define RX_PPDU_START_SW_PHY_META_DATA_MSB 63
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#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000
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#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008
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#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0
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#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31
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#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff
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#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008
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#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32
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#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63
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#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000
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#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010
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#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0
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#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31
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#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff
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#define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010
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#define RX_PPDU_START_TLV64_PADDING_LSB 32
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#define RX_PPDU_START_TLV64_PADDING_MSB 63
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#define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000
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#endif
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