82fbaea349
Below dynamic debug mechanisms are added: 1. Sysfs based control for kernel logs 2. In-memory logging 3. Debug Structures Change-Id: I1da118881b5e79ddd2ada91749da13233e360e16 Signed-off-by: Chelliah Vinu R <quic_chelliah@quicinc.com>
460 lines
11 KiB
C
460 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved..
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*/
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#include <linux/hwspinlock.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <linux/mailbox_client.h>
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#include <linux/mailbox_controller.h>
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#include "ipclite_client.h"
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#define IPCMEM_INIT_COMPLETED 0x1
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#define ACTIVE_CHANNEL 0x1
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#define IPCMEM_TOC_SIZE (4*1024)
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#define MAX_CHANNEL_SIGNALS 6
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#define MAX_PARTITION_COUNT 11 /*11 partitions other than global partition*/
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#define IPCLITE_MSG_SIGNAL 0
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#define IPCLITE_MEM_INIT_SIGNAL 1
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#define IPCLITE_VERSION_SIGNAL 2
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#define IPCLITE_TEST_SIGNAL 3
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#define IPCLITE_SSR_SIGNAL 4
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#define IPCLITE_DEBUG_SIGNAL 5
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/** Flag definitions for the entries */
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#define IPCMEM_TOC_ENTRY_FLAGS_ENABLE_READ_PROTECTION (0x01)
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#define IPCMEM_TOC_ENTRY_FLAGS_ENABLE_WRITE_PROTECTION (0x02)
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#define IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION \
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(IPCMEM_TOC_ENTRY_FLAGS_ENABLE_READ_PROTECTION | \
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_WRITE_PROTECTION)
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#define IPCMEM_TOC_ENTRY_FLAGS_IGNORE_PARTITION (0x00000004)
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/*Hardcoded macro to identify local host on each core*/
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#define LOCAL_HOST IPCMEM_APPS
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/* Timeout (ms) for the trylock of remote spinlocks */
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#define HWSPINLOCK_TIMEOUT 1000
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#define CHANNEL_INACTIVE 0
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#define CHANNEL_ACTIVATE_IN_PROGRESS 1
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#define CHANNEL_ACTIVE 2
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#define CONFIGURED_CORE 1
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#define IPCLITE_DEBUG_SIZE (64 * 1024)
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#define IPCLITE_DEBUG_INFO_SIZE 256
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#define IPCLITE_CORE_DBG_LABEL "APSS:"
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#define IPCLITE_LOG_MSG_SIZE 100
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#define IPCLITE_LOG_BUF_SIZE 512
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#define IPCLITE_DBG_LABEL_SIZE 5
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#define IPCLITE_SIGNAL_LABEL_SIZE 10
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#define PREV_INDEX 2
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#define IPCLITE_OS_LOG(__level, __fmt, arg...) \
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do { \
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if (ipclite_debug_level & __level) { \
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if (ipclite_debug_control & IPCLITE_DMESG_LOG) { \
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pr_info(IPCLITE_CORE_DBG_LABEL "%s:"__fmt, \
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ipclite_dbg_label[__level], ## arg); \
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} \
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if (ipclite_debug_control & IPCLITE_INMEM_LOG) { \
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IPCLITE_OS_INMEM_LOG(IPCLITE_CORE_DBG_LABEL "%s:"__fmt, \
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ipclite_dbg_label[__level], ## arg); \
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} \
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} \
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} while (0)
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/*IPCMEM Structure Definitions*/
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enum ipclite_debug_level {
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IPCLITE_ERR = 0x0001,
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IPCLITE_WARN = 0x0002,
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IPCLITE_INFO = 0x0004,
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IPCLITE_DBG = 0x0008,
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};
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enum ipclite_debug_control {
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IPCLITE_DMESG_LOG = 0x0001,
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IPCLITE_DBG_STRUCT = 0x0002,
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IPCLITE_INMEM_LOG = 0x0004,
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};
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enum ipclite_debug_dump {
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IPCLITE_DUMP_DBG_STRUCT = 0x0001,
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IPCLITE_DUMP_INMEM_LOG = 0x0002,
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IPCLITE_DUMP_SSR = 0x0004,
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};
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static const char ipclite_dbg_label[][IPCLITE_DBG_LABEL_SIZE] = {
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[IPCLITE_ERR] = "err",
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[IPCLITE_WARN] = "warn",
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[IPCLITE_INFO] = "info",
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[IPCLITE_DBG] = "dbg"
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};
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struct ipclite_debug_info_host {
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uint32_t numsig_sent; //no. of signals sent from the core
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uint32_t numsig_recv; //no. of signals received on the core
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uint32_t tx_wr_index; //write index of tx queue
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uint32_t tx_rd_index; //read index of tx queue
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uint32_t rx_wr_index; //write index of rx queue
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uint32_t rx_rd_index; //read index of rx queue
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uint32_t num_intr; //no. of interrupts received on the core
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uint32_t prev_tx_wr_index[PREV_INDEX]; //previous write index of tx queue
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uint32_t prev_tx_rd_index[PREV_INDEX]; //previous read index of tx queue
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uint32_t prev_rx_wr_index[PREV_INDEX]; //previous write index of rx queue
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uint32_t prev_rx_rd_index[PREV_INDEX]; //previous read index of rx queue
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};
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struct ipclite_debug_info_overall {
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uint32_t total_numsig_sent; //total no. of signals sent
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uint32_t total_numsig_recv; //total no. of signals received
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uint32_t last_sent_host_id; //last signal sent to host
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uint32_t last_recv_host_id; //last signal received from host
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uint32_t last_sigid_sent; //last sent signal id
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uint32_t last_sigid_recv; //last received signal id
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};
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struct ipclite_debug_info {
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uint32_t debug_version;
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uint32_t debug_level;
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uint32_t debug_control;
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uint32_t debug_dump;
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uint32_t debug_log_index;
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};
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struct ipclite_debug_inmem_buf {
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char IPCLITELog[IPCLITE_LOG_BUF_SIZE][IPCLITE_LOG_MSG_SIZE];
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};
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struct ipclite_debug_struct {
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struct ipclite_debug_info_overall dbg_info_overall;
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struct ipclite_debug_info_host dbg_info_host[IPCMEM_NUM_HOSTS];
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};
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struct ipclite_features {
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uint32_t global_atomic_support;
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uint32_t version_finalised;
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};
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struct ipclite_recover {
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uint32_t global_atomic_hwlock_owner;
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uint32_t configured_core[IPCMEM_NUM_HOSTS];
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};
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struct ipcmem_partition_header {
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uint32_t type; /*partition type*/
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uint32_t desc_offset; /*descriptor offset*/
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uint32_t desc_size; /*descriptor size*/
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uint32_t fifo0_offset; /*fifo 0 offset*/
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uint32_t fifo0_size; /*fifo 0 size*/
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uint32_t fifo1_offset; /*fifo 1 offset*/
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uint32_t fifo1_size; /*fifo 1 size*/
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};
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struct ipcmem_toc_entry {
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uint32_t base_offset; /*partition offset from IPCMEM base*/
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uint32_t size; /*partition size*/
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uint32_t flags; /*partition flags if required*/
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uint32_t host0; /*subsystem 0 who can access this partition*/
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uint32_t host1; /*subsystem 1 who can access this partition*/
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uint32_t status; /*partition active status*/
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};
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struct ipcmem_toc_header {
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uint32_t size;
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uint32_t init_done;
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};
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struct ipcmem_toc {
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struct ipcmem_toc_header hdr;
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struct ipcmem_toc_entry toc_entry_global;
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struct ipcmem_toc_entry toc_entry[IPCMEM_NUM_HOSTS][IPCMEM_NUM_HOSTS];
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/* Need to have a better implementation here */
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/* as ipcmem is 4k and if host number increases */
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/* it would create problems*/
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struct ipclite_features ipclite_features;
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struct ipclite_recover recovery;
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};
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struct ipcmem_region {
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u64 aux_base;
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void __iomem *virt_base;
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uint32_t size;
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};
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struct ipcmem_partition {
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struct ipcmem_partition_header hdr;
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};
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struct global_partition_header {
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uint32_t partition_type;
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uint32_t region_offset;
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uint32_t region_size;
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};
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struct ipcmem_global_partition {
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struct global_partition_header hdr;
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};
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struct ipclite_mem {
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struct ipcmem_toc *toc;
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struct ipcmem_region mem;
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struct ipcmem_global_partition *global_partition;
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struct ipcmem_partition *partition[MAX_PARTITION_COUNT];
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};
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struct ipclite_fifo {
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uint32_t length;
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__le32 *tail;
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__le32 *head;
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void *fifo;
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size_t (*avail)(struct ipclite_fifo *fifo);
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void (*peak)(struct ipclite_fifo *fifo,
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void *data, size_t count);
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void (*advance)(struct ipclite_fifo *fifo,
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size_t count, uint32_t core_id);
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void (*write)(struct ipclite_fifo *fifo,
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const void *data, size_t dlen, uint32_t core_id, uint32_t signal_id);
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void (*reset)(struct ipclite_fifo *fifo);
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};
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struct ipclite_hw_mutex_ops {
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unsigned long flags;
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void (*acquire)(void);
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void (*release)(void);
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};
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struct ipclite_irq_info {
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struct mbox_client mbox_client;
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struct mbox_chan *mbox_chan;
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int irq;
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int signal_id;
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char irqname[32];
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};
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struct ipclite_client {
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IPCLite_Client callback;
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void *priv_data;
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int reg_complete;
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};
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struct ipclite_channel {
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uint32_t remote_pid;
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struct ipclite_fifo *tx_fifo;
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struct ipclite_fifo *rx_fifo;
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spinlock_t tx_lock;
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struct ipclite_irq_info irq_info[MAX_CHANNEL_SIGNALS];
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struct ipclite_client client;
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uint32_t channel_version;
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uint32_t version_finalised;
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uint32_t channel_status;
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};
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/*Single structure that defines everything about IPCLite*/
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struct ipclite_info {
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struct device *dev;
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struct ipclite_channel channel[IPCMEM_NUM_HOSTS];
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struct ipclite_mem ipcmem;
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struct hwspinlock *hwlock;
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struct ipclite_hw_mutex_ops *ipclite_hw_mutex;
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};
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const struct ipcmem_toc_entry ipcmem_toc_global_partition_entry = {
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/* Global partition. */
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4 * 1024,
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128 * 1024,
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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IPCMEM_GLOBAL_HOST,
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IPCMEM_GLOBAL_HOST,
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};
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const struct ipcmem_toc_entry ipcmem_toc_partition_entries[] = {
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/* Global partition. */
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/* {
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* 4 * 1024,
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* 128 * 1024,
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* IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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* IPCMEM_GLOBAL_HOST,
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* IPCMEM_GLOBAL_HOST,
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* },
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*/
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/* APPS<->CDSP partition. */
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{
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132 * 1024,
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32 * 1024,
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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IPCMEM_APPS,
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IPCMEM_CDSP,
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CHANNEL_INACTIVE,
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},
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/* APPS<->CVP (EVA) partition. */
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{
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164 * 1024,
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32 * 1024,
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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IPCMEM_APPS,
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IPCMEM_CVP,
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CHANNEL_INACTIVE,
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},
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/* APPS<->CAM (ICP) partition. */
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{
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196 * 1024,
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32 * 1024,
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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IPCMEM_APPS,
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IPCMEM_CAM,
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CHANNEL_INACTIVE,
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},
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/* APPS<->VPU (IRIS) partition. */
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{
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228 * 1024,
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32 * 1024,
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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IPCMEM_APPS,
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IPCMEM_VPU,
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CHANNEL_INACTIVE,
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},
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/* CDSP<->CVP (EVA) partition. */
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{
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260 * 1024,
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32 * 1024,
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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IPCMEM_CDSP,
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IPCMEM_CVP,
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CHANNEL_INACTIVE,
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},
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/* CDSP<->CAM (ICP) partition. */
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{
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292 * 1024,
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32 * 1024,
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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IPCMEM_CDSP,
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IPCMEM_CAM,
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CHANNEL_INACTIVE,
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},
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/* CDSP<->VPU (IRIS) partition. */
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{
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324 * 1024,
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32 * 1024,
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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IPCMEM_CDSP,
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IPCMEM_VPU,
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CHANNEL_INACTIVE,
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},
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/* CVP<->CAM (ICP) partition. */
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{
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356 * 1024,
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32 * 1024,
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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IPCMEM_CVP,
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IPCMEM_CAM,
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CHANNEL_INACTIVE,
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},
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/* CVP<->VPU (IRIS) partition. */
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{
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388 * 1024,
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32 * 1024,
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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IPCMEM_CVP,
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IPCMEM_VPU,
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CHANNEL_INACTIVE,
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},
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/* CAM<->VPU (IRIS) partition. */
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{
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420 * 1024,
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32 * 1024,
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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IPCMEM_CAM,
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IPCMEM_VPU,
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CHANNEL_INACTIVE,
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},
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/* APPS<->APPS partition. */
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{
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454 * 1024,
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32 * 1024,
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IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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IPCMEM_APPS,
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IPCMEM_APPS,
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CHANNEL_INACTIVE,
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}
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/* Last entry uses invalid hosts and no protections to signify the end. */
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/* {
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* 0,
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* 0,
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* IPCMEM_TOC_ENTRY_FLAGS_ENABLE_RW_PROTECTION,
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* IPCMEM_INVALID_HOST,
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* IPCMEM_INVALID_HOST,
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* }
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*/
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};
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/*D:wefault partition parameters*/
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#define DEFAULT_PARTITION_TYPE 0x0
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#define DEFAULT_PARTITION_HDR_SIZE 1024
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#define DEFAULT_DESCRIPTOR_OFFSET 1024
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#define DEFAULT_DESCRIPTOR_SIZE (3*1024)
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#define DEFAULT_FIFO0_OFFSET (4*1024)
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#define DEFAULT_FIFO0_SIZE (8*1024)
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#define DEFAULT_FIFO1_OFFSET (12*1024)
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#define DEFAULT_FIFO1_SIZE (8*1024)
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/*Loopback partition parameters*/
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#define LOOPBACK_PARTITION_TYPE 0x1
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/*Global partition parameters*/
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#define GLOBAL_PARTITION_TYPE 0xFF
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#define GLOBAL_PARTITION_HDR_SIZE (4*1024)
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#define GLOBAL_REGION_OFFSET (4*1024)
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#define GLOBAL_REGION_SIZE (124*1024)
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const struct ipcmem_partition_header default_partition_hdr = {
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DEFAULT_PARTITION_TYPE,
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DEFAULT_DESCRIPTOR_OFFSET,
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DEFAULT_DESCRIPTOR_SIZE,
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DEFAULT_FIFO0_OFFSET,
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DEFAULT_FIFO0_SIZE,
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DEFAULT_FIFO1_OFFSET,
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DEFAULT_FIFO1_SIZE,
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};
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/* TX and RX FIFO point to same location for such loopback partition type
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* (FIFO0 offset = FIFO1 offset)
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*/
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const struct ipcmem_partition_header loopback_partition_hdr = {
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LOOPBACK_PARTITION_TYPE,
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DEFAULT_DESCRIPTOR_OFFSET,
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DEFAULT_DESCRIPTOR_SIZE,
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DEFAULT_FIFO0_OFFSET,
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DEFAULT_FIFO0_SIZE,
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DEFAULT_FIFO0_OFFSET,
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DEFAULT_FIFO0_SIZE,
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};
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const struct global_partition_header global_partition_hdr = {
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GLOBAL_PARTITION_TYPE,
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GLOBAL_REGION_OFFSET,
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GLOBAL_REGION_SIZE,
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};
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