0cf22b4439
Add qcn9224 HW headers corresponding. Change-Id: Iaf2dfc04009ffa82b6dd4a40e796148fa99a5744 CRs-Fixed: 3103719
83 baris
3.2 KiB
C
83 baris
3.2 KiB
C
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/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _RX_REO_QUEUE_REFERENCE_H_
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#define _RX_REO_QUEUE_REFERENCE_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_RX_REO_QUEUE_REFERENCE 2
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struct rx_reo_queue_reference {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t rx_reo_queue_desc_addr_31_0 : 32;
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uint32_t rx_reo_queue_desc_addr_39_32 : 8,
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reserved_1 : 8,
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receive_queue_number : 16;
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#else
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uint32_t rx_reo_queue_desc_addr_31_0 : 32;
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uint32_t receive_queue_number : 16,
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reserved_1 : 8,
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rx_reo_queue_desc_addr_39_32 : 8;
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#endif
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};
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#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000000
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#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
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#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31
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#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
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#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000004
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#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
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#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
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#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
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#define RX_REO_QUEUE_REFERENCE_RESERVED_1_OFFSET 0x00000004
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#define RX_REO_QUEUE_REFERENCE_RESERVED_1_LSB 8
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#define RX_REO_QUEUE_REFERENCE_RESERVED_1_MSB 15
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#define RX_REO_QUEUE_REFERENCE_RESERVED_1_MASK 0x0000ff00
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#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004
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#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_LSB 16
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#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MSB 31
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#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000
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#endif
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