748372a24c
This change adds the hooks to enable the active signal override in power collapse sequence. Active signal override is needed to disable the clock gating when the power collapse sequence is running. Change-Id: I9edaed7960b236b3d0179cb67f9cc2c9b3546c9d Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
140 wiersze
3.1 KiB
C
140 wiersze
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*
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*/
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#ifndef _SDE_HW_UIDLE_H
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#define _SDE_HW_UIDLE_H
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#include "sde_hw_catalog.h"
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#include "sde_hw_mdss.h"
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#include "sde_hw_util.h"
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struct sde_hw_uidle;
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#define FAL10_DANGER_SHFT 0
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#define FAL10_EXIT_DANGER_SHFT 4
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#define FAL10_EXIT_CNT_SHFT 16
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#define FAL10_DANGER_MSK GENMASK(2, FAL10_DANGER_SHFT)
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#define FAL10_EXIT_DANGER_MSK GENMASK(6, FAL10_EXIT_DANGER_SHFT)
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#define FAL10_EXIT_CNT_MSK GENMASK(23, FAL10_EXIT_CNT_SHFT)
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#define SDE_UIDLE_WD_GRANULARITY 1
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#define SDE_UIDLE_WD_HEART_BEAT 0
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#define SDE_UIDLE_WD_LOAD_VAL 3
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struct sde_uidle_ctl_cfg {
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u32 fal10_exit_cnt;
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u32 fal10_exit_danger;
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u32 fal10_danger;
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bool uidle_enable;
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};
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struct sde_uidle_wd_cfg {
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u32 granularity;
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u32 heart_beat;
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u32 load_value;
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bool clear;
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bool enable;
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};
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struct sde_uidle_cntr {
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u32 fal1_gate_cntr;
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u32 fal10_gate_cntr;
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u32 fal_wait_gate_cntr;
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u32 fal1_num_transitions_cntr;
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u32 fal10_num_transitions_cntr;
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u32 min_gate_cntr;
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u32 max_gate_cntr;
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};
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struct sde_uidle_status {
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u32 uidle_danger_status_0;
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u32 uidle_danger_status_1;
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u32 uidle_safe_status_0;
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u32 uidle_safe_status_1;
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u32 uidle_idle_status_0;
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u32 uidle_idle_status_1;
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u32 uidle_fal_status_0;
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u32 uidle_fal_status_1;
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u32 uidle_status;
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u32 uidle_en_fal10;
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};
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struct sde_hw_uidle_ops {
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/**
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* set_uidle_ctl - set uidle global config
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* @uidle: uidle context driver
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* @cfg: uidle global config
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*/
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void (*set_uidle_ctl)(struct sde_hw_uidle *uidle,
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struct sde_uidle_ctl_cfg *cfg);
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/**
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* setup_wd_timer - set uidle watchdog timer
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* @uidle: uidle context driver
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* @cfg: uidle wd timer config
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*/
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void (*setup_wd_timer)(struct sde_hw_uidle *uidle,
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struct sde_uidle_wd_cfg *cfg);
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/**
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* uidle_setup_cntr - set uidle perf counters
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* @uidle: uidle context driver
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* @enable: true to enable the counters
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*/
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void (*uidle_setup_cntr)(struct sde_hw_uidle *uidle,
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bool enable);
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/**
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* uidle_get_cntr - get uidle perf counters
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* @uidle: uidle context driver
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* @cntr: pointer to return the counters
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*/
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void (*uidle_get_cntr)(struct sde_hw_uidle *uidle,
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struct sde_uidle_cntr *cntr);
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/**
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* uidle_get_status - get uidle status
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* @uidle: uidle context driver
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* @status: pointer to return the status of uidle
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*/
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void (*uidle_get_status)(struct sde_hw_uidle *uidle,
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struct sde_uidle_status *status);
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/**
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* active_override_enable - enable/disable qactive signal override
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* @uidle: uidle context driver
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* @enable: enable/disable
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*/
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void (*active_override_enable)(struct sde_hw_uidle *uidle,
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bool enable);
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};
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struct sde_hw_uidle {
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/* base */
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struct sde_hw_blk_reg_map hw;
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/* uidle */
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const struct sde_uidle_cfg *cap;
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/* ops */
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struct sde_hw_uidle_ops ops;
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/*
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* uidle is common across all displays, lock to serialize access.
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* must be taken by client before using any ops
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*/
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struct mutex uidle_lock;
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enum sde_uidle idx;
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};
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struct sde_hw_uidle *sde_hw_uidle_init(enum sde_uidle idx,
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void __iomem *addr, unsigned long len,
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struct sde_mdss_cfg *m);
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#endif /*_SDE_HW_UIDLE_H */
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