73c7b7c744
1) Add one counter to track the invaild TX release source 2) Capture he descriptor that caused the issue 3) Print the invalid release source CRs-Fixed: 2380964 Change-Id: I0dc410ae2e7c9df58ef53e3f20ca7979d086659e
1061 行
32 KiB
C
1061 行
32 KiB
C
/*
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* Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#if !defined(HAL_TX_H)
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#define HAL_TX_H
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/*---------------------------------------------------------------------------
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Include files
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---------------------------------------------------------------------------*/
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#include "hal_api.h"
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#include "wcss_version.h"
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#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFFSET 0x00000014
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#define WBM_RELEASE_RING_5_TX_RATE_STATS_LSB 0
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#define WBM_RELEASE_RING_5_TX_RATE_STATS_MASK 0xffffffff
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/*---------------------------------------------------------------------------
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Preprocessor definitions and constants
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---------------------------------------------------------------------------*/
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#define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET
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#define HAL_SET_FLD(desc, block , field) \
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(*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field)))
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#define HAL_SET_FLD_OFFSET(desc, block , field, offset) \
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(*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset)))
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#define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \
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do { \
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((struct tlv_32_hdr *) desc)->tlv_tag = (tag); \
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((struct tlv_32_hdr *) desc)->tlv_len = (len); \
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} while (0)
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#define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E
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#define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E
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#define HAL_TX_SM(block, field, value) \
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((value << (block ## _ ## field ## _LSB)) & \
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(block ## _ ## field ## _MASK))
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#define HAL_TX_MS(block, field, value) \
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(((value) & (block ## _ ## field ## _MASK)) >> \
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(block ## _ ## field ## _LSB))
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#define HAL_TX_DESC_GET(desc, block, field) \
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HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field))
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#define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \
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HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub))
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#define HAL_TX_BUF_TYPE_BUFFER 0
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#define HAL_TX_BUF_TYPE_EXT_DESC 1
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#define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD)
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#define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4)
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#define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION)
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#define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4)
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#define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING)
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#define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4)
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#define HAL_TX_BITS_PER_TID 3
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#define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1)
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#define HAL_TX_NUM_DSCP_PER_REGISTER 10
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#define HAL_MAX_HW_DSCP_TID_MAPS 2
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#define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32
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#define HAL_MAX_HW_DSCP_TID_V2_MAPS 48
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#define HTT_META_HEADER_LEN_BYTES 64
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#define HAL_TX_EXT_DESC_WITH_META_DATA \
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(HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES)
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#define HAL_TX_NUM_PCP_PER_REGISTER 8
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/* Length of WBM release ring without the status words */
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#define HAL_TX_COMPLETION_DESC_BASE_LEN 12
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#define HAL_TX_COMP_RELEASE_SOURCE_TQM 0
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#define HAL_TX_COMP_RELEASE_SOURCE_FW 3
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/* Define a place-holder release reason for FW */
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#define HAL_TX_COMP_RELEASE_REASON_FW 99
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/*
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* Offset of HTT Tx Descriptor in WBM Completion
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* HTT Tx Desc structure is passed from firmware to host overlayed
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* on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions
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* (Exception frames and TQM bypass frames)
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*/
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#define HAL_TX_COMP_HTT_STATUS_OFFSET 8
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#define HAL_TX_COMP_HTT_STATUS_LEN 16
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#define HAL_TX_BUF_TYPE_BUFFER 0
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#define HAL_TX_BUF_TYPE_EXT_DESC 1
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#define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET
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#define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK
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#define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK
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#define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK
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#define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB
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#define HAL_TX_EXT_BUF_WD_SIZE 2
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#define HAL_TX_DESC_ADDRX_EN 0x1
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#define HAL_TX_DESC_ADDRY_EN 0x2
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#define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3
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#define HAL_TX_ADDR_SEARCH_DEFAULT 0x0
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#define HAL_TX_ADDR_INDEX_SEARCH 0x1
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#define HAL_TX_FLOW_INDEX_SEARCH 0x2
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enum hal_tx_ret_buf_manager {
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HAL_WBM_SW0_BM_ID = 3,
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HAL_WBM_SW1_BM_ID = 4,
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HAL_WBM_SW2_BM_ID = 5,
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HAL_WBM_SW3_BM_ID = 6,
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};
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/*---------------------------------------------------------------------------
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Structures
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---------------------------------------------------------------------------*/
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/**
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* struct hal_tx_completion_status - HAL Tx completion descriptor contents
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* @status: frame acked/failed
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* @release_src: release source = TQM/FW
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* @ack_frame_rssi: RSSI of the received ACK or BA frame
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* @first_msdu: Indicates this MSDU is the first MSDU in AMSDU
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* @last_msdu: Indicates this MSDU is the last MSDU in AMSDU
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* @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU
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* @bw: Indicates the BW of the upcoming transmission -
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* <enum 0 transmit_bw_20_MHz>
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* <enum 1 transmit_bw_40_MHz>
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* <enum 2 transmit_bw_80_MHz>
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* <enum 3 transmit_bw_160_MHz>
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* @pkt_type: Transmit Packet Type
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* @stbc: When set, STBC transmission rate was used
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* @ldpc: When set, use LDPC transmission rates
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* @sgi: <enum 0 0_8_us_sgi > Legacy normal GI
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* <enum 1 0_4_us_sgi > Legacy short GI
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* <enum 2 1_6_us_sgi > HE related GI
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* <enum 3 3_2_us_sgi > HE
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* @mcs: Transmit MCS Rate
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* @ofdma: Set when the transmission was an OFDMA transmission
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* @tones_in_ru: The number of tones in the RU used.
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* @tsf: Lower 32 bits of the TSF
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* @ppdu_id: TSF, snapshot of this value when transmission of the
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* PPDU containing the frame finished.
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* @transmit_cnt: Number of times this frame has been transmitted
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* @tid: TID of the flow or MPDU queue
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* @peer_id: Peer ID of the flow or MPDU queue
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*/
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struct hal_tx_completion_status {
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uint8_t status;
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uint8_t release_src;
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uint8_t ack_frame_rssi;
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uint8_t first_msdu:1,
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last_msdu:1,
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msdu_part_of_amsdu:1;
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uint32_t bw:2,
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pkt_type:4,
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stbc:1,
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ldpc:1,
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sgi:2,
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mcs:4,
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ofdma:1,
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tones_in_ru:12,
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valid:1;
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uint32_t tsf;
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uint32_t ppdu_id;
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uint8_t transmit_cnt;
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uint8_t tid;
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uint16_t peer_id;
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};
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/**
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* struct hal_tx_desc_comp_s - hal tx completion descriptor contents
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* @desc: Transmit status information from descriptor
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*/
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struct hal_tx_desc_comp_s {
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uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS];
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};
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/*
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* enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW)
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* @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit
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* @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit
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* @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC
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* @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128
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* @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC
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* @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI
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* @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128
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* @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER
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* @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256
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* @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128
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* @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256
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* @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4
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*/
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enum hal_tx_encrypt_type {
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HAL_TX_ENCRYPT_TYPE_WEP_40 = 0,
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HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 ,
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HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2,
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HAL_TX_ENCRYPT_TYPE_WEP_128 = 3,
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HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4,
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HAL_TX_ENCRYPT_TYPE_WAPI = 5,
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HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6,
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HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7,
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HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8,
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HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9,
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HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10,
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HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11,
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};
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/*
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* enum hal_tx_encap_type - Encapsulation type that HW will perform
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* @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type
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* @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type
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* @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet
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* @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame
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*/
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enum hal_tx_encap_type {
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HAL_TX_ENCAP_TYPE_RAW = 0,
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HAL_TX_ENCAP_TYPE_NWIFI = 1,
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HAL_TX_ENCAP_TYPE_ETHERNET = 2,
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HAL_TX_ENCAP_TYPE_802_3 = 3,
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};
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/**
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* enum hal_tx_tqm_release_reason - TQM Release reason codes
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*
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* @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received
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* @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated
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* by SW
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* @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus
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* initiated by SW
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* @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus
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* initiated by SW
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* @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or
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* “Remove_aged_msdus” initiated by SW
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* @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that
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* remove reason is fw_reason1
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* @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that
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* remove reason is fw_reason2
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* @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that
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* remove reason is fw_reason3
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*/
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enum hal_tx_tqm_release_reason {
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HAL_TX_TQM_RR_FRAME_ACKED,
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HAL_TX_TQM_RR_REM_CMD_REM,
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HAL_TX_TQM_RR_REM_CMD_TX,
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HAL_TX_TQM_RR_REM_CMD_NOTX,
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HAL_TX_TQM_RR_REM_CMD_AGED,
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HAL_TX_TQM_RR_FW_REASON1,
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HAL_TX_TQM_RR_FW_REASON2,
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HAL_TX_TQM_RR_FW_REASON3,
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};
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/* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports
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* @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table
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* @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table
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*/
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enum hal_tx_dscp_tid_table_id {
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HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT,
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HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE,
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};
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/*---------------------------------------------------------------------------
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Function declarations and documentation
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---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------
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TCL Descriptor accessor APIs
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---------------------------------------------------------------------------*/
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/**
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* hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor
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* @desc: Handle to Tx Descriptor
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* @data_length: MSDU length in case of direct descriptor.
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* Length of link extension descriptor in case of Link extension
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* descriptor.Includes the length of Metadata
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* Return: None
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*/
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static inline void hal_tx_desc_set_buf_length(void *desc,
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uint16_t data_length)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |=
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HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length);
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}
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/**
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* hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor
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* @desc: Handle to Tx Descriptor
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* @offset: Packet offset from Metadata in case of direct buffer descriptor.
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_buf_offset(void *desc,
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uint8_t offset)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |=
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HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset);
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}
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/**
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* hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor
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* @desc: Handle to Tx Descriptor
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* @encap_type: Encapsulation that HW will perform
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*
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* Return: void
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*
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*/
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static inline void hal_tx_desc_set_encap_type(void *desc,
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enum hal_tx_encap_type encap_type)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |=
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HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type);
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}
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/**
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* hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor
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* @desc: Handle to Tx Descriptor
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* @type: Encrypt Type
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_encrypt_type(void *desc,
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enum hal_tx_encrypt_type type)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |=
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HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type);
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}
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/**
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* hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags
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* @desc: Handle to Tx Descriptor
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* @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_addr_search_flags(void *desc,
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uint8_t flags)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |=
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HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1));
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HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |=
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HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1));
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}
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/**
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* hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags
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* Tx Descriptor for MSDU_buffer type
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* @desc: Handle to Tx Descriptor
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* @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits)
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_l4_checksum_en(void *desc,
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uint8_t en)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |=
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(HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) |
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HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) |
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HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) |
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HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en));
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}
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/**
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* hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in
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* Tx Descriptor for MSDU_buffer type
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* @desc: Handle to Tx Descriptor
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* @checksum_en_flags: ipv4 checksum enable flags
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_l3_checksum_en(void *desc,
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uint8_t en)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |=
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HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en);
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}
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/**
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* hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor
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* @desc:Handle to Tx Descriptor
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* @metadata: Metadata to be sent to Firmware
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_fw_metadata(void *desc,
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uint16_t metadata)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |=
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HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata);
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}
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/**
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* hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor.
|
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* @desc:Handle to Tx Descriptor
|
|
* @to_fw: if set, Forward packet to FW along with classification result
|
|
*
|
|
* Return: void
|
|
*/
|
|
static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
|
|
{
|
|
HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |=
|
|
HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw);
|
|
}
|
|
|
|
/**
|
|
* hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor
|
|
* @desc: Handle to Tx Descriptor
|
|
* @en: For raw WiFi frames, this indicates transmission to a mesh STA,
|
|
* enabling the interpretation of the 'Mesh Control Present' bit
|
|
* (bit 8) of QoS Control (otherwise this bit is ignored),
|
|
* For native WiFi frames, this indicates that a 'Mesh Control' field
|
|
* is present between the header and the LLC.
|
|
*
|
|
* Return: void
|
|
*/
|
|
static inline void hal_tx_desc_set_mesh_en(void *desc, uint8_t en)
|
|
{
|
|
HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
|
|
HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
|
|
}
|
|
|
|
/**
|
|
* hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in
|
|
* frame) to be used for Tx Frame
|
|
* @desc: Handle to Tx Descriptor
|
|
* @hlos_tid: HLOS TID
|
|
*
|
|
* Return: void
|
|
*/
|
|
static inline void hal_tx_desc_set_hlos_tid(void *desc,
|
|
uint8_t hlos_tid)
|
|
{
|
|
HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |=
|
|
HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid);
|
|
|
|
HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |=
|
|
HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1);
|
|
}
|
|
/**
|
|
* hal_tx_desc_sync - Commit the descriptor to Hardware
|
|
* @hal_tx_des_cached: Cached descriptor that software maintains
|
|
* @hw_desc: Hardware descriptor to be updated
|
|
*/
|
|
static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
|
|
void *hw_desc)
|
|
{
|
|
qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)),
|
|
hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------
|
|
Tx MSDU Extension Descriptor accessor APIs
|
|
---------------------------------------------------------------------------*/
|
|
/**
|
|
* hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag
|
|
* @desc: Handle to Tx MSDU Extension Descriptor
|
|
* @tso_en: bool value set to true if TSO is enabled
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_ext_desc_set_tso_enable(void *desc,
|
|
uint8_t tso_en)
|
|
{
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE) |=
|
|
HAL_TX_SM(TX_MSDU_EXTENSION_0, TSO_ENABLE, tso_en);
|
|
}
|
|
|
|
/**
|
|
* hal_tx_ext_desc_set_tso_flags() - Set TSO Flags
|
|
* @desc: Handle to Tx MSDU Extension Descriptor
|
|
* @falgs: 32-bit word with all TSO flags consolidated
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_ext_desc_set_tso_flags(void *desc,
|
|
uint32_t tso_flags)
|
|
{
|
|
HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE, 0) =
|
|
tso_flags;
|
|
}
|
|
|
|
/**
|
|
* hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload
|
|
* @desc: Handle to Tx MSDU Extension Descriptor
|
|
* @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}
|
|
* @mask: TCP flag mask. Tcp_flag is inserted into the header
|
|
* based on the mask, if tso is enabled
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_ext_desc_set_tcp_flags(void *desc,
|
|
uint16_t tcp_flags,
|
|
uint16_t mask)
|
|
{
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TCP_FLAG) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG, tcp_flags)) |
|
|
(HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG_MASK, mask)));
|
|
}
|
|
|
|
/**
|
|
* hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths
|
|
* @desc: Handle to Tx MSDU Extension Descriptor
|
|
* @l2_len: L2 length for the msdu, if tso is enabled
|
|
* @ip_len: IP length for the msdu, if tso is enabled
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_ext_desc_set_msdu_length(void *desc,
|
|
uint16_t l2_len,
|
|
uint16_t ip_len)
|
|
{
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_1, L2_LENGTH) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_1, L2_LENGTH, l2_len)) |
|
|
(HAL_TX_SM(TX_MSDU_EXTENSION_1, IP_LENGTH, ip_len)));
|
|
}
|
|
|
|
/**
|
|
* hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number
|
|
* @desc: Handle to Tx MSDU Extension Descriptor
|
|
* @seq_num: Tcp_seq_number for the msdu, if tso is enabled
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_ext_desc_set_tcp_seq(void *desc,
|
|
uint32_t seq_num)
|
|
{
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER, seq_num)));
|
|
}
|
|
|
|
|
|
/**
|
|
* hal_tx_ext_desc_set_ip_id() - Set IP Identification field
|
|
* @desc: Handle to Tx MSDU Extension Descriptor
|
|
* @id: IP Id field for the msdu, if tso is enabled
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_ext_desc_set_ip_id(void *desc,
|
|
uint16_t id)
|
|
{
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_3, IP_IDENTIFICATION) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_3, IP_IDENTIFICATION, id)));
|
|
}
|
|
/**
|
|
* hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment
|
|
* @desc: Handle to Tx MSDU Extension Descriptor
|
|
* @frag_num: Fragment number (value can be 0 to 5)
|
|
* @paddr_lo: Lower 32-bit of Buffer Physical address
|
|
* @paddr_hi: Upper 32-bit of Buffer Physical address
|
|
* @length: Buffer Length
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_ext_desc_set_buffer(void *desc,
|
|
uint8_t frag_num,
|
|
uint32_t paddr_lo,
|
|
uint16_t paddr_hi,
|
|
uint16_t length)
|
|
{
|
|
HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0,
|
|
(frag_num << 3)) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo)));
|
|
|
|
HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32,
|
|
(frag_num << 3)) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_PTR_39_32,
|
|
(paddr_hi))));
|
|
|
|
HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_LEN,
|
|
(frag_num << 3)) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length)));
|
|
}
|
|
|
|
/**
|
|
* hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length
|
|
* @desc: Handle to Tx MSDU Extension Descriptor
|
|
* @paddr_lo: Lower 32-bit of Buffer Physical address
|
|
* @paddr_hi: Upper 32-bit of Buffer Physical address
|
|
* @length: Buffer 0 Length
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_ext_desc_set_buffer0_param(void *desc,
|
|
uint32_t paddr_lo,
|
|
uint16_t paddr_hi,
|
|
uint16_t length)
|
|
{
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo)));
|
|
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_7,
|
|
BUF0_PTR_39_32, paddr_hi)));
|
|
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_LEN) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length)));
|
|
}
|
|
|
|
/**
|
|
* hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length
|
|
* @desc: Handle to Tx MSDU Extension Descriptor
|
|
* @paddr_lo: Lower 32-bit of Buffer Physical address
|
|
* @paddr_hi: Upper 32-bit of Buffer Physical address
|
|
* @length: Buffer 1 Length
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_ext_desc_set_buffer1_param(void *desc,
|
|
uint32_t paddr_lo,
|
|
uint16_t paddr_hi,
|
|
uint16_t length)
|
|
{
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_8, BUF1_PTR_31_0) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_8, BUF1_PTR_31_0, paddr_lo)));
|
|
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_PTR_39_32) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_9,
|
|
BUF1_PTR_39_32, paddr_hi)));
|
|
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_LEN) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_9, BUF1_LEN, length)));
|
|
}
|
|
|
|
/**
|
|
* hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length
|
|
* @desc: Handle to Tx MSDU Extension Descriptor
|
|
* @paddr_lo: Lower 32-bit of Buffer Physical address
|
|
* @paddr_hi: Upper 32-bit of Buffer Physical address
|
|
* @length: Buffer 2 Length
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_ext_desc_set_buffer2_param(void *desc,
|
|
uint32_t paddr_lo,
|
|
uint16_t paddr_hi,
|
|
uint16_t length)
|
|
{
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_10, BUF2_PTR_31_0) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_10, BUF2_PTR_31_0,
|
|
paddr_lo)));
|
|
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_PTR_39_32) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_PTR_39_32,
|
|
paddr_hi)));
|
|
|
|
HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_LEN) |=
|
|
((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_LEN, length)));
|
|
}
|
|
|
|
/**
|
|
* hal_tx_ext_desc_sync - Commit the descriptor to Hardware
|
|
* @desc_cached: Cached descriptor that software maintains
|
|
* @hw_desc: Hardware descriptor to be updated
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached,
|
|
uint8_t *hw_desc)
|
|
{
|
|
qdf_mem_copy(&hw_desc[0], &desc_cached[0],
|
|
HAL_TX_EXT_DESC_WITH_META_DATA);
|
|
}
|
|
|
|
/**
|
|
* hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag
|
|
* @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor
|
|
*
|
|
* Return: tso_enable value in the descriptor
|
|
*/
|
|
static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc)
|
|
{
|
|
uint32_t *desc = (uint32_t *) hal_tx_ext_desc;
|
|
return (*desc & TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK) >>
|
|
TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------
|
|
WBM Descriptor accessor APIs for Tx completions
|
|
---------------------------------------------------------------------------*/
|
|
/**
|
|
* hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor
|
|
* @hal_desc: completion ring descriptor pointer
|
|
*
|
|
* This function will tx descriptor id, cookie, within hardware completion
|
|
* descriptor
|
|
*
|
|
* Return: cookie
|
|
*/
|
|
static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc)
|
|
{
|
|
uint32_t comp_desc =
|
|
*(uint32_t *) (((uint8_t *) hal_desc) +
|
|
BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET);
|
|
|
|
/* Cookie is placed on 2nd word */
|
|
return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >>
|
|
BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB;
|
|
}
|
|
|
|
/**
|
|
* hal_tx_comp_get_paddr() - Get paddr within comp descriptor
|
|
* @hal_desc: completion ring descriptor pointer
|
|
*
|
|
* This function will get buffer physical address within hardware completion
|
|
* descriptor
|
|
*
|
|
* Return: Buffer physical address
|
|
*/
|
|
static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc)
|
|
{
|
|
uint32_t paddr_lo;
|
|
uint32_t paddr_hi;
|
|
|
|
paddr_lo = *(uint32_t *) (((uint8_t *) hal_desc) +
|
|
BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET);
|
|
|
|
paddr_hi = *(uint32_t *) (((uint8_t *) hal_desc) +
|
|
BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET);
|
|
|
|
paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >>
|
|
BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB;
|
|
|
|
return (qdf_dma_addr_t) (paddr_lo | (((uint64_t) paddr_hi) << 32));
|
|
}
|
|
|
|
/**
|
|
* hal_tx_comp_get_buffer_source() - Get buffer release source value
|
|
* @hal_desc: completion ring descriptor pointer
|
|
*
|
|
* This function will get buffer release source from Tx completion descriptor
|
|
*
|
|
* Return: buffer release source
|
|
*/
|
|
static inline uint32_t hal_tx_comp_get_buffer_source(void *hal_desc)
|
|
{
|
|
uint32_t comp_desc =
|
|
*(uint32_t *) (((uint8_t *) hal_desc) +
|
|
WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET);
|
|
|
|
return (comp_desc & WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >>
|
|
WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB;
|
|
}
|
|
|
|
/**
|
|
* hal_tx_comp_get_buffer_type() - Buffer or Descriptor type
|
|
* @hal_desc: completion ring descriptor pointer
|
|
*
|
|
* This function will return the type of pointer - buffer or descriptor
|
|
*
|
|
* Return: buffer type
|
|
*/
|
|
static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc)
|
|
{
|
|
uint32_t comp_desc =
|
|
*(uint32_t *) (((uint8_t *) hal_desc) +
|
|
WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET);
|
|
|
|
return (comp_desc & WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >>
|
|
WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB;
|
|
}
|
|
|
|
/**
|
|
* hal_tx_comp_get_release_reason() - TQM Release reason
|
|
* @hal_desc: completion ring descriptor pointer
|
|
*
|
|
* This function will return the type of pointer - buffer or descriptor
|
|
*
|
|
* Return: buffer type
|
|
*/
|
|
static inline uint8_t hal_tx_comp_get_release_reason(void *hal_desc, void *hal)
|
|
{
|
|
struct hal_soc *hal_soc = hal;
|
|
|
|
return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc);
|
|
}
|
|
|
|
|
|
/**
|
|
* hal_tx_comp_desc_sync() - collect hardware descriptor contents
|
|
* @hal_desc: hardware descriptor pointer
|
|
* @comp: software descriptor pointer
|
|
* @read_status: 0 - Do not read status words from descriptors
|
|
* 1 - Enable reading of status words from descriptor
|
|
*
|
|
* This function will collect hardware release ring element contents and
|
|
* translate to software descriptor content
|
|
*
|
|
* Return: none
|
|
*/
|
|
|
|
static inline void hal_tx_comp_desc_sync(void *hw_desc,
|
|
struct hal_tx_desc_comp_s *comp,
|
|
bool read_status)
|
|
{
|
|
if (!read_status)
|
|
qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN);
|
|
else
|
|
qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES);
|
|
}
|
|
|
|
/**
|
|
* hal_dump_comp_desc() - dump tx completion descriptor
|
|
* @hal_desc: hardware descriptor pointer
|
|
*
|
|
* This function will print tx completion descriptor
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_dump_comp_desc(void *hw_desc)
|
|
{
|
|
struct hal_tx_desc_comp_s *comp =
|
|
(struct hal_tx_desc_comp_s *)hw_desc;
|
|
uint32_t i;
|
|
|
|
QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
|
|
"Current tx completion descriptor is");
|
|
|
|
for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) {
|
|
QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
|
|
"DWORD[i] = 0x%x", comp->desc[i]);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor
|
|
* @hal_desc: Hardware (WBM) descriptor pointer
|
|
* @htt_desc: Software HTT descriptor pointer
|
|
*
|
|
* This function will read the HTT structure overlaid on WBM descriptor
|
|
* into a cached software descriptor
|
|
*
|
|
*/
|
|
static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc)
|
|
{
|
|
uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET;
|
|
|
|
qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN);
|
|
}
|
|
|
|
/**
|
|
* hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG
|
|
* @hal_soc: Handle to HAL SoC structure
|
|
* @hal_srng: Handle to HAL SRNG structure
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_init_data_ring(void *hal_soc, void *hal_srng)
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{
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uint8_t *desc_addr;
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struct hal_srng_params srng_params;
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uint32_t desc_size;
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uint32_t num_desc;
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hal_get_srng_params(hal_soc, hal_srng, &srng_params);
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desc_addr = (uint8_t *)srng_params.ring_base_vaddr;
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desc_size = sizeof(struct tcl_data_cmd);
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num_desc = srng_params.num_entries;
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while (num_desc) {
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HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG,
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desc_size);
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desc_addr += (desc_size + sizeof(struct tlv_32_hdr));
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num_desc--;
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}
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}
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/**
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* hal_tx_desc_set_dscp_tid_table_id() - Sets DSCP to TID conversion table ID
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* @hal_soc: Handle to HAL SoC structure
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* @desc: Handle to Tx Descriptor
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* @id: DSCP to tid conversion table to be used for this frame
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_dscp_tid_table_id(struct hal_soc *hal_soc,
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void *desc, uint8_t id)
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{
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hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id(desc, id);
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}
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/**
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* hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table
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*
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* @soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id: mapping table ID - 0,1
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*
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* Return: void
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*/
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static inline void hal_tx_set_dscp_tid_map(struct hal_soc *hal_soc,
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uint8_t *map, uint8_t id)
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|
{
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hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id);
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}
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/**
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* hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user
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*
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* @soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id : MAP ID
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* @dscp: DSCP_TID map index
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*
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* Return: void
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*/
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static inline void hal_tx_update_dscp_tid(struct hal_soc *hal_soc, uint8_t tid,
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uint8_t id, uint8_t dscp)
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|
{
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hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp);
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}
|
|
|
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/**
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* hal_tx_desc_set_lmac_id - Set the lmac_id value
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* @desc: Handle to Tx Descriptor
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|
* @lmac_id: mac Id to ast matching
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* b00 – mac 0
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* b01 – mac 1
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|
* b10 – mac 2
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* b11 – all macs (legacy HK way)
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*
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* Return: void
|
|
*/
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|
static inline void hal_tx_desc_set_lmac_id(struct hal_soc *hal_soc,
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|
void *desc, uint8_t lmac_id)
|
|
{
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hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id);
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}
|
|
|
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/**
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* hal_tx_desc_set_search_type - Set the search type value
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|
* @desc: Handle to Tx Descriptor
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|
* @search_type: search type
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|
* 0 – Normal search
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|
* 1 – Index based address search
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|
* 2 – Index based flow search
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|
*
|
|
* Return: void
|
|
*/
|
|
static inline void hal_tx_desc_set_search_type(struct hal_soc *hal_soc,
|
|
void *desc, uint8_t search_type)
|
|
{
|
|
hal_soc->ops->hal_tx_desc_set_search_type(desc, search_type);
|
|
}
|
|
|
|
/**
|
|
* hal_tx_desc_set_search_index - Set the search index value
|
|
* @desc: Handle to Tx Descriptor
|
|
* @search_index: The index that will be used for index based address or
|
|
* flow search. The field is valid when 'search_type' is
|
|
* 1 0r 2
|
|
*
|
|
* Return: void
|
|
*/
|
|
static inline void hal_tx_desc_set_search_index(struct hal_soc *hal_soc,
|
|
void *desc,
|
|
uint32_t search_index)
|
|
{
|
|
hal_soc->ops->hal_tx_desc_set_search_index(desc, search_index);
|
|
}
|
|
|
|
/**
|
|
* hal_tx_comp_get_status() - TQM Release reason
|
|
* @hal_desc: completion ring Tx status
|
|
*
|
|
* This function will parse the WBM completion descriptor and populate in
|
|
* HAL structure
|
|
*
|
|
* Return: none
|
|
*/
|
|
static inline void hal_tx_comp_get_status(void *desc, void *ts, void *hal)
|
|
{
|
|
struct hal_soc *hal_soc = hal;
|
|
|
|
hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal);
|
|
}
|
|
|
|
|
|
/**
|
|
* hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor
|
|
* @desc: Handle to Tx Descriptor
|
|
* @paddr: Physical Address
|
|
* @pool_id: Return Buffer Manager ID
|
|
* @desc_id: Descriptor ID
|
|
* @type: 0 - Address points to a MSDU buffer
|
|
* 1 - Address points to MSDU extension descriptor
|
|
*
|
|
* Return: void
|
|
*/
|
|
static inline void hal_tx_desc_set_buf_addr(void *desc, dma_addr_t paddr,
|
|
uint8_t pool_id, uint32_t desc_id, uint8_t type, void *hal)
|
|
{
|
|
struct hal_soc *hal_soc = hal;
|
|
|
|
hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id,
|
|
desc_id, type);
|
|
|
|
}
|
|
|
|
/**
|
|
* hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table
|
|
*
|
|
* @soc: HAL SoC context
|
|
* @map: PCP-TID mapping table
|
|
*
|
|
* Return: void
|
|
*/
|
|
static inline void hal_tx_set_pcp_tid_map_default(struct hal_soc *hal_soc,
|
|
uint8_t *map)
|
|
{
|
|
hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map);
|
|
}
|
|
|
|
/**
|
|
* hal_tx_update_pcp_tid_map() - Update PCP to TID map table
|
|
*
|
|
* @soc: HAL SoC context
|
|
* @pcp: pcp value
|
|
* @tid: tid no
|
|
*
|
|
* Return: void
|
|
*/
|
|
static inline void hal_tx_update_pcp_tid_map(struct hal_soc *hal_soc,
|
|
uint8_t pcp, uint8_t tid)
|
|
{
|
|
hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, tid, tid);
|
|
}
|
|
|
|
/**
|
|
* hal_tx_set_tidmap_prty() - Configure TIDmap priority
|
|
*
|
|
* @soc: HAL SoC context
|
|
* @val: priority value
|
|
*
|
|
* Return: void
|
|
*/
|
|
static inline void hal_tx_set_tidmap_prty(struct hal_soc *hal_soc, uint8_t val)
|
|
{
|
|
hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val);
|
|
}
|
|
#endif /* HAL_TX_H */
|