7061cb6d12
Support 600KHz soundwire bus clock scaling for low power voice activation usecases. Change-Id: I46f2697b9e17785396542c9f5ec55ad5b9f6d2f5 Signed-off-by: Meng Wang <mengw@codeaurora.org>
92 lines
3.7 KiB
C
Executable File
92 lines
3.7 KiB
C
Executable File
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _LAHAINA_PORT_CONFIG
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#define _LAHAINA_PORT_CONFIG
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#include <soc/swr-common.h>
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#define WSA_MSTR_PORT_MASK 0xFF
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/*
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* Add port configuration in the format
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*{ si, off1, off2, hstart, hstop, wd_len, bp_mode, bgp_ctrl, lane_ctrl, dir,
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* stream_type}
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*/
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static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
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{7, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{31, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{63, 12, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
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{7, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
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{15, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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};
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static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {
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{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00},
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{31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00},
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{31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x00},
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{7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0, 0x00, 0x00},
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{3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0, 0x00, 0x00},
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};
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/* Headset + PCM Haptics */
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static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = {
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{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, /* HPH/EAR */
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{31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00}, /* HPH_CLH */
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{31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x00}, /* HPH_CMP */
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{7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* LO/AUX */
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{0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */
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{0x18F, 0, 0, 0x8, 0x8, 0x0F, 0x00, 0, 0, 0x00, 0x01}, /* PCM_OUT */
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};
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/* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */
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static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = {
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{7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
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{3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX2 */
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{7, 5, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
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};
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/* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */
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static struct port_params tx_frame_params_shima[SWR_MSTR_PORT_LEN] = {
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{3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
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{3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX2 */
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{7, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
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};
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/* 4.8 MHz clock */
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static struct port_params tx_frame_params_4p8MHz[SWR_MSTR_PORT_LEN] = {
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{7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
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{3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX2 */
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{3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
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};
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/* 0.6 MHz clock */
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static struct port_params tx_frame_params_0p6MHz[SWR_MSTR_PORT_LEN] = {
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{1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
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{1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */
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{1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
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};
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static struct swr_mstr_port_map sm_port_map[] = {
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{TX_MACRO, SWR_UC0, tx_frame_params_default},
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{TX_MACRO, SWR_UC1, tx_frame_params_4p8MHz},
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{TX_MACRO, SWR_UC2, tx_frame_params_0p6MHz},
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{RX_MACRO, SWR_UC0, rx_frame_params_default},
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{RX_MACRO, SWR_UC1, rx_frame_params_dsd},
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{WSA_MACRO, SWR_UC0, wsa_frame_params_default},
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};
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static struct swr_mstr_port_map sm_port_map_shima[] = {
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{TX_MACRO, SWR_UC0, tx_frame_params_shima},
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{RX_MACRO, SWR_UC0, rx_frame_params_default},
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{RX_MACRO, SWR_UC1, rx_frame_params_dsd},
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{WSA_MACRO, SWR_UC0, wsa_frame_params_default},
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};
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#endif /* _LAHAINA_PORT_CONFIG */
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