68df0645ec
- add support to intialise device region by reading data from platform to resources. - add support for iommu_map and iommu_unmap apis. - allocate a 4K page and send this address through HFI_MMAP_ADDR register. - map AON region, send virtual address and size as payload. Change-Id: I5aa26593309a220c5de62836e432c1bd5a63ba1d Signed-off-by: Darshana Patil <quic_darshana@quicinc.com>
97 rivejä
2.9 KiB
C
97 rivejä
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _VENUS_HFI_QUEUE_H_
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#define _VENUS_HFI_QUEUE_H_
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#include <linux/types.h>
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#include "msm_vidc_internal.h"
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#define HFI_MASK_QHDR_TX_TYPE 0xff000000
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#define HFI_MASK_QHDR_RX_TYPE 0x00ff0000
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#define HFI_MASK_QHDR_PRI_TYPE 0x0000ff00
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#define HFI_MASK_QHDR_Q_ID_TYPE 0x000000ff
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#define HFI_Q_ID_HOST_TO_CTRL_CMD_Q 0
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#define HFI_Q_ID_CTRL_TO_HOST_MSG_Q 1
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#define HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q 2
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#define HFI_MASK_QHDR_STATUS 0x000000ff
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#define VIDC_IFACEQ_NUMQ 3
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#define VIDC_IFACEQ_CMDQ_IDX 0
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#define VIDC_IFACEQ_MSGQ_IDX 1
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#define VIDC_IFACEQ_DBGQ_IDX 2
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#define VIDC_IFACEQ_MAX_BUF_COUNT 50
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#define VIDC_IFACE_MAX_PARALLEL_CLNTS 16
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#define VIDC_IFACEQ_DFLT_QHDR 0x01010000
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struct hfi_queue_table_header {
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u32 qtbl_version;
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u32 qtbl_size;
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u32 qtbl_qhdr0_offset;
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u32 qtbl_qhdr_size;
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u32 qtbl_num_q;
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u32 qtbl_num_active_q;
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void *device_addr;
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char name[256];
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};
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struct hfi_queue_header {
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u32 qhdr_status;
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u32 qhdr_start_addr;
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u32 qhdr_type;
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u32 qhdr_q_size;
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u32 qhdr_pkt_size;
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u32 qhdr_pkt_drop_cnt;
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u32 qhdr_rx_wm;
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u32 qhdr_tx_wm;
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u32 qhdr_rx_req;
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u32 qhdr_tx_req;
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u32 qhdr_rx_irq_status;
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u32 qhdr_tx_irq_status;
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u32 qhdr_read_idx;
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u32 qhdr_write_idx;
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};
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#define VIDC_IFACEQ_TABLE_SIZE (sizeof(struct hfi_queue_table_header) + \
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sizeof(struct hfi_queue_header) * VIDC_IFACEQ_NUMQ)
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#define VIDC_IFACEQ_QUEUE_SIZE (VIDC_IFACEQ_MAX_PKT_SIZE * \
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VIDC_IFACEQ_MAX_BUF_COUNT * VIDC_IFACE_MAX_PARALLEL_CLNTS)
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#define VIDC_IFACEQ_GET_QHDR_START_ADDR(ptr, i) \
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(void *)((ptr + sizeof(struct hfi_queue_table_header)) + \
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(i * sizeof(struct hfi_queue_header)))
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#define QDSS_SIZE 4096
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#define SFR_SIZE 4096
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#define MMAP_BUF_SIZE 4096
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#define QUEUE_SIZE (VIDC_IFACEQ_TABLE_SIZE + \
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(VIDC_IFACEQ_QUEUE_SIZE * VIDC_IFACEQ_NUMQ))
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#define ALIGNED_QDSS_SIZE ALIGN(QDSS_SIZE, SZ_4K)
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#define ALIGNED_SFR_SIZE ALIGN(SFR_SIZE, SZ_4K)
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#define ALIGNED_MMAP_BUF_SIZE ALIGN(MMAP_BUF_SIZE, SZ_4K)
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#define ALIGNED_QUEUE_SIZE ALIGN(QUEUE_SIZE, SZ_4K)
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#define SHARED_QSIZE ALIGN(ALIGNED_SFR_SIZE + ALIGNED_QUEUE_SIZE + \
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ALIGNED_QDSS_SIZE + ALIGNED_MMAP_BUF_SIZE, SZ_1M)
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#define TOTAL_QSIZE (SHARED_QSIZE - ALIGNED_SFR_SIZE - ALIGNED_QDSS_SIZE - \
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ALIGNED_MMAP_BUF_SIZE)
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struct msm_vidc_core;
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int venus_hfi_queue_cmd_write(struct msm_vidc_core *core, void *pkt);
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int venus_hfi_queue_cmd_write_intr(struct msm_vidc_core *core, void *pkt,
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bool allow_intr);
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int venus_hfi_queue_msg_read(struct msm_vidc_core *core, void *pkt);
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int venus_hfi_queue_dbg_read(struct msm_vidc_core *core, void *pkt);
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void venus_hfi_queue_deinit(struct msm_vidc_core *core);
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int venus_hfi_queue_init(struct msm_vidc_core *core);
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int venus_hfi_reset_queue_header(struct msm_vidc_core *core);
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#endif
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