627c3c7ec3
Below are the changes in HW headers for E1.5 1) WBM2SW release source enum changed back to lithium values 2) DSCP to tid table num is added in Bank register 3) MCAST ctrl value is moved from Bank to seperate register Change-Id: I342c451d792b1618dcb62ca9d4c77dcf4d4beeac
661 lines
20 KiB
C
661 lines
20 KiB
C
/*
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* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HAL_BE_TX_H_
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#define _HAL_BE_TX_H_
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#include "hal_be_hw_headers.h"
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#include "hal_tx.h"
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enum hal_be_tx_ret_buf_manager {
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HAL_BE_WBM_SW0_BM_ID = 5,
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HAL_BE_WBM_SW1_BM_ID = 6,
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HAL_BE_WBM_SW2_BM_ID = 7,
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HAL_BE_WBM_SW3_BM_ID = 8,
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HAL_BE_WBM_SW4_BM_ID = 9,
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HAL_BE_WBM_SW5_BM_ID = 10,
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HAL_BE_WBM_SW6_BM_ID = 11,
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};
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enum hal_tx_mcast_ctrl {
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/* mcast traffic exceptioned to FW
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* valid only for AP VAP default for AP
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*/
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HAL_TX_MCAST_CTRL_FW_EXCEPTION = 0,
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/* mcast traffic dropped in TCL*/
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HAL_TX_MCAST_CTRL_DROP,
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/* MEC notification are enabled
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* valid only for client VAP
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*/
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HAL_TX_MCAST_CTRL_MEC_NOTIFY,
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/* no special routing for mcast
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* valid for client vap when index search is enabled
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*/
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HAL_TX_MCAST_CTRL_NO_SPECIAL,
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};
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/*---------------------------------------------------------------------------
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* Structures
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* ---------------------------------------------------------------------------
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*/
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/**
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* struct hal_tx_bank_config - SW config bank params
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* @epd: EPD indication flag
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* @encap_type: encapsulation type
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* @encrypt_type: encrypt type
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* @src_buffer_swap: big-endia switch for packet buffer
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* @link_meta_swap: big-endian switch for link metadata
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* @index_lookup_enable: Enabel index lookup
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* @addrx_en: Address-X search
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* @addry_en: Address-Y search
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* @mesh_enable:mesh enable flag
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* @vdev_id_check_en: vdev id check
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* @pmac_id: mac id
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* @mcast_pkt_ctrl: mulitcast packet control
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* @val: value representing bank config
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*/
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union hal_tx_bank_config {
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struct {
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uint32_t epd:1,
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encap_type:2,
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encrypt_type:4,
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src_buffer_swap:1,
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link_meta_swap:1,
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index_lookup_enable:1,
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addrx_en:1,
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addry_en:1,
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mesh_enable:2,
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vdev_id_check_en:1,
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pmac_id:2,
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mcast_pkt_ctrl:2,
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dscp_tid_map_id:6,
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reserved:7;
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};
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uint32_t val;
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};
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/*---------------------------------------------------------------------------
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* Function declarations and documentation
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* ---------------------------------------------------------------------------
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*/
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/*---------------------------------------------------------------------------
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* TCL Descriptor accessor APIs
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*---------------------------------------------------------------------------
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*/
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/**
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* hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor
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* @desc: Handle to Tx Descriptor
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* @data_length: MSDU length in case of direct descriptor.
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* Length of link extension descriptor in case of Link extension
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* descriptor.Includes the length of Metadata
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* Return: None
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*/
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static inline void hal_tx_desc_set_buf_length(void *desc,
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uint16_t data_length)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, DATA_LENGTH) |=
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HAL_TX_SM(TCL_DATA_CMD, DATA_LENGTH, data_length);
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}
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/**
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* hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor
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* @desc: Handle to Tx Descriptor
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* @offset: Packet offset from Metadata in case of direct buffer descriptor.
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_buf_offset(void *desc,
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uint8_t offset)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, PACKET_OFFSET) |=
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HAL_TX_SM(TCL_DATA_CMD, PACKET_OFFSET, offset);
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}
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/**
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* hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags
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* Tx Descriptor for MSDU_buffer type
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* @desc: Handle to Tx Descriptor
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* @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits)
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_l4_checksum_en(void *desc,
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uint8_t en)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |=
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(HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV4_CHECKSUM_EN, en) |
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HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV6_CHECKSUM_EN, en) |
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HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV4_CHECKSUM_EN, en) |
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HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV6_CHECKSUM_EN, en));
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}
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/**
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* hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in
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* Tx Descriptor for MSDU_buffer type
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* @desc: Handle to Tx Descriptor
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* @checksum_en_flags: ipv4 checksum enable flags
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_l3_checksum_en(void *desc,
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uint8_t en)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |=
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HAL_TX_SM(TCL_DATA_CMD, IPV4_CHECKSUM_EN, en);
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}
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/**
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* hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor
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* @desc:Handle to Tx Descriptor
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* @metadata: Metadata to be sent to Firmware
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_fw_metadata(void *desc,
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uint16_t metadata)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_NUMBER) |=
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HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_NUMBER, metadata);
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}
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/**
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* hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor.
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* @desc:Handle to Tx Descriptor
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* @to_fw: if set, Forward packet to FW along with classification result
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, TO_FW) |=
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HAL_TX_SM(TCL_DATA_CMD, TO_FW, to_fw);
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}
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/**
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* hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in
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* frame) to be used for Tx Frame
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* @desc: Handle to Tx Descriptor
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* @hlos_tid: HLOS TID
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_hlos_tid(void *desc,
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uint8_t hlos_tid)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID) |=
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HAL_TX_SM(TCL_DATA_CMD, HLOS_TID, hlos_tid);
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HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID_OVERWRITE) |=
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HAL_TX_SM(TCL_DATA_CMD, HLOS_TID_OVERWRITE, 1);
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}
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/**
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* hal_tx_desc_sync - Commit the descriptor to Hardware
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @hw_desc: Hardware descriptor to be updated
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*/
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static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
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void *hw_desc)
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{
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qdf_mem_copy(hw_desc, hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
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}
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/**
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* hal_tx_desc_set_vdev_id - set vdev id to the descriptor to Hardware
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @vdev_id: vdev id
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*/
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static inline void hal_tx_desc_set_vdev_id(void *desc, uint8_t vdev_id)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, VDEV_ID) |=
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HAL_TX_SM(TCL_DATA_CMD, VDEV_ID, vdev_id);
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}
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/**
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* hal_tx_desc_set_bank_id - set bank id to the descriptor to Hardware
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @bank_id: bank id
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*/
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static inline void hal_tx_desc_set_bank_id(void *desc, uint8_t bank_id)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, BANK_ID) |=
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HAL_TX_SM(TCL_DATA_CMD, BANK_ID, bank_id);
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}
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/**
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* hal_tx_desc_set_tcl_cmd_type - set tcl command type to the descriptor
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* to Hardware
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @tcl_cmd_type: tcl command type
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*/
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static inline void
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hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_TYPE) |=
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HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_TYPE, tcl_cmd_type);
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}
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/**
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* hal_tx_desc_set_lmac_id_be - set lmac id to the descriptor to Hardware
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* @hal_soc_hdl: hal soc handle
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @lmac_id: lmac id
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*/
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static inline void
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hal_tx_desc_set_lmac_id_be(hal_soc_handle_t hal_soc_hdl, void *desc,
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uint8_t lmac_id)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, PMAC_ID) |=
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HAL_TX_SM(TCL_DATA_CMD, PMAC_ID, lmac_id);
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}
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/**
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* hal_tx_desc_set_search_index_be - set search index to the
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* descriptor to Hardware
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* @hal_soc_hdl: hal soc handle
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @search_index: search index
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*/
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static inline void
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hal_tx_desc_set_search_index_be(hal_soc_handle_t hal_soc_hdl, void *desc,
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uint32_t search_index)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, SEARCH_INDEX) |=
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HAL_TX_SM(TCL_DATA_CMD, SEARCH_INDEX, search_index);
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}
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/**
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* hal_tx_desc_set_cache_set_num - set cache set num to the
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* descriptor to Hardware
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* @hal_soc_hdl: hal soc handle
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @cache_num: cache number
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*/
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static inline void
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hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, void *desc,
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uint8_t cache_num)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, CACHE_SET_NUM) |=
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HAL_TX_SM(TCL_DATA_CMD, CACHE_SET_NUM, cache_num);
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}
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/*---------------------------------------------------------------------------
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* WBM Descriptor accessor APIs for Tx completions
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* ---------------------------------------------------------------------------
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*/
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/**
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* hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring
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*
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* Return: BM ID for first tx completion ring
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*/
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static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void)
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{
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return HAL_BE_WBM_SW0_BM_ID;
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}
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/**
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* hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor
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* @hal_desc: completion ring descriptor pointer
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*
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* This function will tx descriptor id, cookie, within hardware completion
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* descriptor. For cases when cookie conversion is disabled, the sw_cookie
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* is present in the 2nd DWORD.
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*
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* Return: cookie
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*/
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static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc)
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{
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uint32_t comp_desc =
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*(uint32_t *)(((uint8_t *)hal_desc) +
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BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET);
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/* Cookie is placed on 2nd word */
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return (comp_desc & BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK) >>
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BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB;
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}
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/**
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* hal_tx_comp_get_paddr() - Get paddr within comp descriptor
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* @hal_desc: completion ring descriptor pointer
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*
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* This function will get buffer physical address within hardware completion
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* descriptor
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*
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* Return: Buffer physical address
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*/
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static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc)
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{
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uint32_t paddr_lo;
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uint32_t paddr_hi;
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paddr_lo = *(uint32_t *)(((uint8_t *)hal_desc) +
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BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET);
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paddr_hi = *(uint32_t *)(((uint8_t *)hal_desc) +
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BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET);
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paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) >>
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BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB;
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return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32));
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}
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#ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
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/* HW set dowrd-2 bit30 to 1 if HW CC is done */
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#define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_OFFSET 0x8
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#define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_MASK 0x40000000
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#define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_LSB 0x1E
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/**
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* hal_tx_comp_get_cookie_convert_done() - Get cookie conversion done flag
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* @hal_desc: completion ring descriptor pointer
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*
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* This function will get the bit value that indicate HW cookie
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* conversion done or not
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*
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* Return: 1 - HW cookie conversion done, 0 - not
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*/
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static inline uint8_t hal_tx_comp_get_cookie_convert_done(void *hal_desc)
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{
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return HAL_TX_DESC_GET(hal_desc, HAL_WBM2SW_COMPLETION_RING_TX,
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CC_DONE);
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}
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#endif
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/**
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* hal_tx_comp_get_desc_va() - Get Desc virtual address within completion Desc
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* @hal_desc: completion ring descriptor pointer
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*
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* This function will get the TX Desc virtual address
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*
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* Return: TX desc virtual address
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*/
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static inline uintptr_t hal_tx_comp_get_desc_va(void *hal_desc)
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{
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uint64_t va_from_desc;
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va_from_desc = HAL_TX_DESC_GET(hal_desc,
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WBM2SW_COMPLETION_RING_TX,
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BUFFER_VIRT_ADDR_31_0) |
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(((uint64_t)HAL_TX_DESC_GET(
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hal_desc,
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WBM2SW_COMPLETION_RING_TX,
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BUFFER_VIRT_ADDR_63_32)) << 32);
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return (uintptr_t)va_from_desc;
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}
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/*---------------------------------------------------------------------------
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* TX BANK register accessor APIs
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* ---------------------------------------------------------------------------
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*/
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/**
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* hal_tx_get_num_tcl_banks() - Get number of banks for target
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*
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* Return: None
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*/
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static inline uint8_t
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hal_tx_get_num_tcl_banks(hal_soc_handle_t hal_soc_hdl)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (hal_soc->ops->hal_tx_get_num_tcl_banks)
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return hal_soc->ops->hal_tx_get_num_tcl_banks();
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return 0;
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}
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/**
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* hal_tx_populate_bank_register() - populate the bank register with
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* the software configs.
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* @soc: HAL soc handle
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* @config: bank config
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* @bank_id: bank id to be configured
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*
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* Returns: None
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*/
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#ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT
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static inline void
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hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl,
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union hal_tx_bank_config *config,
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uint8_t bank_id)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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uint32_t reg_addr, reg_val = 0;
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reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
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bank_id);
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reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
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reg_val |= (config->encap_type <<
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HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
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reg_val |= (config->encrypt_type <<
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HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
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reg_val |= (config->src_buffer_swap <<
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HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
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reg_val |= (config->link_meta_swap <<
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HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
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reg_val |= (config->index_lookup_enable <<
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HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
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reg_val |= (config->addrx_en <<
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HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
|
|
reg_val |= (config->addry_en <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
|
|
reg_val |= (config->mesh_enable <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
|
|
reg_val |= (config->vdev_id_check_en <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
|
|
reg_val |= (config->pmac_id <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
|
|
reg_val |= (config->mcast_pkt_ctrl <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT);
|
|
|
|
HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
|
|
}
|
|
#else
|
|
static inline void
|
|
hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl,
|
|
union hal_tx_bank_config *config,
|
|
uint8_t bank_id)
|
|
{
|
|
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
|
|
uint32_t reg_addr, reg_val = 0;
|
|
|
|
reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
|
|
bank_id);
|
|
|
|
reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
|
|
reg_val |= (config->encap_type <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
|
|
reg_val |= (config->encrypt_type <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
|
|
reg_val |= (config->src_buffer_swap <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
|
|
reg_val |= (config->link_meta_swap <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
|
|
reg_val |= (config->index_lookup_enable <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
|
|
reg_val |= (config->addrx_en <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
|
|
reg_val |= (config->addry_en <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
|
|
reg_val |= (config->mesh_enable <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
|
|
reg_val |= (config->vdev_id_check_en <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
|
|
reg_val |= (config->pmac_id <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
|
|
reg_val |= (config->mcast_pkt_ctrl <<
|
|
HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT);
|
|
|
|
HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
|
|
}
|
|
#endif
|
|
|
|
#define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK
|
|
#define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT
|
|
|
|
#define RBM_PPE2TCL_OFFSET \
|
|
(HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2)
|
|
#define RBM_TCL_CMD_CREDIT_OFFSET \
|
|
(HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2)
|
|
|
|
/**
|
|
* hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id
|
|
* @hal_soc: HAL SoC context
|
|
* @hal_ring_hdl: Source ring pointer
|
|
* @rbm_id: return buffer manager ring id
|
|
*
|
|
* Return: void
|
|
*/
|
|
static inline void
|
|
hal_tx_config_rbm_mapping_be(struct hal_soc *hal_soc,
|
|
hal_ring_handle_t hal_ring_hdl,
|
|
uint8_t rbm_id)
|
|
{
|
|
struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
|
|
uint32_t reg_addr = 0;
|
|
uint32_t reg_val = 0;
|
|
uint32_t val = 0;
|
|
uint8_t ring_num;
|
|
enum hal_ring_type ring_type;
|
|
|
|
ring_type = srng->ring_type;
|
|
ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id;
|
|
ring_num = ring_num - srng->ring_id;
|
|
|
|
reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE);
|
|
|
|
if (ring_type == PPE2TCL)
|
|
ring_num = ring_num + RBM_PPE2TCL_OFFSET;
|
|
else if (ring_type == TCL_CMD_CREDIT)
|
|
ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET;
|
|
|
|
/* get current value stored in register address */
|
|
val = HAL_REG_READ(hal_soc, reg_addr);
|
|
|
|
/* mask out other stored value */
|
|
val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num)));
|
|
|
|
reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) <<
|
|
(RBM_MAPPING_SHFT * ring_num));
|
|
|
|
/* write rbm mapped value to register address */
|
|
HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
|
|
}
|
|
|
|
/**
|
|
* hal_tx_desc_set_buf_addr_be - Fill Buffer Address information in Tx Desc
|
|
* @desc: Handle to Tx Descriptor
|
|
* @paddr: Physical Address
|
|
* @pool_id: Return Buffer Manager ID
|
|
* @desc_id: Descriptor ID
|
|
* @type: 0 - Address points to a MSDU buffer
|
|
* 1 - Address points to MSDU extension descriptor
|
|
*
|
|
* Return: void
|
|
*/
|
|
static inline void
|
|
hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc,
|
|
dma_addr_t paddr, uint8_t rbm_id,
|
|
uint32_t desc_id, uint8_t type)
|
|
{
|
|
/* Set buffer_addr_info.buffer_addr_31_0 */
|
|
HAL_SET_FLD(desc, TCL_DATA_CMD,
|
|
BUF_ADDR_INFO_BUFFER_ADDR_31_0) =
|
|
HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr);
|
|
|
|
/* Set buffer_addr_info.buffer_addr_39_32 */
|
|
HAL_SET_FLD(desc, TCL_DATA_CMD,
|
|
BUF_ADDR_INFO_BUFFER_ADDR_39_32) |=
|
|
HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32,
|
|
(((uint64_t)paddr) >> 32));
|
|
|
|
/* Set buffer_addr_info.return_buffer_manager = rbm id */
|
|
HAL_SET_FLD(desc, TCL_DATA_CMD,
|
|
BUF_ADDR_INFO_RETURN_BUFFER_MANAGER) |=
|
|
HAL_TX_SM(TCL_DATA_CMD,
|
|
BUF_ADDR_INFO_RETURN_BUFFER_MANAGER, rbm_id);
|
|
|
|
/* Set buffer_addr_info.sw_buffer_cookie = desc_id */
|
|
HAL_SET_FLD(desc, TCL_DATA_CMD,
|
|
BUF_ADDR_INFO_SW_BUFFER_COOKIE) |=
|
|
HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE,
|
|
desc_id);
|
|
|
|
/* Set Buffer or Ext Descriptor Type */
|
|
HAL_SET_FLD(desc, TCL_DATA_CMD,
|
|
BUF_OR_EXT_DESC_TYPE) |=
|
|
HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type);
|
|
}
|
|
|
|
#ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT
|
|
|
|
#define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4)
|
|
#define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF)
|
|
#define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3
|
|
#define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2
|
|
|
|
/**
|
|
* hal_tx_vdev_mcast_ctrl_set - set mcast_ctrl value
|
|
* @hal_soc: HAL SoC context
|
|
* @mcast_ctrl_val: mcast ctrl value for this VAP
|
|
*
|
|
* Return: void
|
|
*/
|
|
static inline void
|
|
hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl,
|
|
uint8_t vdev_id,
|
|
uint8_t mcast_ctrl_val)
|
|
{
|
|
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
|
|
uint32_t reg_addr, reg_val = 0;
|
|
uint32_t val;
|
|
uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id);
|
|
uint8_t index_in_reg =
|
|
HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id);
|
|
|
|
reg_addr =
|
|
HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE,
|
|
reg_idx);
|
|
|
|
val = HAL_REG_READ(hal_soc, reg_addr);
|
|
|
|
/* mask out other stored value */
|
|
val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK <<
|
|
(HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)));
|
|
|
|
reg_val = val |
|
|
((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) <<
|
|
(HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg));
|
|
|
|
HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
|
|
}
|
|
#else
|
|
static inline void
|
|
hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl,
|
|
uint8_t vdev_id,
|
|
uint8_t mcast_ctrl_val)
|
|
{
|
|
}
|
|
#endif
|
|
#endif /* _HAL_BE_TX_H_ */
|