d9b2e528a7
Header update as per wcss_r43 version. Change-Id: Ia254ce19ff0740cbaf46bc2c19329c43a97344cb CRs-Fixed: 2262786
758 lines
22 KiB
C
758 lines
22 KiB
C
/*
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* Copyright (c) 2018 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _RX_MPDU_END_H_
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#define _RX_MPDU_END_H_
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#if !defined(__ASSEMBLER__)
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#endif
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// ################ START SUMMARY #################
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//
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// Dword Fields
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// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
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// 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29]
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//
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// ################ END SUMMARY #################
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#define NUM_OF_DWORDS_RX_MPDU_END 2
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struct rx_mpdu_end {
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uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0]
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sw_frame_group_id : 7, //[8:2]
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reserved_0 : 7, //[15:9]
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phy_ppdu_id : 16; //[31:16]
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uint32_t reserved_1a : 11, //[10:0]
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unsup_ktype_short_frame : 1, //[11]
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rx_in_tx_decrypt_byp : 1, //[12]
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overflow_err : 1, //[13]
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mpdu_length_err : 1, //[14]
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tkip_mic_err : 1, //[15]
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decrypt_err : 1, //[16]
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unencrypted_frame_err : 1, //[17]
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pn_fields_contain_valid_info : 1, //[18]
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fcs_err : 1, //[19]
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msdu_length_err : 1, //[20]
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rxdma0_destination_ring : 2, //[22:21]
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rxdma1_destination_ring : 2, //[24:23]
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decrypt_status_code : 3, //[27:25]
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rx_bitmap_not_updated : 1, //[28]
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reserved_1b : 3; //[31:29]
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};
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/*
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rxpcu_mpdu_filter_in_category
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Field indicates what the reason was that this MPDU frame
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was allowed to come into the receive path by RXPCU
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<enum 0 rxpcu_filter_pass> This MPDU passed the normal
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frame filter programming of rxpcu
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<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
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regular frame filter and would have been dropped, were it
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not for the frame fitting into the 'monitor_client'
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category.
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<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
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regular frame filter and also did not pass the
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rxpcu_monitor_client filter. It would have been dropped
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accept that it did pass the 'monitor_other' category.
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<legal 0-2>
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sw_frame_group_id
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SW processes frames based on certain classifications.
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This field indicates to what sw classification this MPDU is
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mapped.
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The classification is given in priority order
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<enum 0 sw_frame_group_NDP_frame>
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<enum 1 sw_frame_group_Multicast_data>
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<enum 2 sw_frame_group_Unicast_data>
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<enum 3 sw_frame_group_Null_data > This includes mpdus
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of type Data Null as well as QoS Data Null
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<enum 4 sw_frame_group_mgmt_0000 >
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<enum 5 sw_frame_group_mgmt_0001 >
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<enum 6 sw_frame_group_mgmt_0010 >
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<enum 7 sw_frame_group_mgmt_0011 >
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<enum 8 sw_frame_group_mgmt_0100 >
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<enum 9 sw_frame_group_mgmt_0101 >
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<enum 10 sw_frame_group_mgmt_0110 >
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<enum 11 sw_frame_group_mgmt_0111 >
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<enum 12 sw_frame_group_mgmt_1000 >
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<enum 13 sw_frame_group_mgmt_1001 >
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<enum 14 sw_frame_group_mgmt_1010 >
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<enum 15 sw_frame_group_mgmt_1011 >
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<enum 16 sw_frame_group_mgmt_1100 >
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<enum 17 sw_frame_group_mgmt_1101 >
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<enum 18 sw_frame_group_mgmt_1110 >
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<enum 19 sw_frame_group_mgmt_1111 >
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<enum 20 sw_frame_group_ctrl_0000 >
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<enum 21 sw_frame_group_ctrl_0001 >
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<enum 22 sw_frame_group_ctrl_0010 >
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<enum 23 sw_frame_group_ctrl_0011 >
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<enum 24 sw_frame_group_ctrl_0100 >
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<enum 25 sw_frame_group_ctrl_0101 >
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<enum 26 sw_frame_group_ctrl_0110 >
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<enum 27 sw_frame_group_ctrl_0111 >
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<enum 28 sw_frame_group_ctrl_1000 >
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<enum 29 sw_frame_group_ctrl_1001 >
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<enum 30 sw_frame_group_ctrl_1010 >
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<enum 31 sw_frame_group_ctrl_1011 >
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<enum 32 sw_frame_group_ctrl_1100 >
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<enum 33 sw_frame_group_ctrl_1101 >
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<enum 34 sw_frame_group_ctrl_1110 >
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<enum 35 sw_frame_group_ctrl_1111 >
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<enum 36 sw_frame_group_unsupported> This covers type 3
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and protocol version != 0
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<legal 0-37>
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reserved_0
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<legal 0>
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phy_ppdu_id
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A ppdu counter value that PHY increments for every PPDU
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received. The counter value wraps around
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<legal all>
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reserved_1a
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<legal 0>
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unsup_ktype_short_frame
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This bit will be '1' when WEP or TKIP or WAPI key type
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is received for 11ah short frame. Crypto will bypass the
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received packet without decryption to RxOLE after setting
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this bit.
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rx_in_tx_decrypt_byp
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Indicates that RX packet is not decrypted as Crypto is
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busy with TX packet processing.
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overflow_err
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RXPCU Receive FIFO ran out of space to receive the full
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MPDU. Therefor this MPDU is terminated early and is thus
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corrupted.
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This MPDU will not be ACKed.
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RXPCU might still be able to correctly receive the
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following MPDUs in the PPDU if enough fifo space became
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available in time
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mpdu_length_err
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Set by RXPCU if the expected MPDU length does not
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correspond with the actually received number of bytes in the
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MPDU.
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tkip_mic_err
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Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
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for this MPDU
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decrypt_err
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Set by RX CRYPTO when CRYPTO detected a decrypt error
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for this MPDU or CRYPTO received an encrypted frame, but did
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not get a valid corresponding key id in the peer entry.
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unencrypted_frame_err
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Set by RX CRYPTO when CRYPTO detected an unencrypted
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frame while in the peer entry field
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'All_frames_shall_be_encrypted' is set.
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pn_fields_contain_valid_info
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Set by RX CRYPTO to indicate that there is a valid PN
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field present in this MPDU
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fcs_err
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Set by RXPCU when there is an FCS error detected for
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this MPDU
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NOTE that when this field is set, all other (error)
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field settings should be ignored as modules could have made
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wrong decisions based on the corrupted data.
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msdu_length_err
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Set by RXOLE when there is an msdu length error detected
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in at least 1 of the MSDUs embedded within the MPDU
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rxdma0_destination_ring
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The ring to which RXDMA0 shall push the frame, assuming
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no MPDU level errors are detected. In case of MPDU level
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errors, RXDMA0 might change the RXDMA0 destination
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<enum 0 rxdma_release_ring > RXDMA0 shall push the
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frame to the Release ring. Effectively this means the frame
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needs to be dropped.
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<enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to
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the FW ring
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<enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to
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the SW ring
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<enum 3 rxdma2reo_ring > RXDMA0 shall push the frame
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to the REO entrance ring
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<legal all>
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rxdma1_destination_ring
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The ring to which RXDMA1 shall push the frame, assuming
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no MPDU level errors are detected. In case of MPDU level
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errors, RXDMA1 might change the RXDMA destination
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<enum 0 rxdma_release_ring > RXDMA1 shall push the
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frame to the Release ring. Effectively this means the frame
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needs to be dropped.
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<enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to
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the FW ring
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<enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to
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the SW ring
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<enum 3 rxdma2reo_ring > RXDMA1 shall push the frame
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to the REO entrance ring
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<legal all>
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decrypt_status_code
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Field provides insight into the decryption performed
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<enum 0 decrypt_ok> Frame had protection enabled and
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decrypted properly
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<enum 1 decrypt_unprotected_frame > Frame is unprotected
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and hence bypassed
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<enum 2 decrypt_data_err > Frame has protection enabled
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and could not be properly decrypted due to MIC/ICV mismatch
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etc.
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<enum 3 decrypt_key_invalid > Frame has protection
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enabled but the key that was required to decrypt this frame
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was not valid
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<enum 4 decrypt_peer_entry_invalid > Frame has
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protection enabled but the key that was required to decrypt
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this frame was not valid
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<enum 5 decrypt_other > Reserved for other indications
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<legal 0 - 5>
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rx_bitmap_not_updated
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Frame is received, but RXPCU could not update the
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receive bitmap due to (temporary) fifo contraints.
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<legal all>
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reserved_1b
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<legal 0>
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*/
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/* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY
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Field indicates what the reason was that this MPDU frame
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was allowed to come into the receive path by RXPCU
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<enum 0 rxpcu_filter_pass> This MPDU passed the normal
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frame filter programming of rxpcu
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<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
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regular frame filter and would have been dropped, were it
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not for the frame fitting into the 'monitor_client'
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category.
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<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
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regular frame filter and also did not pass the
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rxpcu_monitor_client filter. It would have been dropped
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accept that it did pass the 'monitor_other' category.
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<legal 0-2>
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*/
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#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
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#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
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#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
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/* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID
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SW processes frames based on certain classifications.
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This field indicates to what sw classification this MPDU is
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mapped.
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The classification is given in priority order
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<enum 0 sw_frame_group_NDP_frame>
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<enum 1 sw_frame_group_Multicast_data>
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<enum 2 sw_frame_group_Unicast_data>
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<enum 3 sw_frame_group_Null_data > This includes mpdus
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of type Data Null as well as QoS Data Null
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<enum 4 sw_frame_group_mgmt_0000 >
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<enum 5 sw_frame_group_mgmt_0001 >
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<enum 6 sw_frame_group_mgmt_0010 >
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<enum 7 sw_frame_group_mgmt_0011 >
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<enum 8 sw_frame_group_mgmt_0100 >
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<enum 9 sw_frame_group_mgmt_0101 >
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<enum 10 sw_frame_group_mgmt_0110 >
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<enum 11 sw_frame_group_mgmt_0111 >
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<enum 12 sw_frame_group_mgmt_1000 >
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<enum 13 sw_frame_group_mgmt_1001 >
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<enum 14 sw_frame_group_mgmt_1010 >
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<enum 15 sw_frame_group_mgmt_1011 >
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<enum 16 sw_frame_group_mgmt_1100 >
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<enum 17 sw_frame_group_mgmt_1101 >
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<enum 18 sw_frame_group_mgmt_1110 >
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<enum 19 sw_frame_group_mgmt_1111 >
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<enum 20 sw_frame_group_ctrl_0000 >
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<enum 21 sw_frame_group_ctrl_0001 >
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<enum 22 sw_frame_group_ctrl_0010 >
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<enum 23 sw_frame_group_ctrl_0011 >
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<enum 24 sw_frame_group_ctrl_0100 >
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<enum 25 sw_frame_group_ctrl_0101 >
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<enum 26 sw_frame_group_ctrl_0110 >
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<enum 27 sw_frame_group_ctrl_0111 >
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<enum 28 sw_frame_group_ctrl_1000 >
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<enum 29 sw_frame_group_ctrl_1001 >
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<enum 30 sw_frame_group_ctrl_1010 >
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<enum 31 sw_frame_group_ctrl_1011 >
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<enum 32 sw_frame_group_ctrl_1100 >
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<enum 33 sw_frame_group_ctrl_1101 >
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<enum 34 sw_frame_group_ctrl_1110 >
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<enum 35 sw_frame_group_ctrl_1111 >
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<enum 36 sw_frame_group_unsupported> This covers type 3
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and protocol version != 0
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<legal 0-37>
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*/
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#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
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#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2
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#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
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/* Description RX_MPDU_END_0_RESERVED_0
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<legal 0>
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*/
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#define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000
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#define RX_MPDU_END_0_RESERVED_0_LSB 9
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#define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00
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/* Description RX_MPDU_END_0_PHY_PPDU_ID
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A ppdu counter value that PHY increments for every PPDU
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received. The counter value wraps around
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<legal all>
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*/
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#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000
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#define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16
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#define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000
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/* Description RX_MPDU_END_1_RESERVED_1A
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<legal 0>
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*/
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#define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004
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#define RX_MPDU_END_1_RESERVED_1A_LSB 0
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#define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff
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/* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME
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This bit will be '1' when WEP or TKIP or WAPI key type
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is received for 11ah short frame. Crypto will bypass the
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received packet without decryption to RxOLE after setting
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this bit.
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*/
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#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004
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#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11
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#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800
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/* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP
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Indicates that RX packet is not decrypted as Crypto is
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busy with TX packet processing.
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*/
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#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004
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#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12
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#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000
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/* Description RX_MPDU_END_1_OVERFLOW_ERR
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RXPCU Receive FIFO ran out of space to receive the full
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MPDU. Therefor this MPDU is terminated early and is thus
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corrupted.
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This MPDU will not be ACKed.
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RXPCU might still be able to correctly receive the
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following MPDUs in the PPDU if enough fifo space became
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available in time
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*/
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#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004
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#define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13
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#define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000
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/* Description RX_MPDU_END_1_MPDU_LENGTH_ERR
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Set by RXPCU if the expected MPDU length does not
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correspond with the actually received number of bytes in the
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MPDU.
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*/
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#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004
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#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14
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#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000
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/* Description RX_MPDU_END_1_TKIP_MIC_ERR
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Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
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for this MPDU
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*/
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#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004
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#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15
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#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000
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/* Description RX_MPDU_END_1_DECRYPT_ERR
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Set by RX CRYPTO when CRYPTO detected a decrypt error
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for this MPDU or CRYPTO received an encrypted frame, but did
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not get a valid corresponding key id in the peer entry.
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*/
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#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004
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#define RX_MPDU_END_1_DECRYPT_ERR_LSB 16
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#define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000
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/* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR
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Set by RX CRYPTO when CRYPTO detected an unencrypted
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frame while in the peer entry field
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'All_frames_shall_be_encrypted' is set.
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*/
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#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004
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#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17
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#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000
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/* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO
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Set by RX CRYPTO to indicate that there is a valid PN
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field present in this MPDU
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*/
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#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004
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#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18
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#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000
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/* Description RX_MPDU_END_1_FCS_ERR
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Set by RXPCU when there is an FCS error detected for
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this MPDU
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NOTE that when this field is set, all other (error)
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field settings should be ignored as modules could have made
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wrong decisions based on the corrupted data.
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*/
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#define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004
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#define RX_MPDU_END_1_FCS_ERR_LSB 19
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#define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000
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/* Description RX_MPDU_END_1_MSDU_LENGTH_ERR
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Set by RXOLE when there is an msdu length error detected
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in at least 1 of the MSDUs embedded within the MPDU
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*/
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#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004
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#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20
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#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000
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/* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING
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The ring to which RXDMA0 shall push the frame, assuming
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no MPDU level errors are detected. In case of MPDU level
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errors, RXDMA0 might change the RXDMA0 destination
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<enum 0 rxdma_release_ring > RXDMA0 shall push the
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frame to the Release ring. Effectively this means the frame
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needs to be dropped.
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<enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to
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the FW ring
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<enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to
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the SW ring
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<enum 3 rxdma2reo_ring > RXDMA0 shall push the frame
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to the REO entrance ring
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<legal all>
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*/
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#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004
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#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21
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#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000
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/* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING
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The ring to which RXDMA1 shall push the frame, assuming
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no MPDU level errors are detected. In case of MPDU level
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errors, RXDMA1 might change the RXDMA destination
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<enum 0 rxdma_release_ring > RXDMA1 shall push the
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frame to the Release ring. Effectively this means the frame
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needs to be dropped.
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<enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to
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the FW ring
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<enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to
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the SW ring
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<enum 3 rxdma2reo_ring > RXDMA1 shall push the frame
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to the REO entrance ring
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<legal all>
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*/
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#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004
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#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23
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#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000
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/* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE
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Field provides insight into the decryption performed
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<enum 0 decrypt_ok> Frame had protection enabled and
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decrypted properly
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<enum 1 decrypt_unprotected_frame > Frame is unprotected
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and hence bypassed
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<enum 2 decrypt_data_err > Frame has protection enabled
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and could not be properly decrypted due to MIC/ICV mismatch
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etc.
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<enum 3 decrypt_key_invalid > Frame has protection
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enabled but the key that was required to decrypt this frame
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was not valid
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<enum 4 decrypt_peer_entry_invalid > Frame has
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protection enabled but the key that was required to decrypt
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this frame was not valid
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<enum 5 decrypt_other > Reserved for other indications
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<legal 0 - 5>
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*/
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#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004
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#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25
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#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000
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/* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED
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Frame is received, but RXPCU could not update the
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receive bitmap due to (temporary) fifo contraints.
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<legal all>
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*/
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#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004
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#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28
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#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000
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/* Description RX_MPDU_END_1_RESERVED_1B
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<legal 0>
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*/
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#define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004
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#define RX_MPDU_END_1_RESERVED_1B_LSB 29
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#define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000
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#endif // _RX_MPDU_END_H_
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