0cf22b4439
Add qcn9224 HW headers corresponding. Change-Id: Iaf2dfc04009ffa82b6dd4a40e796148fa99a5744 CRs-Fixed: 3103719
223 lines
10 KiB
C
223 lines
10 KiB
C
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/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _TCL_GSE_CMD_H_
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#define _TCL_GSE_CMD_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_TCL_GSE_CMD 8
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struct tcl_gse_cmd {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t control_buffer_addr_31_0 : 32;
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uint32_t control_buffer_addr_39_32 : 8,
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gse_ctrl : 4,
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gse_sel : 1,
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status_destination_ring_id : 1,
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swap : 1,
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index_search_en : 1,
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cache_set_num : 4,
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reserved_1a : 12;
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uint32_t tcl_cmd_type : 1,
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reserved_2a : 31;
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uint32_t cmd_meta_data_31_0 : 32;
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uint32_t cmd_meta_data_63_32 : 32;
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uint32_t reserved_5a : 32;
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uint32_t reserved_6a : 32;
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uint32_t reserved_7a : 20,
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ring_id : 8,
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looping_count : 4;
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#else
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uint32_t control_buffer_addr_31_0 : 32;
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uint32_t reserved_1a : 12,
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cache_set_num : 4,
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index_search_en : 1,
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swap : 1,
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status_destination_ring_id : 1,
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gse_sel : 1,
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gse_ctrl : 4,
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control_buffer_addr_39_32 : 8;
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uint32_t reserved_2a : 31,
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tcl_cmd_type : 1;
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uint32_t cmd_meta_data_31_0 : 32;
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uint32_t cmd_meta_data_63_32 : 32;
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uint32_t reserved_5a : 32;
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uint32_t reserved_6a : 32;
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uint32_t looping_count : 4,
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ring_id : 8,
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reserved_7a : 20;
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#endif
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};
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7
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#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff
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#define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004
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#define TCL_GSE_CMD_GSE_CTRL_LSB 8
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#define TCL_GSE_CMD_GSE_CTRL_MSB 11
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#define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00
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#define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004
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#define TCL_GSE_CMD_GSE_SEL_LSB 12
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#define TCL_GSE_CMD_GSE_SEL_MSB 12
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#define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000
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#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004
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#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13
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#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13
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#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000
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#define TCL_GSE_CMD_SWAP_OFFSET 0x00000004
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#define TCL_GSE_CMD_SWAP_LSB 14
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#define TCL_GSE_CMD_SWAP_MSB 14
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#define TCL_GSE_CMD_SWAP_MASK 0x00004000
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#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004
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#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15
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#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15
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#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000
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#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004
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#define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16
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#define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19
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#define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000
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#define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004
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#define TCL_GSE_CMD_RESERVED_1A_LSB 20
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#define TCL_GSE_CMD_RESERVED_1A_MSB 31
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#define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000
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#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008
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#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0
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#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0
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#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001
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#define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008
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#define TCL_GSE_CMD_RESERVED_2A_LSB 1
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#define TCL_GSE_CMD_RESERVED_2A_MSB 31
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#define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe
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#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c
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#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0
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#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31
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#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff
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#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010
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#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0
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#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31
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#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff
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#define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014
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#define TCL_GSE_CMD_RESERVED_5A_LSB 0
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#define TCL_GSE_CMD_RESERVED_5A_MSB 31
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#define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff
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#define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018
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#define TCL_GSE_CMD_RESERVED_6A_LSB 0
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#define TCL_GSE_CMD_RESERVED_6A_MSB 31
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#define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff
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#define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c
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#define TCL_GSE_CMD_RESERVED_7A_LSB 0
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#define TCL_GSE_CMD_RESERVED_7A_MSB 19
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#define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff
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#define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c
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#define TCL_GSE_CMD_RING_ID_LSB 20
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#define TCL_GSE_CMD_RING_ID_MSB 27
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#define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000
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#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c
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#define TCL_GSE_CMD_LOOPING_COUNT_LSB 28
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#define TCL_GSE_CMD_LOOPING_COUNT_MSB 31
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#define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000
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#endif
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