50af1eb43b
The change allows for configuring a command DMA window during which the command is triggered. The DMA window must not intersect with the MDP tear check window. Once the command transfer is successful, the trigger control needs to reset to the default DMA trigger specified by the panel. Change-Id: I5485ca1f8e141ed92dc8c77c2daf579634271022 Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
338 lines
12 KiB
C
338 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/errno.h>
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#include "dsi_catalog.h"
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/**
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* dsi_catalog_cmn_init() - catalog init for dsi controller v1.4
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*/
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static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl,
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enum dsi_ctrl_version version)
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{
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/* common functions */
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ctrl->ops.host_setup = dsi_ctrl_hw_cmn_host_setup;
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ctrl->ops.video_engine_en = dsi_ctrl_hw_cmn_video_engine_en;
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ctrl->ops.video_engine_setup = dsi_ctrl_hw_cmn_video_engine_setup;
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ctrl->ops.set_video_timing = dsi_ctrl_hw_cmn_set_video_timing;
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ctrl->ops.set_timing_db = dsi_ctrl_hw_cmn_set_timing_db;
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ctrl->ops.cmd_engine_setup = dsi_ctrl_hw_cmn_cmd_engine_setup;
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ctrl->ops.setup_cmd_stream = dsi_ctrl_hw_cmn_setup_cmd_stream;
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ctrl->ops.ctrl_en = dsi_ctrl_hw_cmn_ctrl_en;
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ctrl->ops.cmd_engine_en = dsi_ctrl_hw_cmn_cmd_engine_en;
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ctrl->ops.phy_sw_reset = dsi_ctrl_hw_cmn_phy_sw_reset;
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ctrl->ops.soft_reset = dsi_ctrl_hw_cmn_soft_reset;
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ctrl->ops.kickoff_command = dsi_ctrl_hw_cmn_kickoff_command;
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ctrl->ops.kickoff_fifo_command = dsi_ctrl_hw_cmn_kickoff_fifo_command;
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ctrl->ops.reset_cmd_fifo = dsi_ctrl_hw_cmn_reset_cmd_fifo;
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ctrl->ops.trigger_command_dma = dsi_ctrl_hw_cmn_trigger_command_dma;
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ctrl->ops.get_interrupt_status = dsi_ctrl_hw_cmn_get_interrupt_status;
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ctrl->ops.get_error_status = dsi_ctrl_hw_cmn_get_error_status;
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ctrl->ops.clear_error_status = dsi_ctrl_hw_cmn_clear_error_status;
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ctrl->ops.clear_interrupt_status =
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dsi_ctrl_hw_cmn_clear_interrupt_status;
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ctrl->ops.enable_status_interrupts =
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dsi_ctrl_hw_cmn_enable_status_interrupts;
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ctrl->ops.enable_error_interrupts =
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dsi_ctrl_hw_cmn_enable_error_interrupts;
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ctrl->ops.video_test_pattern_setup =
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dsi_ctrl_hw_cmn_video_test_pattern_setup;
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ctrl->ops.cmd_test_pattern_setup =
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dsi_ctrl_hw_cmn_cmd_test_pattern_setup;
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ctrl->ops.test_pattern_enable = dsi_ctrl_hw_cmn_test_pattern_enable;
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ctrl->ops.trigger_cmd_test_pattern =
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dsi_ctrl_hw_cmn_trigger_cmd_test_pattern;
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ctrl->ops.clear_phy0_ln_err = dsi_ctrl_hw_dln0_phy_err;
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ctrl->ops.phy_reset_config = dsi_ctrl_hw_cmn_phy_reset_config;
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ctrl->ops.setup_misr = dsi_ctrl_hw_cmn_setup_misr;
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ctrl->ops.collect_misr = dsi_ctrl_hw_cmn_collect_misr;
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ctrl->ops.get_cmd_read_data = dsi_ctrl_hw_cmn_get_cmd_read_data;
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ctrl->ops.clear_rdbk_register = dsi_ctrl_hw_cmn_clear_rdbk_reg;
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ctrl->ops.ctrl_reset = dsi_ctrl_hw_cmn_ctrl_reset;
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ctrl->ops.mask_error_intr = dsi_ctrl_hw_cmn_mask_error_intr;
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ctrl->ops.error_intr_ctrl = dsi_ctrl_hw_cmn_error_intr_ctrl;
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ctrl->ops.get_error_mask = dsi_ctrl_hw_cmn_get_error_mask;
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ctrl->ops.get_hw_version = dsi_ctrl_hw_cmn_get_hw_version;
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ctrl->ops.wait_for_cmd_mode_mdp_idle =
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dsi_ctrl_hw_cmn_wait_for_cmd_mode_mdp_idle;
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ctrl->ops.setup_avr = dsi_ctrl_hw_cmn_setup_avr;
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ctrl->ops.set_continuous_clk = dsi_ctrl_hw_cmn_set_continuous_clk;
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ctrl->ops.wait4dynamic_refresh_done =
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dsi_ctrl_hw_cmn_wait4dynamic_refresh_done;
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ctrl->ops.hs_req_sel = dsi_ctrl_hw_cmn_hs_req_sel;
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switch (version) {
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case DSI_CTRL_VERSION_1_4:
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ctrl->ops.setup_lane_map = dsi_ctrl_hw_14_setup_lane_map;
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ctrl->ops.ulps_ops.ulps_request = dsi_ctrl_hw_cmn_ulps_request;
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ctrl->ops.ulps_ops.ulps_exit = dsi_ctrl_hw_cmn_ulps_exit;
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ctrl->ops.wait_for_lane_idle =
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dsi_ctrl_hw_14_wait_for_lane_idle;
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ctrl->ops.ulps_ops.get_lanes_in_ulps =
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dsi_ctrl_hw_cmn_get_lanes_in_ulps;
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ctrl->ops.clamp_enable = dsi_ctrl_hw_14_clamp_enable;
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ctrl->ops.clamp_disable = dsi_ctrl_hw_14_clamp_disable;
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ctrl->ops.reg_dump_to_buffer =
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dsi_ctrl_hw_14_reg_dump_to_buffer;
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ctrl->ops.schedule_dma_cmd = NULL;
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ctrl->ops.kickoff_command_non_embedded_mode = NULL;
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ctrl->ops.config_clk_gating = NULL;
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ctrl->ops.configure_cmddma_window = NULL;
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ctrl->ops.reset_trig_ctrl = NULL;
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break;
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case DSI_CTRL_VERSION_2_0:
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ctrl->ops.setup_lane_map = dsi_ctrl_hw_20_setup_lane_map;
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ctrl->ops.wait_for_lane_idle =
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dsi_ctrl_hw_20_wait_for_lane_idle;
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ctrl->ops.reg_dump_to_buffer =
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dsi_ctrl_hw_20_reg_dump_to_buffer;
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ctrl->ops.ulps_ops.ulps_request = NULL;
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ctrl->ops.ulps_ops.ulps_exit = NULL;
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ctrl->ops.ulps_ops.get_lanes_in_ulps = NULL;
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ctrl->ops.clamp_enable = NULL;
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ctrl->ops.clamp_disable = NULL;
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ctrl->ops.schedule_dma_cmd = NULL;
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ctrl->ops.kickoff_command_non_embedded_mode = NULL;
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ctrl->ops.config_clk_gating = NULL;
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ctrl->ops.configure_cmddma_window = NULL;
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ctrl->ops.reset_trig_ctrl = NULL;
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break;
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case DSI_CTRL_VERSION_2_2:
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case DSI_CTRL_VERSION_2_3:
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case DSI_CTRL_VERSION_2_4:
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case DSI_CTRL_VERSION_2_5:
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ctrl->ops.phy_reset_config = dsi_ctrl_hw_22_phy_reset_config;
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ctrl->ops.config_clk_gating = dsi_ctrl_hw_22_config_clk_gating;
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ctrl->ops.setup_lane_map = dsi_ctrl_hw_22_setup_lane_map;
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ctrl->ops.wait_for_lane_idle =
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dsi_ctrl_hw_22_wait_for_lane_idle;
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ctrl->ops.reg_dump_to_buffer =
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dsi_ctrl_hw_22_reg_dump_to_buffer;
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ctrl->ops.ulps_ops.ulps_request = dsi_ctrl_hw_cmn_ulps_request;
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ctrl->ops.ulps_ops.ulps_exit = dsi_ctrl_hw_cmn_ulps_exit;
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ctrl->ops.ulps_ops.get_lanes_in_ulps =
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dsi_ctrl_hw_cmn_get_lanes_in_ulps;
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ctrl->ops.clamp_enable = NULL;
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ctrl->ops.clamp_disable = NULL;
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ctrl->ops.schedule_dma_cmd = dsi_ctrl_hw_22_schedule_dma_cmd;
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ctrl->ops.kickoff_command_non_embedded_mode =
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dsi_ctrl_hw_kickoff_non_embedded_mode;
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ctrl->ops.configure_cmddma_window =
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dsi_ctrl_hw_22_configure_cmddma_window;
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ctrl->ops.reset_trig_ctrl =
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dsi_ctrl_hw_22_reset_trigger_controls;
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break;
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default:
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break;
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}
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}
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/**
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* dsi_catalog_ctrl_setup() - return catalog info for dsi controller
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* @ctrl: Pointer to DSI controller hw object.
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* @version: DSI controller version.
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* @index: DSI controller instance ID.
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* @phy_isolation_enabled: DSI controller works isolated from phy.
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* @null_insertion_enabled: DSI controller inserts null packet.
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*
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* This function setups the catalog information in the dsi_ctrl_hw object.
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*
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* return: error code for failure and 0 for success.
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*/
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int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl,
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enum dsi_ctrl_version version, u32 index,
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bool phy_isolation_enabled, bool null_insertion_enabled)
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{
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int rc = 0;
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if (version == DSI_CTRL_VERSION_UNKNOWN ||
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version >= DSI_CTRL_VERSION_MAX) {
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DSI_ERR("Unsupported version: %d\n", version);
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return -ENOTSUPP;
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}
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ctrl->index = index;
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ctrl->null_insertion_enabled = null_insertion_enabled;
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set_bit(DSI_CTRL_VIDEO_TPG, ctrl->feature_map);
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set_bit(DSI_CTRL_CMD_TPG, ctrl->feature_map);
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set_bit(DSI_CTRL_VARIABLE_REFRESH_RATE, ctrl->feature_map);
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set_bit(DSI_CTRL_DYNAMIC_REFRESH, ctrl->feature_map);
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set_bit(DSI_CTRL_DESKEW_CALIB, ctrl->feature_map);
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set_bit(DSI_CTRL_DPHY, ctrl->feature_map);
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switch (version) {
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case DSI_CTRL_VERSION_1_4:
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dsi_catalog_cmn_init(ctrl, version);
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break;
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case DSI_CTRL_VERSION_2_0:
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case DSI_CTRL_VERSION_2_2:
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case DSI_CTRL_VERSION_2_3:
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case DSI_CTRL_VERSION_2_4:
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ctrl->phy_isolation_enabled = phy_isolation_enabled;
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dsi_catalog_cmn_init(ctrl, version);
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break;
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case DSI_CTRL_VERSION_2_5:
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ctrl->widebus_support = true;
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ctrl->phy_isolation_enabled = phy_isolation_enabled;
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dsi_catalog_cmn_init(ctrl, version);
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break;
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default:
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return -ENOTSUPP;
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}
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return rc;
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}
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/**
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* dsi_catalog_phy_2_0_init() - catalog init for DSI PHY 14nm
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*/
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static void dsi_catalog_phy_2_0_init(struct dsi_phy_hw *phy)
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{
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phy->ops.regulator_enable = dsi_phy_hw_v2_0_regulator_enable;
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phy->ops.regulator_disable = dsi_phy_hw_v2_0_regulator_disable;
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phy->ops.enable = dsi_phy_hw_v2_0_enable;
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phy->ops.disable = dsi_phy_hw_v2_0_disable;
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phy->ops.calculate_timing_params =
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dsi_phy_hw_calculate_timing_params;
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phy->ops.phy_idle_on = dsi_phy_hw_v2_0_idle_on;
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phy->ops.phy_idle_off = dsi_phy_hw_v2_0_idle_off;
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phy->ops.calculate_timing_params =
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dsi_phy_hw_calculate_timing_params;
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phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v2_0;
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phy->ops.clamp_ctrl = dsi_phy_hw_v2_0_clamp_ctrl;
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phy->ops.dyn_refresh_ops.dyn_refresh_config =
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dsi_phy_hw_v2_0_dyn_refresh_config;
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phy->ops.dyn_refresh_ops.dyn_refresh_pipe_delay =
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dsi_phy_hw_v2_0_dyn_refresh_pipe_delay;
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phy->ops.dyn_refresh_ops.dyn_refresh_helper =
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dsi_phy_hw_v2_0_dyn_refresh_helper;
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phy->ops.dyn_refresh_ops.cache_phy_timings =
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dsi_phy_hw_v2_0_cache_phy_timings;
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}
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/**
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* dsi_catalog_phy_3_0_init() - catalog init for DSI PHY 10nm
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*/
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static void dsi_catalog_phy_3_0_init(struct dsi_phy_hw *phy)
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{
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phy->ops.regulator_enable = dsi_phy_hw_v3_0_regulator_enable;
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phy->ops.regulator_disable = dsi_phy_hw_v3_0_regulator_disable;
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phy->ops.enable = dsi_phy_hw_v3_0_enable;
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phy->ops.disable = dsi_phy_hw_v3_0_disable;
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phy->ops.calculate_timing_params =
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dsi_phy_hw_calculate_timing_params;
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phy->ops.ulps_ops.wait_for_lane_idle =
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dsi_phy_hw_v3_0_wait_for_lane_idle;
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phy->ops.ulps_ops.ulps_request =
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dsi_phy_hw_v3_0_ulps_request;
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phy->ops.ulps_ops.ulps_exit =
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dsi_phy_hw_v3_0_ulps_exit;
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phy->ops.ulps_ops.get_lanes_in_ulps =
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dsi_phy_hw_v3_0_get_lanes_in_ulps;
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phy->ops.ulps_ops.is_lanes_in_ulps =
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dsi_phy_hw_v3_0_is_lanes_in_ulps;
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phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v3_0;
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phy->ops.clamp_ctrl = dsi_phy_hw_v3_0_clamp_ctrl;
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phy->ops.phy_lane_reset = dsi_phy_hw_v3_0_lane_reset;
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phy->ops.toggle_resync_fifo = dsi_phy_hw_v3_0_toggle_resync_fifo;
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phy->ops.dyn_refresh_ops.dyn_refresh_config =
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dsi_phy_hw_v3_0_dyn_refresh_config;
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phy->ops.dyn_refresh_ops.dyn_refresh_pipe_delay =
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dsi_phy_hw_v3_0_dyn_refresh_pipe_delay;
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phy->ops.dyn_refresh_ops.dyn_refresh_helper =
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dsi_phy_hw_v3_0_dyn_refresh_helper;
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phy->ops.dyn_refresh_ops.cache_phy_timings =
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dsi_phy_hw_v3_0_cache_phy_timings;
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}
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/**
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* dsi_catalog_phy_4_0_init() - catalog init for DSI PHY 7nm
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*/
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static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy)
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{
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phy->ops.regulator_enable = NULL;
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phy->ops.regulator_disable = NULL;
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phy->ops.enable = dsi_phy_hw_v4_0_enable;
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phy->ops.disable = dsi_phy_hw_v4_0_disable;
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phy->ops.calculate_timing_params =
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dsi_phy_hw_calculate_timing_params;
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phy->ops.ulps_ops.wait_for_lane_idle =
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dsi_phy_hw_v4_0_wait_for_lane_idle;
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phy->ops.ulps_ops.ulps_request =
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dsi_phy_hw_v4_0_ulps_request;
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phy->ops.ulps_ops.ulps_exit =
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dsi_phy_hw_v4_0_ulps_exit;
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phy->ops.ulps_ops.get_lanes_in_ulps =
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dsi_phy_hw_v4_0_get_lanes_in_ulps;
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phy->ops.ulps_ops.is_lanes_in_ulps =
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dsi_phy_hw_v4_0_is_lanes_in_ulps;
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phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v4_0;
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phy->ops.phy_lane_reset = dsi_phy_hw_v4_0_lane_reset;
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phy->ops.toggle_resync_fifo = dsi_phy_hw_v4_0_toggle_resync_fifo;
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phy->ops.reset_clk_en_sel = dsi_phy_hw_v4_0_reset_clk_en_sel;
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phy->ops.dyn_refresh_ops.dyn_refresh_config =
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dsi_phy_hw_v4_0_dyn_refresh_config;
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phy->ops.dyn_refresh_ops.dyn_refresh_pipe_delay =
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dsi_phy_hw_v4_0_dyn_refresh_pipe_delay;
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phy->ops.dyn_refresh_ops.dyn_refresh_helper =
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dsi_phy_hw_v4_0_dyn_refresh_helper;
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phy->ops.dyn_refresh_ops.cache_phy_timings =
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dsi_phy_hw_v4_0_cache_phy_timings;
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phy->ops.set_continuous_clk = dsi_phy_hw_v4_0_set_continuous_clk;
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phy->ops.commit_phy_timing = dsi_phy_hw_v4_0_commit_phy_timing;
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}
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/**
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* dsi_catalog_phy_setup() - return catalog info for dsi phy hardware
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* @ctrl: Pointer to DSI PHY hw object.
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* @version: DSI PHY version.
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* @index: DSI PHY instance ID.
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*
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* This function setups the catalog information in the dsi_phy_hw object.
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*
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* return: error code for failure and 0 for success.
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*/
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int dsi_catalog_phy_setup(struct dsi_phy_hw *phy,
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enum dsi_phy_version version,
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u32 index)
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{
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int rc = 0;
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if (version == DSI_PHY_VERSION_UNKNOWN ||
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version >= DSI_PHY_VERSION_MAX) {
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DSI_ERR("Unsupported version: %d\n", version);
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return -ENOTSUPP;
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}
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phy->index = index;
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phy->version = version;
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set_bit(DSI_PHY_DPHY, phy->feature_map);
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dsi_phy_timing_calc_init(phy, version);
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switch (version) {
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case DSI_PHY_VERSION_2_0:
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dsi_catalog_phy_2_0_init(phy);
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break;
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case DSI_PHY_VERSION_3_0:
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dsi_catalog_phy_3_0_init(phy);
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break;
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case DSI_PHY_VERSION_4_0:
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case DSI_PHY_VERSION_4_1:
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case DSI_PHY_VERSION_4_2:
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dsi_catalog_phy_4_0_init(phy);
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break;
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case DSI_PHY_VERSION_0_0_HPM:
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case DSI_PHY_VERSION_0_0_LPM:
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case DSI_PHY_VERSION_1_0:
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default:
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return -ENOTSUPP;
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}
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return rc;
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}
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