e3dd0df678
Added change to handle TxBF standalone sounding CQI data. 1. Define and handle structure to support new TLV for CQI data. 2. API to extract new meta data TLV added for CQI data 3. API to handle processing CQI data. Change-Id: If6e654fc03cc5c150b85bc9af487c58b77d78e1d CRs-Fixed: 3594811
230 lines
7.4 KiB
C
230 lines
7.4 KiB
C
/*
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* Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _WMI_UNIFIED_DBR_PARAM_H_
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#define _WMI_UNIFIED_DBR_PARAM_H_
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#define WMI_HOST_DBR_RING_ADDR_LO_S 0
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#define WMI_HOST_DBR_RING_ADDR_LO_M 0xffffffff
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#define WMI_HOST_DBR_RING_ADDR_LO \
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(WMI_HOST_DBR_RING_ADDR_LO_M << WMI_HOST_DBR_RING_ADDR_LO_S)
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#define WMI_HOST_DBR_RING_ADDR_LO_GET(dword) \
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WMI_HOST_F_MS(dword, WMI_HOST_DBR_RING_ADDR_LO)
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#define WMI_HOST_DBR_RING_ADDR_LO_SET(dword, val) \
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WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_RING_ADDR_LO)
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#define WMI_HOST_DBR_RING_ADDR_HI_S 0
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#define WMI_HOST_DBR_RING_ADDR_HI_M 0xf
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#define WMI_HOST_DBR_RING_ADDR_HI \
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(WMI_HOST_DBR_RING_ADDR_HI_M << WMI_HOST_DBR_RING_ADDR_HI_S)
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#define WMI_HOST_DBR_RING_ADDR_HI_GET(dword) \
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WMI_HOST_F_MS(dword, WMI_HOST_DBR_RING_ADDR_HI)
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#define WMI_HOST_DBR_RING_ADDR_HI_SET(dword, val) \
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WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_RING_ADDR_HI)
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#define WMI_HOST_DBR_DATA_ADDR_LO_S 0
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#define WMI_HOST_DBR_DATA_ADDR_LO_M 0xffffffff
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#define WMI_HOST_DBR_DATA_ADDR_LO \
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(WMI_HOST_DBR_DATA_ADDR_LO_M << WMI_HOST_DBR_DATA_ADDR_LO_S)
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#define WMI_HOST_DBR_DATA_ADDR_LO_GET(dword) \
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WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_LO)
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#define WMI_HOST_DBR_DATA_ADDR_LO_SET(dword, val) \
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WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_LO)
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#define WMI_HOST_DBR_DATA_ADDR_HI_S 0
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#define WMI_HOST_DBR_DATA_ADDR_HI_M 0xf
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#define WMI_HOST_DBR_DATA_ADDR_HI \
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(WMI_HOST_DBR_DATA_ADDR_HI_M << WMI_HOST_DBR_DATA_ADDR_HI_S)
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#define WMI_HOST_DBR_DATA_ADDR_HI_GET(dword) \
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WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_HI)
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#define WMI_HOST_DBR_DATA_ADDR_HI_SET(dword, val) \
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WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_HI)
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#define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_S 12
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#define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_M 0x7ffff
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#define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA \
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(WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_M << \
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WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_S)
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#define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_GET(dword) \
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WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA)
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#define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_SET(dword, val) \
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WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA)
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#define WMI_HOST_MAX_NUM_CHAINS 8
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/**
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* struct direct_buf_rx_rsp: direct buffer rx response structure
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*
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* @pdev_id: Index of the pdev for which response is received
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* @mod_id: Index of the module for which respone is received
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* @num_buf_release_entry: Number of buffers released through event
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* @num_meta_data_entry: Number of meta data released
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* @num_cv_meta_data_entry: Number of cv meta data released
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* @num_cqi_meta_data_entry: Number of cqi meta data released
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* @dbr_entries: Pointer to direct buffer rx entry struct
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*/
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struct direct_buf_rx_rsp {
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uint32_t pdev_id;
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uint32_t mod_id;
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uint32_t num_buf_release_entry;
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uint32_t num_meta_data_entry;
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uint32_t num_cv_meta_data_entry;
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uint32_t num_cqi_meta_data_entry;
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struct direct_buf_rx_entry *dbr_entries;
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};
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/**
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* struct direct_buf_rx_cfg_req: direct buffer rx config request structure
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*
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* @pdev_id: Index of the pdev for which response is received
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* @mod_id: Index of the module for which respone is received
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* @base_paddr_lo: Lower 32bits of ring base address
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* @base_paddr_hi: Higher 32bits of ring base address
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* @head_idx_paddr_lo: Lower 32bits of head idx register address
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* @head_idx_paddr_hi: Higher 32bits of head idx register address
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* @tail_idx_paddr_lo: Lower 32bits of tail idx register address
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* @tail_idx_paddr_hi: Higher 32bits of tail idx register address
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* @buf_size: Size of the buffer for each pointer in the ring
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* @num_elems: Number of pointers allocated and part of the source ring
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* @event_timeout_ms:
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* @num_resp_per_event:
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*/
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struct direct_buf_rx_cfg_req {
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uint32_t pdev_id;
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uint32_t mod_id;
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uint32_t base_paddr_lo;
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uint32_t base_paddr_hi;
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uint32_t head_idx_paddr_lo;
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uint32_t head_idx_paddr_hi;
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uint32_t tail_idx_paddr_hi;
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uint32_t tail_idx_paddr_lo;
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uint32_t buf_size;
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uint32_t num_elems;
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uint32_t event_timeout_ms;
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uint32_t num_resp_per_event;
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};
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/**
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* struct direct_buf_rx_metadata: direct buffer metadata
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*
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* @noisefloor: noisefloor
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* @reset_delay: reset delay
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* @cfreq1: center frequency 1
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* @cfreq2: center frequency 2
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* @ch_width: channel width
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*/
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struct direct_buf_rx_metadata {
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int32_t noisefloor[WMI_HOST_MAX_NUM_CHAINS];
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uint32_t reset_delay;
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uint32_t cfreq1;
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uint32_t cfreq2;
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uint32_t ch_width;
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};
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/**
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* struct direct_buf_rx_cv_metadata: direct buffer metadata for TxBF CV upload
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*
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* @is_valid: Set cv metadata is valid,
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* false if sw_peer_id is invalid or FCS error
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* @fb_type: Feedback type, 0 for SU 1 for MU
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* @asnr_len: Average SNR length
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* @asnr_offset: Average SNR offset
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* @dsnr_len: Delta SNR length
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* @dsnr_offset: Delta SNR offset
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* @peer_mac: Peer macaddr
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* @fb_params: Feedback params, [1:0] Nc [3:2] nss_num
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*/
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struct direct_buf_rx_cv_metadata {
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uint32_t is_valid;
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uint32_t fb_type;
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uint16_t asnr_len;
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uint16_t asnr_offset;
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uint16_t dsnr_len;
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uint16_t dsnr_offset;
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struct qdf_mac_addr peer_mac;
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uint32_t fb_params;
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};
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/*
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* In CQI data buffer, each user CQI data will be stored
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* in a fixed offset of 64 locations from each other,
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* and each location corresponds to 64-bit length.
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*/
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#define CQI_USER_DATA_LENGTH (64 * 8)
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#define CQI_USER_DATA_OFFSET(idx) ((idx) * CQI_USER_DATA_LENGTH)
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#define MAX_NUM_CQI_USERS 3
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/*
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* struct direct_buf_rx_cqi_per_user_info: Per user CQI data
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*
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* @asnr_len: Average SNR length
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* @asnr_offset: Average SNR offset
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* @fb_params: Feedback params, [1:0] Nc
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* @peer_mac: Peer macaddr
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*/
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struct direct_buf_rx_cqi_per_user_info {
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uint16_t asnr_len;
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uint16_t asnr_offset;
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uint32_t fb_params;
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struct qdf_mac_addr peer_mac;
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};
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/**
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* struct direct_buf_rx_cqi_metadata: direct buffer metadata for CQI upload
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*
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* @num_users: Number of user info in a metadta buffer
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* @is_valid: Set cqi metadata is valid,
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* false if sw_peer_id is invalid or FCS error
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* @fb_type: Feedback type, 0 for SU 1 for MU 2 for CQI
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* @fb_params: Feedback params
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* [0] is_valid0
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* [1] is_valid1
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* [2] is_valid2
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* [4:3] Nc0
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* [5:4] Nc1
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* [6:5] Nc2
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* @user_info: Per user CQI info
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*/
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struct direct_buf_rx_cqi_metadata {
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uint8_t num_users;
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uint32_t is_valid;
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uint32_t fb_type;
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uint32_t fb_params;
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struct direct_buf_rx_cqi_per_user_info user_info[MAX_NUM_CQI_USERS];
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};
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/**
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* struct direct_buf_rx_entry: direct buffer rx release entry structure
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*
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* @paddr_lo: LSB 32-bits of the buffer
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* @paddr_hi: MSB 32-bits of the buffer
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* @len: Length of the buffer
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*/
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struct direct_buf_rx_entry {
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uint32_t paddr_lo;
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uint32_t paddr_hi;
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uint32_t len;
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};
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#endif /* _WMI_UNIFIED_DBR_PARAM_H_ */
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