3709853456
This change brings msm display driver including sde, dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel project. It is first source code snapshot from base kernel project. Change-Id: Iec864c064ce5ea04e170f24414c728684002f284 Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
243 sor
10 KiB
C
243 sor
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DSI_CATALOG_H_
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#define _DSI_CATALOG_H_
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#include "dsi_ctrl_hw.h"
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#include "dsi_phy_hw.h"
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/**
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* dsi_catalog_ctrl_setup() - return catalog info for dsi controller
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* @ctrl: Pointer to DSI controller hw object.
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* @version: DSI controller version.
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* @index: DSI controller instance ID.
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* @phy_isolation_enabled: DSI controller works isolated from phy.
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* @null_insertion_enabled: DSI controller inserts null packet.
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*
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* This function setups the catalog information in the dsi_ctrl_hw object.
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*
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* return: error code for failure and 0 for success.
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*/
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int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl,
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enum dsi_ctrl_version version, u32 index,
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bool phy_isolation_enabled, bool null_insertion_enabled);
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/**
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* dsi_catalog_phy_setup() - return catalog info for dsi phy hardware
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* @phy: Pointer to DSI PHY hw object.
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* @version: DSI PHY version.
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* @index: DSI PHY instance ID.
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*
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* This function setups the catalog information in the dsi_phy_hw object.
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*
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* return: error code for failure and 0 for success.
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*/
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int dsi_catalog_phy_setup(struct dsi_phy_hw *phy,
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enum dsi_phy_version version,
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u32 index);
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/**
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* dsi_phy_timing_calc_init() - initialize info for DSI PHY timing calculations
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* @phy: Pointer to DSI PHY hw object.
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* @version: DSI PHY version.
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*
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* This function setups the catalog information in the dsi_phy_hw object.
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*
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* return: error code for failure and 0 for success.
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*/
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int dsi_phy_timing_calc_init(struct dsi_phy_hw *phy,
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enum dsi_phy_version version);
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/**
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* dsi_phy_hw_calculate_timing_params() - DSI PHY timing parameter calculations
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* @phy: Pointer to DSI PHY hw object.
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* @mode: DSI mode information.
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* @host: DSI host configuration.
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* @timing: DSI phy lane configurations.
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*
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* This function setups the catalog information in the dsi_phy_hw object.
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*
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* return: error code for failure and 0 for success.
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*/
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int dsi_phy_hw_calculate_timing_params(struct dsi_phy_hw *phy,
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struct dsi_mode_info *mode,
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struct dsi_host_common_cfg *host,
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struct dsi_phy_per_lane_cfgs *timing);
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/* Definitions for 14nm PHY hardware driver */
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void dsi_phy_hw_v2_0_regulator_enable(struct dsi_phy_hw *phy,
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struct dsi_phy_per_lane_cfgs *cfg);
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void dsi_phy_hw_v2_0_regulator_disable(struct dsi_phy_hw *phy);
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void dsi_phy_hw_v2_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
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void dsi_phy_hw_v2_0_disable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
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void dsi_phy_hw_v2_0_idle_on(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
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void dsi_phy_hw_v2_0_idle_off(struct dsi_phy_hw *phy);
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int dsi_phy_hw_timing_val_v2_0(struct dsi_phy_per_lane_cfgs *timing_cfg,
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u32 *timing_val, u32 size);
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void dsi_phy_hw_v2_0_clamp_ctrl(struct dsi_phy_hw *phy, bool enable);
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/* Definitions for 10nm PHY hardware driver */
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void dsi_phy_hw_v3_0_regulator_enable(struct dsi_phy_hw *phy,
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struct dsi_phy_per_lane_cfgs *cfg);
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void dsi_phy_hw_v3_0_regulator_disable(struct dsi_phy_hw *phy);
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void dsi_phy_hw_v3_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
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void dsi_phy_hw_v3_0_disable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
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int dsi_phy_hw_v3_0_wait_for_lane_idle(struct dsi_phy_hw *phy, u32 lanes);
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void dsi_phy_hw_v3_0_ulps_request(struct dsi_phy_hw *phy,
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struct dsi_phy_cfg *cfg, u32 lanes);
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void dsi_phy_hw_v3_0_ulps_exit(struct dsi_phy_hw *phy,
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struct dsi_phy_cfg *cfg, u32 lanes);
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u32 dsi_phy_hw_v3_0_get_lanes_in_ulps(struct dsi_phy_hw *phy);
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bool dsi_phy_hw_v3_0_is_lanes_in_ulps(u32 lanes, u32 ulps_lanes);
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int dsi_phy_hw_timing_val_v3_0(struct dsi_phy_per_lane_cfgs *timing_cfg,
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u32 *timing_val, u32 size);
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void dsi_phy_hw_v3_0_clamp_ctrl(struct dsi_phy_hw *phy, bool enable);
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int dsi_phy_hw_v3_0_lane_reset(struct dsi_phy_hw *phy);
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void dsi_phy_hw_v3_0_toggle_resync_fifo(struct dsi_phy_hw *phy);
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/* Definitions for 7nm PHY hardware driver */
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void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
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void dsi_phy_hw_v4_0_disable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
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int dsi_phy_hw_v4_0_wait_for_lane_idle(struct dsi_phy_hw *phy, u32 lanes);
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void dsi_phy_hw_v4_0_ulps_request(struct dsi_phy_hw *phy,
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struct dsi_phy_cfg *cfg, u32 lanes);
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void dsi_phy_hw_v4_0_ulps_exit(struct dsi_phy_hw *phy,
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struct dsi_phy_cfg *cfg, u32 lanes);
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u32 dsi_phy_hw_v4_0_get_lanes_in_ulps(struct dsi_phy_hw *phy);
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bool dsi_phy_hw_v4_0_is_lanes_in_ulps(u32 lanes, u32 ulps_lanes);
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int dsi_phy_hw_timing_val_v4_0(struct dsi_phy_per_lane_cfgs *timing_cfg,
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u32 *timing_val, u32 size);
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int dsi_phy_hw_v4_0_lane_reset(struct dsi_phy_hw *phy);
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void dsi_phy_hw_v4_0_toggle_resync_fifo(struct dsi_phy_hw *phy);
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void dsi_phy_hw_v4_0_reset_clk_en_sel(struct dsi_phy_hw *phy);
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/* DSI controller common ops */
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u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);
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void dsi_ctrl_hw_cmn_debug_bus(struct dsi_ctrl_hw *ctrl, u32 *entries,
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u32 size);
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void dsi_ctrl_hw_cmn_clear_interrupt_status(struct dsi_ctrl_hw *ctrl, u32 ints);
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void dsi_ctrl_hw_cmn_enable_status_interrupts(struct dsi_ctrl_hw *ctrl,
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u32 ints);
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u64 dsi_ctrl_hw_cmn_get_error_status(struct dsi_ctrl_hw *ctrl);
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void dsi_ctrl_hw_cmn_clear_error_status(struct dsi_ctrl_hw *ctrl, u64 errors);
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void dsi_ctrl_hw_cmn_enable_error_interrupts(struct dsi_ctrl_hw *ctrl,
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u64 errors);
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void dsi_ctrl_hw_cmn_video_test_pattern_setup(struct dsi_ctrl_hw *ctrl,
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enum dsi_test_pattern type,
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u32 init_val);
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void dsi_ctrl_hw_cmn_cmd_test_pattern_setup(struct dsi_ctrl_hw *ctrl,
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enum dsi_test_pattern type,
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u32 init_val,
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u32 stream_id);
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void dsi_ctrl_hw_cmn_test_pattern_enable(struct dsi_ctrl_hw *ctrl, bool enable);
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void dsi_ctrl_hw_cmn_trigger_cmd_test_pattern(struct dsi_ctrl_hw *ctrl,
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u32 stream_id);
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void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,
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struct dsi_host_common_cfg *config);
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void dsi_ctrl_hw_cmn_video_engine_en(struct dsi_ctrl_hw *ctrl, bool on);
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void dsi_ctrl_hw_cmn_video_engine_setup(struct dsi_ctrl_hw *ctrl,
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struct dsi_host_common_cfg *common_cfg,
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struct dsi_video_engine_cfg *cfg);
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void dsi_ctrl_hw_cmn_setup_avr(struct dsi_ctrl_hw *ctrl, bool enable);
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void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl,
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struct dsi_mode_info *mode);
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void dsi_ctrl_hw_cmn_set_timing_db(struct dsi_ctrl_hw *ctrl,
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bool enable);
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void dsi_ctrl_hw_cmn_cmd_engine_setup(struct dsi_ctrl_hw *ctrl,
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struct dsi_host_common_cfg *common_cfg,
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struct dsi_cmd_engine_cfg *cfg);
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void dsi_ctrl_hw_cmn_ctrl_en(struct dsi_ctrl_hw *ctrl, bool on);
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void dsi_ctrl_hw_cmn_cmd_engine_en(struct dsi_ctrl_hw *ctrl, bool on);
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void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,
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struct dsi_mode_info *mode,
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u32 h_stride,
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u32 vc_id,
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struct dsi_rect *roi);
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void dsi_ctrl_hw_cmn_phy_sw_reset(struct dsi_ctrl_hw *ctrl);
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void dsi_ctrl_hw_cmn_soft_reset(struct dsi_ctrl_hw *ctrl);
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void dsi_ctrl_hw_cmn_setup_misr(struct dsi_ctrl_hw *ctrl,
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enum dsi_op_mode panel_mode,
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bool enable, u32 frame_count);
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u32 dsi_ctrl_hw_cmn_collect_misr(struct dsi_ctrl_hw *ctrl,
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enum dsi_op_mode panel_mode);
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void dsi_ctrl_hw_cmn_kickoff_command(struct dsi_ctrl_hw *ctrl,
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struct dsi_ctrl_cmd_dma_info *cmd,
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u32 flags);
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void dsi_ctrl_hw_cmn_kickoff_fifo_command(struct dsi_ctrl_hw *ctrl,
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struct dsi_ctrl_cmd_dma_fifo_info *cmd,
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u32 flags);
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void dsi_ctrl_hw_cmn_reset_cmd_fifo(struct dsi_ctrl_hw *ctrl);
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void dsi_ctrl_hw_cmn_trigger_command_dma(struct dsi_ctrl_hw *ctrl);
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void dsi_ctrl_hw_dln0_phy_err(struct dsi_ctrl_hw *ctrl);
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void dsi_ctrl_hw_cmn_phy_reset_config(struct dsi_ctrl_hw *ctrl,
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bool enable);
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void dsi_ctrl_hw_22_phy_reset_config(struct dsi_ctrl_hw *ctrl,
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bool enable);
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u32 dsi_ctrl_hw_cmn_get_cmd_read_data(struct dsi_ctrl_hw *ctrl,
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u8 *rd_buf,
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u32 read_offset,
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u32 rx_byte,
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u32 pkt_size, u32 *hw_read_cnt);
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void dsi_ctrl_hw_cmn_clear_rdbk_reg(struct dsi_ctrl_hw *ctrl);
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void dsi_ctrl_hw_22_schedule_dma_cmd(struct dsi_ctrl_hw *ctrl, int line_on);
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int dsi_ctrl_hw_cmn_ctrl_reset(struct dsi_ctrl_hw *ctrl,
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int mask);
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void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx,
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bool en);
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void dsi_ctrl_hw_cmn_error_intr_ctrl(struct dsi_ctrl_hw *ctrl, bool en);
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u32 dsi_ctrl_hw_cmn_get_error_mask(struct dsi_ctrl_hw *ctrl);
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u32 dsi_ctrl_hw_cmn_get_hw_version(struct dsi_ctrl_hw *ctrl);
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int dsi_ctrl_hw_cmn_wait_for_cmd_mode_mdp_idle(struct dsi_ctrl_hw *ctrl);
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/* Definitions specific to 1.4 DSI controller hardware */
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int dsi_ctrl_hw_14_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes);
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void dsi_ctrl_hw_14_setup_lane_map(struct dsi_ctrl_hw *ctrl,
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struct dsi_lane_map *lane_map);
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void dsi_ctrl_hw_cmn_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes);
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void dsi_ctrl_hw_cmn_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes);
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u32 dsi_ctrl_hw_cmn_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl);
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void dsi_ctrl_hw_14_clamp_enable(struct dsi_ctrl_hw *ctrl,
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u32 lanes,
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bool enable_ulps);
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void dsi_ctrl_hw_14_clamp_disable(struct dsi_ctrl_hw *ctrl,
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u32 lanes,
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bool disable_ulps);
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ssize_t dsi_ctrl_hw_14_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,
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char *buf,
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u32 size);
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/* Definitions specific to 2.0 DSI controller hardware */
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void dsi_ctrl_hw_20_setup_lane_map(struct dsi_ctrl_hw *ctrl,
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struct dsi_lane_map *lane_map);
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int dsi_ctrl_hw_20_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes);
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ssize_t dsi_ctrl_hw_20_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,
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char *buf,
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u32 size);
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void dsi_ctrl_hw_kickoff_non_embedded_mode(struct dsi_ctrl_hw *ctrl,
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struct dsi_ctrl_cmd_dma_info *cmd,
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u32 flags);
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/* Definitions specific to 2.2 DSI controller hardware */
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bool dsi_ctrl_hw_22_get_cont_splash_status(struct dsi_ctrl_hw *ctrl);
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void dsi_ctrl_hw_22_config_clk_gating(struct dsi_ctrl_hw *ctrl, bool enable,
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enum dsi_clk_gate_type clk_selection);
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void dsi_ctrl_hw_cmn_set_continuous_clk(struct dsi_ctrl_hw *ctrl, bool enable);
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#endif /* _DSI_CATALOG_H_ */
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