33fce952a9
Link descriptor were getting freed by the pointer of the previous freed link descriptor. This patch fixes by copying the address of the current in a local descriptor info and using it to free the current. Change-Id: I95e137ba5b1f0ad21b0e6fb39f6671e1d5b65ba6 CRs-Fixed: 2577624
366 lines
12 KiB
C
366 lines
12 KiB
C
/*
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* Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HAL_HW_INTERNAL_H_
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#define _HAL_HW_INTERNAL_H_
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#include "qdf_types.h"
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#include "qdf_lock.h"
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#include "qdf_mem.h"
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#include "rx_msdu_link.h"
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#include "rx_reo_queue.h"
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#include "rx_reo_queue_ext.h"
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#include "wcss_seq_hwiobase.h"
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#include "tlv_hdr.h"
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#include "tlv_tag_def.h"
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#include "reo_destination_ring.h"
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#include "reo_reg_seq_hwioreg.h"
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#include "reo_entrance_ring.h"
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#include "reo_get_queue_stats.h"
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#include "reo_get_queue_stats_status.h"
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#include "tcl_data_cmd.h"
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#include "tcl_gse_cmd.h"
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#include "tcl_status_ring.h"
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#include "mac_tcl_reg_seq_hwioreg.h"
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#include "ce_src_desc.h"
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#include "ce_stat_desc.h"
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#ifdef QCA_WIFI_QCA6490
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#include "wfss_ce_channel_dst_reg_seq_hwioreg.h"
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#else
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#include "wfss_ce_reg_seq_hwioreg.h"
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#endif /* QCA_WIFI_QCA6490 */
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#include "wbm_link_descriptor_ring.h"
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#include "wbm_reg_seq_hwioreg.h"
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#include "wbm_buffer_ring.h"
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#include "wbm_release_ring.h"
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#include "rx_msdu_desc_info.h"
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#include "rx_mpdu_start.h"
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#include "rx_mpdu_end.h"
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#include "rx_msdu_start.h"
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#include "rx_msdu_end.h"
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#include "rx_attention.h"
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#include "rx_ppdu_start.h"
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#include "rx_ppdu_start_user_info.h"
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#include "rx_ppdu_end_user_stats.h"
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#include "rx_ppdu_end_user_stats_ext.h"
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#include "rx_mpdu_desc_info.h"
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#include "rxpcu_ppdu_end_info.h"
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#include "phyrx_he_sig_a_su.h"
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#include "phyrx_he_sig_a_mu_dl.h"
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#if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX)
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#include "phyrx_he_sig_a_mu_ul.h"
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#endif
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#include "phyrx_he_sig_b1_mu.h"
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#include "phyrx_he_sig_b2_mu.h"
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#include "phyrx_he_sig_b2_ofdma.h"
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#include "phyrx_l_sig_a.h"
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#include "phyrx_l_sig_b.h"
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#include "phyrx_vht_sig_a.h"
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#include "phyrx_ht_sig.h"
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#include "tx_msdu_extension.h"
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#include "receive_rssi_info.h"
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#include "phyrx_pkt_end.h"
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#include "phyrx_rssi_legacy.h"
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#include "wcss_version.h"
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#include "rx_msdu_link.h"
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#include "hal_internal.h"
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#define HAL_SRNG_REO_EXCEPTION HAL_SRNG_REO2SW1
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#define HAL_SRNG_REO_ALTERNATE_SELECT 0x7
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#define HAL_NON_QOS_TID 16
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/* TODO: Check if the following can be provided directly by HW headers */
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#define SRNG_LOOP_CNT_MASK REO_DESTINATION_RING_15_LOOPING_COUNT_MASK
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#define SRNG_LOOP_CNT_LSB REO_DESTINATION_RING_15_LOOPING_COUNT_LSB
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/* HAL Macro to get the buffer info size */
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#define HAL_RX_BUFFINFO_NUM_DWORDS NUM_OF_DWORDS_BUFFER_ADDR_INFO
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#define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS 100 /* milliseconds */
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#define HAL_DEFAULT_VO_REO_TIMEOUT_MS 40 /* milliseconds */
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#define HAL_DESC_SET_FIELD(_desc, _word, _fld, _value) do { \
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((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] &= \
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~(_word ## _ ## _fld ## _MASK); \
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((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] |= \
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((_value) << _word ## _ ## _fld ## _LSB); \
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} while (0)
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#define HAL_SM(_reg, _fld, _val) \
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(((_val) << (_reg ## _ ## _fld ## _SHFT)) & \
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(_reg ## _ ## _fld ## _BMSK))
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#define HAL_MS(_reg, _fld, _val) \
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(((_val) & (_reg ## _ ## _fld ## _BMSK)) >> \
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(_reg ## _ ## _fld ## _SHFT))
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#define HAL_REG_WRITE(_soc, _reg, _value) \
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hal_write32_mb(_soc, (_reg), (_value))
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/* Check register writing result */
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#define HAL_REG_WRITE_CONFIRM(_soc, _reg, _value) \
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hal_write32_mb_confirm(_soc, (_reg), (_value))
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#define HAL_REG_READ(_soc, _offset) \
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hal_read32_mb(_soc, (_offset))
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#define WBM_IDLE_DESC_LIST 1
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/**
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* Common SRNG register access macros:
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* The SRNG registers are distributed across various UMAC and LMAC HW blocks,
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* but the register group and format is exactly same for all rings, with some
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* difference between producer rings (these are 'producer rings' with respect
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* to HW and referred as 'destination rings' in SW) and consumer rings (these
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* are 'consumer rings' with respect to HW and
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* referred as 'source rings' in SW).
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* The following macros provide uniform access to all SRNG rings.
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*/
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/* SRNG registers are split among two groups R0 and R2 and following
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* definitions identify the group to which each register belongs to
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*/
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#define R0_INDEX 0
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#define R2_INDEX 1
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#define HWREG_INDEX(_reg_group) _reg_group ## _ ## INDEX
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/* Registers in R0 group */
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#define BASE_LSB_GROUP R0
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#define BASE_MSB_GROUP R0
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#define ID_GROUP R0
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#define STATUS_GROUP R0
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#define MISC_GROUP R0
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#define HP_ADDR_LSB_GROUP R0
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#define HP_ADDR_MSB_GROUP R0
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#define PRODUCER_INT_SETUP_GROUP R0
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#define PRODUCER_INT_STATUS_GROUP R0
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#define PRODUCER_FULL_COUNTER_GROUP R0
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#define MSI1_BASE_LSB_GROUP R0
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#define MSI1_BASE_MSB_GROUP R0
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#define MSI1_DATA_GROUP R0
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#define HP_TP_SW_OFFSET_GROUP R0
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#define TP_ADDR_LSB_GROUP R0
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#define TP_ADDR_MSB_GROUP R0
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#define CONSUMER_INT_SETUP_IX0_GROUP R0
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#define CONSUMER_INT_SETUP_IX1_GROUP R0
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#define CONSUMER_INT_STATUS_GROUP R0
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#define CONSUMER_EMPTY_COUNTER_GROUP R0
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#define CONSUMER_PREFETCH_TIMER_GROUP R0
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#define CONSUMER_PREFETCH_STATUS_GROUP R0
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/* Registers in R2 group */
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#define HP_GROUP R2
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#define TP_GROUP R2
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/**
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* Register definitions for all SRNG based rings are same, except few
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* differences between source (HW consumer) and destination (HW producer)
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* registers. Following macros definitions provide generic access to all
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* SRNG based rings.
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* For source rings, we will use the register/field definitions of SW2TCL1
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* ring defined in the HW header file mac_tcl_reg_seq_hwioreg.h. To setup
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* individual fields, SRNG_SM macros should be used with fields specified
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* using SRNG_SRC_FLD(<register>, <field>), Register writes should be done
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* using SRNG_SRC_REG_WRITE(<hal_srng>, <register>, <value>).
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* Similarly for destination rings we will use definitions of REO2SW1 ring
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* defined in the register reo_destination_ring.h. To setup individual
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* fields SRNG_SM macros should be used with fields specified using
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* SRNG_DST_FLD(<register>, <field>). Register writes should be done using
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* SRNG_DST_REG_WRITE(<hal_srng>, <register>, <value>).
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*/
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#define SRNG_DST_REG_OFFSET(_reg, _reg_group) \
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HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg##_ADDR(0)
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#define SRNG_SRC_REG_OFFSET(_reg, _reg_group) \
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HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg ## _ADDR(0)
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#define _SRNG_DST_FLD(_reg_group, _reg_fld) \
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HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg_fld
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#define _SRNG_SRC_FLD(_reg_group, _reg_fld) \
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HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg_fld
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#define _SRNG_FLD(_reg_group, _reg_fld, _dir) \
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_SRNG_ ## _dir ## _FLD(_reg_group, _reg_fld)
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#define SRNG_DST_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, DST)
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#define SRNG_SRC_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, SRC)
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#define SRNG_SRC_R0_START_OFFSET SRNG_SRC_REG_OFFSET(BASE_LSB, R0)
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#define SRNG_DST_R0_START_OFFSET SRNG_DST_REG_OFFSET(BASE_LSB, R0)
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#define SRNG_SRC_R2_START_OFFSET SRNG_SRC_REG_OFFSET(HP, R2)
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#define SRNG_DST_R2_START_OFFSET SRNG_DST_REG_OFFSET(HP, R2)
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#define SRNG_SRC_START_OFFSET(_reg_group) \
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SRNG_SRC_ ## _reg_group ## _START_OFFSET
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#define SRNG_DST_START_OFFSET(_reg_group) \
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SRNG_DST_ ## _reg_group ## _START_OFFSET
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#define SRNG_REG_ADDR(_srng, _reg, _reg_group, _dir) \
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((_srng)->hwreg_base[HWREG_INDEX(_reg_group)] + \
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((_srng)->hal_soc->hal_hw_reg_offset[_dir ## _ ##_reg]))
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#define CALCULATE_REG_OFFSET(_dir, _reg, _reg_group) \
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(SRNG_ ## _dir ## _REG_OFFSET(_reg, _reg_group) - \
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SRNG_ ## _dir ## _START_OFFSET(_reg_group))
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#define REG_OFFSET(_dir, _reg) \
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CALCULATE_REG_OFFSET(_dir, _reg, _reg ## _GROUP)
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#define SRNG_DST_ADDR(_srng, _reg) \
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SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, DST)
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#define SRNG_SRC_ADDR(_srng, _reg) \
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SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, SRC)
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#define SRNG_REG_WRITE(_srng, _reg, _value, _dir) \
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hal_write_address_32_mb(_srng->hal_soc, \
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SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value))
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#define SRNG_REG_READ(_srng, _reg, _dir) \
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hal_read_address_32_mb(_srng->hal_soc, \
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SRNG_ ## _dir ## _ADDR(_srng, _reg))
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#define SRNG_SRC_REG_WRITE(_srng, _reg, _value) \
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SRNG_REG_WRITE(_srng, _reg, _value, SRC)
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#define SRNG_DST_REG_WRITE(_srng, _reg, _value) \
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SRNG_REG_WRITE(_srng, _reg, _value, DST)
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#define SRNG_SRC_REG_READ(_srng, _reg) \
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SRNG_REG_READ(_srng, _reg, SRC)
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#define SRNG_DST_REG_READ(_srng, _reg) \
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SRNG_REG_READ(_srng, _reg, DST)
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#define _SRNG_FM(_reg_fld) _reg_fld ## _BMSK
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#define _SRNG_FS(_reg_fld) _reg_fld ## _SHFT
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#define SRNG_SM(_reg_fld, _val) \
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(((_val) << _SRNG_FS(_reg_fld)) & _SRNG_FM(_reg_fld))
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#define SRNG_MS(_reg_fld, _val) \
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(((_val) & _SRNG_FM(_reg_fld)) >> _SRNG_FS(_reg_fld))
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#define SRNG_MAX_SIZE_DWORDS \
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(SRNG_MS(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 0xffffffff))
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/**
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* HW ring configuration table to identify hardware ring attributes like
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* register addresses, number of rings, ring entry size etc., for each type
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* of SRNG ring.
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*
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* Currently there is just one HW ring table, but there could be multiple
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* configurations in future based on HW variants from the same wifi3.0 family
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* and hence need to be attached with hal_soc based on HW type
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*/
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#define HAL_SRNG_CONFIG(_hal_soc, _ring_type) \
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(&_hal_soc->hw_srng_table[_ring_type])
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enum SRNG_REGISTERS {
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DST_HP = 0,
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DST_TP,
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DST_ID,
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DST_MISC,
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DST_HP_ADDR_LSB,
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DST_HP_ADDR_MSB,
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DST_MSI1_BASE_LSB,
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DST_MSI1_BASE_MSB,
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DST_MSI1_DATA,
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DST_BASE_LSB,
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DST_BASE_MSB,
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DST_PRODUCER_INT_SETUP,
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SRC_HP,
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SRC_TP,
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SRC_ID,
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SRC_MISC,
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SRC_TP_ADDR_LSB,
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SRC_TP_ADDR_MSB,
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SRC_MSI1_BASE_LSB,
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SRC_MSI1_BASE_MSB,
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SRC_MSI1_DATA,
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SRC_BASE_LSB,
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SRC_BASE_MSB,
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SRC_CONSUMER_INT_SETUP_IX0,
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SRC_CONSUMER_INT_SETUP_IX1,
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};
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/**
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* hal_set_link_desc_addr - Setup link descriptor in a buffer_addr_info
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* HW structure
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*
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* @desc: Descriptor entry (from WBM_IDLE_LINK ring)
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* @cookie: SW cookie for the buffer/descriptor
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* @link_desc_paddr: Physical address of link descriptor entry
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*
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*/
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static inline void hal_set_link_desc_addr(void *desc, uint32_t cookie,
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qdf_dma_addr_t link_desc_paddr)
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{
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uint32_t *buf_addr = (uint32_t *)desc;
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HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0,
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link_desc_paddr & 0xffffffff);
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HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
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(uint64_t)link_desc_paddr >> 32);
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HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER,
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WBM_IDLE_DESC_LIST);
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HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE,
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cookie);
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}
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/**
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* hal_get_reo_qdesc_size - Get size of reo queue descriptor
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*
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* @hal_soc: Opaque HAL SOC handle
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* @ba_window_size: BlockAck window size
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* @tid: TID number
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*
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*/
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static inline
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uint32_t hal_get_reo_qdesc_size(hal_soc_handle_t hal_soc_hdl,
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uint32_t ba_window_size, int tid)
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{
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/* Return descriptor size corresponding to window size of 2 since
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* we set ba_window_size to 2 while setting up REO descriptors as
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* a WAR to get 2k jump exception aggregates are received without
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* a BA session.
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*/
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if (ba_window_size <= 1) {
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if (tid != HAL_NON_QOS_TID)
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return sizeof(struct rx_reo_queue) +
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sizeof(struct rx_reo_queue_ext);
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else
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return sizeof(struct rx_reo_queue);
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}
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if (ba_window_size <= 105)
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return sizeof(struct rx_reo_queue) +
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sizeof(struct rx_reo_queue_ext);
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if (ba_window_size <= 210)
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return sizeof(struct rx_reo_queue) +
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(2 * sizeof(struct rx_reo_queue_ext));
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return sizeof(struct rx_reo_queue) +
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(3 * sizeof(struct rx_reo_queue_ext));
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}
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#endif /* _HAL_HW_INTERNAL_H_ */
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