3709853456
This change brings msm display driver including sde, dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel project. It is first source code snapshot from base kernel project. Change-Id: Iec864c064ce5ea04e170f24414c728684002f284 Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
549 行
13 KiB
C
549 行
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/clk/msm-clk-provider.h>
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#include <linux/clk/msm-clk.h>
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#include <linux/workqueue.h>
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#include <linux/clk/msm-clock-generic.h>
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#include <dt-bindings/clock/msm-clocks-8996.h>
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#include "pll_drv.h"
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#include "dsi_pll.h"
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#include "dsi_pll_8996.h"
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#define VCO_DELAY_USEC 1
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static struct dsi_pll_db pll_db[DSI_PLL_NUM];
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static const struct clk_ops n2_clk_src_ops;
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static const struct clk_ops shadow_n2_clk_src_ops;
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static const struct clk_ops byte_clk_src_ops;
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static const struct clk_ops post_n1_div_clk_src_ops;
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static const struct clk_ops shadow_post_n1_div_clk_src_ops;
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static const struct clk_ops clk_ops_gen_mux_dsi;
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/* Op structures */
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static const struct clk_ops clk_ops_dsi_vco = {
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.set_rate = pll_vco_set_rate_8996,
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.round_rate = pll_vco_round_rate_8996,
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.handoff = pll_vco_handoff_8996,
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.prepare = pll_vco_prepare_8996,
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.unprepare = pll_vco_unprepare_8996,
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};
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static struct clk_div_ops post_n1_div_ops = {
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.set_div = post_n1_div_set_div,
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.get_div = post_n1_div_get_div,
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};
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static struct clk_div_ops n2_div_ops = { /* hr_oclk3 */
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.set_div = n2_div_set_div,
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.get_div = n2_div_get_div,
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};
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static struct clk_mux_ops mdss_byte_mux_ops = {
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.set_mux_sel = set_mdss_byte_mux_sel_8996,
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.get_mux_sel = get_mdss_byte_mux_sel_8996,
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};
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static struct clk_mux_ops mdss_pixel_mux_ops = {
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.set_mux_sel = set_mdss_pixel_mux_sel_8996,
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.get_mux_sel = get_mdss_pixel_mux_sel_8996,
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};
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/* Shadow ops for dynamic refresh */
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static const struct clk_ops clk_ops_shadow_dsi_vco = {
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.set_rate = shadow_pll_vco_set_rate_8996,
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.round_rate = pll_vco_round_rate_8996,
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.handoff = shadow_pll_vco_handoff_8996,
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};
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static struct clk_div_ops shadow_post_n1_div_ops = {
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.set_div = post_n1_div_set_div,
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};
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static struct clk_div_ops shadow_n2_div_ops = {
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.set_div = shadow_n2_div_set_div,
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};
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static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
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.ref_clk_rate = 19200000UL,
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.min_rate = 1300000000UL,
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.max_rate = 2600000000UL,
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.pll_en_seq_cnt = 1,
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.pll_enable_seqs[0] = dsi_pll_enable_seq_8996,
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.c = {
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.dbg_name = "dsi0pll_vco_clk_8996",
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.ops = &clk_ops_dsi_vco,
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CLK_INIT(dsi0pll_vco_clk.c),
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},
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};
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static struct dsi_pll_vco_clk dsi0pll_shadow_vco_clk = {
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.ref_clk_rate = 19200000u,
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.min_rate = 1300000000u,
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.max_rate = 2600000000u,
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.c = {
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.dbg_name = "dsi0pll_shadow_vco_clk",
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.ops = &clk_ops_shadow_dsi_vco,
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CLK_INIT(dsi0pll_shadow_vco_clk.c),
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},
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};
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static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
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.ref_clk_rate = 19200000UL,
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.min_rate = 1300000000UL,
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.max_rate = 2600000000UL,
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.pll_en_seq_cnt = 1,
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.pll_enable_seqs[0] = dsi_pll_enable_seq_8996,
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.c = {
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.dbg_name = "dsi1pll_vco_clk_8996",
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.ops = &clk_ops_dsi_vco,
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CLK_INIT(dsi1pll_vco_clk.c),
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},
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};
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static struct dsi_pll_vco_clk dsi1pll_shadow_vco_clk = {
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.ref_clk_rate = 19200000u,
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.min_rate = 1300000000u,
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.max_rate = 2600000000u,
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.pll_en_seq_cnt = 1,
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.pll_enable_seqs[0] = dsi_pll_enable_seq_8996,
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.c = {
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.dbg_name = "dsi1pll_shadow_vco_clk",
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.ops = &clk_ops_shadow_dsi_vco,
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CLK_INIT(dsi1pll_shadow_vco_clk.c),
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},
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};
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static struct div_clk dsi0pll_post_n1_div_clk = {
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.data = {
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.max_div = 15,
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.min_div = 1,
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},
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.ops = &post_n1_div_ops,
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.c = {
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.parent = &dsi0pll_vco_clk.c,
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.dbg_name = "dsi0pll_post_n1_div_clk",
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.ops = &post_n1_div_clk_src_ops,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi0pll_post_n1_div_clk.c),
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},
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};
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static struct div_clk dsi0pll_shadow_post_n1_div_clk = {
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.data = {
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.max_div = 15,
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.min_div = 1,
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},
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.ops = &shadow_post_n1_div_ops,
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.c = {
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.parent = &dsi0pll_shadow_vco_clk.c,
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.dbg_name = "dsi0pll_shadow_post_n1_div_clk",
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.ops = &shadow_post_n1_div_clk_src_ops,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi0pll_shadow_post_n1_div_clk.c),
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},
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};
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static struct div_clk dsi1pll_post_n1_div_clk = {
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.data = {
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.max_div = 15,
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.min_div = 1,
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},
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.ops = &post_n1_div_ops,
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.c = {
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.parent = &dsi1pll_vco_clk.c,
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.dbg_name = "dsi1pll_post_n1_div_clk",
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.ops = &post_n1_div_clk_src_ops,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi1pll_post_n1_div_clk.c),
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},
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};
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static struct div_clk dsi1pll_shadow_post_n1_div_clk = {
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.data = {
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.max_div = 15,
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.min_div = 1,
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},
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.ops = &shadow_post_n1_div_ops,
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.c = {
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.parent = &dsi1pll_shadow_vco_clk.c,
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.dbg_name = "dsi1pll_shadow_post_n1_div_clk",
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.ops = &shadow_post_n1_div_clk_src_ops,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi1pll_shadow_post_n1_div_clk.c),
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},
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};
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static struct div_clk dsi0pll_n2_div_clk = {
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.data = {
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.max_div = 15,
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.min_div = 1,
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},
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.ops = &n2_div_ops,
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.c = {
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.parent = &dsi0pll_post_n1_div_clk.c,
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.dbg_name = "dsi0pll_n2_div_clk",
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.ops = &n2_clk_src_ops,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi0pll_n2_div_clk.c),
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},
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};
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static struct div_clk dsi0pll_shadow_n2_div_clk = {
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.data = {
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.max_div = 15,
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.min_div = 1,
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},
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.ops = &shadow_n2_div_ops,
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.c = {
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.parent = &dsi0pll_shadow_post_n1_div_clk.c,
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.dbg_name = "dsi0pll_shadow_n2_div_clk",
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.ops = &shadow_n2_clk_src_ops,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi0pll_shadow_n2_div_clk.c),
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},
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};
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static struct div_clk dsi1pll_n2_div_clk = {
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.data = {
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.max_div = 15,
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.min_div = 1,
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},
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.ops = &n2_div_ops,
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.c = {
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.parent = &dsi1pll_post_n1_div_clk.c,
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.dbg_name = "dsi1pll_n2_div_clk",
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.ops = &n2_clk_src_ops,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi1pll_n2_div_clk.c),
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},
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};
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static struct div_clk dsi1pll_shadow_n2_div_clk = {
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.data = {
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.max_div = 15,
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.min_div = 1,
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},
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.ops = &shadow_n2_div_ops,
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.c = {
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.parent = &dsi1pll_shadow_post_n1_div_clk.c,
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.dbg_name = "dsi1pll_shadow_n2_div_clk",
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.ops = &shadow_n2_clk_src_ops,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi1pll_shadow_n2_div_clk.c),
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},
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};
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static struct div_clk dsi0pll_pixel_clk_src = {
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.data = {
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.div = 2,
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.min_div = 2,
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.max_div = 2,
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},
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.c = {
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.parent = &dsi0pll_n2_div_clk.c,
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.dbg_name = "dsi0pll_pixel_clk_src",
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.ops = &clk_ops_div,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi0pll_pixel_clk_src.c),
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},
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};
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static struct div_clk dsi0pll_shadow_pixel_clk_src = {
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.data = {
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.div = 2,
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.min_div = 2,
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.max_div = 2,
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},
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.c = {
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.parent = &dsi0pll_shadow_n2_div_clk.c,
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.dbg_name = "dsi0pll_shadow_pixel_clk_src",
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.ops = &clk_ops_div,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi0pll_shadow_pixel_clk_src.c),
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},
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};
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static struct div_clk dsi1pll_pixel_clk_src = {
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.data = {
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.div = 2,
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.min_div = 2,
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.max_div = 2,
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},
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.c = {
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.parent = &dsi1pll_n2_div_clk.c,
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.dbg_name = "dsi1pll_pixel_clk_src",
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.ops = &clk_ops_div,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi1pll_pixel_clk_src.c),
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},
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};
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static struct div_clk dsi1pll_shadow_pixel_clk_src = {
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.data = {
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.div = 2,
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.min_div = 2,
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.max_div = 2,
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},
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.c = {
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.parent = &dsi1pll_shadow_n2_div_clk.c,
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.dbg_name = "dsi1pll_shadow_pixel_clk_src",
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.ops = &clk_ops_div,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi1pll_shadow_pixel_clk_src.c),
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},
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};
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static struct mux_clk dsi0pll_pixel_clk_mux = {
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.num_parents = 2,
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.parents = (struct clk_src[]) {
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{&dsi0pll_pixel_clk_src.c, 0},
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{&dsi0pll_shadow_pixel_clk_src.c, 1},
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},
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.ops = &mdss_pixel_mux_ops,
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.c = {
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.parent = &dsi0pll_pixel_clk_src.c,
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.dbg_name = "dsi0pll_pixel_clk_mux",
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.ops = &clk_ops_gen_mux_dsi,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi0pll_pixel_clk_mux.c),
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}
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};
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static struct mux_clk dsi1pll_pixel_clk_mux = {
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.num_parents = 2,
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.parents = (struct clk_src[]) {
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{&dsi1pll_pixel_clk_src.c, 0},
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{&dsi1pll_shadow_pixel_clk_src.c, 1},
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},
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.ops = &mdss_pixel_mux_ops,
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.c = {
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.parent = &dsi1pll_pixel_clk_src.c,
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.dbg_name = "dsi1pll_pixel_clk_mux",
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.ops = &clk_ops_gen_mux_dsi,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi1pll_pixel_clk_mux.c),
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}
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};
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static struct div_clk dsi0pll_byte_clk_src = {
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.data = {
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.div = 8,
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.min_div = 8,
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.max_div = 8,
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},
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.c = {
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.parent = &dsi0pll_post_n1_div_clk.c,
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.dbg_name = "dsi0pll_byte_clk_src",
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.ops = &clk_ops_div,
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CLK_INIT(dsi0pll_byte_clk_src.c),
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},
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};
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static struct div_clk dsi0pll_shadow_byte_clk_src = {
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.data = {
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.div = 8,
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.min_div = 8,
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.max_div = 8,
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},
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.c = {
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.parent = &dsi0pll_shadow_post_n1_div_clk.c,
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.dbg_name = "dsi0pll_shadow_byte_clk_src",
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.ops = &clk_ops_div,
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CLK_INIT(dsi0pll_shadow_byte_clk_src.c),
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},
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};
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static struct div_clk dsi1pll_byte_clk_src = {
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.data = {
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.div = 8,
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.min_div = 8,
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.max_div = 8,
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},
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.c = {
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.parent = &dsi1pll_post_n1_div_clk.c,
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.dbg_name = "dsi1pll_byte_clk_src",
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.ops = &clk_ops_div,
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CLK_INIT(dsi1pll_byte_clk_src.c),
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},
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};
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static struct div_clk dsi1pll_shadow_byte_clk_src = {
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.data = {
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.div = 8,
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.min_div = 8,
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.max_div = 8,
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},
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.c = {
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.parent = &dsi1pll_shadow_post_n1_div_clk.c,
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.dbg_name = "dsi1pll_shadow_byte_clk_src",
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.ops = &clk_ops_div,
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CLK_INIT(dsi1pll_shadow_byte_clk_src.c),
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},
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};
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static struct mux_clk dsi0pll_byte_clk_mux = {
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.num_parents = 2,
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.parents = (struct clk_src[]) {
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{&dsi0pll_byte_clk_src.c, 0},
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{&dsi0pll_shadow_byte_clk_src.c, 1},
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},
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.ops = &mdss_byte_mux_ops,
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.c = {
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.parent = &dsi0pll_byte_clk_src.c,
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.dbg_name = "dsi0pll_byte_clk_mux",
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.ops = &clk_ops_gen_mux_dsi,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi0pll_byte_clk_mux.c),
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}
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};
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static struct mux_clk dsi1pll_byte_clk_mux = {
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.num_parents = 2,
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.parents = (struct clk_src[]) {
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{&dsi1pll_byte_clk_src.c, 0},
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{&dsi1pll_shadow_byte_clk_src.c, 1},
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},
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.ops = &mdss_byte_mux_ops,
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.c = {
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.parent = &dsi1pll_byte_clk_src.c,
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.dbg_name = "dsi1pll_byte_clk_mux",
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.ops = &clk_ops_gen_mux_dsi,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi1pll_byte_clk_mux.c),
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}
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};
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static struct clk_lookup mdss_dsi_pllcc_8996[] = {
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CLK_LIST(dsi0pll_byte_clk_mux),
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CLK_LIST(dsi0pll_byte_clk_src),
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CLK_LIST(dsi0pll_pixel_clk_mux),
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CLK_LIST(dsi0pll_pixel_clk_src),
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CLK_LIST(dsi0pll_n2_div_clk),
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CLK_LIST(dsi0pll_post_n1_div_clk),
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CLK_LIST(dsi0pll_vco_clk),
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CLK_LIST(dsi0pll_shadow_byte_clk_src),
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CLK_LIST(dsi0pll_shadow_pixel_clk_src),
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CLK_LIST(dsi0pll_shadow_n2_div_clk),
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CLK_LIST(dsi0pll_shadow_post_n1_div_clk),
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CLK_LIST(dsi0pll_shadow_vco_clk),
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};
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static struct clk_lookup mdss_dsi_pllcc_8996_1[] = {
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CLK_LIST(dsi1pll_byte_clk_mux),
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CLK_LIST(dsi1pll_byte_clk_src),
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CLK_LIST(dsi1pll_pixel_clk_mux),
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CLK_LIST(dsi1pll_pixel_clk_src),
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CLK_LIST(dsi1pll_n2_div_clk),
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CLK_LIST(dsi1pll_post_n1_div_clk),
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CLK_LIST(dsi1pll_vco_clk),
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CLK_LIST(dsi1pll_shadow_byte_clk_src),
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CLK_LIST(dsi1pll_shadow_pixel_clk_src),
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CLK_LIST(dsi1pll_shadow_n2_div_clk),
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CLK_LIST(dsi1pll_shadow_post_n1_div_clk),
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CLK_LIST(dsi1pll_shadow_vco_clk),
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};
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|
|
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int dsi_pll_clock_register_8996(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
|
|
{
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int rc = 0, ndx;
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int const ssc_freq_default = 31500; /* default h/w recommended value */
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int const ssc_ppm_default = 5000; /* default h/w recommended value */
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struct dsi_pll_db *pdb;
|
|
|
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if (pll_res->index >= DSI_PLL_NUM) {
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pr_err("pll ndx=%d is NOT supported\n", pll_res->index);
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|
return -EINVAL;
|
|
}
|
|
|
|
ndx = pll_res->index;
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|
pdb = &pll_db[ndx];
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|
pll_res->priv = pdb;
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|
pdb->pll = pll_res;
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|
ndx++;
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|
ndx %= DSI_PLL_NUM;
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|
pdb->next = &pll_db[ndx];
|
|
|
|
/* Set clock source operations */
|
|
|
|
/* hr_oclk3, pixel */
|
|
n2_clk_src_ops = clk_ops_slave_div;
|
|
n2_clk_src_ops.prepare = mdss_pll_div_prepare;
|
|
|
|
shadow_n2_clk_src_ops = clk_ops_slave_div;
|
|
|
|
/* hr_ockl2, byte, vco pll */
|
|
post_n1_div_clk_src_ops = clk_ops_div;
|
|
post_n1_div_clk_src_ops.prepare = mdss_pll_div_prepare;
|
|
|
|
shadow_post_n1_div_clk_src_ops = clk_ops_div;
|
|
|
|
byte_clk_src_ops = clk_ops_div;
|
|
byte_clk_src_ops.prepare = mdss_pll_div_prepare;
|
|
|
|
clk_ops_gen_mux_dsi = clk_ops_gen_mux;
|
|
clk_ops_gen_mux_dsi.round_rate = parent_round_rate;
|
|
clk_ops_gen_mux_dsi.set_rate = parent_set_rate;
|
|
|
|
if (pll_res->ssc_en) {
|
|
if (!pll_res->ssc_freq)
|
|
pll_res->ssc_freq = ssc_freq_default;
|
|
if (!pll_res->ssc_ppm)
|
|
pll_res->ssc_ppm = ssc_ppm_default;
|
|
}
|
|
|
|
/* Set client data to mux, div and vco clocks. */
|
|
if (pll_res->index == DSI_PLL_1) {
|
|
dsi1pll_byte_clk_src.priv = pll_res;
|
|
dsi1pll_pixel_clk_src.priv = pll_res;
|
|
dsi1pll_post_n1_div_clk.priv = pll_res;
|
|
dsi1pll_n2_div_clk.priv = pll_res;
|
|
dsi1pll_vco_clk.priv = pll_res;
|
|
|
|
dsi1pll_shadow_byte_clk_src.priv = pll_res;
|
|
dsi1pll_shadow_pixel_clk_src.priv = pll_res;
|
|
dsi1pll_shadow_post_n1_div_clk.priv = pll_res;
|
|
dsi1pll_shadow_n2_div_clk.priv = pll_res;
|
|
dsi1pll_shadow_vco_clk.priv = pll_res;
|
|
|
|
pll_res->vco_delay = VCO_DELAY_USEC;
|
|
rc = of_msm_clock_register(pdev->dev.of_node,
|
|
mdss_dsi_pllcc_8996_1,
|
|
ARRAY_SIZE(mdss_dsi_pllcc_8996_1));
|
|
} else {
|
|
dsi0pll_byte_clk_src.priv = pll_res;
|
|
dsi0pll_pixel_clk_src.priv = pll_res;
|
|
dsi0pll_post_n1_div_clk.priv = pll_res;
|
|
dsi0pll_n2_div_clk.priv = pll_res;
|
|
dsi0pll_vco_clk.priv = pll_res;
|
|
|
|
dsi0pll_shadow_byte_clk_src.priv = pll_res;
|
|
dsi0pll_shadow_pixel_clk_src.priv = pll_res;
|
|
dsi0pll_shadow_post_n1_div_clk.priv = pll_res;
|
|
dsi0pll_shadow_n2_div_clk.priv = pll_res;
|
|
dsi0pll_shadow_vco_clk.priv = pll_res;
|
|
|
|
pll_res->vco_delay = VCO_DELAY_USEC;
|
|
rc = of_msm_clock_register(pdev->dev.of_node,
|
|
mdss_dsi_pllcc_8996,
|
|
ARRAY_SIZE(mdss_dsi_pllcc_8996));
|
|
}
|
|
|
|
if (!rc) {
|
|
pr_info("Registered DSI PLL ndx=%d clocks successfully\n",
|
|
pll_res->index);
|
|
}
|
|
|
|
return rc;
|
|
}
|