a855ce2006
Bring in E3.R38 HW header files for kiwi, as the final set of header files from emulation drop. In addition cleanup header files w.r.t comments, add appropriate copyright header. Change-Id: I3cee05e506c4171f8641193a0f12456f5cfaf890 CRs-Fixed: 2850521
378 lines
17 KiB
C
378 lines
17 KiB
C
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/*
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _TCL_DATA_CMD_H_
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#define _TCL_DATA_CMD_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "buffer_addr_info.h"
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#define NUM_OF_DWORDS_TCL_DATA_CMD 8
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struct tcl_data_cmd {
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struct buffer_addr_info buf_addr_info;
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uint32_t tcl_cmd_type : 1,
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buf_or_ext_desc_type : 1,
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bank_id : 6,
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tx_notify_frame : 3,
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header_length_read_sel : 1,
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buffer_timestamp : 19,
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buffer_timestamp_valid : 1;
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uint32_t reserved_3a : 16,
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tcl_cmd_number : 16;
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uint32_t data_length : 16,
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ipv4_checksum_en : 1,
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udp_over_ipv4_checksum_en : 1,
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udp_over_ipv6_checksum_en : 1,
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tcp_over_ipv4_checksum_en : 1,
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tcp_over_ipv6_checksum_en : 1,
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to_fw : 1,
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reserved_4a : 1,
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packet_offset : 9;
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uint32_t hlos_tid_overwrite : 1,
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flow_override_enable : 1,
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who_classify_info_sel : 2,
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hlos_tid : 4,
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flow_override : 1,
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pmac_id : 2,
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reserved_5a : 13,
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vdev_id : 8;
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uint32_t search_index : 20,
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cache_set_num : 4,
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index_lookup_override : 1,
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reserved_6a : 7;
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uint32_t reserved_7a : 20,
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ring_id : 8,
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looping_count : 4;
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};
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#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
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#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
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#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
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#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
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#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
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#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
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#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
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#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
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#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
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#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
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#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
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#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
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#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
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#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
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#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
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#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
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#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008
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#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0
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#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0
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#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001
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#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008
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#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1
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#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1
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#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002
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#define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008
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#define TCL_DATA_CMD_BANK_ID_LSB 2
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#define TCL_DATA_CMD_BANK_ID_MSB 7
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#define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc
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#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008
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#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8
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#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10
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#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700
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#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008
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#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11
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#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11
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#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800
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#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008
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#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12
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#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30
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#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000
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#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008
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#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31
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#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31
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#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000
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#define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c
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#define TCL_DATA_CMD_RESERVED_3A_LSB 0
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#define TCL_DATA_CMD_RESERVED_3A_MSB 15
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#define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff
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#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c
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#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16
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#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31
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#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000
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#define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010
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#define TCL_DATA_CMD_DATA_LENGTH_LSB 0
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#define TCL_DATA_CMD_DATA_LENGTH_MSB 15
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#define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff
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#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010
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#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16
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#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16
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#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000
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#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010
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#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17
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#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17
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#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000
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#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010
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#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18
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#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18
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#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000
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#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010
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#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19
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#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19
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#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000
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#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010
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#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20
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#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20
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#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000
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#define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010
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#define TCL_DATA_CMD_TO_FW_LSB 21
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#define TCL_DATA_CMD_TO_FW_MSB 21
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#define TCL_DATA_CMD_TO_FW_MASK 0x00200000
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#define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010
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#define TCL_DATA_CMD_RESERVED_4A_LSB 22
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#define TCL_DATA_CMD_RESERVED_4A_MSB 22
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#define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000
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#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010
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#define TCL_DATA_CMD_PACKET_OFFSET_LSB 23
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#define TCL_DATA_CMD_PACKET_OFFSET_MSB 31
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#define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000
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#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014
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#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0
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#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0
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#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001
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#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014
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#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1
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#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1
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#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002
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#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014
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#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2
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#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3
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#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c
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#define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014
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#define TCL_DATA_CMD_HLOS_TID_LSB 4
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#define TCL_DATA_CMD_HLOS_TID_MSB 7
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#define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0
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#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014
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#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8
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#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8
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#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100
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#define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014
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#define TCL_DATA_CMD_PMAC_ID_LSB 9
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#define TCL_DATA_CMD_PMAC_ID_MSB 10
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#define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600
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#define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014
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#define TCL_DATA_CMD_RESERVED_5A_LSB 11
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#define TCL_DATA_CMD_RESERVED_5A_MSB 23
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#define TCL_DATA_CMD_RESERVED_5A_MASK 0x00fff800
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#define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014
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#define TCL_DATA_CMD_VDEV_ID_LSB 24
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#define TCL_DATA_CMD_VDEV_ID_MSB 31
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#define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000
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#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018
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#define TCL_DATA_CMD_SEARCH_INDEX_LSB 0
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#define TCL_DATA_CMD_SEARCH_INDEX_MSB 19
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#define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff
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#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018
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#define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20
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#define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23
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#define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000
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#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018
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#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24
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#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24
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#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000
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#define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018
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#define TCL_DATA_CMD_RESERVED_6A_LSB 25
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#define TCL_DATA_CMD_RESERVED_6A_MSB 31
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#define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000
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#define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c
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#define TCL_DATA_CMD_RESERVED_7A_LSB 0
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#define TCL_DATA_CMD_RESERVED_7A_MSB 19
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#define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff
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#define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c
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#define TCL_DATA_CMD_RING_ID_LSB 20
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#define TCL_DATA_CMD_RING_ID_MSB 27
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#define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000
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#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c
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#define TCL_DATA_CMD_LOOPING_COUNT_LSB 28
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#define TCL_DATA_CMD_LOOPING_COUNT_MSB 31
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#define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000
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#endif
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