c88b38afa1
Currently RBM id is not assigned properly for RX buffers in Rhine architecture. Fix this by assigning RBM id during soc attach in Rhine. Change-Id: I8f3a781bfaf81366417107f4bd3da61b142ca1e2 CRs-Fixed: 3573342
359 lines
11 KiB
C
359 lines
11 KiB
C
/*
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* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HAL_RH_TX_H_
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#define _HAL_RH_TX_H_
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enum hal_rh_tx_ret_buf_manager {
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HAL_RH_WBM_SW0_BM_ID = 3,
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HAL_RH_WBM_SW1_BM_ID = 4,
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HAL_RH_WBM_SW2_BM_ID = 5,
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HAL_RH_WBM_SW3_BM_ID = 6,
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HAL_RH_WBM_SW4_BM_ID = 7,
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};
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/*---------------------------------------------------------------------------
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* Function declarations and documentation
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* ---------------------------------------------------------------------------
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*/
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/*---------------------------------------------------------------------------
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* TCL Descriptor accessor APIs
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* ---------------------------------------------------------------------------
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*/
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/**
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* hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor
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* @hal_soc_hdl: HAL SOC handle
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* @desc: Handle to Tx Descriptor
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* @paddr: Physical Address
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* @pool_id: Return Buffer Manager ID
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* @desc_id: Descriptor ID
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* @type: 0 - Address points to a MSDU buffer
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* 1 - Address points to MSDU extension descriptor
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*
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* Return: void
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*/
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static inline
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void hal_tx_desc_set_buf_addr(hal_soc_handle_t hal_soc_hdl, void *desc,
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dma_addr_t paddr,
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uint8_t pool_id, uint32_t desc_id,
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uint8_t type)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id,
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desc_id, type);
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}
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/**
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* hal_tx_desc_set_lmac_id - Set the lmac_id value
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* @hal_soc_hdl: HAL SOC handle
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* @desc: Handle to Tx Descriptor
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* @lmac_id: mac Id to ast matching
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* b00 – mac 0
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* b01 – mac 1
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* b10 – mac 2
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* b11 – all macs (legacy HK way)
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_lmac_id(hal_soc_handle_t hal_soc_hdl,
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void *desc, uint8_t lmac_id)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id);
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}
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/**
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* hal_tx_desc_set_search_type - Set the search type value
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* @hal_soc_hdl: HAL SOC handle
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* @desc: Handle to Tx Descriptor
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* @search_type: search type
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* 0 – Normal search
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* 1 – Index based address search
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* 2 – Index based flow search
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_search_type(hal_soc_handle_t hal_soc_hdl,
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void *desc,
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uint8_t search_type)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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hal_soc->ops->hal_tx_desc_set_search_type(desc, search_type);
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}
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/**
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* hal_tx_desc_set_search_index - Set the search index value
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* @hal_soc_hdl: HAL SOC handle
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* @desc: Handle to Tx Descriptor
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* @search_index: The index that will be used for index based address or
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* flow search. The field is valid when 'search_type' is
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* 1 0r 2
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_search_index(hal_soc_handle_t hal_soc_hdl,
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void *desc,
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uint32_t search_index)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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hal_soc->ops->hal_tx_desc_set_search_index(desc, search_index);
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}
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/**
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* hal_tx_desc_set_cache_set_num - Set the cache-set-num value
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* @hal_soc_hdl: HAL SOC handle
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* @desc: Handle to Tx Descriptor
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* @cache_num: Cache set number that should be used to cache the index
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* based search results, for address and flow search.
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* This value should be equal to LSB four bits of the hash value
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* of match data, in case of search index points to an entry
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* which may be used in content based search also. The value can
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* be anything when the entry pointed by search index will not be
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* used for content based search.
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl,
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void *desc,
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uint8_t cache_num)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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hal_soc->ops->hal_tx_desc_set_cache_set_num(desc, cache_num);
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}
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/**
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* hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor
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* @desc: Handle to Tx Descriptor
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* @data_length: MSDU length in case of direct descriptor.
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* Length of link extension descriptor in case of Link extension
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* descriptor.Includes the length of Metadata
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* Return: None
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*/
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static inline void hal_tx_desc_set_buf_length(void *desc,
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uint16_t data_length)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |=
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HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length);
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}
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/**
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* hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor
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* @desc: Handle to Tx Descriptor
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* @offset: Packet offset from Metadata in case of direct buffer descriptor.
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_buf_offset(void *desc,
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uint8_t offset)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |=
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HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset);
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}
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/**
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* hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor
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* @desc: Handle to Tx Descriptor
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* @encap_type: Encapsulation that HW will perform
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*
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* Return: void
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*
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*/
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static inline void hal_tx_desc_set_encap_type(void *desc,
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enum hal_tx_encap_type encap_type)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |=
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HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type);
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}
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/**
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* hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor
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* @desc: Handle to Tx Descriptor
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* @type: Encrypt Type
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_encrypt_type(void *desc,
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enum hal_tx_encrypt_type type)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |=
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HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type);
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}
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/**
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* hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags
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* @desc: Handle to Tx Descriptor
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* @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_addr_search_flags(void *desc,
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uint8_t flags)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |=
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HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1));
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HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |=
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HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1));
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}
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/**
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* hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags
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* Tx Descriptor for MSDU_buffer type
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* @desc: Handle to Tx Descriptor
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* @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits)
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_l4_checksum_en(void *desc,
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uint8_t en)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |=
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(HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) |
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HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) |
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HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) |
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HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en));
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}
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/**
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* hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in
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* Tx Descriptor for MSDU_buffer type
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* @desc: Handle to Tx Descriptor
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* @en: ipv4 checksum enable flags
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_l3_checksum_en(void *desc,
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uint8_t en)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |=
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HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en);
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}
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/**
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* hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor
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* @desc:Handle to Tx Descriptor
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* @metadata: Metadata to be sent to Firmware
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_fw_metadata(void *desc,
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uint16_t metadata)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |=
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HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata);
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}
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/**
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* hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor.
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* @desc:Handle to Tx Descriptor
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* @to_fw: if set, Forward packet to FW along with classification result
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |=
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HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw);
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}
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/**
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* hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor
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* @hal_soc_hdl: hal soc handle
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* @desc: Handle to Tx Descriptor
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* @en: For raw WiFi frames, this indicates transmission to a mesh STA,
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* enabling the interpretation of the 'Mesh Control Present' bit
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* (bit 8) of QoS Control (otherwise this bit is ignored),
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* For native WiFi frames, this indicates that a 'Mesh Control' field
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* is present between the header and the LLC.
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_mesh_en(hal_soc_handle_t hal_soc_hdl,
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void *desc, uint8_t en)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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hal_soc->ops->hal_tx_desc_set_mesh_en(desc, en);
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}
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/**
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* hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in
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* frame) to be used for Tx Frame
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* @desc: Handle to Tx Descriptor
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* @hlos_tid: HLOS TID
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_hlos_tid(void *desc,
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uint8_t hlos_tid)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |=
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HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid);
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HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |=
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HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1);
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}
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/**
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* hal_tx_desc_clear - Clear the HW descriptor entry
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* @hw_desc: Hardware descriptor to be cleared
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*
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* Return: void
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*/
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static inline void hal_tx_desc_clear(void *hw_desc)
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{
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qdf_mem_set(hw_desc + sizeof(struct tlv_32_hdr),
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HAL_TX_DESC_LEN_BYTES, 0);
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}
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/**
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* hal_tx_desc_sync - Commit the descriptor to Hardware
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* @hal_tx_desc_cached: Cached descriptor that software maintains
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* @hw_desc: Hardware descriptor to be updated
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*/
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static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
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void *hw_desc)
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{
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qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)),
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hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
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}
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/*---------------------------------------------------------------------------
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* WBM Descriptor accessor APIs for Tx completions
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*---------------------------------------------------------------------------
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*/
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/**
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* hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring
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*
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* Return: BM ID for first tx completion ring
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*/
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static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void)
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{
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return HAL_RH_WBM_SW0_BM_ID;
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}
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#endif /* _HAL_RH_TX_H_ */
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