2d29d9afc7
Add HW header files to bring-in support for Peach WIFI. Change-Id: I73ee0a2c4f22a90013b441ecd5e666d673d77ae0 CRs-Fixed: 3580269
205 lines
14 KiB
C
205 lines
14 KiB
C
/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _EXPECTED_RESPONSE_H_
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#define _EXPECTED_RESPONSE_H_
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#define NUM_OF_DWORDS_EXPECTED_RESPONSE 5
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struct expected_response {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t tx_ad2_31_0 : 32;
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uint32_t tx_ad2_47_32 : 16,
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expected_response_type : 5,
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response_to_response : 3,
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su_ba_user_number : 1,
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response_info_part2_required : 1,
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transmitted_bssid_check_en : 1,
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reserved_1 : 5;
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uint32_t ndp_sta_partial_aid_2_8_0 : 11,
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reserved_2 : 10,
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ndp_sta_partial_aid1_8_0 : 11;
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uint32_t ast_index : 16,
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capture_ack_ba_sounding : 1,
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capture_sounding_1str_20mhz : 1,
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capture_sounding_1str_40mhz : 1,
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capture_sounding_1str_80mhz : 1,
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capture_sounding_1str_160mhz : 1,
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capture_sounding_1str_240mhz : 1,
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capture_sounding_1str_320mhz : 1,
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reserved_3a : 9;
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uint32_t fcs : 9,
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reserved_4a : 1,
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crc : 4,
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scrambler_seed : 7,
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reserved_4b : 11;
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#else
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uint32_t tx_ad2_31_0 : 32;
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uint32_t reserved_1 : 5,
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transmitted_bssid_check_en : 1,
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response_info_part2_required : 1,
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su_ba_user_number : 1,
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response_to_response : 3,
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expected_response_type : 5,
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tx_ad2_47_32 : 16;
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uint32_t ndp_sta_partial_aid1_8_0 : 11,
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reserved_2 : 10,
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ndp_sta_partial_aid_2_8_0 : 11;
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uint32_t reserved_3a : 9,
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capture_sounding_1str_320mhz : 1,
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capture_sounding_1str_240mhz : 1,
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capture_sounding_1str_160mhz : 1,
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capture_sounding_1str_80mhz : 1,
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capture_sounding_1str_40mhz : 1,
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capture_sounding_1str_20mhz : 1,
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capture_ack_ba_sounding : 1,
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ast_index : 16;
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uint32_t reserved_4b : 11,
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scrambler_seed : 7,
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crc : 4,
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reserved_4a : 1,
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fcs : 9;
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#endif
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};
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#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x00000000
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#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0
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#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31
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#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0xffffffff
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#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x00000004
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#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 0
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#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 15
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#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff
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#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x00000004
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#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 16
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#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 20
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#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f0000
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#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x00000004
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#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 21
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#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 23
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#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e00000
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#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x00000004
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#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 24
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#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 24
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#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x01000000
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#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x00000004
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#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 25
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#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 25
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#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x02000000
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#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x00000004
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#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 26
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#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 26
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#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x04000000
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#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x00000004
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#define EXPECTED_RESPONSE_RESERVED_1_LSB 27
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#define EXPECTED_RESPONSE_RESERVED_1_MSB 31
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#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf8000000
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#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x00000008
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#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0
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#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10
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#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x000007ff
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#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x00000008
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#define EXPECTED_RESPONSE_RESERVED_2_LSB 11
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#define EXPECTED_RESPONSE_RESERVED_2_MSB 20
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#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x001ff800
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#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x00000008
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#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21
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#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31
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#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0xffe00000
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#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000c
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#define EXPECTED_RESPONSE_AST_INDEX_LSB 0
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#define EXPECTED_RESPONSE_AST_INDEX_MSB 15
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#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff
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#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000c
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#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 16
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#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 16
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#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x00010000
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000c
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 17
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 17
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x00020000
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000c
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 18
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 18
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x00040000
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000c
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 19
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 19
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x00080000
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000c
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 20
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 20
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x00100000
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000c
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 21
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 21
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x00200000
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000c
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 22
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 22
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#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x00400000
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#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000c
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#define EXPECTED_RESPONSE_RESERVED_3A_LSB 23
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#define EXPECTED_RESPONSE_RESERVED_3A_MSB 31
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#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff800000
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#define EXPECTED_RESPONSE_FCS_OFFSET 0x00000010
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#define EXPECTED_RESPONSE_FCS_LSB 0
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#define EXPECTED_RESPONSE_FCS_MSB 8
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#define EXPECTED_RESPONSE_FCS_MASK 0x000001ff
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#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x00000010
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#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9
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#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9
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#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x00000200
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#define EXPECTED_RESPONSE_CRC_OFFSET 0x00000010
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#define EXPECTED_RESPONSE_CRC_LSB 10
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#define EXPECTED_RESPONSE_CRC_MSB 13
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#define EXPECTED_RESPONSE_CRC_MASK 0x00003c00
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#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x00000010
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#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14
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#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20
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#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x001fc000
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#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x00000010
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#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21
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#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31
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#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0xffe00000
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#endif
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