
Add HW header files to bring-in support for Peach WIFI. Change-Id: I73ee0a2c4f22a90013b441ecd5e666d673d77ae0 CRs-Fixed: 3580269
142 行
9.3 KiB
C
142 行
9.3 KiB
C
/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _COEX_RX_STATUS_H_
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#define _COEX_RX_STATUS_H_
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#define NUM_OF_DWORDS_COEX_RX_STATUS 2
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struct coex_rx_status {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t rx_mac_frame_status : 2,
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rx_with_tx_response : 1,
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rx_rate : 5,
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rx_bw : 3,
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single_mpdu : 1,
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filter_status : 1,
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ampdu : 1,
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directed : 1,
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reserved_0 : 1,
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rx_nss : 3,
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rx_rssi : 8,
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rx_type : 3,
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retry_bit_setting : 1,
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more_data_bit_setting : 1;
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uint32_t remain_rx_packet_time : 16,
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rx_remaining_fes_time : 16;
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#else
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uint32_t more_data_bit_setting : 1,
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retry_bit_setting : 1,
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rx_type : 3,
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rx_rssi : 8,
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rx_nss : 3,
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reserved_0 : 1,
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directed : 1,
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ampdu : 1,
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filter_status : 1,
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single_mpdu : 1,
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rx_bw : 3,
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rx_rate : 5,
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rx_with_tx_response : 1,
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rx_mac_frame_status : 2;
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uint32_t rx_remaining_fes_time : 16,
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remain_rx_packet_time : 16;
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#endif
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};
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#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x00000000
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#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0
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#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1
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#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x00000003
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#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x00000000
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#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2
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#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2
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#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x00000004
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#define COEX_RX_STATUS_RX_RATE_OFFSET 0x00000000
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#define COEX_RX_STATUS_RX_RATE_LSB 3
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#define COEX_RX_STATUS_RX_RATE_MSB 7
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#define COEX_RX_STATUS_RX_RATE_MASK 0x000000f8
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#define COEX_RX_STATUS_RX_BW_OFFSET 0x00000000
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#define COEX_RX_STATUS_RX_BW_LSB 8
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#define COEX_RX_STATUS_RX_BW_MSB 10
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#define COEX_RX_STATUS_RX_BW_MASK 0x00000700
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#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x00000000
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#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11
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#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11
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#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x00000800
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#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x00000000
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#define COEX_RX_STATUS_FILTER_STATUS_LSB 12
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#define COEX_RX_STATUS_FILTER_STATUS_MSB 12
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#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x00001000
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#define COEX_RX_STATUS_AMPDU_OFFSET 0x00000000
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#define COEX_RX_STATUS_AMPDU_LSB 13
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#define COEX_RX_STATUS_AMPDU_MSB 13
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#define COEX_RX_STATUS_AMPDU_MASK 0x00002000
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#define COEX_RX_STATUS_DIRECTED_OFFSET 0x00000000
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#define COEX_RX_STATUS_DIRECTED_LSB 14
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#define COEX_RX_STATUS_DIRECTED_MSB 14
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#define COEX_RX_STATUS_DIRECTED_MASK 0x00004000
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#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x00000000
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#define COEX_RX_STATUS_RESERVED_0_LSB 15
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#define COEX_RX_STATUS_RESERVED_0_MSB 15
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#define COEX_RX_STATUS_RESERVED_0_MASK 0x00008000
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#define COEX_RX_STATUS_RX_NSS_OFFSET 0x00000000
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#define COEX_RX_STATUS_RX_NSS_LSB 16
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#define COEX_RX_STATUS_RX_NSS_MSB 18
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#define COEX_RX_STATUS_RX_NSS_MASK 0x00070000
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#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x00000000
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#define COEX_RX_STATUS_RX_RSSI_LSB 19
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#define COEX_RX_STATUS_RX_RSSI_MSB 26
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#define COEX_RX_STATUS_RX_RSSI_MASK 0x07f80000
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#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x00000000
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#define COEX_RX_STATUS_RX_TYPE_LSB 27
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#define COEX_RX_STATUS_RX_TYPE_MSB 29
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#define COEX_RX_STATUS_RX_TYPE_MASK 0x38000000
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#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x00000000
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#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30
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#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30
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#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x40000000
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#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x00000000
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#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31
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#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31
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#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x80000000
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#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x00000004
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#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 0
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#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 15
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#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff
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#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x00000004
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#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 16
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#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 31
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#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff0000
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#endif
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