c82996e90f
Extracts DSP buffer information for log printing upon SMMU faults Change-Id: I36b1900ea84a85cdfdb2dec8ad62b67a5ff57119 Signed-off-by: Jingyu Su <quic_jingyus@quicinc.com>
316 lines
7.1 KiB
C
316 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef MSM_CVP_DSP_H
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#define MSM_CVP_DSP_H
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#include <linux/types.h>
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#include <linux/refcount.h>
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#include "msm_cvp_debug.h"
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#include "cvp_core_hfi.h"
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#include <linux/pid.h>
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#include <linux/sched.h>
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#ifdef CVP_FASTRPC_ENABLED
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#include <fastrpc.h>
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#else
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struct fastrpc_device {
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int handle;
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};
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enum fastrpc_driver_status {
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FASTRPC_CVP_B,
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};
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enum fastrpc_driver_invoke_nums {
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FASTRPC_DEV_MAP_DMA = 1,
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FASTRPC_DEV_UNMAP_DMA,
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FASTRPC_DEV_GET_HLOS_PID,
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};
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struct fastrpc_driver {
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struct device_driver driver;
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int handle;
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int (*probe)(struct fastrpc_device *dev);
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int (*callback)(struct fastrpc_device *dev,
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enum fastrpc_driver_status status);
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};
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#endif /* End of CVP_FASTRPC_ENABLED */
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#define CVP_APPS_DSP_GLINK_GUID "cvp-glink-apps-dsp"
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#define CVP_APPS_DSP_SMD_GUID "cvp-smd-apps-dsp"
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#define VMID_CDSP_Q6 (30)
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#define HLOS_VM_NUM 1
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#define DSP_VM_NUM 2
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#define CVP_DSP_MAX_RESERVED 5
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#define CVP_DSP2CPU_RESERVED 8
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#define CVP_DSP_RESPONSE_TIMEOUT 1000
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#define CVP_INVALID_RPMSG_TYPE 0xBADDFACE
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#define MAX_FRAME_BUF_NUM 16
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#define BITPTRSIZE32 (4)
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#define BITPTRSIZE64 (8)
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#define HIGH32 (0xFFFFFFFF00000000LL)
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#define LOW32 (0xFFFFFFFFLL)
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#define CVP_FASTRPC_DRIVER_NAME_SIZE 16
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/* Supports up to 8 DSP sessions in 8 processes */
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#define MAX_DSP_SESSION_NUM (8)
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#define MAX_FASTRPC_DRIVER_NUM (MAX_DSP_SESSION_NUM)
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int cvp_dsp_device_init(void);
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void cvp_dsp_device_exit(void);
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void cvp_dsp_send_hfi_queue(void);
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void cvp_dsp_init_hfi_queue_hdr(struct iris_hfi_device *device);
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enum CPU2DSP_STATUS {
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CPU2DSP_SUCCESS = 0,
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CPU2DSP_EFAIL = 1,
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CPU2DSP_EFATAL = 2,
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CPU2DSP_EUNAVAILABLE = 3,
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CPU2DSP_EINVALSTATE = 4,
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CPU2DSP_EUNSUPPORTED = 5,
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};
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enum CVP_DSP_COMMAND {
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CPU2DSP_SEND_HFI_QUEUE = 0,
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CPU2DSP_SUSPEND = 1,
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CPU2DSP_RESUME = 2,
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CPU2DSP_SHUTDOWN = 3,
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CPU2DSP_REGISTER_BUFFER = 4,
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CPU2DSP_DEREGISTER_BUFFER = 5,
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CPU2DSP_INIT = 6,
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CPU2DSP_SET_DEBUG_LEVEL = 7,
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CPU2DSP_MAX_CMD = 8,
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DSP2CPU_POWERON = 11,
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DSP2CPU_POWEROFF = 12,
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DSP2CPU_CREATE_SESSION = 13,
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DSP2CPU_DETELE_SESSION = 14,
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DSP2CPU_POWER_REQUEST = 15,
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DSP2CPU_POWER_CANCEL = 16,
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DSP2CPU_REGISTER_BUFFER = 17,
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DSP2CPU_DEREGISTER_BUFFER = 18,
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DSP2CPU_MEM_ALLOC = 19,
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DSP2CPU_MEM_FREE = 20,
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DSP2CPU_START_SESSION = 21,
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DSP2CPU_STOP_SESSION = 22,
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CVP_DSP_MAX_CMD = 23,
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};
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struct eva_power_req {
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uint32_t clock_fdu;
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uint32_t clock_ica;
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uint32_t clock_od;
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uint32_t clock_mpu;
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uint32_t clock_fw;
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uint32_t bw_ddr;
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uint32_t bw_sys_cache;
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uint32_t op_clock_fdu;
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uint32_t op_clock_ica;
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uint32_t op_clock_od;
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uint32_t op_clock_mpu;
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uint32_t op_clock_fw;
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uint32_t op_bw_ddr;
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uint32_t op_bw_sys_cache;
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};
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struct eva_mem_remote {
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uint32_t type;
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uint32_t size;
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uint32_t fd;
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uint32_t offset;
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uint32_t index;
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uint32_t iova;
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uint32_t dsp_remote_map;
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uint64_t v_dsp_addr;
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};
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/*
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* command: defined as a packet initiated from one party.
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* message: defined as a packet sent as response to a command
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*/
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/*
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* cvp_dsp_cmd_msg contains
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* the message sent from CPU to DSP
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* or
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* the command sent from CPU to DSP
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*/
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struct cvp_dsp_cmd_msg {
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uint32_t type;
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int32_t ret;
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uint64_t msg_ptr;
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uint32_t msg_ptr_len;
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uint32_t buff_fd_iova;
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uint32_t buff_index;
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uint32_t buff_size;
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uint32_t session_id;
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int32_t ddr_type;
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uint32_t buff_fd;
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uint32_t buff_offset;
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uint32_t buff_fd_size;
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uint32_t eva_dsp_debug_mask;
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/* Create Session */
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uint32_t session_cpu_low;
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uint32_t session_cpu_high;
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struct eva_mem_remote sbuf;
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uint32_t reserved1;
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uint32_t reserved2;
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};
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/* cvp_dsp_rsp_msg contains the message sent from DSP to CPU */
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struct cvp_dsp_rsp_msg {
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uint32_t type;
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int32_t ret;
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uint32_t dsp_state;
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uint32_t reserved[CVP_DSP_MAX_RESERVED - 1];
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};
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/* cvp_dsp2cpu_cmd contains the command sent from DSP to cpu*/
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struct cvp_dsp2cpu_cmd {
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uint32_t type;
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uint32_t ver;
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uint32_t len;
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/* Create Session */
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uint32_t session_type;
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uint32_t kernel_mask;
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uint32_t session_prio;
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uint32_t is_secure;
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uint32_t dsp_access_mask;
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uint32_t session_id;
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uint32_t session_cpu_low;
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uint32_t session_cpu_high;
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int32_t pid;
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struct eva_power_req power_req;
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struct eva_mem_remote sbuf;
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uint32_t data[CVP_DSP2CPU_RESERVED];
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};
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struct driver_name {
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uint32_t status;
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char name[CVP_FASTRPC_DRIVER_NAME_SIZE];
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};
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enum DRIVER_NAME_STATUS {
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DRIVER_NAME_INVALID = 0,
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DRIVER_NAME_AVAILABLE = 1,
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DRIVER_NAME_USED = 2,
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};
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struct cvp_dsp_fastrpc_driver_entry {
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struct list_head list;
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uint32_t handle; /*handle is not PID*/
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uint32_t session_cnt;
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uint32_t driver_name_idx;
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atomic_t refcount;
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struct fastrpc_driver cvp_fastrpc_driver;
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struct fastrpc_device *cvp_fastrpc_device;
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struct completion fastrpc_probe_completion;
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/* all dsp sessions list */
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struct msm_cvp_list dsp_sessions;
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};
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struct cvp_dsp_apps {
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/*
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* tx_lock for sending CPU2DSP cmds or msgs
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* and dsp state change
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*/
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struct mutex tx_lock;
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/* rx_lock for receiving DSP2CPU cmds or msgs */
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struct mutex rx_lock;
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struct mutex driver_name_lock;
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struct rpmsg_device *chan;
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uint32_t state;
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uint32_t debug_mask;
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bool hyp_assigned;
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uint64_t addr;
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uint32_t size;
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struct completion completions[CPU2DSP_MAX_CMD + 1];
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struct cvp_dsp2cpu_cmd pending_dsp2cpu_cmd;
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struct cvp_dsp_rsp_msg pending_dsp2cpu_rsp;
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struct task_struct *dsp_thread;
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/* dsp buffer mapping, set of dma function pointer */
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const struct file_operations *dmabuf_f_op;
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uint32_t buf_num;
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struct msm_cvp_list fastrpc_driver_list;
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struct driver_name cvp_fastrpc_name[MAX_FASTRPC_DRIVER_NUM];
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};
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#define EVA_TRACE_MAX_SESSION_NUM 16
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#define EVA_TRACE_MAX_INSTANCE_NUM 6
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#define EVA_TRACE_MAX_BUF_NUM 256
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#define CONFIG_SIZE_IN_BYTES 2048
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#define CONFIG_SIZE_IN_WORDS (CONFIG_SIZE_IN_BYTES >> 2)
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// iova is eva_dsp_buf->iova
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// pkt_type is frame packet type using the buffer
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// buf_idx is the index of the buffer in a frame packet
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// transaction_id is the transaction id of frame packet
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struct cvp_dsp_trace_buf {
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u32 iova;
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u32 pkt_type;
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u32 buf_idx;
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u32 transaction_id;
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u32 fd;
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};
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// Saving config packet for each intance
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struct cvp_dsp_trace_instance {
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u32 feature_type;
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u32 config_pkt[CONFIG_SIZE_IN_WORDS];
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};
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struct cvp_dsp_trace_session {
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u32 session_id;
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u32 buf_cnt;
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u32 inst_cnt;
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struct cvp_dsp_trace_instance instance[EVA_TRACE_MAX_INSTANCE_NUM];
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struct cvp_dsp_trace_buf buf[EVA_TRACE_MAX_BUF_NUM];
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};
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struct cvp_dsp_trace {
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struct cvp_dsp_trace_session sessions[EVA_TRACE_MAX_SESSION_NUM];
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};
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extern struct cvp_dsp_apps gfa_cv;
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/*
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* API for CVP driver to suspend CVP session during
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* power collapse
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*/
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int cvp_dsp_suspend(bool force);
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/*
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* API for CVP driver to resume CVP session during
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* power collapse
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*/
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int cvp_dsp_resume(void);
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/*
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* API for CVP driver to shutdown CVP session during
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* cvp subsystem error.
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*/
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int cvp_dsp_shutdown(void);
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int cvp_dsp_fastrpc_unmap(uint32_t handle, struct cvp_internal_buf *buf);
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int cvp_dsp_del_sess(uint32_t handle, struct msm_cvp_inst *inst);
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void cvp_dsp_send_debug_mask(void);
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#endif // MSM_CVP_DSP_H
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