25f1b0434b
Change REO queue descriptor delete sequence to flush base and extension descriptors separately, since flushing base descriptor alone results in extensions flushed by HW much later, sometimes after freeing descriptor memory, causing use-after-free corruptions. Also increase REO command and status ring sizes since number of commands per RX TID flush has increased with this change. Fix interrupt batch count setting for non pkt/buffer rings, which includes REO status ring. Also remove callbacks during reo command list destroy, done as part of SOC detach. This should not be done since callbacks will access stale data structures that are freed as part of PDEV/SOC detach. Change-Id: I4337454d3f53cc0b3c3014ef07cc2ba13cfebb18 CRs-Fixed: 2175989
326 lines
11 KiB
C
326 lines
11 KiB
C
/*
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* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hal_api.h"
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#include "qdf_module.h"
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/* TODO: See if the following definition is available in HW headers */
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#define HAL_REO_OWNED 4
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#define HAL_REO_QUEUE_DESC 8
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#define HAL_REO_QUEUE_EXT_DESC 9
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/* TODO: Using associated link desc counter 1 for Rx. Check with FW on
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* how these counters are assigned
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*/
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#define HAL_RX_LINK_DESC_CNTR 1
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/* TODO: Following definition should be from HW headers */
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#define HAL_DESC_REO_OWNED 4
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/* TODO: Move this to common header file */
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static inline void hal_uniform_desc_hdr_setup(uint32_t *desc, uint32_t owner,
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uint32_t buffer_type)
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{
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HAL_DESC_SET_FIELD(desc, UNIFORM_DESCRIPTOR_HEADER_0, OWNER,
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owner);
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HAL_DESC_SET_FIELD(desc, UNIFORM_DESCRIPTOR_HEADER_0, BUFFER_TYPE,
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buffer_type);
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}
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#ifndef TID_TO_WME_AC
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#define WME_AC_BE 0 /* best effort */
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#define WME_AC_BK 1 /* background */
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#define WME_AC_VI 2 /* video */
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#define WME_AC_VO 3 /* voice */
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#define TID_TO_WME_AC(_tid) ( \
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(((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
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(((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
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(((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
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WME_AC_VO)
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#endif
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#define HAL_NON_QOS_TID 16
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/**
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* hal_reo_qdesc_setup - Setup HW REO queue descriptor
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*
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* @hal_soc: Opaque HAL SOC handle
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* @ba_window_size: BlockAck window size
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* @start_seq: Starting sequence number
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* @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
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* @hw_qdesc_paddr: Physical address of REO queue descriptor memory
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* @tid: TID
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*
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*/
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void hal_reo_qdesc_setup(void *hal_soc, int tid, uint32_t ba_window_size,
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uint32_t start_seq, void *hw_qdesc_vaddr, qdf_dma_addr_t hw_qdesc_paddr,
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int pn_type)
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{
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uint32_t *reo_queue_desc = (uint32_t *)hw_qdesc_vaddr;
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uint32_t *reo_queue_ext_desc;
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uint32_t reg_val;
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uint32_t pn_enable, pn_size;
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qdf_mem_zero(hw_qdesc_vaddr, sizeof(struct rx_reo_queue));
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hal_uniform_desc_hdr_setup(reo_queue_desc, HAL_DESC_REO_OWNED,
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HAL_REO_QUEUE_DESC);
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/* Fixed pattern in reserved bits for debugging */
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HAL_DESC_SET_FIELD(reo_queue_desc, UNIFORM_DESCRIPTOR_HEADER_0,
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RESERVED_0A, 0xDDBEEF);
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/* This a just a SW meta data and will be copied to REO destination
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* descriptors indicated by hardware.
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* TODO: Setting TID in this field. See if we should set something else.
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*/
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_1,
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RECEIVE_QUEUE_NUMBER, tid);
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
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VLD, 1);
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
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ASSOCIATED_LINK_DESCRIPTOR_COUNTER, HAL_RX_LINK_DESC_CNTR);
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/*
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* Fields DISABLE_DUPLICATE_DETECTION and SOFT_REORDER_ENABLE will be 0
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*/
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reg_val = TID_TO_WME_AC(tid);
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, AC, reg_val);
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if (ba_window_size < 1)
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ba_window_size = 1;
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/* Set RTY bit for non-BA case. Duplicate detection is currently not
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* done by HW in non-BA case if RTY bit is not set.
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* TODO: This is a temporary War and should be removed once HW fix is
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* made to check and discard duplicates even if RTY bit is not set.
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*/
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if (ba_window_size == 1)
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, RTY, 1);
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, BA_WINDOW_SIZE,
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ba_window_size - 1);
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switch (pn_type) {
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case HAL_PN_WPA:
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pn_enable = 1;
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pn_size = PN_SIZE_48;
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case HAL_PN_WAPI_EVEN:
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case HAL_PN_WAPI_UNEVEN:
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pn_enable = 1;
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pn_size = PN_SIZE_128;
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default:
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pn_enable = 0;
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}
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_CHECK_NEEDED,
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pn_enable);
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if (pn_type == HAL_PN_WAPI_EVEN)
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
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PN_SHALL_BE_EVEN, 1);
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else if (pn_type == HAL_PN_WAPI_UNEVEN)
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
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PN_SHALL_BE_UNEVEN, 1);
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_HANDLING_ENABLE,
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pn_enable);
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_SIZE,
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pn_size);
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/* TODO: Check if RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG need to be set
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* based on BA window size and/or AMPDU capabilities
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*/
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
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IGNORE_AMPDU_FLAG, 1);
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if (start_seq <= 0xfff)
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_3, SSN,
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start_seq);
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/* TODO: SVLD should be set to 1 if a valid SSN is received in ADDBA,
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* but REO is not delivering packets if we set it to 1. Need to enable
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* this once the issue is resolved */
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HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_3, SVLD, 0);
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/* TODO: Check if we should set start PN for WAPI */
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#ifdef notyet
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/* Setup first queue extension if BA window size is more than 1 */
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if (ba_window_size > 1) {
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reo_queue_ext_desc =
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(uint32_t *)(((struct rx_reo_queue *)reo_queue_desc) +
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1);
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qdf_mem_zero(reo_queue_ext_desc,
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sizeof(struct rx_reo_queue_ext));
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hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
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HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
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}
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/* Setup second queue extension if BA window size is more than 105 */
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if (ba_window_size > 105) {
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reo_queue_ext_desc = (uint32_t *)
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(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
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qdf_mem_zero(reo_queue_ext_desc,
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sizeof(struct rx_reo_queue_ext));
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hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
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HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
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}
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/* Setup third queue extension if BA window size is more than 210 */
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if (ba_window_size > 210) {
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reo_queue_ext_desc = (uint32_t *)
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(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
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qdf_mem_zero(reo_queue_ext_desc,
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sizeof(struct rx_reo_queue_ext));
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hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
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HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
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}
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#else
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/* TODO: HW queue descriptors are currently allocated for max BA
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* window size for all QOS TIDs so that same descriptor can be used
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* later when ADDBA request is recevied. This should be changed to
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* allocate HW queue descriptors based on BA window size being
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* negotiated (0 for non BA cases), and reallocate when BA window
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* size changes and also send WMI message to FW to change the REO
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* queue descriptor in Rx peer entry as part of dp_rx_tid_update.
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*/
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if (tid != HAL_NON_QOS_TID) {
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reo_queue_ext_desc = (uint32_t *)
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(((struct rx_reo_queue *)reo_queue_desc) + 1);
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qdf_mem_zero(reo_queue_ext_desc, 3 *
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sizeof(struct rx_reo_queue_ext));
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/* Initialize first reo queue extension descriptor */
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hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
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HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
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/* Fixed pattern in reserved bits for debugging */
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HAL_DESC_SET_FIELD(reo_queue_ext_desc,
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UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A, 0xADBEEF);
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/* Initialize second reo queue extension descriptor */
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reo_queue_ext_desc = (uint32_t *)
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(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
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hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
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HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
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/* Fixed pattern in reserved bits for debugging */
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HAL_DESC_SET_FIELD(reo_queue_ext_desc,
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UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A, 0xBDBEEF);
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/* Initialize third reo queue extension descriptor */
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reo_queue_ext_desc = (uint32_t *)
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(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
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hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
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HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
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/* Fixed pattern in reserved bits for debugging */
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HAL_DESC_SET_FIELD(reo_queue_ext_desc,
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UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A, 0xCDBEEF);
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}
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#endif
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}
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qdf_export_symbol(hal_reo_qdesc_setup);
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/**
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* hal_reo_setup - Initialize HW REO block
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*
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* @hal_soc: Opaque HAL SOC handle
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* @reo_params: parameters needed by HAL for REO config
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*/
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void hal_reo_setup(void *hal_soc,
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struct hal_reo_params *reo_params)
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{
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struct hal_soc *soc = (struct hal_soc *)hal_soc;
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HAL_REG_WRITE(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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HAL_SM(HWIO_REO_R0_GENERAL_ENABLE,
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FRAGMENT_DEST_RING, reo_params->frag_dst_ring) |
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HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_LIST_ENABLE, 1) |
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HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_FLUSH_ENABLE, 1));
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/* Other ring enable bits and REO_ENABLE will be set by FW */
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/* TODO: Setup destination ring mapping if enabled */
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/* TODO: Error destination ring setting is left to default.
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* Default setting is to send all errors to release ring.
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*/
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HAL_REG_WRITE(soc,
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HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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HAL_DEFAULT_REO_TIMEOUT_MS * 1000);
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HAL_REG_WRITE(soc,
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HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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(HAL_DEFAULT_REO_TIMEOUT_MS * 1000));
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HAL_REG_WRITE(soc,
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HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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(HAL_DEFAULT_REO_TIMEOUT_MS * 1000));
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HAL_REG_WRITE(soc,
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HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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(HAL_DEFAULT_REO_TIMEOUT_MS * 1000));
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/*
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* When hash based routing is enabled, routing of the rx packet
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* is done based on the following value: 1 _ _ _ _ The last 4
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* bits are based on hash[3:0]. This means the possible values
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* are 0x10 to 0x1f. This value is used to look-up the
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* ring ID configured in Destination_Ring_Ctrl_IX_* register.
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* The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
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* registers need to be configured to set-up the 16 entries to
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* map the hash values to a ring number. There are 3 bits per
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* hash entry which are mapped as follows:
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* 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
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* 7: NOT_USED.
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*/
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if (reo_params->rx_hash_enabled) {
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HAL_REG_WRITE(soc,
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HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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reo_params->remap1);
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QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
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FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x\n"),
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HAL_REG_READ(soc,
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HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET)));
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HAL_REG_WRITE(soc,
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HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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reo_params->remap2);
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QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
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FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x\n"),
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HAL_REG_READ(soc,
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HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET)));
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}
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/* TODO: Check if the following registers shoould be setup by host:
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* AGING_CONTROL
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* HIGH_MEMORY_THRESHOLD
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* GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
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* GLOBAL_LINK_DESC_COUNT_CTRL
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*/
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}
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qdf_export_symbol(hal_reo_setup);
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