0cf22b4439
Add qcn9224 HW headers corresponding. Change-Id: Iaf2dfc04009ffa82b6dd4a40e796148fa99a5744 CRs-Fixed: 3103719
195 行
8.9 KiB
C
195 行
8.9 KiB
C
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/* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _REO_FLUSH_QUEUE_H_
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#define _REO_FLUSH_QUEUE_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "uniform_reo_cmd_header.h"
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#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10
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#define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5
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struct reo_flush_queue {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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struct uniform_reo_cmd_header cmd_header;
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uint32_t flush_desc_addr_31_0 : 32;
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uint32_t flush_desc_addr_39_32 : 8,
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block_desc_addr_usage_after_flush : 1,
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block_resource_index : 2,
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reserved_2a : 21;
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uint32_t reserved_3a : 32;
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uint32_t reserved_4a : 32;
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uint32_t reserved_5a : 32;
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uint32_t reserved_6a : 32;
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uint32_t reserved_7a : 32;
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uint32_t reserved_8a : 32;
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uint32_t tlv64_padding : 32;
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#else
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struct uniform_reo_cmd_header cmd_header;
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uint32_t flush_desc_addr_31_0 : 32;
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uint32_t reserved_2a : 21,
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block_resource_index : 2,
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block_desc_addr_usage_after_flush : 1,
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flush_desc_addr_39_32 : 8;
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uint32_t reserved_3a : 32;
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uint32_t reserved_4a : 32;
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uint32_t reserved_5a : 32;
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uint32_t reserved_6a : 32;
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uint32_t reserved_7a : 32;
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uint32_t reserved_8a : 32;
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uint32_t tlv64_padding : 32;
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#endif
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};
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#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
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#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
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#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
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#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
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#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
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#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
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#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
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#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
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#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
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#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17
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#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31
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#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
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#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000
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#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32
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#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63
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#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000
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#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008
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#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0
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#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7
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#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff
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#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008
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#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8
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#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8
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#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100
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#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008
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#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9
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#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10
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#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600
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#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008
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#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11
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#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31
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#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800
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#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008
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#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32
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#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63
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#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000
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#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010
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#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0
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#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31
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#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff
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#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010
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#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32
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#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63
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#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000
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#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018
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#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0
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#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31
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#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff
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#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018
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#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32
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#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63
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#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000
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#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020
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#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0
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#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31
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#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff
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#define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020
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#define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32
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#define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63
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#define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000
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#endif
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