8f2ef48ebc
Bring in V2 HW header files for peach, also cleanup the header files 1. Remove comments; 2. Add appropriate copyright header; 3. Remove references to HW sensitive IP (structs, macros and etc). Change-Id: Iaa4db993ce08d04e5e571c740a4f30ff42890474 CRs-Fixed: 3691183
74 lines
4.3 KiB
C
74 lines
4.3 KiB
C
/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _RESPONSE_START_STATUS_H_
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#define _RESPONSE_START_STATUS_H_
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#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2
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struct response_start_status {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t generated_response : 3,
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__reserved_g_0012 : 2,
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trig_response_related : 1,
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response_sta_count : 7,
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reserved : 19;
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uint32_t phy_ppdu_id : 16,
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sw_peer_id : 16;
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#else
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uint32_t reserved : 19,
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response_sta_count : 7,
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trig_response_related : 1,
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__reserved_g_0012 : 2,
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generated_response : 3;
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uint32_t sw_peer_id : 16,
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phy_ppdu_id : 16;
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#endif
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};
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#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x00000000
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#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0
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#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2
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#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x00000007
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#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x00000000
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#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5
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#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5
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#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x00000020
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#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x00000000
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#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6
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#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12
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#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x00001fc0
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#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x00000000
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#define RESPONSE_START_STATUS_RESERVED_LSB 13
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#define RESPONSE_START_STATUS_RESERVED_MSB 31
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#define RESPONSE_START_STATUS_RESERVED_MASK 0xffffe000
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#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x00000004
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#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 0
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#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 15
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#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff
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#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x00000004
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#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 16
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#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 31
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#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff0000
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#endif
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