8f2ef48ebc
Bring in V2 HW header files for peach, also cleanup the header files 1. Remove comments; 2. Add appropriate copyright header; 3. Remove references to HW sensitive IP (structs, macros and etc). Change-Id: Iaa4db993ce08d04e5e571c740a4f30ff42890474 CRs-Fixed: 3691183
242 lines
17 KiB
C
242 lines
17 KiB
C
/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _PHYTX_PKT_END_H_
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#define _PHYTX_PKT_END_H_
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#define NUM_OF_WORDS_PHYTX_PKT_END 26
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#define NUM_OF_DWORDS_PHYTX_PKT_END 13
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struct phytx_pkt_end {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint16_t start_of_frame_timestamp_15_0 : 16;
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uint16_t start_of_frame_timestamp_31_16 : 16;
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uint16_t end_of_frame_timestamp_15_0 : 16;
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uint16_t end_of_frame_timestamp_31_16 : 16;
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uint16_t tx_group_delay : 12,
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timing_status : 2,
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phyrx_entered_nap_state : 1,
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dpdtrain_done : 1;
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uint16_t transmit_delay : 16;
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uint16_t tpc_dbg_info_cmn_15_0 : 16;
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uint16_t tpc_dbg_info_cmn_31_16 : 16;
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uint16_t tpc_dbg_info_cmn_47_32 : 16;
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uint16_t tpc_dbg_info_chn1_15_0 : 16;
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uint16_t tpc_dbg_info_chn1_31_16 : 16;
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uint16_t tpc_dbg_info_chn1_47_32 : 16;
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uint16_t tpc_dbg_info_chn1_63_48 : 16;
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uint16_t tpc_dbg_info_chn1_79_64 : 16;
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uint16_t tpc_dbg_info_chn2_15_0 : 16;
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uint16_t tpc_dbg_info_chn2_31_16 : 16;
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uint16_t tpc_dbg_info_chn2_47_32 : 16;
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uint16_t tpc_dbg_info_chn2_63_48 : 16;
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uint16_t tpc_dbg_info_chn2_79_64 : 16;
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uint16_t phytx_tx_end_sw_info_15_0 : 16;
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uint16_t phytx_tx_end_sw_info_31_16 : 16;
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uint16_t phytx_tx_end_sw_info_47_32 : 16;
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uint16_t phytx_tx_end_sw_info_63_48 : 16;
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uint16_t beamform_masked_user_bitmap_15_0 : 16;
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uint16_t beamform_masked_user_bitmap_31_16 : 16;
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uint16_t beamform_masked_user_bitmap_36_32 : 5,
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reserved_23 : 11;
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#else
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uint16_t start_of_frame_timestamp_15_0 : 16;
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uint16_t start_of_frame_timestamp_31_16 : 16;
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uint16_t end_of_frame_timestamp_15_0 : 16;
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uint16_t end_of_frame_timestamp_31_16 : 16;
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uint16_t dpdtrain_done : 1,
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phyrx_entered_nap_state : 1,
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timing_status : 2,
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tx_group_delay : 12;
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uint16_t transmit_delay : 16;
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uint16_t tpc_dbg_info_cmn_15_0 : 16;
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uint16_t tpc_dbg_info_cmn_31_16 : 16;
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uint16_t tpc_dbg_info_cmn_47_32 : 16;
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uint16_t tpc_dbg_info_chn1_15_0 : 16;
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uint16_t tpc_dbg_info_chn1_31_16 : 16;
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uint16_t tpc_dbg_info_chn1_47_32 : 16;
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uint16_t tpc_dbg_info_chn1_63_48 : 16;
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uint16_t tpc_dbg_info_chn1_79_64 : 16;
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uint16_t tpc_dbg_info_chn2_15_0 : 16;
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uint16_t tpc_dbg_info_chn2_31_16 : 16;
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uint16_t tpc_dbg_info_chn2_47_32 : 16;
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uint16_t tpc_dbg_info_chn2_63_48 : 16;
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uint16_t tpc_dbg_info_chn2_79_64 : 16;
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uint16_t phytx_tx_end_sw_info_15_0 : 16;
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uint16_t phytx_tx_end_sw_info_31_16 : 16;
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uint16_t phytx_tx_end_sw_info_47_32 : 16;
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uint16_t phytx_tx_end_sw_info_63_48 : 16;
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uint16_t beamform_masked_user_bitmap_15_0 : 16;
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uint16_t beamform_masked_user_bitmap_31_16 : 16;
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uint16_t reserved_23 : 11,
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beamform_masked_user_bitmap_36_32 : 5;
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#endif
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};
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#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000
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#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0
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#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15
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#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff
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#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002
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#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0
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#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15
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#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff
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#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004
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#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0
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#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15
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#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff
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#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006
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#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0
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#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15
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#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff
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#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008
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#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0
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#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11
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#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff
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#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008
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#define PHYTX_PKT_END_TIMING_STATUS_LSB 12
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#define PHYTX_PKT_END_TIMING_STATUS_MSB 13
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#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000
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#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008
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#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14
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#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14
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#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000
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#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008
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#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15
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#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15
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#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000
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#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a
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#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0
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#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15
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#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c
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#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e
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#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010
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#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15
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#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15
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#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff
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#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e
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#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0
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#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15
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#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff
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#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030
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#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0
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#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15
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#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff
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#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032
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#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0
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#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4
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#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f
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#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032
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#define PHYTX_PKT_END_RESERVED_23_LSB 5
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#define PHYTX_PKT_END_RESERVED_23_MSB 15
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#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0
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#endif
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