2d29d9afc7
Add HW header files to bring-in support for Peach WIFI. Change-Id: I73ee0a2c4f22a90013b441ecd5e666d673d77ae0 CRs-Fixed: 3580269
79 lines
4.6 KiB
C
79 lines
4.6 KiB
C
/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _MON_BUFFER_ADDR_H_
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#define _MON_BUFFER_ADDR_H_
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#define NUM_OF_DWORDS_MON_BUFFER_ADDR 3
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struct mon_buffer_addr {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t buffer_virt_addr_31_0 : 32;
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uint32_t buffer_virt_addr_63_32 : 32;
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uint32_t dma_length : 12,
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reserved_2a : 4,
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msdu_continuation : 1,
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truncated : 1,
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reserved_2b : 14;
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#else
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uint32_t buffer_virt_addr_31_0 : 32;
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uint32_t buffer_virt_addr_63_32 : 32;
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uint32_t reserved_2b : 14,
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truncated : 1,
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msdu_continuation : 1,
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reserved_2a : 4,
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dma_length : 12;
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#endif
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};
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 0
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 31
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#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
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#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x00000008
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#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0
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#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11
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#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x00000fff
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#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x00000008
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#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12
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#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15
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#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x0000f000
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#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x00000008
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#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16
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#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16
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#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x00010000
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#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x00000008
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#define MON_BUFFER_ADDR_TRUNCATED_LSB 17
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#define MON_BUFFER_ADDR_TRUNCATED_MSB 17
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#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x00020000
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#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x00000008
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#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18
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#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31
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#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0xfffc0000
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#endif
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