17a7fb3f4d
1. Update RX CLK config for 11P2896MHz. 2. Add condition to update Droop sel coeffs for 11P28MHz and 9P6MHz RX CLK. 3. Upate SWR port config for 44.1Khz sample rate usecase. 4. Unselect RX_TOP.SWR_CTRL(0x6AC0008) for RX CLK 11P28MHz. 5. Update HD2_CTL L/R registers as per latest seq version. Change-Id: Ifac2c03e3d1bf522fe2a4d942341d9071a1e6239 Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
109 lines
6.1 KiB
C
109 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _PINEAPPLE_PORT_CONFIG
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#define _PINEAPPLE_PORT_CONFIG
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#include <soc/swr-common.h>
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#define WSA_MSTR_PORT_MASK 0xFF
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/*
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* Add port configuration in the format
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*{ si, off1, off2, hstart, hstop, wd_len, bp_mode, bgp_ctrl, lane_ctrl, dir,
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* stream_type}
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*/
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static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
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{7, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR1 */
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{31, 3, 7, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP1 */
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{63, 5, 31, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* SB1 */
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{7, 2, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR2 */
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{31, 4, 7, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP2 */
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{63, 21, 31, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* SB2 */
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{399, 0, 0xFF, 8, 8, 8, 0, 0xFF, 0xFF, 0x00, 0x01}, /* PBR */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* HAPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x01}, /* OCPM */
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{15, 6, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS1 */
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{15, 13, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS2 */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x01, 0x01}, /* ICPM */
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{799, 0, 0xFF, 15, 15, 24, 0, 0xFF, 0xFF, 0x01, 0x01}, /* CPS */
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};
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static struct port_params wsa_frame_params_receiver[SWR_MSTR_PORT_LEN] = {
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{3, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR1 */
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{31, 3, 7, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP1 */
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{63, 5, 31, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* SB1 */
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{3, 2, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR2 */
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{31, 4, 7, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP2 */
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{63, 21, 31, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* SB2 */
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{399, 0xFF, 0xFF, 8, 8, 8, 0, 0xFF, 0xFF, 0x00, 0x01}, /* PBR */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* HAPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x01}, /* OCPM */
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{15, 6, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS1 */
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{15, 13, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS2 */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x01, 0x01}, /* ICPM */
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{799, 0xFF, 0xFF, 15, 15, 24, 0, 0xFF, 0xFF, 0x01, 0x01}, /* CPS */
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};
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static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {
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{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, /* HPH/EAR */
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{31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x02}, /* HPH_CLH */
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{31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x02}, /* HPH_CMP */
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{7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0, 0x00, 0x00}, /* LO/AUX */
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{3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0, 0x00, 0x00}, /* DSD */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* GPPO */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HAPT */
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{49, 0, 0, 0, 15, 24, 1, 0, 1, 0x00, 0x01}, /* HIFI */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HPHT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* CMPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* IPCM */
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};
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/* Headset + PCM Haptics */
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static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = {
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{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, /* HPH/EAR */
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{31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x02}, /* HPH_CLH */
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{31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x02}, /* HPH_CMP */
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{7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* LO/AUX */
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{0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */
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{0x18F, 0, 0, 0x8, 0x8, 0x0F, 0x00, 0, 0, 0x00, 0x01}, /* PCM_OUT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* GPPO */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HAPT */
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{49, 0, 0, 0, 15, 24, 1, 0, 1, 0x00, 0x01}, /* HIFI */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HPHT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* CMPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* IPCM */
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};
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/* Headset(44.1K) + PCM Haptics */
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static struct port_params rx_frame_params_44p1KHz[SWR_MSTR_PORT_LEN] = {
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{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, /* HPH/EAR */
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{63, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x02}, /* HPH_CLH */
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{31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x02}, /* HPH_CMP */
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{3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0, 0x00, 0x00}, /* LO/AUX */
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{0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */
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{0x1FF, 0, 0, 0x8, 0x8, 0x0F, 0, 0, 0, 0x00, 0x01}, /* PCM_OUT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* GPPO */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HAPT */
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{63, 0, 0, 0, 15, 31, 1, 0, 1, 0x00, 0x01}, /* HIFI */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HPHT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* CMPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* IPCM */
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};
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static struct swr_mstr_port_map sm_port_map[] = {
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{RX_MACRO, SWR_UC0, rx_frame_params_default},
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{RX_MACRO, SWR_UC1, rx_frame_params_dsd},
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{RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz},
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{WSA_MACRO, SWR_UC0, wsa_frame_params_default},
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{WSA_MACRO, SWR_UC1, wsa_frame_params_receiver},
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{WSA2_MACRO, SWR_UC0, wsa_frame_params_default},
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{WSA2_MACRO, SWR_UC1, wsa_frame_params_receiver},
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};
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#endif /* _PINEAPPLE_PORT_CONFIG */
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