53615194b4
Destination scaler hw can be enabled and disabled runtime for sharpness only case through QDCM. Customer is using shared DSI solution and issue scenario is: 1) DS0 configured and enabled for INTF1 display1. 2) Suspend commit is triggered with DS0 disable configuration but driver programming doesn't happen as crtc is not enabled. for customer case, GDSC is not turned off due to extra vote. 3) On resume commit on INTF1 display2 with different resolution, DS0 is not configured from userspace, but in HW, DS0 programming is retained. 4) Due to this retained programming, DSI underflow is seen in resume commit. Add changes to disable dest scaler qseed opmode and merge ctrl as part of cp crtc disable sequence. Change-Id: Ibb39814e02870394da4c7c7318e6e2780fed9081 Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
116 lines
3.2 KiB
C
116 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_HW_DS_H
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#define _SDE_HW_DS_H
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#include "sde_hw_mdss.h"
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#include "sde_hw_util.h"
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#include "sde_hw_catalog.h"
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struct sde_hw_ds;
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/* Destination Scaler DUAL mode overfetch pixel count */
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#define SDE_DS_OVERFETCH_SIZE 5
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/* Destination scaler DUAL mode operation bit */
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#define SDE_DS_OP_MODE_DUAL BIT(16)
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/* struct sde_hw_ds_cfg - destination scaler config
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* @idx : DS selection index
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* @flags : Flag to switch between mode for DS
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* @lm_width : Layer mixer width configuration
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* @lm_heigh : Layer mixer height configuration
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* @scl3_cfg : Configuration data for scaler
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*/
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struct sde_hw_ds_cfg {
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u32 idx;
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int flags;
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u32 lm_width;
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u32 lm_height;
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struct sde_hw_scaler3_cfg scl3_cfg;
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};
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/**
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* struct sde_hw_ds_ops - interface to the destination scaler
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* hardware driver functions
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* Caller must call the init function to get the ds context for each ds
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* Assumption is these functions will be called after clocks are enabled
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*/
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struct sde_hw_ds_ops {
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/**
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* setup_opmode - destination scaler op mode setup
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* @hw_ds : Pointer to ds context
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* @op_mode : Op mode configuration
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*/
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void (*setup_opmode)(struct sde_hw_ds *hw_ds,
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u32 op_mode);
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/**
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* setup_scaler - destination scaler block setup
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* @hw_ds : Pointer to ds context
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* @scaler_cfg : Pointer to scaler data
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* @scaler_lut_cfg : Pointer to scaler lut
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*/
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void (*setup_scaler)(struct sde_hw_ds *hw_ds,
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void *scaler_cfg,
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void *scaler_lut_cfg);
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/**
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* disable_dest_scl - disable destination scaler hw block
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* @hw_ds : Pointer to ds context
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*/
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void (*disable_dest_scl)(struct sde_hw_ds *hw_ds);
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};
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/**
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* struct sde_hw_ds - destination scaler description
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* @base : Hardware block base structure
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* @hw : Block hardware details
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* @idx : Destination scaler index
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* @scl : Pointer to
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* - scaler offset relative to top offset
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* - capabilities
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* @ops : Pointer to operations for this DS
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*/
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struct sde_hw_ds {
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struct sde_hw_blk_reg_map hw;
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enum sde_ds idx;
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struct sde_ds_cfg *scl;
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struct sde_hw_ds_ops ops;
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};
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/**
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* to_sde_hw_ds - convert base hw object to sde_hw_ds container
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* @hw: Pointer to hardware block register map object
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* return: Pointer to hardware block container
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*/
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static inline struct sde_hw_ds *to_sde_hw_ds(struct sde_hw_blk_reg_map *hw)
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{
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return container_of(hw, struct sde_hw_ds, hw);
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}
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/**
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* sde_hw_ds_init - initializes the destination scaler
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* hw driver object and should be called once before
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* accessing every destination scaler
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* @idx : DS index for which driver object is required
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* @addr: Mapped register io address of MDP
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* @m : MDSS catalog information
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* @Return: pointer to structure or ERR_PTR
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*/
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struct sde_hw_blk_reg_map *sde_hw_ds_init(enum sde_ds idx,
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void __iomem *addr,
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struct sde_mdss_cfg *m);
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/**
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* sde_hw_ds_destroy - destroys destination scaler driver context
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* @hw: Pointer to hardware block register map object
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*/
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void sde_hw_ds_destroy(struct sde_hw_blk_reg_map *hw);
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#endif /*_SDE_HW_DS_H */
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