f0b6f5d927
MDSS 10.0 supports additional dedicated cwb pingpong pair. This change updates downscaler block mux programming to support when second dcwb pinpong pair is in use. Change-Id: I1d5bdb557132c56874b13d06b9fe1aafeaadb36a Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
288 行
8.4 KiB
C
288 行
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#include "sde_hw_mdss.h"
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#include "sde_hwio.h"
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#include "sde_hw_catalog.h"
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#include "sde_hw_dnsc_blur.h"
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#include "sde_dbg.h"
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#include "sde_kms.h"
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#define DNSC_BLUR_OP_MODE 0x0
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#define DNSC_BLUR_BLUR_RATIO_H 0x4
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#define DNSC_BLUR_BLUR_RATIO_V 0x8
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#define DNSC_BLUR_PCMN_PHASE_INIT_H 0xC
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#define DNSC_BLUR_PCMN_PHASE_STEP_H 0x10
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#define DNSC_BLUR_PCMN_PHASE_INIT_V 0x14
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#define DNSC_BLUR_PCMN_PHASE_STEP_V 0x18
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#define DNSC_BLUR_OUT_IMG_SIZE 0x1C
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#define DNSC_BLUR_GAUS_COEF_LUT_SEL 0x20
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#define DNSC_BLUR_MUX 0x24
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#define DNSC_BLUR_SRC_IMG_SIZE 0x28
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#define DNSC_BLUR_GAUS_COEF_LUT_H0 0x0
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#define DNSC_BLUR_GAUS_COEF_LUT_V0 0x100
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#define DNSC_BLUR_GAUS_COEF_LUT_H1 0x200
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#define DNSC_BLUR_GAUS_COEF_LUT_V1 0x300
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#define DNSC_BLUR_DITHER_OP_MODE 0x0
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#define DNSC_BLUR_DITHER_BITDEPTH 0x4
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#define DNSC_BLUR_DITHER_MATRIX_ROW0 0x8
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/* DNSC_BLUR_OP_MODE bits */
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#define DNSC_BLUR_OPMODE_ENABLE BIT(0)
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#define DNSC_BLUR_OPMODE_DWNS_H_EN BIT(1)
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#define DNSC_BLUR_OPMODE_DWNS_V_EN BIT(2)
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#define DNSC_BLUR_OPMODE_PCMN_H BIT(8)
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#define DNSC_BLUR_OPMODE_PCMN_V BIT(12)
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#define DNSC_BLUR_OPMODE_OUT_RND_8B_EN BIT(16)
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static struct sde_dnsc_blur_cfg *_dnsc_blur_offset(enum sde_dnsc_blur idx,
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struct sde_mdss_cfg *m, void __iomem *addr, struct sde_hw_blk_reg_map *b)
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{
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int i;
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for (i = 0; i < m->dnsc_blur_count; i++) {
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if (idx == m->dnsc_blur[i].id) {
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b->base_off = addr;
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b->blk_off = m->dnsc_blur[i].base;
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b->length = m->dnsc_blur[i].len;
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b->hw_rev = m->hw_rev;
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b->log_mask = SDE_DBG_MASK_DNSC_BLUR;
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return &m->dnsc_blur[i];
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}
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}
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return ERR_PTR(-EINVAL);
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}
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static inline int _dnsc_blur_subblk_offset(struct sde_hw_dnsc_blur *hw_dnsc_blur,
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int s_id, u32 *base)
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{
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const struct sde_dnsc_blur_sub_blks *sblk;
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sblk = hw_dnsc_blur->caps->sblk;
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switch (s_id) {
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case SDE_DNSC_BLUR_GAUS_LUT:
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*base = sblk->gaus_lut.base;
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break;
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case SDE_DNSC_BLUR_DITHER:
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*base = sblk->dither.base;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void _sde_hw_dnsc_blur_gaus_lut_setup(struct sde_hw_dnsc_blur *hw_dnsc_blur,
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struct sde_drm_dnsc_blur_cfg *cfg, u32 lut_sel)
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{
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struct sde_hw_blk_reg_map *hw = &hw_dnsc_blur->hw;
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u32 lut_off, base;
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int i;
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if (_dnsc_blur_subblk_offset(hw_dnsc_blur, SDE_DNSC_BLUR_GAUS_LUT, &base))
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return;
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SDE_REG_WRITE(hw, DNSC_BLUR_GAUS_COEF_LUT_SEL, lut_sel);
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if (cfg->flags_h & DNSC_BLUR_GAUS_FILTER) {
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lut_off = lut_sel ? DNSC_BLUR_GAUS_COEF_LUT_H1 : DNSC_BLUR_GAUS_COEF_LUT_H0;
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for (i = 0; i < DNSC_BLUR_COEF_NUM; i++)
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SDE_REG_WRITE(hw, lut_off + (i * 0x4) + base, cfg->coef_hori[i]);
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}
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if (cfg->flags_v & DNSC_BLUR_GAUS_FILTER) {
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lut_off = lut_sel ? DNSC_BLUR_GAUS_COEF_LUT_V1 : DNSC_BLUR_GAUS_COEF_LUT_V0;
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for (i = 0; i < DNSC_BLUR_COEF_NUM; i++)
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SDE_REG_WRITE(hw, lut_off + (i * 0x4) + base, cfg->coef_vert[i]);
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}
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}
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static void _sde_hw_dnsc_blur_filter_setup(struct sde_hw_dnsc_blur *hw_dnsc_blur,
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struct sde_drm_dnsc_blur_cfg *cfg, u32 lut_sel)
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{
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struct sde_hw_blk_reg_map *hw = &hw_dnsc_blur->hw;
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u32 val;
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/* PCMN */
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if (cfg->flags_h & DNSC_BLUR_PCMN_FILTER) {
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SDE_REG_WRITE(hw, DNSC_BLUR_PCMN_PHASE_INIT_H, cfg->phase_init_h);
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SDE_REG_WRITE(hw, DNSC_BLUR_PCMN_PHASE_STEP_H, cfg->phase_step_h);
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}
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if (cfg->flags_v & DNSC_BLUR_PCMN_FILTER) {
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SDE_REG_WRITE(hw, DNSC_BLUR_PCMN_PHASE_INIT_V, cfg->phase_init_v);
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SDE_REG_WRITE(hw, DNSC_BLUR_PCMN_PHASE_STEP_V, cfg->phase_step_v);
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}
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/* Gaussian */
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if (cfg->flags_h & DNSC_BLUR_GAUS_FILTER) {
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val = (cfg->norm_h << 16) | cfg->ratio_h;
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SDE_REG_WRITE(hw, DNSC_BLUR_BLUR_RATIO_H, val);
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}
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if (cfg->flags_v & DNSC_BLUR_GAUS_FILTER) {
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val = (cfg->norm_v << 16) | cfg->ratio_v;
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SDE_REG_WRITE(hw, DNSC_BLUR_BLUR_RATIO_V, val);
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}
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if ((cfg->flags_v | cfg->flags_h) & DNSC_BLUR_GAUS_FILTER)
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_sde_hw_dnsc_blur_gaus_lut_setup(hw_dnsc_blur, cfg, lut_sel);
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}
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static void _sde_hw_dnsc_blur_setup(struct sde_hw_dnsc_blur *hw_dnsc_blur,
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struct sde_drm_dnsc_blur_cfg *cfg, u32 lut_sel)
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{
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struct sde_hw_blk_reg_map *hw = &hw_dnsc_blur->hw;
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u32 opmode = 0;
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/* disable, when no scaling involved */
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if (!cfg || !(cfg->flags & DNSC_BLUR_EN)) {
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SDE_REG_WRITE(hw, DNSC_BLUR_OP_MODE, 0x0);
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return;
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}
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opmode = DNSC_BLUR_OPMODE_ENABLE;
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opmode |= (cfg->flags & DNSC_BLUR_RND_8B_EN) ? DNSC_BLUR_OPMODE_OUT_RND_8B_EN : 0;
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if (cfg->flags_h) {
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opmode |= DNSC_BLUR_OPMODE_DWNS_H_EN;
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opmode |= (cfg->flags_h & DNSC_BLUR_PCMN_FILTER) ? DNSC_BLUR_OPMODE_PCMN_H : 0;
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}
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if (cfg->flags_v) {
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opmode |= DNSC_BLUR_OPMODE_DWNS_V_EN;
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opmode |= (cfg->flags_v & DNSC_BLUR_PCMN_FILTER) ? DNSC_BLUR_OPMODE_PCMN_V : 0;
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}
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_sde_hw_dnsc_blur_filter_setup(hw_dnsc_blur, cfg, lut_sel);
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SDE_REG_WRITE(hw, DNSC_BLUR_OP_MODE, opmode);
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SDE_REG_WRITE(hw, DNSC_BLUR_OUT_IMG_SIZE, (cfg->dst_height << 16) | cfg->dst_width);
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SDE_REG_WRITE(hw, DNSC_BLUR_SRC_IMG_SIZE, (cfg->src_height << 16) | cfg->src_width);
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}
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static void _sde_hw_dnsc_blur_dither_setup(struct sde_hw_dnsc_blur *hw_dnsc_blur,
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struct sde_drm_dnsc_blur_cfg *cfg)
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{
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struct sde_hw_blk_reg_map *hw = &hw_dnsc_blur->hw;
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int i;
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u32 base, data, offset;
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if (_dnsc_blur_subblk_offset(hw_dnsc_blur, SDE_DNSC_BLUR_DITHER, &base))
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return;
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/* disable case */
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if (!cfg || !(cfg->flags & DNSC_BLUR_DITHER_EN)) {
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SDE_REG_WRITE(hw, DNSC_BLUR_DITHER_OP_MODE + base, 0x0);
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return;
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}
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data = (dither_depth_map[cfg->c0_bitdepth] & REG_MASK(2)) |
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((dither_depth_map[cfg->c1_bitdepth] & REG_MASK(2)) << 2) |
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((dither_depth_map[cfg->c2_bitdepth] & REG_MASK(2)) << 4) |
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((dither_depth_map[cfg->c3_bitdepth] & REG_MASK(2)) << 6) |
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((cfg->temporal_en) ? (1 << 8) : 0);
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SDE_REG_WRITE(hw, DNSC_BLUR_DITHER_BITDEPTH + base, data);
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offset = DNSC_BLUR_DITHER_MATRIX_ROW0;
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for (i = 0; i < DNSC_BLUR_DITHER_MATRIX_SZ - 3; i += 4) {
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data = (cfg->dither_matrix[i] & REG_MASK(4)) |
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((cfg->dither_matrix[i + 1] & REG_MASK(4)) << 4) |
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((cfg->dither_matrix[i + 2] & REG_MASK(4)) << 8) |
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((cfg->dither_matrix[i + 3] & REG_MASK(4)) << 12);
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SDE_REG_WRITE(hw, base + offset, data);
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offset += 4;
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}
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data = BIT(0);
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data |= (cfg->dither_flags & DNSC_BLUR_DITHER_LUMA_MODE) ? BIT(4) : 0;
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SDE_REG_WRITE(hw, DNSC_BLUR_DITHER_OP_MODE + base, data);
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}
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static void _sde_hw_dnsc_blur_bind_pingpong_blk(struct sde_hw_dnsc_blur *hw_dnsc_blur,
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bool enable, const enum sde_pingpong pp, bool cwb)
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{
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struct sde_hw_blk_reg_map *hw = &hw_dnsc_blur->hw;
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int mux_cfg;
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if (enable && (pp < PINGPONG_0 || pp >= PINGPONG_MAX)) {
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SDE_ERROR("invalid args enable:%d pp:%d\n", enable, pp - PINGPONG_0);
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return;
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}
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if (cwb && pp < PINGPONG_CWB_0) {
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SDE_ERROR("invalid pp:%d for cwb\n", pp - PINGPONG_0);
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return;
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}
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if (enable)
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mux_cfg = cwb ? (pp < PINGPONG_CWB_2 ? 0xd : 0xb) : (pp - PINGPONG_0) & 0x7;
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else
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mux_cfg = 0xF;
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SDE_REG_WRITE(hw, DNSC_BLUR_MUX, mux_cfg);
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}
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static void _setup_dnsc_blur_ops(struct sde_hw_dnsc_blur_ops *ops, unsigned long features)
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{
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ops->setup_dnsc_blur = _sde_hw_dnsc_blur_setup;
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ops->setup_dither = _sde_hw_dnsc_blur_dither_setup;
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ops->bind_pingpong_blk = _sde_hw_dnsc_blur_bind_pingpong_blk;
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}
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struct sde_hw_blk_reg_map *sde_hw_dnsc_blur_init(enum sde_dnsc_blur idx,
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void __iomem *addr, struct sde_mdss_cfg *m)
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{
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struct sde_hw_dnsc_blur *c;
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struct sde_dnsc_blur_cfg *cfg;
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if (!addr || !m)
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return ERR_PTR(-EINVAL);
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c = kzalloc(sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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cfg = _dnsc_blur_offset(idx, m, addr, &c->hw);
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if (IS_ERR_OR_NULL(cfg)) {
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kfree(c);
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return ERR_PTR(-EINVAL);
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}
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c->idx = idx;
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c->caps = cfg;
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_setup_dnsc_blur_ops(&c->ops, c->caps->features);
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sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
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c->hw.blk_off + c->hw.length, c->hw.xin_id);
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if (cfg->sblk->gaus_lut.base && cfg->sblk->gaus_lut.len)
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sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->sblk->gaus_lut.name,
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c->hw.blk_off + cfg->sblk->gaus_lut.base,
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c->hw.blk_off + cfg->sblk->gaus_lut.base +
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cfg->sblk->gaus_lut.len, c->hw.xin_id);
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if (cfg->sblk->dither.base && cfg->sblk->dither.len)
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sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->sblk->dither.name,
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c->hw.blk_off + cfg->sblk->dither.base,
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c->hw.blk_off + cfg->sblk->dither.base +
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cfg->sblk->dither.len, c->hw.xin_id);
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return &c->hw;
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}
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void sde_hw_dnsc_blur_destroy(struct sde_hw_blk_reg_map *hw)
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{
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if (hw)
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kfree(to_sde_hw_dnsc_blur(hw));
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}
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