9c3a4825b8
This change removes tx_wait during DMS for targets which have dsc_hw_rev_2. For targets with dsc_hw_rev_1, during DMS the tx_wait is needed since DSC registers are not double buffered and frame trigger needs to be serialized to avoid pp_timeout issues. Change-Id: Icf3c0e0ed0cf9369db634419cfb28fcccbe88b8b Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com> Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
47 lines
1.4 KiB
C
47 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved.
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*/
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#ifndef __SDE_ENCODER_DCE_H__
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#define __SDE_ENCODER_DCE_H__
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#include "sde_encoder.h"
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/**
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* sde_encoder_dce_set_bpp : set src_bpp and target_bpp in sde_crtc
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* @msm_mode_info: Mode info
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* @crtc: Pointer to drm crtc structure
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*/
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void sde_encoder_dce_set_bpp(
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struct msm_mode_info mode_info, struct drm_crtc *crtc);
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/**
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* sde_encoder_dce_disable : function to disable compression
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* @sde_enc: pointer to virtual encoder structure
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*/
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void sde_encoder_dce_disable(struct sde_encoder_virt *sde_enc);
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/**
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* sde_encoder_dce_setup : function to configure compression block
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* @sde_enc: pointer to virtual encoder structure
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* @params: pointer to kickoff params
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*/
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int sde_encoder_dce_setup(struct sde_encoder_virt *sde_enc,
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struct sde_encoder_kickoff_params *params);
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/**
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* sde_encoder_dce_flush :function to flush the compression configuration
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* @sde_enc: pointer to virtual encoder structure
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*/
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void sde_encoder_dce_flush(struct sde_encoder_virt *sde_enc);
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/**
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* sde_encoder_has_dsc_hw_rev_2 :checks if dsc_hw_rev_1_2 feature is enabled
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* @sde_enc: pointer to virtual encoder structure
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*/
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bool sde_encoder_has_dsc_hw_rev_2(struct sde_encoder_virt *sde_enc);
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#endif /* __SDE_ENCODER_DCE_H__ */
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