0d6245c0ac
1. Assert if length received from FW is not equal to the expected length 2. Count the number of PPDU stats received by host and print in "iwpriv athX txrx_stats 260" 3. Optimize the PPDU stats tag mask sent to FW for enhanced stats enabling Change-Id: I60019de93bb3914955a03546504efc820c960746 CRs-Fixed: 2170704
877 lines
25 KiB
C
877 lines
25 KiB
C
/*
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* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
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*
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* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* This file was originally distributed by Qualcomm Atheros, Inc.
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* under proprietary terms before Copyright ownership was assigned
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* to the Linux Foundation.
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*/
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/**
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* @file cdp_txrx_stats_struct.h
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* @brief Define the host data path stats API functions
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* called by the host control SW and the OS interface module
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*/
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#ifndef _CDP_TXRX_STATS_STRUCT_H_
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#define _CDP_TXRX_STATS_STRUCT_H_
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#ifndef CONFIG_WIN
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#include <wlan_defs.h>
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#endif
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#define TXRX_STATS_LEVEL_OFF 0
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#define TXRX_STATS_LEVEL_BASIC 1
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#define TXRX_STATS_LEVEL_FULL 2
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#define BSS_CHAN_INFO_READ 1
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#define BSS_CHAN_INFO_READ_AND_CLEAR 2
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#define TX_FRAME_TYPE_DATA 0
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#define TX_FRAME_TYPE_MGMT 1
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#define TX_FRAME_TYPE_BEACON 2
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#ifndef TXRX_STATS_LEVEL
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#define TXRX_STATS_LEVEL TXRX_STATS_LEVEL_BASIC
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#endif
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/* 1 additional MCS is for invalid values */
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#define MAX_MCS (12 + 1)
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#define MAX_MCS_11A 8
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#define MAX_MCS_11B 7
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#define MAX_MCS_11AC 12
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/* 1 additional GI is for invalid values */
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#define MAX_GI (4 + 1)
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#define SS_COUNT 8
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#define MAX_BW 7
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#define MAX_RECEPTION_TYPES 4
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/* WME stream classes */
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#define WME_AC_BE 0 /* best effort */
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#define WME_AC_BK 1 /* background */
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#define WME_AC_VI 2 /* video */
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#define WME_AC_VO 3 /* voice */
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#define WME_AC_MAX 4 /* MAX AC Value */
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#define CDP_MAX_RX_RINGS 4
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/*
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* Number of TLVs sent by FW. Needs to reflect
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* HTT_PPDU_STATS_MAX_TAG declared in FW
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*/
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#define CDP_PPDU_STATS_MAX_TAG 14
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/* Different Packet Types */
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enum cdp_packet_type {
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DOT11_A = 0,
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DOT11_B = 1,
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DOT11_N = 2,
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DOT11_AC = 3,
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DOT11_AX = 4,
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DOT11_MAX = 5,
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};
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/* packet info */
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struct cdp_pkt_info {
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/*no of packets*/
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uint32_t num;
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/* total no of bytes */
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uint64_t bytes;
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};
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/* Tx Stats */
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struct cdp_tx_stats {
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/* Pkt Info for which completions were received */
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struct cdp_pkt_info comp_pkt;
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/* Unicast Packet Count */
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struct cdp_pkt_info ucast;
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/* Multicast Packet Count */
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struct cdp_pkt_info mcast;
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/* Broadcast Packet Count*/
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struct cdp_pkt_info bcast;
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/*NAWDS Multicast Packet Count */
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struct cdp_pkt_info nawds_mcast;
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/*NAWDS Multicast Drop Count */
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uint32_t nawds_mcast_drop;
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/* Successful Tx Packets */
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struct cdp_pkt_info tx_success;
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/* Total Tx failure */
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uint32_t tx_failed;
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/* Total Packets as ofdma*/
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uint32_t ofdma;
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/* Packets in STBC */
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uint32_t stbc;
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/* Packets in LDPC */
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uint32_t ldpc;
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/* Packet retries */
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uint32_t retries;
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/* Number of MSDUs with no MSDU level aggregation */
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uint32_t non_amsdu_cnt;
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/* Number of MSDUs part of AMSDU*/
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uint32_t amsdu_cnt;
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/* Tx Rate */
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uint32_t tx_rate;
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/* RSSI of last packet */
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uint32_t last_ack_rssi;
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/* Packet Type */
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struct {
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/* MCS Count */
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uint32_t mcs_count[MAX_MCS];
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} pkt_type[DOT11_MAX];
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/* SGI count */
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uint32_t sgi_count[MAX_GI];
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/* Packet count for different num_spatial_stream values */
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uint32_t nss[SS_COUNT];
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/* Packet Count for different bandwidths */
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uint32_t bw[MAX_BW];
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/* Wireless Multimedia type Count */
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uint32_t wme_ac_type[WME_AC_MAX];
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/* Wireless Multimedia type Count */
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uint32_t excess_retries_per_ac[WME_AC_MAX];
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/* Packets dropped on the Tx side */
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struct {
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/* Discarded by firmware */
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uint32_t fw_rem;
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/* firmware_discard_untransmitted */
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uint32_t fw_rem_notx;
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/* firmware_discard_transmitted */
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uint32_t fw_rem_tx;
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/* aged out in mpdu/msdu queues*/
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uint32_t age_out;
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} dropped;
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};
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/* Rx Level Stats */
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struct cdp_rx_stats {
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/* Total packets sent up the stack */
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struct cdp_pkt_info to_stack;
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/* Packets received on the reo ring */
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struct cdp_pkt_info rcvd_reo[CDP_MAX_RX_RINGS];
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/* Total unicast packets */
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struct cdp_pkt_info unicast;
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/* Total multicast packets */
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struct cdp_pkt_info multicast;
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/* Broadcast Packet Count*/
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struct cdp_pkt_info bcast;
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/* WDS packets received */
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struct cdp_pkt_info wds;
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/* Raw Pakets received */
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struct cdp_pkt_info raw;
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/* Total multicast packets */
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struct cdp_pkt_info nawds_mcast_drop;
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struct {
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/* Intra BSS packets received */
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struct cdp_pkt_info pkts;
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struct cdp_pkt_info fail;
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} intra_bss;
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/* Errors */
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struct {
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/* Rx MIC errors */
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uint32_t mic_err;
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/* Rx Decryption Errors */
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uint32_t decrypt_err;
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} err;
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/* Wireless Multimedia type Count */
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uint32_t wme_ac_type[WME_AC_MAX];
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/* Reception type os packets */
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uint32_t reception_type[MAX_RECEPTION_TYPES];
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/* Packet Type */
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struct {
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/* MCS Count */
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uint32_t mcs_count[MAX_MCS];
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} pkt_type[DOT11_MAX];
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/* SGI count */
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uint32_t sgi_count[MAX_GI];
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/* Packet count in spatiel Streams */
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uint32_t nss[SS_COUNT];
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/* Packet Count in different bandwidths */
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uint32_t bw[MAX_BW];
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/* Number of MSDUs with no MPDU level aggregation */
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uint32_t non_ampdu_cnt;
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/* Number of MSDUs part of AMSPU */
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uint32_t ampdu_cnt;
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/* Number of MSDUs with no MSDU level aggregation */
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uint32_t non_amsdu_cnt;
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/* Number of MSDUs part of AMSDU*/
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uint32_t amsdu_cnt;
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/* Number of bar received */
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uint32_t bar_recv_cnt;
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/* RSSI of received signal */
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uint32_t rssi;
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/*Rx rate */
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uint32_t rx_rate;
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};
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/* Tx ingress Stats */
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struct cdp_tx_ingress_stats {
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/* Total packets received for transmission */
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struct cdp_pkt_info rcvd;
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/* Tx packets processed*/
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struct cdp_pkt_info processed;
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/* Total packets passed Reinject handler */
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struct cdp_pkt_info reinject_pkts;
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/* Total packets passed to inspect handler */
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struct cdp_pkt_info inspect_pkts;
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/*NAWDS Multicast Packet Count */
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struct cdp_pkt_info nawds_mcast;
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/* Number of broadcast packets */
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struct cdp_pkt_info bcast;
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struct {
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/* Total Raw packets */
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struct cdp_pkt_info raw_pkt;
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/* DMA map error */
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uint32_t dma_map_error;
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} raw;
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/* TSO packets info */
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struct {
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/* No of segments in TSO packets */
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uint32_t num_seg;
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/* total no of TSO packets */
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struct cdp_pkt_info tso_pkt;
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/* TSO packets dropped by host */
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uint32_t dropped_host;
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/* TSO packets dropped by target */
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uint32_t dropped_target;
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} tso;
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/* Scatter Gather packet info */
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struct {
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/* Total scatter gather packets */
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struct cdp_pkt_info sg_pkt;
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/* SG packets dropped by host */
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uint32_t dropped_host;
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/* SG packets dropped by target */
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uint32_t dropped_target;
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/* Dma map error */
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uint32_t dma_map_error;
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} sg;
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/* Multicast Enhancement packets info */
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struct {
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/* total no of multicast conversion packets */
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struct cdp_pkt_info mcast_pkt;
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/* packets dropped due to map error */
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uint32_t dropped_map_error;
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/* packets dropped due to self Mac address */
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uint32_t dropped_self_mac;
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/* Packets dropped due to send fail */
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uint32_t dropped_send_fail;
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/* total unicast packets transmitted */
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uint32_t ucast;
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/* Segment allocation failure */
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uint32_t fail_seg_alloc;
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/* NBUF clone failure */
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uint32_t clone_fail;
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} mcast_en;
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/* Packets dropped on the Tx side */
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struct {
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/* Total scatter gather packets */
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struct cdp_pkt_info dropped_pkt;
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/* Desc Not Available */
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uint32_t desc_na;
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/* Ring Full */
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uint32_t ring_full;
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/* Hwenqueue failed */
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uint32_t enqueue_fail;
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/* DMA failed */
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uint32_t dma_error;
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/* Resource Full: Congestion Control */
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uint32_t res_full;
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} dropped;
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/* Mesh packets info */
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struct {
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/* packets sent to fw */
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uint32_t exception_fw;
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/* packets completions received from fw */
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uint32_t completion_fw;
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} mesh;
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/*Number of packets classified by CCE*/
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uint32_t cce_classified;
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/*Number of raw packets classified by CCE*/
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uint32_t cce_classified_raw;
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};
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struct cdp_vdev_stats {
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/* Tx ingress stats */
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struct cdp_tx_ingress_stats tx_i;
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/* CDP Tx Stats */
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struct cdp_tx_stats tx;
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/* CDP Rx Stats */
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struct cdp_rx_stats rx;
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};
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struct cdp_peer_stats {
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/* CDP Tx Stats */
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struct cdp_tx_stats tx;
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/* CDP Rx Stats */
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struct cdp_rx_stats rx;
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};
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/* Tx completions per interrupt */
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struct cdp_hist_tx_comp {
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uint32_t pkts_1;
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uint32_t pkts_2_20;
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uint32_t pkts_21_40;
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uint32_t pkts_41_60;
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uint32_t pkts_61_80;
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uint32_t pkts_81_100;
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uint32_t pkts_101_200;
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uint32_t pkts_201_plus;
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};
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/* Rx ring descriptors reaped per interrupt */
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struct cdp_hist_rx_ind {
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uint32_t pkts_1;
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uint32_t pkts_2_20;
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uint32_t pkts_21_40;
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uint32_t pkts_41_60;
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uint32_t pkts_61_80;
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uint32_t pkts_81_100;
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uint32_t pkts_101_200;
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uint32_t pkts_201_plus;
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};
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struct cdp_pdev_stats {
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/* packets dropped on rx */
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struct {
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/* packets dropped because nsdu_done bit not set */
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uint32_t msdu_not_done;
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/* Multicast Echo check */
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uint32_t mec;
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/* Mesh Filtered packets */
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uint32_t mesh_filter;
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} dropped;
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struct {
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/* total packets replnished */
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struct cdp_pkt_info pkts;
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/* rxdma errors */
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uint32_t rxdma_err;
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/* nbuf alloc failed */
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uint32_t nbuf_alloc_fail;
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/* Mapping failure */
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uint32_t map_err;
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/* x86 failures */
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uint32_t x86_fail;
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/* low threshold interrupts */
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uint32_t low_thresh_intrs;
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} replenish;
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/* Rx Raw Packets */
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uint32_t rx_raw_pkts;
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/* Mesh Rx Stats Alloc fail */
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uint32_t mesh_mem_alloc;
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/* Rx errors */
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struct {
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/* desc alloc failed errors */
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uint32_t desc_alloc_fail;
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} err;
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/* buffers added back in freelist */
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uint32_t buf_freelist;
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/* Tx Ingress stats */
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struct cdp_tx_ingress_stats tx_i;
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/* CDP Tx Stats */
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struct cdp_tx_stats tx;
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/* CDP Rx Stats */
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struct cdp_rx_stats rx;
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/* Number of Tx completions per interrupt */
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struct cdp_hist_tx_comp tx_comp_histogram;
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/* Number of Rx ring descriptors reaped per interrupt */
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struct cdp_hist_rx_ind rx_ind_histogram;
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uint64_t ppdu_stats_counter[CDP_PPDU_STATS_MAX_TAG];
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};
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#ifndef BIG_ENDIAN_HOST
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typedef struct {
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uint64_t pkts;
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uint64_t bytes;
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} ol_txrx_stats_elem;
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#else
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struct ol_txrx_elem_t {
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uint64_t pkts;
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uint64_t bytes;
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};
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typedef struct ol_txrx_elem_t ol_txrx_stats_elem;
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#endif
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#ifndef CONFIG_MCL
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/**
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* @brief data stats published by the host txrx layer
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*/
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struct ol_txrx_stats {
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struct {
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/* MSDUs received from the stack */
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ol_txrx_stats_elem from_stack;
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/* MSDUs successfully sent across the WLAN */
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ol_txrx_stats_elem delivered;
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struct {
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/* MSDUs that the host did not accept */
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ol_txrx_stats_elem host_reject;
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/* MSDUs which could not be downloaded to the target */
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ol_txrx_stats_elem download_fail;
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/*
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* MSDUs which the target discarded
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* (lack of mem or old age)
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*/
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ol_txrx_stats_elem target_discard;
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/*
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* MSDUs which the target sent but couldn't get
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* an ack for
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*/
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ol_txrx_stats_elem no_ack;
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/* MSDUs dropped in NSS-FW */
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ol_txrx_stats_elem nss_ol_dropped;
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} dropped;
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u_int32_t desc_in_use;
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u_int32_t desc_alloc_fails;
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u_int32_t ce_ring_full;
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u_int32_t dma_map_error;
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/* MSDUs given to the txrx layer by the management stack */
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ol_txrx_stats_elem mgmt;
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struct {
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/* TSO applied jumbo packets received from NW Stack */
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ol_txrx_stats_elem tso_pkts;
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/* Non - TSO packets */
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ol_txrx_stats_elem non_tso_pkts;
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/* TSO packets : Dropped during TCP segmentation*/
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ol_txrx_stats_elem tso_dropped;
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/* TSO Descriptors */
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u_int32_t tso_desc_cnt;
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} tso;
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struct {
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/* TSO applied jumbo packets received from NW Stack */
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ol_txrx_stats_elem sg_pkts;
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/* Non - TSO packets */
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ol_txrx_stats_elem non_sg_pkts;
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/* TSO packets : Dropped during TCP segmentation*/
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ol_txrx_stats_elem sg_dropped;
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/* TSO Descriptors */
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u_int32_t sg_desc_cnt;
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} sg;
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struct {
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/* packets enqueued for flow control */
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u_int32_t fl_ctrl_enqueue;
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/* packets discarded for flow control is full */
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u_int32_t fl_ctrl_discard;
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/* packets sent to CE without flow control */
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u_int32_t fl_ctrl_avoid;
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} fl_ctrl;
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} tx;
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struct {
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/* MSDUs given to the OS shim */
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ol_txrx_stats_elem delivered;
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/* MSDUs forwarded from the rx path to the tx path */
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ol_txrx_stats_elem forwarded;
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/* MSDUs in which ipv4 chksum error detected by HW */
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ol_txrx_stats_elem ipv4_cksum_err;
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/* MSDUs in which tcp chksum error detected by HW */
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ol_txrx_stats_elem tcp_ipv4_cksum_err;
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/* MSDUs in which udp chksum error detected by HW */
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ol_txrx_stats_elem udp_ipv4_cksum_err;
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/* MSDUs in which tcp V6 chksum error detected by HW */
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ol_txrx_stats_elem tcp_ipv6_cksum_err;
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/* MSDUs in which UDP V6 chksum error detected by HW */
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ol_txrx_stats_elem udp_ipv6_cksum_err;
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} rx;
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|
struct {
|
|
/* Number of mcast received for conversion */
|
|
u_int32_t num_me_rcvd;
|
|
/* Number of unicast sent as part of mcast conversion */
|
|
u_int32_t num_me_ucast;
|
|
/* Number of multicast frames dropped due to dma_map failure */
|
|
u_int32_t num_me_dropped_m;
|
|
/*
|
|
* Number of multicast frames dropped due to allocation
|
|
* failure
|
|
*/
|
|
u_int32_t num_me_dropped_a;
|
|
/* Number of multicast frames dropped due to internal failure */
|
|
u_int32_t num_me_dropped_i;
|
|
/* Number of me buf currently in use */
|
|
u_int32_t num_me_buf;
|
|
/* Number of me buf frames to self mac address */
|
|
u_int32_t num_me_dropped_s;
|
|
/* Number of me buf in use in non pool based allocation*/
|
|
u_int32_t num_me_nonpool;
|
|
/* Number of me buf allocated using non pool based allocation*/
|
|
u_int32_t num_me_nonpool_count;
|
|
} mcast_enhance;
|
|
};
|
|
|
|
struct ol_ath_dbg_rx_rssi {
|
|
A_UINT8 rx_rssi_pri20;
|
|
A_UINT8 rx_rssi_sec20;
|
|
A_UINT8 rx_rssi_sec40;
|
|
A_UINT8 rx_rssi_sec80;
|
|
};
|
|
|
|
struct ol_ath_radiostats {
|
|
A_UINT64 tx_beacon;
|
|
A_UINT32 be_nobuf;
|
|
A_UINT32 tx_buf_count;
|
|
A_UINT32 tx_packets;
|
|
A_UINT32 rx_packets;
|
|
A_INT32 tx_mgmt;
|
|
A_UINT32 tx_num_data;
|
|
A_UINT32 rx_num_data;
|
|
A_INT32 rx_mgmt;
|
|
A_UINT32 rx_num_mgmt;
|
|
A_UINT32 rx_num_ctl;
|
|
A_UINT32 tx_rssi;
|
|
A_UINT32 tx_mcs[10];
|
|
A_UINT32 rx_mcs[10];
|
|
A_UINT32 rx_rssi_comb;
|
|
struct ol_ath_dbg_rx_rssi rx_rssi_chain0;
|
|
struct ol_ath_dbg_rx_rssi rx_rssi_chain1;
|
|
struct ol_ath_dbg_rx_rssi rx_rssi_chain2;
|
|
struct ol_ath_dbg_rx_rssi rx_rssi_chain3;
|
|
A_UINT64 rx_bytes;
|
|
A_UINT64 tx_bytes;
|
|
A_UINT32 tx_compaggr;
|
|
A_UINT32 rx_aggr;
|
|
A_UINT32 tx_bawadv;
|
|
A_UINT32 tx_compunaggr;
|
|
A_UINT32 rx_overrun;
|
|
A_UINT32 rx_badcrypt;
|
|
A_UINT32 rx_badmic;
|
|
A_UINT32 rx_crcerr;
|
|
A_UINT32 rx_phyerr;
|
|
A_UINT32 ackRcvBad;
|
|
A_UINT32 rtsBad;
|
|
A_UINT32 rtsGood;
|
|
A_UINT32 fcsBad;
|
|
A_UINT32 noBeacons;
|
|
A_UINT32 mib_int_count;
|
|
A_UINT32 rx_looplimit_start;
|
|
A_UINT32 rx_looplimit_end;
|
|
A_UINT8 ap_stats_tx_cal_enable;
|
|
A_UINT32 tgt_asserts;
|
|
A_INT16 chan_nf;
|
|
A_UINT32 rx_last_msdu_unset_cnt;
|
|
A_INT16 chan_nf_sec80;
|
|
A_UINT64 wmi_tx_mgmt;
|
|
A_UINT64 wmi_tx_mgmt_completions;
|
|
A_UINT32 wmi_tx_mgmt_completion_err;
|
|
A_UINT32 peer_delete_req;
|
|
A_UINT32 peer_delete_resp;
|
|
A_UINT32 rx_mgmt_rssi_drop;
|
|
A_UINT32 tx_retries;
|
|
A_UINT32 rx_data_bytes;
|
|
A_UINT32 tx_frame_count;
|
|
A_UINT32 rx_frame_count;
|
|
A_UINT32 rx_clear_count;
|
|
A_UINT32 cycle_count;
|
|
A_UINT32 phy_err_count;
|
|
A_UINT32 chan_tx_pwr;
|
|
};
|
|
|
|
/*
|
|
* Enumeration of PDEV Configuration parameter
|
|
*/
|
|
enum _ol_ath_param_t {
|
|
OL_ATH_PARAM_TXCHAINMASK = 1,
|
|
OL_ATH_PARAM_RXCHAINMASK = 2,
|
|
OL_ATH_PARAM_AMPDU = 6,
|
|
OL_ATH_PARAM_AMPDU_LIMIT = 7,
|
|
OL_ATH_PARAM_AMPDU_SUBFRAMES = 8,
|
|
OL_ATH_PARAM_TXPOWER_LIMIT2G = 12,
|
|
OL_ATH_PARAM_TXPOWER_LIMIT5G = 13,
|
|
OL_ATH_PARAM_LDPC = 32,
|
|
OL_ATH_PARAM_VOW_EXT_STATS = 45,
|
|
OL_ATH_PARAM_DYN_TX_CHAINMASK = 73,
|
|
OL_ATH_PARAM_BURST_ENABLE = 77,
|
|
OL_ATH_PARAM_BURST_DUR = 78,
|
|
OL_ATH_PARAM_BCN_BURST = 80,
|
|
OL_ATH_PARAM_DCS = 82,
|
|
#if UMAC_SUPPORT_PERIODIC_PERFSTATS
|
|
OL_ATH_PARAM_PRDPERFSTAT_THRPUT_ENAB = 83,
|
|
OL_ATH_PARAM_PRDPERFSTAT_THRPUT_WIN = 84,
|
|
OL_ATH_PARAM_PRDPERFSTAT_THRPUT = 85,
|
|
OL_ATH_PARAM_PRDPERFSTAT_PER_ENAB = 86,
|
|
OL_ATH_PARAM_PRDPERFSTAT_PER_WIN = 87,
|
|
OL_ATH_PARAM_PRDPERFSTAT_PER = 88,
|
|
#endif
|
|
/* UMAC_SUPPORT_PERIODIC_PERFSTATS */
|
|
OL_ATH_PARAM_TOTAL_PER = 89,
|
|
/* set manual rate for rts frame */
|
|
OL_ATH_PARAM_RTS_CTS_RATE = 92,
|
|
/* co channel interference threshold level */
|
|
OL_ATH_PARAM_DCS_COCH_THR = 93,
|
|
/* transmit error threshold */
|
|
OL_ATH_PARAM_DCS_TXERR_THR = 94,
|
|
/* phy error threshold */
|
|
OL_ATH_PARAM_DCS_PHYERR_THR = 95,
|
|
/*
|
|
* The IOCTL number is 114, it is made 114, inorder to make the IOCTL
|
|
* number same as Direct-attach IOCTL.
|
|
* Please, don't change number. This IOCTL gets the Interface code path
|
|
* it should be either DIRECT-ATTACH or OFF-LOAD.
|
|
*/
|
|
OL_ATH_PARAM_GET_IF_ID = 114,
|
|
/* Enable Acs back Ground Channel selection Scan timer in AP mode*/
|
|
OL_ATH_PARAM_ACS_ENABLE_BK_SCANTIMEREN = 118,
|
|
/* ACS scan timer value in Seconds */
|
|
OL_ATH_PARAM_ACS_SCANTIME = 119,
|
|
/* Negligence Delta RSSI between two channel */
|
|
OL_ATH_PARAM_ACS_RSSIVAR = 120,
|
|
/* Negligence Delta Channel load between two channel*/
|
|
OL_ATH_PARAM_ACS_CHLOADVAR = 121,
|
|
/* Enable Limited OBSS check */
|
|
OL_ATH_PARAM_ACS_LIMITEDOBSS = 122,
|
|
/* Acs control flag for Scan timer */
|
|
OL_ATH_PARAM_ACS_CTRLFLAG = 123,
|
|
/* Acs Run time Debug level*/
|
|
OL_ATH_PARAM_ACS_DEBUGTRACE = 124,
|
|
OL_ATH_PARAM_SET_FW_HANG_ID = 137,
|
|
/* Radio type 1:11ac 0:11abgn */
|
|
OL_ATH_PARAM_RADIO_TYPE = 138,
|
|
OL_ATH_PARAM_IGMPMLD_OVERRIDE, /* IGMP/MLD packet override */
|
|
OL_ATH_PARAM_IGMPMLD_TID, /* IGMP/MLD packet TID no */
|
|
OL_ATH_PARAM_ARPDHCP_AC_OVERRIDE,
|
|
OL_ATH_PARAM_NON_AGG_SW_RETRY_TH,
|
|
OL_ATH_PARAM_AGG_SW_RETRY_TH,
|
|
/* Dont change this number it as per sync with DA
|
|
Blocking certian channel from ic channel list */
|
|
OL_ATH_PARAM_DISABLE_DFS = 144,
|
|
OL_ATH_PARAM_ENABLE_AMSDU = 145,
|
|
OL_ATH_PARAM_ENABLE_AMPDU = 146,
|
|
OL_ATH_PARAM_STA_KICKOUT_TH,
|
|
OL_ATH_PARAM_WLAN_PROF_ENABLE,
|
|
OL_ATH_PARAM_LTR_ENABLE,
|
|
OL_ATH_PARAM_LTR_AC_LATENCY_BE = 150,
|
|
OL_ATH_PARAM_LTR_AC_LATENCY_BK,
|
|
OL_ATH_PARAM_LTR_AC_LATENCY_VI,
|
|
OL_ATH_PARAM_LTR_AC_LATENCY_VO,
|
|
OL_ATH_PARAM_LTR_AC_LATENCY_TIMEOUT,
|
|
OL_ATH_PARAM_LTR_TX_ACTIVITY_TIMEOUT = 155,
|
|
OL_ATH_PARAM_LTR_SLEEP_OVERRIDE,
|
|
OL_ATH_PARAM_LTR_RX_OVERRIDE,
|
|
OL_ATH_PARAM_L1SS_ENABLE,
|
|
OL_ATH_PARAM_DSLEEP_ENABLE,
|
|
/* radar error threshold */
|
|
OL_ATH_PARAM_DCS_RADAR_ERR_THR = 160,
|
|
/* Tx channel utilization due to AP's tx and rx */
|
|
OL_ATH_PARAM_DCS_USERMAX_CU_THR,
|
|
/* interference detection threshold */
|
|
OL_ATH_PARAM_DCS_INTR_DETECT_THR,
|
|
/* sampling window, default 10secs */
|
|
OL_ATH_PARAM_DCS_SAMPLE_WINDOW,
|
|
/* debug logs enable/disable */
|
|
OL_ATH_PARAM_DCS_DEBUG,
|
|
OL_ATH_PARAM_ANI_ENABLE = 165,
|
|
OL_ATH_PARAM_ANI_POLL_PERIOD,
|
|
OL_ATH_PARAM_ANI_LISTEN_PERIOD,
|
|
OL_ATH_PARAM_ANI_OFDM_LEVEL,
|
|
OL_ATH_PARAM_ANI_CCK_LEVEL,
|
|
OL_ATH_PARAM_DSCP_TID_MAP = 170,
|
|
OL_ATH_PARAM_TXPOWER_SCALE,
|
|
/* Phy error penalty */
|
|
OL_ATH_PARAM_DCS_PHYERR_PENALTY,
|
|
#if ATH_SUPPORT_DSCP_OVERRIDE
|
|
/* set/get TID for sending HMMC packets */
|
|
OL_ATH_PARAM_HMMC_DSCP_TID_MAP,
|
|
/* set/get DSCP mapping override */
|
|
OL_ATH_PARAM_DSCP_OVERRIDE,
|
|
/* set/get HMMC-DSCP mapping override */
|
|
OL_ATH_PARAM_HMMC_DSCP_OVERRIDE = 175,
|
|
#endif
|
|
#if ATH_RX_LOOPLIMIT_TIMER
|
|
OL_ATH_PARAM_LOOPLIMIT_NUM,
|
|
#endif
|
|
OL_ATH_PARAM_ANTENNA_GAIN_2G,
|
|
OL_ATH_PARAM_ANTENNA_GAIN_5G,
|
|
OL_ATH_PARAM_RX_FILTER,
|
|
#if ATH_SUPPORT_HYFI_ENHANCEMENTS
|
|
OL_ATH_PARAM_BUFF_THRESH = 180,
|
|
OL_ATH_PARAM_BLK_REPORT_FLOOD,
|
|
OL_ATH_PARAM_DROP_STA_QUERY,
|
|
#endif
|
|
OL_ATH_PARAM_QBOOST,
|
|
OL_ATH_PARAM_SIFS_FRMTYPE,
|
|
OL_ATH_PARAM_SIFS_UAPSD = 185,
|
|
OL_ATH_PARAM_FW_RECOVERY_ID,
|
|
OL_ATH_PARAM_RESET_OL_STATS,
|
|
OL_ATH_PARAM_AGGR_BURST,
|
|
/* Number of deauth sent in consecutive rx_peer_invalid */
|
|
OL_ATH_PARAM_DEAUTH_COUNT,
|
|
OL_ATH_PARAM_BLOCK_INTERBSS = 190,
|
|
/* Firmware reset control for Bmiss / timeout / reset */
|
|
OL_ATH_PARAM_FW_DISABLE_RESET,
|
|
OL_ATH_PARAM_MSDU_TTL,
|
|
OL_ATH_PARAM_PPDU_DURATION,
|
|
OL_ATH_PARAM_SET_TXBF_SND_PERIOD,
|
|
OL_ATH_PARAM_ALLOW_PROMISC = 195,
|
|
OL_ATH_PARAM_BURST_MODE,
|
|
OL_ATH_PARAM_DYN_GROUPING,
|
|
OL_ATH_PARAM_DPD_ENABLE,
|
|
OL_ATH_PARAM_DBGLOG_RATELIM,
|
|
/* firmware should intimate us about ps state change for node */
|
|
OL_ATH_PARAM_PS_STATE_CHANGE = 200,
|
|
OL_ATH_PARAM_MCAST_BCAST_ECHO,
|
|
/* OBSS RSSI threshold for 20/40 coexistance */
|
|
OL_ATH_PARAM_OBSS_RSSI_THRESHOLD,
|
|
/* Link/node RX RSSI threshold for 20/40 coexistance */
|
|
OL_ATH_PARAM_OBSS_RX_RSSI_THRESHOLD,
|
|
#if ATH_CHANNEL_BLOCKING
|
|
OL_ATH_PARAM_ACS_BLOCK_MODE = 205,
|
|
#endif
|
|
OL_ATH_PARAM_ACS_TX_POWER_OPTION,
|
|
/*
|
|
* Default Antenna Polarization MSB 8 bits (24:31) specifying
|
|
* enable/disable ; LSB 24 bits (0:23) antenna mask value
|
|
*/
|
|
OL_ATH_PARAM_ANT_POLARIZATION,
|
|
/* rate limit mute type error prints */
|
|
OL_ATH_PARAM_PRINT_RATE_LIMIT,
|
|
OL_ATH_PARAM_PDEV_RESET, /* Reset FW PDEV*/
|
|
/* Do not crash host when target assert happened*/
|
|
OL_ATH_PARAM_FW_DUMP_NO_HOST_CRASH = 210,
|
|
/* Consider OBSS non-erp to change to long slot*/
|
|
OL_ATH_PARAM_CONSIDER_OBSS_NON_ERP_LONG_SLOT = 211,
|
|
OL_ATH_PARAM_STATS_FC,
|
|
OL_ATH_PARAM_QFLUSHINTERVAL,
|
|
OL_ATH_PARAM_TOTAL_Q_SIZE,
|
|
OL_ATH_PARAM_TOTAL_Q_SIZE_RANGE0,
|
|
OL_ATH_PARAM_TOTAL_Q_SIZE_RANGE1,
|
|
OL_ATH_PARAM_TOTAL_Q_SIZE_RANGE2,
|
|
OL_ATH_PARAM_TOTAL_Q_SIZE_RANGE3,
|
|
OL_ATH_PARAM_MIN_THRESHOLD,
|
|
OL_ATH_PARAM_MAX_Q_LIMIT,
|
|
OL_ATH_PARAM_MIN_Q_LIMIT,
|
|
OL_ATH_PARAM_CONG_CTRL_TIMER_INTV,
|
|
OL_ATH_PARAM_STATS_TIMER_INTV,
|
|
OL_ATH_PARAM_ROTTING_TIMER_INTV,
|
|
OL_ATH_PARAM_LATENCY_PROFILE,
|
|
OL_ATH_PARAM_HOSTQ_DUMP,
|
|
OL_ATH_PARAM_TIDQ_MAP,
|
|
OL_ATH_PARAM_DBG_ARP_SRC_ADDR, /* ARP DEBUG source address*/
|
|
OL_ATH_PARAM_DBG_ARP_DST_ADDR, /* ARP DEBUG destination address*/
|
|
OL_ATH_PARAM_ARP_DBG_CONF, /* ARP debug configuration */
|
|
OL_ATH_PARAM_DISABLE_STA_VAP_AMSDU, /* Disable AMSDU for station vap */
|
|
#if ATH_SUPPORT_DFS && ATH_SUPPORT_STA_DFS
|
|
OL_ATH_PARAM_STADFS_ENABLE = 300, /* STA DFS is enabled or not */
|
|
#endif
|
|
#if QCA_AIRTIME_FAIRNESS
|
|
OL_ATH_PARAM_ATF_STRICT_SCHED = 301,
|
|
OL_ATH_PARAM_ATF_GROUP_POLICY = 302,
|
|
#endif
|
|
#if DBDC_REPEATER_SUPPORT
|
|
OL_ATH_PARAM_PRIMARY_RADIO,
|
|
OL_ATH_PARAM_DBDC_ENABLE,
|
|
#endif
|
|
OL_ATH_PARAM_TXPOWER_DBSCALE,
|
|
OL_ATH_PARAM_CTL_POWER_SCALE,
|
|
#if QCA_AIRTIME_FAIRNESS
|
|
OL_ATH_PARAM_ATF_OBSS_SCHED = 307,
|
|
OL_ATH_PARAM_ATF_OBSS_SCALE = 308,
|
|
#endif
|
|
OL_ATH_PARAM_PHY_OFDM_ERR = 309,
|
|
OL_ATH_PARAM_PHY_CCK_ERR = 310,
|
|
OL_ATH_PARAM_FCS_ERR = 311,
|
|
OL_ATH_PARAM_CHAN_UTIL = 312,
|
|
#if DBDC_REPEATER_SUPPORT
|
|
OL_ATH_PARAM_CLIENT_MCAST,
|
|
#endif
|
|
OL_ATH_PARAM_EMIWAR_80P80 = 314,
|
|
OL_ATH_PARAM_BATCHMODE = 315,
|
|
OL_ATH_PARAM_PACK_AGGR_DELAY = 316,
|
|
#if UMAC_SUPPORT_ACFG
|
|
OL_ATH_PARAM_DIAG_ENABLE = 317,
|
|
#endif
|
|
#if ATH_SUPPORT_VAP_QOS
|
|
OL_ATH_PARAM_VAP_QOS = 318,
|
|
#endif
|
|
OL_ATH_PARAM_CHAN_STATS_TH = 319,
|
|
/* Passive scan is enabled or disabled */
|
|
OL_ATH_PARAM_PASSIVE_SCAN_ENABLE = 320,
|
|
OL_ATH_MIN_RSSI_ENABLE = 321,
|
|
OL_ATH_MIN_RSSI = 322,
|
|
OL_ATH_PARAM_ACS_2G_ALLCHAN = 323,
|
|
#if DBDC_REPEATER_SUPPORT
|
|
OL_ATH_PARAM_DELAY_STAVAP_UP = 324,
|
|
#endif
|
|
/* It is used to set the channel switch options */
|
|
OL_ATH_PARAM_CHANSWITCH_OPTIONS = 327,
|
|
OL_ATH_BTCOEX_ENABLE = 328,
|
|
OL_ATH_BTCOEX_WL_PRIORITY = 329,
|
|
OL_ATH_PARAM_TID_OVERRIDE_QUEUE_MAPPING = 330,
|
|
OL_ATH_PARAM_CAL_VER_CHECK = 331,
|
|
OL_ATH_PARAM_NO_VLAN = 332,
|
|
OL_ATH_PARAM_CCA_THRESHOLD = 333,
|
|
OL_ATH_PARAM_ATF_LOGGING = 334,
|
|
OL_ATH_PARAM_STRICT_DOTH = 335,
|
|
OL_ATH_PARAM_DISCONNECTION_TIMEOUT = 336,
|
|
OL_ATH_PARAM_RECONFIGURATION_TIMEOUT = 337,
|
|
OL_ATH_PARAM_CHANNEL_SWITCH_COUNT = 338,
|
|
OL_ATH_PARAM_ALWAYS_PRIMARY = 339,
|
|
OL_ATH_PARAM_FAST_LANE = 340,
|
|
OL_ATH_GET_BTCOEX_DUTY_CYCLE = 341,
|
|
OL_ATH_PARAM_SECONDARY_OFFSET_IE = 342,
|
|
OL_ATH_PARAM_WIDE_BAND_SUB_ELEMENT = 343,
|
|
OL_ATH_PARAM_PREFERRED_UPLINK = 344,
|
|
OL_ATH_PARAM_PRECAC_ENABLE = 345,
|
|
OL_ATH_PARAM_PRECAC_TIMEOUT = 346,
|
|
OL_ATH_COEX_VER_CFG = 347,
|
|
OL_ATH_PARAM_DUMP_TARGET = 348,
|
|
OL_ATH_PARAM_PDEV_TO_REO_DEST = 349,
|
|
OL_ATH_PARAM_DUMP_CHAINMASK_TABLES = 350,
|
|
OL_ATH_PARAM_DUMP_OBJECTS = 351,
|
|
OL_ATH_PARAM_ACS_SRLOADVAR = 352,
|
|
OL_ATH_PARAM_MGMT_RSSI_THRESHOLD = 353,
|
|
OL_ATH_PARAM_EXT_NSS_CAPABLE = 354,
|
|
OL_ATH_PARAM_MGMT_PDEV_STATS_TIMER = 355,
|
|
OL_ATH_PARAM_TXACKTIMEOUT = 356,
|
|
OL_ATH_PARAM_ICM_ACTIVE = 357,
|
|
OL_ATH_PARAM_NOMINAL_NOISEFLOOR = 358,
|
|
OL_ATH_PARAM_CHAN_INFO = 359,
|
|
OL_ATH_PARAM_ACS_RANK = 360,
|
|
OL_ATH_PARAM_TXCHAINSOFT = 361,
|
|
OL_ATH_PARAM_WIDE_BAND_SCAN = 362,
|
|
};
|
|
|
|
/* Enumeration of PDEV Configuration parameter */
|
|
enum _ol_hal_param_t {
|
|
OL_HAL_CONFIG_DMA_BEACON_RESPONSE_TIME = 0
|
|
};
|
|
#endif
|
|
|
|
/* Bitmasks for stats that can block */
|
|
#define EXT_TXRX_FW_STATS 0x0001
|
|
#endif
|