8fdc77b72c
New hardware header files for Napier E6. CRs-Fixed: 2033542 Change-Id: I996dbff402c2ba27c2e34ba89cdbb60101ae7d2d
490 lines
14 KiB
C
Executable File
490 lines
14 KiB
C
Executable File
/*
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* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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//
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// DO NOT EDIT! This file is automatically generated
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// These definitions are tied to a particular hardware layout
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#ifndef _REO_FLUSH_CACHE_H_
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#define _REO_FLUSH_CACHE_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "uniform_reo_cmd_header.h"
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// ################ START SUMMARY #################
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//
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// Dword Fields
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// 0 struct uniform_reo_cmd_header cmd_header;
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// 1 flush_addr_31_0[31:0]
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// 2 flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15]
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// 3 reserved_3a[31:0]
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// 4 reserved_4a[31:0]
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// 5 reserved_5a[31:0]
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// 6 reserved_6a[31:0]
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// 7 reserved_7a[31:0]
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// 8 reserved_8a[31:0]
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//
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// ################ END SUMMARY #################
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#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9
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struct reo_flush_cache {
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struct uniform_reo_cmd_header cmd_header;
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uint32_t flush_addr_31_0 : 32; //[31:0]
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uint32_t flush_addr_39_32 : 8, //[7:0]
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forward_all_mpdus_in_queue : 1, //[8]
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release_cache_block_index : 1, //[9]
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cache_block_resource_index : 2, //[11:10]
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flush_without_invalidate : 1, //[12]
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block_cache_usage_after_flush : 1, //[13]
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flush_entire_cache : 1, //[14]
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reserved_2b : 17; //[31:15]
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uint32_t reserved_3a : 32; //[31:0]
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uint32_t reserved_4a : 32; //[31:0]
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uint32_t reserved_5a : 32; //[31:0]
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uint32_t reserved_6a : 32; //[31:0]
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uint32_t reserved_7a : 32; //[31:0]
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uint32_t reserved_8a : 32; //[31:0]
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};
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/*
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struct uniform_reo_cmd_header cmd_header
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Consumer: REO
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Producer: SW
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Details for command execution tracking purposes.
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flush_addr_31_0
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Consumer: REO
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Producer: SW
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Address (lower 32 bits) of the descriptor to flush
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<legal all>
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flush_addr_39_32
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Consumer: REO
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Producer: SW
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Address (upper 8 bits) of the descriptor to flush
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<legal all>
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forward_all_mpdus_in_queue
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Is only allowed to be set when the flush address
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corresponds with a REO descriptor.
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When set, REO shall first forward all the MPDUs held in
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the indicated re-order queue, before flushing the descriptor
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from the cache.
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<legal all>
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release_cache_block_index
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Field not valid when Flush_entire_cache is set.
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If SW has previously used a blocking resource that it
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now wants to re-use for this command, this bit shall be set.
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It prevents SW from having to send a separate
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REO_UNBLOCK_CACHE command.
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When set, HW will first release the blocking resource
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(indicated in field 'Cache_block_resouce_index') before this
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command gets executed.
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If that resource was already unblocked, this will be
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considered an error. This command will not be executed, and
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an error shall be returned.
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<legal all>
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cache_block_resource_index
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Field not valid when Flush_entire_cache is set.
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Indicates which of the four blocking resources in REO
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will be assigned for managing the blocking of this
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(descriptor) address
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<legal all>
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flush_without_invalidate
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Field not valid when Flush_entire_cache is set.
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When set, REO shall flush the cache line contents from
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the cache, but there is NO need to invalidate the cache line
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entry... The contents in the cache can be maintained. This
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feature can be used by SW (and DV) to get a current snapshot
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of the contents in the cache
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<legal all>
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block_cache_usage_after_flush
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Field not valid when Flush_entire_cache is set.
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When set, REO shall block any cache accesses to this
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address till explicitly unblocked.
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Whenever SW sets this bit, SW shall also set bit
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'Forward_all_mpdus_in_queue' to ensure all packets are
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flushed out in order to make sure this queue desc is not in
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one of the aging link lists. In case SW does not want to
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flush the MPDUs in the queue, see the recipe description
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below this TLV definition.
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The 'blocking' index to be used for this is indicated in
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field 'cache_block_resource_index'. If SW had previously
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used this blocking resource and was not freed up yet, SW
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shall first unblock that index (by setting bit
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Release_cache_block_index) or use an unblock command.
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If the resource indicated here was already blocked (and
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did not get unblocked in this command), it is considered an
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error scenario...
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No flush shall happen. The status for this command shall
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indicate error.
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<legal all>
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flush_entire_cache
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When set, the entire cache shall be flushed. The entire
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cache will also remain blocked, till the
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'REO_UNBLOCK_COMMAND' is received with bit unblock type set
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to unblock_cache. All other fields in this command are to be
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ignored.
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Note that flushing the entire cache has no changes to
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the current settings of the blocking resource settings
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<legal all>
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reserved_2b
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<legal 0>
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reserved_3a
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<legal 0>
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reserved_4a
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<legal 0>
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reserved_5a
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<legal 0>
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reserved_6a
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<legal 0>
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reserved_7a
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<legal 0>
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reserved_8a
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
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#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
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#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
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/* Description REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0
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Consumer: REO
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Producer: SW
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Address (lower 32 bits) of the descriptor to flush
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<legal all>
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*/
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#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004
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#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0
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#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff
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/* Description REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32
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Consumer: REO
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Producer: SW
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Address (upper 8 bits) of the descriptor to flush
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<legal all>
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*/
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#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008
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#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0
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#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff
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/* Description REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE
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Is only allowed to be set when the flush address
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corresponds with a REO descriptor.
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When set, REO shall first forward all the MPDUs held in
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the indicated re-order queue, before flushing the descriptor
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from the cache.
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<legal all>
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*/
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#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008
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#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8
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#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100
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/* Description REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX
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Field not valid when Flush_entire_cache is set.
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If SW has previously used a blocking resource that it
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now wants to re-use for this command, this bit shall be set.
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It prevents SW from having to send a separate
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REO_UNBLOCK_CACHE command.
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When set, HW will first release the blocking resource
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(indicated in field 'Cache_block_resouce_index') before this
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command gets executed.
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If that resource was already unblocked, this will be
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considered an error. This command will not be executed, and
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an error shall be returned.
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<legal all>
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*/
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#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008
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#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9
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#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200
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/* Description REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX
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Field not valid when Flush_entire_cache is set.
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Indicates which of the four blocking resources in REO
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will be assigned for managing the blocking of this
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(descriptor) address
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<legal all>
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*/
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#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
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#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10
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#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00
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/* Description REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE
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Field not valid when Flush_entire_cache is set.
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When set, REO shall flush the cache line contents from
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the cache, but there is NO need to invalidate the cache line
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entry... The contents in the cache can be maintained. This
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feature can be used by SW (and DV) to get a current snapshot
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of the contents in the cache
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<legal all>
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*/
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#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008
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#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12
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#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000
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/* Description REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH
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Field not valid when Flush_entire_cache is set.
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When set, REO shall block any cache accesses to this
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address till explicitly unblocked.
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Whenever SW sets this bit, SW shall also set bit
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'Forward_all_mpdus_in_queue' to ensure all packets are
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flushed out in order to make sure this queue desc is not in
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one of the aging link lists. In case SW does not want to
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flush the MPDUs in the queue, see the recipe description
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below this TLV definition.
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The 'blocking' index to be used for this is indicated in
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field 'cache_block_resource_index'. If SW had previously
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used this blocking resource and was not freed up yet, SW
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shall first unblock that index (by setting bit
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Release_cache_block_index) or use an unblock command.
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If the resource indicated here was already blocked (and
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did not get unblocked in this command), it is considered an
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error scenario...
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No flush shall happen. The status for this command shall
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indicate error.
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<legal all>
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*/
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#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008
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#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13
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#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000
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/* Description REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE
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When set, the entire cache shall be flushed. The entire
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cache will also remain blocked, till the
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'REO_UNBLOCK_COMMAND' is received with bit unblock type set
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to unblock_cache. All other fields in this command are to be
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ignored.
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Note that flushing the entire cache has no changes to
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the current settings of the blocking resource settings
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<legal all>
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*/
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#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008
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#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14
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#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000
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/* Description REO_FLUSH_CACHE_2_RESERVED_2B
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008
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#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15
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#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000
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/* Description REO_FLUSH_CACHE_3_RESERVED_3A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c
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#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0
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#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff
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/* Description REO_FLUSH_CACHE_4_RESERVED_4A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010
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#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0
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#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff
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/* Description REO_FLUSH_CACHE_5_RESERVED_5A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014
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#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0
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#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff
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/* Description REO_FLUSH_CACHE_6_RESERVED_6A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018
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#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0
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#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff
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/* Description REO_FLUSH_CACHE_7_RESERVED_7A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c
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#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0
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#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff
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/* Description REO_FLUSH_CACHE_8_RESERVED_8A
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<legal 0>
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*/
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#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020
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#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0
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#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff
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#endif // _REO_FLUSH_CACHE_H_
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