051a8c4457
FW common files needs to be in sync with host and fw. There are duplicate definition of target attach API when latest copy of fw common files are used. Remove duplicate definition of target attach from hif layer. Change-Id: Ie4a80ba07bc3ec2d9d1466c32062c373c9759a94 CRs-Fixed: 1012542
744 行
34 KiB
C
744 行
34 KiB
C
/*
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* Copyright (c) 2011-2016 The Linux Foundation. All rights reserved.
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*
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* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* This file was originally distributed by Qualcomm Atheros, Inc.
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* under proprietary terms before Copyright ownership was assigned
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* to the Linux Foundation.
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*/
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#ifndef _REGTABLE_PCIE_H_
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#define _REGTABLE_PCIE_H_
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#define MISSING 0
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#define A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK \
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(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
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#define A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 \
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(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1)
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#define A_SOC_CORE_SPARE_1_REGISTER \
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(scn->targetdef->d_A_SOC_CORE_SPARE_1_REGISTER)
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#define A_SOC_CORE_PCIE_INTR_CLR_GRP1 \
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(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CLR_GRP1)
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#define A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 \
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(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1)
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#define A_SOC_PCIE_PCIE_SCRATCH_0 \
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(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_0)
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#define A_SOC_PCIE_PCIE_SCRATCH_1 \
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(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_1)
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#define A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA \
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(scn->targetdef->d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA)
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#define A_SOC_PCIE_PCIE_SCRATCH_2 \
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(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_2)
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/* end Q6 iHelium emu registers */
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#define PCIE_INTR_FIRMWARE_ROUTE_MASK \
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(scn->targetdef->d_PCIE_INTR_FIRMWARE_ROUTE_MASK)
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#define A_SOC_CORE_SPARE_0_REGISTER \
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(scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER)
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#define A_SOC_CORE_SCRATCH_0_ADDRESS \
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(scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS)
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#define A_SOC_CORE_SCRATCH_1_ADDRESS \
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(scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS)
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#define A_SOC_CORE_SCRATCH_2_ADDRESS \
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(scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS)
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#define A_SOC_CORE_SCRATCH_3_ADDRESS \
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(scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS)
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#define A_SOC_CORE_SCRATCH_4_ADDRESS \
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(scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS)
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#define A_SOC_CORE_SCRATCH_5_ADDRESS \
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(scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS)
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#define A_SOC_CORE_SCRATCH_6_ADDRESS \
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(scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS)
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#define A_SOC_CORE_SCRATCH_7_ADDRESS \
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(scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS)
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#define RTC_SOC_BASE_ADDRESS (scn->targetdef->d_RTC_SOC_BASE_ADDRESS)
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#define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS)
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#define SYSTEM_SLEEP_OFFSET (scn->targetdef->d_SYSTEM_SLEEP_OFFSET)
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#define WLAN_SYSTEM_SLEEP_OFFSET \
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(scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET)
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#define WLAN_SYSTEM_SLEEP_DISABLE_LSB \
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(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB)
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#define WLAN_SYSTEM_SLEEP_DISABLE_MASK \
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(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK)
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#define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET)
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#define CLOCK_CONTROL_SI0_CLK_MASK \
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(scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
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#define RESET_CONTROL_OFFSET (scn->targetdef->d_RESET_CONTROL_OFFSET)
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#define RESET_CONTROL_MBOX_RST_MASK \
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(scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK)
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#define RESET_CONTROL_SI0_RST_MASK \
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(scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK)
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#define WLAN_RESET_CONTROL_OFFSET \
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(scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET)
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#define WLAN_RESET_CONTROL_COLD_RST_MASK \
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(scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK)
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#define WLAN_RESET_CONTROL_WARM_RST_MASK \
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(scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK)
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#define GPIO_BASE_ADDRESS (scn->targetdef->d_GPIO_BASE_ADDRESS)
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#define GPIO_PIN0_OFFSET (scn->targetdef->d_GPIO_PIN0_OFFSET)
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#define GPIO_PIN1_OFFSET (scn->targetdef->d_GPIO_PIN1_OFFSET)
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#define GPIO_PIN0_CONFIG_MASK (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK)
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#define GPIO_PIN1_CONFIG_MASK (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK)
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#define A_SOC_CORE_SCRATCH_0 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0)
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#define SI_CONFIG_BIDIR_OD_DATA_LSB \
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(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
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#define SI_CONFIG_BIDIR_OD_DATA_MASK \
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(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
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#define SI_CONFIG_I2C_LSB (scn->targetdef->d_SI_CONFIG_I2C_LSB)
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#define SI_CONFIG_I2C_MASK \
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(scn->targetdef->d_SI_CONFIG_I2C_MASK)
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#define SI_CONFIG_POS_SAMPLE_LSB \
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(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
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#define SI_CONFIG_POS_SAMPLE_MASK \
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(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
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#define SI_CONFIG_INACTIVE_CLK_LSB \
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(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
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#define SI_CONFIG_INACTIVE_CLK_MASK \
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(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
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#define SI_CONFIG_INACTIVE_DATA_LSB \
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(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
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#define SI_CONFIG_INACTIVE_DATA_MASK \
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(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
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#define SI_CONFIG_DIVIDER_LSB (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB)
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#define SI_CONFIG_DIVIDER_MASK (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK)
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#define SI_BASE_ADDRESS (scn->targetdef->d_SI_BASE_ADDRESS)
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#define SI_CONFIG_OFFSET (scn->targetdef->d_SI_CONFIG_OFFSET)
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#define SI_TX_DATA0_OFFSET (scn->targetdef->d_SI_TX_DATA0_OFFSET)
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#define SI_TX_DATA1_OFFSET (scn->targetdef->d_SI_TX_DATA1_OFFSET)
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#define SI_RX_DATA0_OFFSET (scn->targetdef->d_SI_RX_DATA0_OFFSET)
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#define SI_RX_DATA1_OFFSET (scn->targetdef->d_SI_RX_DATA1_OFFSET)
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#define SI_CS_OFFSET (scn->targetdef->d_SI_CS_OFFSET)
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#define SI_CS_DONE_ERR_MASK (scn->targetdef->d_SI_CS_DONE_ERR_MASK)
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#define SI_CS_DONE_INT_MASK (scn->targetdef->d_SI_CS_DONE_INT_MASK)
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#define SI_CS_START_LSB (scn->targetdef->d_SI_CS_START_LSB)
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#define SI_CS_START_MASK (scn->targetdef->d_SI_CS_START_MASK)
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#define SI_CS_RX_CNT_LSB (scn->targetdef->d_SI_CS_RX_CNT_LSB)
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#define SI_CS_RX_CNT_MASK (scn->targetdef->d_SI_CS_RX_CNT_MASK)
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#define SI_CS_TX_CNT_LSB (scn->targetdef->d_SI_CS_TX_CNT_LSB)
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#define SI_CS_TX_CNT_MASK (scn->targetdef->d_SI_CS_TX_CNT_MASK)
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#define EEPROM_SZ (scn->targetdef->d_BOARD_DATA_SZ)
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#define EEPROM_EXT_SZ (scn->targetdef->d_BOARD_EXT_DATA_SZ)
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#define MBOX_BASE_ADDRESS (scn->targetdef->d_MBOX_BASE_ADDRESS)
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#define LOCAL_SCRATCH_OFFSET (scn->targetdef->d_LOCAL_SCRATCH_OFFSET)
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#define CPU_CLOCK_OFFSET (scn->targetdef->d_CPU_CLOCK_OFFSET)
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#define LPO_CAL_OFFSET (scn->targetdef->d_LPO_CAL_OFFSET)
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#define GPIO_PIN10_OFFSET (scn->targetdef->d_GPIO_PIN10_OFFSET)
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#define GPIO_PIN11_OFFSET (scn->targetdef->d_GPIO_PIN11_OFFSET)
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#define GPIO_PIN12_OFFSET (scn->targetdef->d_GPIO_PIN12_OFFSET)
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#define GPIO_PIN13_OFFSET (scn->targetdef->d_GPIO_PIN13_OFFSET)
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#define CLOCK_GPIO_OFFSET (scn->targetdef->d_CLOCK_GPIO_OFFSET)
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#define CPU_CLOCK_STANDARD_LSB (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB)
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#define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK)
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#define LPO_CAL_ENABLE_LSB (scn->targetdef->d_LPO_CAL_ENABLE_LSB)
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#define LPO_CAL_ENABLE_MASK (scn->targetdef->d_LPO_CAL_ENABLE_MASK)
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#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \
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(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
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#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \
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(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
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#define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS)
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#define WLAN_MAC_BASE_ADDRESS (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS)
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#define FW_INDICATOR_ADDRESS (scn->targetdef->d_FW_INDICATOR_ADDRESS)
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#define DRAM_BASE_ADDRESS (scn->targetdef->d_DRAM_BASE_ADDRESS)
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#define SOC_CORE_BASE_ADDRESS (scn->targetdef->d_SOC_CORE_BASE_ADDRESS)
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#define CORE_CTRL_ADDRESS (scn->targetdef->d_CORE_CTRL_ADDRESS)
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#define CE_COUNT (scn->targetdef->d_CE_COUNT)
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#define PCIE_INTR_ENABLE_ADDRESS (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS)
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#define PCIE_INTR_CLR_ADDRESS (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS)
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#define PCIE_INTR_FIRMWARE_MASK (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK)
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#define PCIE_INTR_CE_MASK_ALL (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL)
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#define CORE_CTRL_CPU_INTR_MASK (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK)
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#define PCIE_INTR_CAUSE_ADDRESS (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS)
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#define SOC_RESET_CONTROL_ADDRESS (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS)
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#define HOST_GROUP0_MASK (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL | \
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A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
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#define SOC_RESET_CONTROL_CE_RST_MASK \
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(scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK)
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#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \
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(scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
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#define CPU_INTR_ADDRESS (scn->targetdef->d_CPU_INTR_ADDRESS)
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#define SOC_LF_TIMER_CONTROL0_ADDRESS \
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(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
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#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \
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(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
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#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \
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(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
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#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \
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(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
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#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) \
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(((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> \
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SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
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#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) \
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(((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & \
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SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
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/* hif_pci.c */
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#define CHIP_ID_ADDRESS (scn->targetdef->d_SOC_CHIP_ID_ADDRESS)
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#define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK)
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#define SOC_CHIP_ID_REVISION_LSB (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB)
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#define SOC_CHIP_ID_VERSION_MASK (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK)
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#define SOC_CHIP_ID_VERSION_LSB (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB)
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#define CHIP_ID_REVISION_GET(x) \
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(((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB)
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#define CHIP_ID_VERSION_GET(x) \
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(((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB)
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/* hif_pci.c end */
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/* misc */
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#define SR_WR_INDEX_ADDRESS (scn->targetdef->d_SR_WR_INDEX_ADDRESS)
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#define DST_WATERMARK_ADDRESS (scn->targetdef->d_DST_WATERMARK_ADDRESS)
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#define SOC_POWER_REG_OFFSET (scn->targetdef->d_SOC_POWER_REG_OFFSET)
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/* end */
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#ifndef CONFIG_WIN
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/* htt_rx.c */
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#define RX_MSDU_END_4_FIRST_MSDU_MASK \
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(pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_MASK)
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#define RX_MSDU_END_4_FIRST_MSDU_LSB \
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(pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_LSB)
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#define RX_MPDU_START_0_RETRY_LSB \
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(pdev->targetdef->d_RX_MPDU_START_0_RETRY_LSB)
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#define RX_MPDU_START_0_RETRY_MASK \
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(pdev->targetdef->d_RX_MPDU_START_0_RETRY_MASK)
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#define RX_MPDU_START_0_SEQ_NUM_MASK \
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(pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_MASK)
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#define RX_MPDU_START_0_SEQ_NUM_LSB \
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(pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_LSB)
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#define RX_MPDU_START_2_PN_47_32_LSB \
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(pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_LSB)
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#define RX_MPDU_START_2_PN_47_32_MASK \
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(pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_MASK)
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#define RX_MPDU_START_2_TID_LSB \
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(pdev->targetdef->d_RX_MPDU_START_2_TID_LSB)
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#define RX_MPDU_START_2_TID_MASK \
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(pdev->targetdef->d_RX_MPDU_START_2_TID_MASK)
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#define RX_MSDU_END_1_KEY_ID_OCT_MASK \
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(pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_MASK)
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#define RX_MSDU_END_1_KEY_ID_OCT_LSB \
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(pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_LSB)
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#define RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK \
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(pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK)
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#define RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB \
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(pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB)
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#define RX_MSDU_END_4_LAST_MSDU_MASK \
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(pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_MASK)
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#define RX_MSDU_END_4_LAST_MSDU_LSB \
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(pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_LSB)
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#define RX_ATTENTION_0_MCAST_BCAST_MASK \
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(pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_MASK)
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#define RX_ATTENTION_0_MCAST_BCAST_LSB \
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(pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_LSB)
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#define RX_ATTENTION_0_FRAGMENT_MASK \
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(pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_MASK)
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#define RX_ATTENTION_0_FRAGMENT_LSB \
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(pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_LSB)
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#define RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK \
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(pdev->targetdef->d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK)
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#define RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK \
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(pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK)
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#define RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB \
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(pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB)
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#define RX_MSDU_START_0_MSDU_LENGTH_MASK \
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(pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_MASK)
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#define RX_MSDU_START_0_MSDU_LENGTH_LSB \
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(pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_LSB)
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#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET \
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(pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET)
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#define RX_MSDU_START_2_DECAP_FORMAT_MASK \
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(pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_MASK)
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#define RX_MSDU_START_2_DECAP_FORMAT_LSB \
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(pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_LSB)
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#define RX_MPDU_START_0_ENCRYPTED_MASK \
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(pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_MASK)
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#define RX_MPDU_START_0_ENCRYPTED_LSB \
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(pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_LSB)
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#define RX_ATTENTION_0_MORE_DATA_MASK \
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(pdev->targetdef->d_RX_ATTENTION_0_MORE_DATA_MASK)
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#define RX_ATTENTION_0_MSDU_DONE_MASK \
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(pdev->targetdef->d_RX_ATTENTION_0_MSDU_DONE_MASK)
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#define RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK \
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(pdev->targetdef->d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK)
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/* end */
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#endif
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/* copy_engine.c */
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/* end */
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/* PLL start */
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#define EFUSE_OFFSET (scn->targetdef->d_EFUSE_OFFSET)
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#define EFUSE_XTAL_SEL_MSB (scn->targetdef->d_EFUSE_XTAL_SEL_MSB)
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#define EFUSE_XTAL_SEL_LSB (scn->targetdef->d_EFUSE_XTAL_SEL_LSB)
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#define EFUSE_XTAL_SEL_MASK (scn->targetdef->d_EFUSE_XTAL_SEL_MASK)
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#define BB_PLL_CONFIG_OFFSET (scn->targetdef->d_BB_PLL_CONFIG_OFFSET)
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#define BB_PLL_CONFIG_OUTDIV_MSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB)
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#define BB_PLL_CONFIG_OUTDIV_LSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB)
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#define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK)
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#define BB_PLL_CONFIG_FRAC_MSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB)
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#define BB_PLL_CONFIG_FRAC_LSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB)
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#define BB_PLL_CONFIG_FRAC_MASK (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK)
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#define WLAN_PLL_SETTLE_TIME_MSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB)
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#define WLAN_PLL_SETTLE_TIME_LSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB)
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#define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK)
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#define WLAN_PLL_SETTLE_OFFSET (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET)
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#define WLAN_PLL_SETTLE_SW_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK)
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#define WLAN_PLL_SETTLE_RSTMASK (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK)
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#define WLAN_PLL_SETTLE_RESET (scn->targetdef->d_WLAN_PLL_SETTLE_RESET)
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#define WLAN_PLL_CONTROL_NOPWD_MSB \
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(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB)
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#define WLAN_PLL_CONTROL_NOPWD_LSB \
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(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB)
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#define WLAN_PLL_CONTROL_NOPWD_MASK \
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(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK)
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#define WLAN_PLL_CONTROL_BYPASS_MSB \
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(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB)
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#define WLAN_PLL_CONTROL_BYPASS_LSB \
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(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB)
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#define WLAN_PLL_CONTROL_BYPASS_MASK \
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(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK)
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#define WLAN_PLL_CONTROL_BYPASS_RESET \
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(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET)
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#define WLAN_PLL_CONTROL_CLK_SEL_MSB \
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(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB)
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#define WLAN_PLL_CONTROL_CLK_SEL_LSB \
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(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB)
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#define WLAN_PLL_CONTROL_CLK_SEL_MASK \
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(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK)
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#define WLAN_PLL_CONTROL_CLK_SEL_RESET \
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(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET)
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#define WLAN_PLL_CONTROL_REFDIV_MSB \
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(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB)
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#define WLAN_PLL_CONTROL_REFDIV_LSB \
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(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB)
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#define WLAN_PLL_CONTROL_REFDIV_MASK \
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(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK)
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#define WLAN_PLL_CONTROL_REFDIV_RESET \
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(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET)
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#define WLAN_PLL_CONTROL_DIV_MSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB)
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#define WLAN_PLL_CONTROL_DIV_LSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB)
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#define WLAN_PLL_CONTROL_DIV_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK)
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#define WLAN_PLL_CONTROL_DIV_RESET \
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(scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET)
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#define WLAN_PLL_CONTROL_OFFSET (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET)
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#define WLAN_PLL_CONTROL_SW_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK)
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#define WLAN_PLL_CONTROL_RSTMASK (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK)
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#define WLAN_PLL_CONTROL_RESET (scn->targetdef->d_WLAN_PLL_CONTROL_RESET)
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#define SOC_CORE_CLK_CTRL_OFFSET (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET)
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#define SOC_CORE_CLK_CTRL_DIV_MSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB)
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#define SOC_CORE_CLK_CTRL_DIV_LSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB)
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#define SOC_CORE_CLK_CTRL_DIV_MASK \
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(scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK)
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#define RTC_SYNC_STATUS_PLL_CHANGING_MSB \
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(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB)
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#define RTC_SYNC_STATUS_PLL_CHANGING_LSB \
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(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB)
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#define RTC_SYNC_STATUS_PLL_CHANGING_MASK \
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(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK)
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#define RTC_SYNC_STATUS_PLL_CHANGING_RESET \
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(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET)
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#define RTC_SYNC_STATUS_OFFSET (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET)
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#define SOC_CPU_CLOCK_OFFSET (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET)
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#define SOC_CPU_CLOCK_STANDARD_MSB \
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(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB)
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#define SOC_CPU_CLOCK_STANDARD_LSB \
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(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB)
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#define SOC_CPU_CLOCK_STANDARD_MASK \
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(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK)
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/* PLL end */
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#define FW_CPU_PLL_CONFIG \
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(scn->targetdef->d_FW_CPU_PLL_CONFIG)
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#define WIFICMN_PCIE_BAR_REG_ADDRESS \
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(sc->targetdef->d_WIFICMN_PCIE_BAR_REG_ADDRESS)
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/* htt tx */
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#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK \
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(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK)
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#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK \
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(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK)
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#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK \
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(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK)
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#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK \
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(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK)
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#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB \
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(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB)
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#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB \
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(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB)
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#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB \
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(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB)
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#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB \
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(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB)
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#define CE_CMD_ADDRESS \
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(scn->targetdef->d_CE_CMD_ADDRESS)
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#define CE_CMD_HALT_MASK \
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(scn->targetdef->d_CE_CMD_HALT_MASK)
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#define CE_CMD_HALT_STATUS_MASK \
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(scn->targetdef->d_CE_CMD_HALT_STATUS_MASK)
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#define CE_CMD_HALT_STATUS_LSB \
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(scn->targetdef->d_CE_CMD_HALT_STATUS_LSB)
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#define SI_CONFIG_ERR_INT_MASK \
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(scn->targetdef->d_SI_CONFIG_ERR_INT_MASK)
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#define SI_CONFIG_ERR_INT_LSB \
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(scn->targetdef->d_SI_CONFIG_ERR_INT_LSB)
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#define GPIO_ENABLE_W1TS_LOW_ADDRESS \
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(scn->targetdef->d_GPIO_ENABLE_W1TS_LOW_ADDRESS)
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#define GPIO_PIN0_CONFIG_LSB \
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(scn->targetdef->d_GPIO_PIN0_CONFIG_LSB)
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#define GPIO_PIN0_PAD_PULL_LSB \
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(scn->targetdef->d_GPIO_PIN0_PAD_PULL_LSB)
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#define GPIO_PIN0_PAD_PULL_MASK \
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(scn->targetdef->d_GPIO_PIN0_PAD_PULL_MASK)
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#define SOC_CHIP_ID_REVISION_MSB \
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(scn->targetdef->d_SOC_CHIP_ID_REVISION_MSB)
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#define FW_AXI_MSI_ADDR \
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(scn->targetdef->d_FW_AXI_MSI_ADDR)
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#define FW_AXI_MSI_DATA \
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(scn->targetdef->d_FW_AXI_MSI_DATA)
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#define WLAN_SUBSYSTEM_CORE_ID_ADDRESS \
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(scn->targetdef->d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS)
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#define FPGA_VERSION_ADDRESS \
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(scn->targetdef->d_FPGA_VERSION_ADDRESS)
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/* SET macros */
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#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \
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(((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \
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WLAN_SYSTEM_SLEEP_DISABLE_MASK)
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#define SI_CONFIG_BIDIR_OD_DATA_SET(x) \
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(((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
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#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
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#define SI_CONFIG_POS_SAMPLE_SET(x) \
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(((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
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#define SI_CONFIG_INACTIVE_CLK_SET(x) \
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(((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
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#define SI_CONFIG_INACTIVE_DATA_SET(x) \
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(((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
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#define SI_CONFIG_DIVIDER_SET(x) \
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(((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
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#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
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#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
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#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
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|
#define LPO_CAL_ENABLE_SET(x) \
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|
(((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
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#define CPU_CLOCK_STANDARD_SET(x) \
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|
(((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
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|
#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \
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(((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
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|
/* copy_engine.c */
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|
/* end */
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/* PLL start */
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|
#define EFUSE_XTAL_SEL_GET(x) \
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|
(((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB)
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|
#define EFUSE_XTAL_SEL_SET(x) \
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|
(((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK)
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|
#define BB_PLL_CONFIG_OUTDIV_GET(x) \
|
|
(((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB)
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|
#define BB_PLL_CONFIG_OUTDIV_SET(x) \
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|
(((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK)
|
|
#define BB_PLL_CONFIG_FRAC_GET(x) \
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|
(((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB)
|
|
#define BB_PLL_CONFIG_FRAC_SET(x) \
|
|
(((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK)
|
|
#define WLAN_PLL_SETTLE_TIME_GET(x) \
|
|
(((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB)
|
|
#define WLAN_PLL_SETTLE_TIME_SET(x) \
|
|
(((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK)
|
|
#define WLAN_PLL_CONTROL_NOPWD_GET(x) \
|
|
(((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB)
|
|
#define WLAN_PLL_CONTROL_NOPWD_SET(x) \
|
|
(((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK)
|
|
#define WLAN_PLL_CONTROL_BYPASS_GET(x) \
|
|
(((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB)
|
|
#define WLAN_PLL_CONTROL_BYPASS_SET(x) \
|
|
(((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK)
|
|
#define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \
|
|
(((x) & WLAN_PLL_CONTROL_CLK_SEL_MASK) >> WLAN_PLL_CONTROL_CLK_SEL_LSB)
|
|
#define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \
|
|
(((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & WLAN_PLL_CONTROL_CLK_SEL_MASK)
|
|
#define WLAN_PLL_CONTROL_REFDIV_GET(x) \
|
|
(((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB)
|
|
#define WLAN_PLL_CONTROL_REFDIV_SET(x) \
|
|
(((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK)
|
|
#define WLAN_PLL_CONTROL_DIV_GET(x) \
|
|
(((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB)
|
|
#define WLAN_PLL_CONTROL_DIV_SET(x) \
|
|
(((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK)
|
|
#define SOC_CORE_CLK_CTRL_DIV_GET(x) \
|
|
(((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB)
|
|
#define SOC_CORE_CLK_CTRL_DIV_SET(x) \
|
|
(((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK)
|
|
#define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \
|
|
(((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \
|
|
RTC_SYNC_STATUS_PLL_CHANGING_LSB)
|
|
#define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \
|
|
(((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \
|
|
RTC_SYNC_STATUS_PLL_CHANGING_MASK)
|
|
#define SOC_CPU_CLOCK_STANDARD_GET(x) \
|
|
(((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB)
|
|
#define SOC_CPU_CLOCK_STANDARD_SET(x) \
|
|
(((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK)
|
|
/* PLL end */
|
|
#define WLAN_GPIO_PIN0_CONFIG_SET(x) \
|
|
(((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK)
|
|
#define WLAN_GPIO_PIN0_PAD_PULL_SET(x) \
|
|
(((x) << GPIO_PIN0_PAD_PULL_LSB) & GPIO_PIN0_PAD_PULL_MASK)
|
|
#define SI_CONFIG_ERR_INT_SET(x) \
|
|
(((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
|
|
|
|
|
|
#ifdef QCA_WIFI_3_0_ADRASTEA
|
|
#define Q6_ENABLE_REGISTER_0 \
|
|
(scn->targetdef->d_Q6_ENABLE_REGISTER_0)
|
|
#define Q6_ENABLE_REGISTER_1 \
|
|
(scn->targetdef->d_Q6_ENABLE_REGISTER_1)
|
|
#define Q6_CAUSE_REGISTER_0 \
|
|
(scn->targetdef->d_Q6_CAUSE_REGISTER_0)
|
|
#define Q6_CAUSE_REGISTER_1 \
|
|
(scn->targetdef->d_Q6_CAUSE_REGISTER_1)
|
|
#define Q6_CLEAR_REGISTER_0 \
|
|
(scn->targetdef->d_Q6_CLEAR_REGISTER_0)
|
|
#define Q6_CLEAR_REGISTER_1 \
|
|
(scn->targetdef->d_Q6_CLEAR_REGISTER_1)
|
|
#endif
|
|
|
|
#ifdef CONFIG_BYPASS_QMI
|
|
#define BYPASS_QMI_TEMP_REGISTER \
|
|
(scn->targetdef->d_BYPASS_QMI_TEMP_REGISTER)
|
|
#endif
|
|
|
|
#define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START)
|
|
#define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK)
|
|
#define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK)
|
|
#define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK)
|
|
#define HOST_CE_COUNT (scn->hostdef->d_HOST_CE_COUNT)
|
|
#define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI)
|
|
#define INT_STATUS_ENABLE_ERROR_LSB \
|
|
(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)
|
|
#define INT_STATUS_ENABLE_ERROR_MASK \
|
|
(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)
|
|
#define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)
|
|
#define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)
|
|
#define INT_STATUS_ENABLE_COUNTER_LSB \
|
|
(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB)
|
|
#define INT_STATUS_ENABLE_COUNTER_MASK \
|
|
(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK)
|
|
#define INT_STATUS_ENABLE_MBOX_DATA_LSB \
|
|
(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB)
|
|
#define INT_STATUS_ENABLE_MBOX_DATA_MASK \
|
|
(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK)
|
|
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \
|
|
(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
|
|
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \
|
|
(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
|
|
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB \
|
|
(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
|
|
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \
|
|
(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
|
|
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB \
|
|
(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB)
|
|
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK \
|
|
(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK)
|
|
#define INT_STATUS_ENABLE_ADDRESS \
|
|
(scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS)
|
|
#define CPU_INT_STATUS_ENABLE_BIT_LSB \
|
|
(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB)
|
|
#define CPU_INT_STATUS_ENABLE_BIT_MASK \
|
|
(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK)
|
|
#define HOST_INT_STATUS_ADDRESS (scn->hostdef->d_HOST_INT_STATUS_ADDRESS)
|
|
#define CPU_INT_STATUS_ADDRESS (scn->hostdef->d_CPU_INT_STATUS_ADDRESS)
|
|
#define ERROR_INT_STATUS_ADDRESS (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS)
|
|
#define ERROR_INT_STATUS_WAKEUP_MASK \
|
|
(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK)
|
|
#define ERROR_INT_STATUS_WAKEUP_LSB \
|
|
(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB)
|
|
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \
|
|
(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
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#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \
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(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
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#define ERROR_INT_STATUS_TX_OVERFLOW_MASK \
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(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK)
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#define ERROR_INT_STATUS_TX_OVERFLOW_LSB \
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(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB)
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#define COUNT_DEC_ADDRESS (scn->hostdef->d_COUNT_DEC_ADDRESS)
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#define HOST_INT_STATUS_CPU_MASK (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK)
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#define HOST_INT_STATUS_CPU_LSB (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB)
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#define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK)
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#define HOST_INT_STATUS_ERROR_LSB (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB)
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#define HOST_INT_STATUS_COUNTER_MASK \
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(scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK)
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#define HOST_INT_STATUS_COUNTER_LSB \
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(scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB)
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#define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS)
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#define WINDOW_DATA_ADDRESS (scn->hostdef->d_WINDOW_DATA_ADDRESS)
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#define WINDOW_READ_ADDR_ADDRESS (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS)
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#define WINDOW_WRITE_ADDR_ADDRESS (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS)
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#define SOC_GLOBAL_RESET_ADDRESS (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS)
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#define RTC_STATE_ADDRESS (scn->hostdef->d_RTC_STATE_ADDRESS)
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#define RTC_STATE_COLD_RESET_MASK (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK)
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#define PCIE_LOCAL_BASE_ADDRESS (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS)
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#define PCIE_SOC_WAKE_RESET (scn->hostdef->d_PCIE_SOC_WAKE_RESET)
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#define PCIE_SOC_WAKE_ADDRESS (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS)
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#define PCIE_SOC_WAKE_V_MASK (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK)
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#define RTC_STATE_V_MASK (scn->hostdef->d_RTC_STATE_V_MASK)
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#define RTC_STATE_V_LSB (scn->hostdef->d_RTC_STATE_V_LSB)
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#define FW_IND_EVENT_PENDING (scn->hostdef->d_FW_IND_EVENT_PENDING)
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#define FW_IND_INITIALIZED (scn->hostdef->d_FW_IND_INITIALIZED)
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#define FW_IND_HELPER (scn->hostdef->d_FW_IND_HELPER)
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#define RTC_STATE_V_ON (scn->hostdef->d_RTC_STATE_V_ON)
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#define FW_IND_HOST_READY (scn->hostdef->d_FW_IND_HOST_READY)
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#if defined(SDIO_3_0)
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#define HOST_INT_STATUS_MBOX_DATA_MASK \
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(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK)
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#define HOST_INT_STATUS_MBOX_DATA_LSB \
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(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB)
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#endif
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#if !defined(SOC_PCIE_BASE_ADDRESS)
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#define SOC_PCIE_BASE_ADDRESS 0
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#endif
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#if !defined(PCIE_SOC_RDY_STATUS_ADDRESS)
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#define PCIE_SOC_RDY_STATUS_ADDRESS 0
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#define PCIE_SOC_RDY_STATUS_BAR_MASK 0
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#endif
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#if !defined(MSI_MAGIC_ADR_ADDRESS)
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#define MSI_MAGIC_ADR_ADDRESS 0
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#define MSI_MAGIC_ADDRESS 0
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#endif
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/* SET/GET macros */
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#define INT_STATUS_ENABLE_ERROR_SET(x) \
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(((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
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#define INT_STATUS_ENABLE_CPU_SET(x) \
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(((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
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#define INT_STATUS_ENABLE_COUNTER_SET(x) \
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(((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \
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INT_STATUS_ENABLE_COUNTER_MASK)
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#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \
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(((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \
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INT_STATUS_ENABLE_MBOX_DATA_MASK)
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#define CPU_INT_STATUS_ENABLE_BIT_SET(x) \
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(((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \
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CPU_INT_STATUS_ENABLE_BIT_MASK)
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \
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(((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \
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ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \
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(((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \
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ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
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#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \
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(((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \
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COUNTER_INT_STATUS_ENABLE_BIT_MASK)
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|
#define ERROR_INT_STATUS_WAKEUP_GET(x) \
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(((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \
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ERROR_INT_STATUS_WAKEUP_LSB)
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|
#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \
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|
(((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \
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|
ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
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|
#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \
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|
(((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \
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ERROR_INT_STATUS_TX_OVERFLOW_LSB)
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|
#define HOST_INT_STATUS_CPU_GET(x) \
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|
(((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
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|
#define HOST_INT_STATUS_ERROR_GET(x) \
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|
(((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
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|
#define HOST_INT_STATUS_COUNTER_GET(x) \
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|
(((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
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|
#define RTC_STATE_V_GET(x) \
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|
(((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
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|
#if defined(SDIO_3_0)
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|
#define HOST_INT_STATUS_MBOX_DATA_GET(x) \
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|
(((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \
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|
HOST_INT_STATUS_MBOX_DATA_LSB)
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|
#endif
|
|
|
|
#define INVALID_REG_LOC_DUMMY_DATA 0xAA
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|
|
|
#define AR6320_CORE_CLK_DIV_ADDR 0x403fa8
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|
#define AR6320_CPU_PLL_INIT_DONE_ADDR 0x403fd0
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|
#define AR6320_CPU_SPEED_ADDR 0x403fa4
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|
#define AR6320V2_CORE_CLK_DIV_ADDR 0x403fd8
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|
#define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0
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|
#define AR6320V2_CPU_SPEED_ADDR 0x403fd4
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|
#define AR6320V3_CORE_CLK_DIV_ADDR 0x404028
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|
#define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020
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|
#define AR6320V3_CPU_SPEED_ADDR 0x404024
|
|
|
|
typedef enum {
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|
SOC_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */
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|
SOC_REFCLK_48_MHZ = 0,
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|
SOC_REFCLK_19_2_MHZ = 1,
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|
SOC_REFCLK_24_MHZ = 2,
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|
SOC_REFCLK_26_MHZ = 3,
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|
SOC_REFCLK_37_4_MHZ = 4,
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|
SOC_REFCLK_38_4_MHZ = 5,
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|
SOC_REFCLK_40_MHZ = 6,
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|
SOC_REFCLK_52_MHZ = 7,
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|
} A_refclk_speed_t;
|
|
|
|
#define A_REFCLK_UNKNOWN SOC_REFCLK_UNKNOWN
|
|
#define A_REFCLK_48_MHZ SOC_REFCLK_48_MHZ
|
|
#define A_REFCLK_19_2_MHZ SOC_REFCLK_19_2_MHZ
|
|
#define A_REFCLK_24_MHZ SOC_REFCLK_24_MHZ
|
|
#define A_REFCLK_26_MHZ SOC_REFCLK_26_MHZ
|
|
#define A_REFCLK_37_4_MHZ SOC_REFCLK_37_4_MHZ
|
|
#define A_REFCLK_38_4_MHZ SOC_REFCLK_38_4_MHZ
|
|
#define A_REFCLK_40_MHZ SOC_REFCLK_40_MHZ
|
|
#define A_REFCLK_52_MHZ SOC_REFCLK_52_MHZ
|
|
|
|
#define TARGET_CPU_FREQ 176000000
|
|
|
|
struct wlan_pll_s {
|
|
uint32_t refdiv;
|
|
uint32_t div;
|
|
uint32_t rnfrac;
|
|
uint32_t outdiv;
|
|
};
|
|
|
|
struct cmnos_clock_s {
|
|
A_refclk_speed_t refclk_speed;
|
|
uint32_t refclk_hz;
|
|
uint32_t pll_settling_time; /* 50us */
|
|
struct wlan_pll_s wlan_pll;
|
|
};
|
|
|
|
typedef struct TGT_REG_SECTION {
|
|
uint32_t start_addr;
|
|
uint32_t end_addr;
|
|
} tgt_reg_section;
|
|
|
|
typedef struct TGT_REG_TABLE {
|
|
tgt_reg_section *section;
|
|
uint32_t section_size;
|
|
} tgt_reg_table;
|
|
|
|
struct hif_softc;
|
|
void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type);
|
|
void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type);
|
|
|
|
#endif /* _REGTABLE_PCIE_H_ */
|