dp_ipa.c 108 KB

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  1. /*
  2. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifdef IPA_OFFLOAD
  18. #include <wlan_ipa_ucfg_api.h>
  19. #include <qdf_ipa_wdi3.h>
  20. #include <qdf_types.h>
  21. #include <qdf_lock.h>
  22. #include <hal_hw_headers.h>
  23. #include <hal_api.h>
  24. #include <hal_reo.h>
  25. #include <hif.h>
  26. #include <htt.h>
  27. #include <wdi_event.h>
  28. #include <queue.h>
  29. #include "dp_types.h"
  30. #include "dp_htt.h"
  31. #include "dp_tx.h"
  32. #include "dp_rx.h"
  33. #include "dp_ipa.h"
  34. #include "dp_internal.h"
  35. #ifdef WIFI_MONITOR_SUPPORT
  36. #include "dp_mon.h"
  37. #endif
  38. #ifdef FEATURE_WDS
  39. #include "dp_txrx_wds.h"
  40. #endif
  41. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  42. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  43. /* WAR for IPA_OFFLOAD case. In some cases, its observed that WBM tries to
  44. * release a buffer into WBM2SW RELEASE ring for IPA, and the ring is full.
  45. * This causes back pressure, resulting in a FW crash.
  46. * By leaving some entries with no buffer attached, WBM will be able to write
  47. * to the ring, and from dumps we can figure out the buffer which is causing
  48. * this issue.
  49. */
  50. #define DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES 16
  51. /**
  52. *struct dp_ipa_reo_remap_record - history for dp ipa reo remaps
  53. * @ix0_reg: reo destination ring IX0 value
  54. * @ix2_reg: reo destination ring IX2 value
  55. * @ix3_reg: reo destination ring IX3 value
  56. */
  57. struct dp_ipa_reo_remap_record {
  58. uint64_t timestamp;
  59. uint32_t ix0_reg;
  60. uint32_t ix2_reg;
  61. uint32_t ix3_reg;
  62. };
  63. #ifdef IPA_WDS_EASYMESH_FEATURE
  64. #define WLAN_IPA_META_DATA_MASK htonl(0x000000FF)
  65. #else
  66. #define WLAN_IPA_META_DATA_MASK htonl(0x00FF0000)
  67. #endif
  68. #define REO_REMAP_HISTORY_SIZE 32
  69. struct dp_ipa_reo_remap_record dp_ipa_reo_remap_history[REO_REMAP_HISTORY_SIZE];
  70. static qdf_atomic_t dp_ipa_reo_remap_history_index;
  71. static int dp_ipa_reo_remap_record_index_next(qdf_atomic_t *index)
  72. {
  73. int next = qdf_atomic_inc_return(index);
  74. if (next == REO_REMAP_HISTORY_SIZE)
  75. qdf_atomic_sub(REO_REMAP_HISTORY_SIZE, index);
  76. return next % REO_REMAP_HISTORY_SIZE;
  77. }
  78. /**
  79. * dp_ipa_reo_remap_history_add() - Record dp ipa reo remap values
  80. * @ix0_val: reo destination ring IX0 value
  81. * @ix2_val: reo destination ring IX2 value
  82. * @ix3_val: reo destination ring IX3 value
  83. *
  84. * Return: None
  85. */
  86. static void dp_ipa_reo_remap_history_add(uint32_t ix0_val, uint32_t ix2_val,
  87. uint32_t ix3_val)
  88. {
  89. int idx = dp_ipa_reo_remap_record_index_next(
  90. &dp_ipa_reo_remap_history_index);
  91. struct dp_ipa_reo_remap_record *record = &dp_ipa_reo_remap_history[idx];
  92. record->timestamp = qdf_get_log_timestamp();
  93. record->ix0_reg = ix0_val;
  94. record->ix2_reg = ix2_val;
  95. record->ix3_reg = ix3_val;
  96. }
  97. static QDF_STATUS __dp_ipa_handle_buf_smmu_mapping(struct dp_soc *soc,
  98. qdf_nbuf_t nbuf,
  99. uint32_t size,
  100. bool create,
  101. const char *func,
  102. uint32_t line)
  103. {
  104. qdf_mem_info_t mem_map_table = {0};
  105. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  106. qdf_ipa_wdi_hdl_t hdl;
  107. /* Need to handle the case when one soc will
  108. * have multiple pdev(radio's), Currently passing
  109. * pdev_id as 0 assuming 1 soc has only 1 radio.
  110. */
  111. hdl = wlan_ipa_get_hdl(soc->ctrl_psoc, 0);
  112. if (hdl == DP_IPA_HDL_INVALID) {
  113. dp_err("IPA handle is invalid");
  114. return QDF_STATUS_E_INVAL;
  115. }
  116. qdf_update_mem_map_table(soc->osdev, &mem_map_table,
  117. qdf_nbuf_get_frag_paddr(nbuf, 0),
  118. size);
  119. if (create) {
  120. /* Assert if PA is zero */
  121. qdf_assert_always(mem_map_table.pa);
  122. ret = qdf_nbuf_smmu_map_debug(nbuf, hdl, 1, &mem_map_table,
  123. func, line);
  124. } else {
  125. ret = qdf_nbuf_smmu_unmap_debug(nbuf, hdl, 1, &mem_map_table,
  126. func, line);
  127. }
  128. qdf_assert_always(!ret);
  129. /* Return status of mapping/unmapping is stored in
  130. * mem_map_table.result field, assert if the result
  131. * is failure
  132. */
  133. if (create)
  134. qdf_assert_always(!mem_map_table.result);
  135. else
  136. qdf_assert_always(mem_map_table.result >= mem_map_table.size);
  137. return ret;
  138. }
  139. QDF_STATUS dp_ipa_handle_rx_buf_smmu_mapping(struct dp_soc *soc,
  140. qdf_nbuf_t nbuf,
  141. uint32_t size,
  142. bool create, const char *func,
  143. uint32_t line)
  144. {
  145. struct dp_pdev *pdev;
  146. int i;
  147. for (i = 0; i < soc->pdev_count; i++) {
  148. pdev = soc->pdev_list[i];
  149. if (pdev && dp_monitor_is_configured(pdev))
  150. return QDF_STATUS_SUCCESS;
  151. }
  152. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx) ||
  153. !qdf_mem_smmu_s1_enabled(soc->osdev))
  154. return QDF_STATUS_SUCCESS;
  155. /**
  156. * Even if ipa pipes is disabled, but if it's unmap
  157. * operation and nbuf has done ipa smmu map before,
  158. * do ipa smmu unmap as well.
  159. */
  160. if (!qdf_atomic_read(&soc->ipa_pipes_enabled)) {
  161. if (!create && qdf_nbuf_is_rx_ipa_smmu_map(nbuf)) {
  162. DP_STATS_INC(soc, rx.err.ipa_unmap_no_pipe, 1);
  163. } else {
  164. return QDF_STATUS_SUCCESS;
  165. }
  166. }
  167. if (qdf_unlikely(create == qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  168. if (create) {
  169. DP_STATS_INC(soc, rx.err.ipa_smmu_map_dup, 1);
  170. } else {
  171. DP_STATS_INC(soc, rx.err.ipa_smmu_unmap_dup, 1);
  172. }
  173. return QDF_STATUS_E_INVAL;
  174. }
  175. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  176. return __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, size, create,
  177. func, line);
  178. }
  179. static QDF_STATUS __dp_ipa_tx_buf_smmu_mapping(
  180. struct dp_soc *soc,
  181. struct dp_pdev *pdev,
  182. bool create,
  183. const char *func,
  184. uint32_t line)
  185. {
  186. uint32_t index;
  187. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  188. uint32_t tx_buffer_cnt = soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  189. qdf_nbuf_t nbuf;
  190. uint32_t buf_len;
  191. if (!ipa_is_ready()) {
  192. dp_info("IPA is not READY");
  193. return 0;
  194. }
  195. for (index = 0; index < tx_buffer_cnt; index++) {
  196. nbuf = (qdf_nbuf_t)
  197. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[index];
  198. if (!nbuf)
  199. continue;
  200. buf_len = qdf_nbuf_get_data_len(nbuf);
  201. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  202. create, func, line);
  203. }
  204. return ret;
  205. }
  206. #ifndef QCA_OL_DP_SRNG_LOCK_LESS_ACCESS
  207. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  208. bool lock_required)
  209. {
  210. hal_ring_handle_t hal_ring_hdl;
  211. int ring;
  212. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  213. hal_ring_hdl = soc->reo_dest_ring[ring].hal_srng;
  214. hal_srng_lock(hal_ring_hdl);
  215. soc->ipa_reo_ctx_lock_required[ring] = lock_required;
  216. hal_srng_unlock(hal_ring_hdl);
  217. }
  218. }
  219. #else
  220. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  221. bool lock_required)
  222. {
  223. }
  224. #endif
  225. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  226. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  227. struct dp_pdev *pdev,
  228. bool create,
  229. const char *func,
  230. uint32_t line)
  231. {
  232. struct rx_desc_pool *rx_pool;
  233. uint8_t pdev_id;
  234. uint32_t num_desc, page_id, offset, i;
  235. uint16_t num_desc_per_page;
  236. union dp_rx_desc_list_elem_t *rx_desc_elem;
  237. struct dp_rx_desc *rx_desc;
  238. qdf_nbuf_t nbuf;
  239. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  240. if (!qdf_ipa_is_ready())
  241. return ret;
  242. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  243. return ret;
  244. pdev_id = pdev->pdev_id;
  245. rx_pool = &soc->rx_desc_buf[pdev_id];
  246. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  247. qdf_spin_lock_bh(&rx_pool->lock);
  248. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  249. num_desc = rx_pool->pool_size;
  250. num_desc_per_page = rx_pool->desc_pages.num_element_per_page;
  251. for (i = 0; i < num_desc; i++) {
  252. page_id = i / num_desc_per_page;
  253. offset = i % num_desc_per_page;
  254. if (qdf_unlikely(!(rx_pool->desc_pages.cacheable_pages)))
  255. break;
  256. rx_desc_elem = dp_rx_desc_find(page_id, offset, rx_pool);
  257. rx_desc = &rx_desc_elem->rx_desc;
  258. if ((!(rx_desc->in_use)) || rx_desc->unmapped)
  259. continue;
  260. nbuf = rx_desc->nbuf;
  261. if (qdf_unlikely(create ==
  262. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  263. if (create) {
  264. DP_STATS_INC(soc,
  265. rx.err.ipa_smmu_map_dup, 1);
  266. } else {
  267. DP_STATS_INC(soc,
  268. rx.err.ipa_smmu_unmap_dup, 1);
  269. }
  270. continue;
  271. }
  272. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  273. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  274. rx_pool->buf_size,
  275. create, func, line);
  276. }
  277. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  278. qdf_spin_unlock_bh(&rx_pool->lock);
  279. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  280. return ret;
  281. }
  282. #else
  283. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(
  284. struct dp_soc *soc,
  285. struct dp_pdev *pdev,
  286. bool create,
  287. const char *func,
  288. uint32_t line)
  289. {
  290. struct rx_desc_pool *rx_pool;
  291. uint8_t pdev_id;
  292. qdf_nbuf_t nbuf;
  293. int i;
  294. if (!qdf_ipa_is_ready())
  295. return QDF_STATUS_SUCCESS;
  296. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  297. return QDF_STATUS_SUCCESS;
  298. pdev_id = pdev->pdev_id;
  299. rx_pool = &soc->rx_desc_buf[pdev_id];
  300. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  301. qdf_spin_lock_bh(&rx_pool->lock);
  302. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  303. for (i = 0; i < rx_pool->pool_size; i++) {
  304. if ((!(rx_pool->array[i].rx_desc.in_use)) ||
  305. rx_pool->array[i].rx_desc.unmapped)
  306. continue;
  307. nbuf = rx_pool->array[i].rx_desc.nbuf;
  308. if (qdf_unlikely(create ==
  309. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  310. if (create) {
  311. DP_STATS_INC(soc,
  312. rx.err.ipa_smmu_map_dup, 1);
  313. } else {
  314. DP_STATS_INC(soc,
  315. rx.err.ipa_smmu_unmap_dup, 1);
  316. }
  317. continue;
  318. }
  319. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  320. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, rx_pool->buf_size,
  321. create, func, line);
  322. }
  323. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  324. qdf_spin_unlock_bh(&rx_pool->lock);
  325. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  326. return QDF_STATUS_SUCCESS;
  327. }
  328. #endif /* RX_DESC_MULTI_PAGE_ALLOC */
  329. static QDF_STATUS dp_ipa_get_shared_mem_info(qdf_device_t osdev,
  330. qdf_shared_mem_t *shared_mem,
  331. void *cpu_addr,
  332. qdf_dma_addr_t dma_addr,
  333. uint32_t size)
  334. {
  335. qdf_dma_addr_t paddr;
  336. int ret;
  337. shared_mem->vaddr = cpu_addr;
  338. qdf_mem_set_dma_size(osdev, &shared_mem->mem_info, size);
  339. *qdf_mem_get_dma_addr_ptr(osdev, &shared_mem->mem_info) = dma_addr;
  340. paddr = qdf_mem_paddr_from_dmaaddr(osdev, dma_addr);
  341. qdf_mem_set_dma_pa(osdev, &shared_mem->mem_info, paddr);
  342. ret = qdf_mem_dma_get_sgtable(osdev->dev, &shared_mem->sgtable,
  343. shared_mem->vaddr, dma_addr, size);
  344. if (ret) {
  345. dp_err("Unable to get DMA sgtable");
  346. return QDF_STATUS_E_NOMEM;
  347. }
  348. qdf_dma_get_sgtable_dma_addr(&shared_mem->sgtable);
  349. return QDF_STATUS_SUCCESS;
  350. }
  351. /**
  352. * dp_ipa_get_tx_bank_id - API to get TCL bank id
  353. * @soc: dp_soc handle
  354. * @bank_id: out parameter for bank id
  355. *
  356. * Return: QDF_STATUS
  357. */
  358. static QDF_STATUS dp_ipa_get_tx_bank_id(struct dp_soc *soc, uint8_t *bank_id)
  359. {
  360. if (soc->arch_ops.ipa_get_bank_id) {
  361. *bank_id = soc->arch_ops.ipa_get_bank_id(soc);
  362. if (*bank_id < 0) {
  363. return QDF_STATUS_E_INVAL;
  364. } else {
  365. dp_info("bank_id %u", *bank_id);
  366. return QDF_STATUS_SUCCESS;
  367. }
  368. } else {
  369. return QDF_STATUS_E_NOSUPPORT;
  370. }
  371. }
  372. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  373. defined(CONFIG_IPA_WDI_UNIFIED_API)
  374. static void dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  375. qdf_ipa_wdi_pipe_setup_info_t *tx)
  376. {
  377. uint8_t bank_id;
  378. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  379. QDF_IPA_WDI_SETUP_INFO_RX_BANK_ID(tx, bank_id);
  380. }
  381. static void
  382. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  383. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  384. {
  385. uint8_t bank_id;
  386. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  387. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_BANK_ID(tx_smmu, bank_id);
  388. }
  389. #else
  390. static inline void
  391. dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  392. qdf_ipa_wdi_pipe_setup_info_t *tx)
  393. {
  394. }
  395. static inline void
  396. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  397. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  398. {
  399. }
  400. #endif
  401. #ifdef IPA_WDI3_TX_TWO_PIPES
  402. static void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  403. {
  404. struct dp_ipa_resources *ipa_res;
  405. qdf_nbuf_t nbuf;
  406. int idx;
  407. for (idx = 0; idx < soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt; idx++) {
  408. nbuf = (qdf_nbuf_t)
  409. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx];
  410. if (!nbuf)
  411. continue;
  412. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  413. qdf_mem_dp_tx_skb_cnt_dec();
  414. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  415. qdf_nbuf_free(nbuf);
  416. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx] =
  417. (void *)NULL;
  418. }
  419. qdf_mem_free(soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  420. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  421. ipa_res = &pdev->ipa_resource;
  422. if (!ipa_res->is_db_ddr_mapped)
  423. iounmap(ipa_res->tx_alt_comp_doorbell_vaddr);
  424. qdf_mem_free_sgtable(&ipa_res->tx_alt_ring.sgtable);
  425. qdf_mem_free_sgtable(&ipa_res->tx_alt_comp_ring.sgtable);
  426. }
  427. static int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  428. {
  429. uint32_t tx_buffer_count;
  430. uint32_t ring_base_align = 8;
  431. qdf_dma_addr_t buffer_paddr;
  432. struct hal_srng *wbm_srng = (struct hal_srng *)
  433. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  434. struct hal_srng_params srng_params;
  435. uint32_t wbm_bm_id;
  436. void *ring_entry;
  437. int num_entries;
  438. qdf_nbuf_t nbuf;
  439. int retval = QDF_STATUS_SUCCESS;
  440. int max_alloc_count = 0;
  441. /*
  442. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  443. * unsigned int uc_tx_buf_sz =
  444. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  445. */
  446. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  447. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  448. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  449. IPA_TX_ALT_RING_IDX);
  450. hal_get_srng_params(soc->hal_soc,
  451. hal_srng_to_hal_ring_handle(wbm_srng),
  452. &srng_params);
  453. num_entries = srng_params.num_entries;
  454. max_alloc_count =
  455. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  456. if (max_alloc_count <= 0) {
  457. dp_err("incorrect value for buffer count %u", max_alloc_count);
  458. return -EINVAL;
  459. }
  460. dp_info("requested %d buffers to be posted to wbm ring",
  461. max_alloc_count);
  462. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned =
  463. qdf_mem_malloc(num_entries *
  464. sizeof(*soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned));
  465. if (!soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned) {
  466. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  467. return -ENOMEM;
  468. }
  469. hal_srng_access_start_unlocked(soc->hal_soc,
  470. hal_srng_to_hal_ring_handle(wbm_srng));
  471. /*
  472. * Allocate Tx buffers as many as possible.
  473. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  474. * Populate Tx buffers into WBM2IPA ring
  475. * This initial buffer population will simulate H/W as source ring,
  476. * and update HP
  477. */
  478. for (tx_buffer_count = 0;
  479. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  480. nbuf = qdf_nbuf_alloc(soc->osdev, alloc_size, 0, 256, FALSE);
  481. if (!nbuf)
  482. break;
  483. ring_entry = hal_srng_dst_get_next_hp(
  484. soc->hal_soc,
  485. hal_srng_to_hal_ring_handle(wbm_srng));
  486. if (!ring_entry) {
  487. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  488. "%s: Failed to get WBM ring entry",
  489. __func__);
  490. qdf_nbuf_free(nbuf);
  491. break;
  492. }
  493. qdf_nbuf_map_single(soc->osdev, nbuf,
  494. QDF_DMA_BIDIRECTIONAL);
  495. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  496. qdf_mem_dp_tx_skb_cnt_inc();
  497. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  498. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  499. buffer_paddr, 0, wbm_bm_id);
  500. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[
  501. tx_buffer_count] = (void *)nbuf;
  502. }
  503. hal_srng_access_end_unlocked(soc->hal_soc,
  504. hal_srng_to_hal_ring_handle(wbm_srng));
  505. soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt = tx_buffer_count;
  506. if (tx_buffer_count) {
  507. dp_info("IPA TX buffer pool2: %d allocated", tx_buffer_count);
  508. } else {
  509. dp_err("Failed to allocate IPA TX buffer pool2");
  510. qdf_mem_free(
  511. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  512. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  513. retval = -ENOMEM;
  514. }
  515. return retval;
  516. }
  517. static QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  518. {
  519. struct dp_soc *soc = pdev->soc;
  520. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  521. ipa_res->tx_alt_ring_num_alloc_buffer =
  522. (uint32_t)soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt;
  523. dp_ipa_get_shared_mem_info(
  524. soc->osdev, &ipa_res->tx_alt_ring,
  525. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  526. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  527. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  528. dp_ipa_get_shared_mem_info(
  529. soc->osdev, &ipa_res->tx_alt_comp_ring,
  530. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  531. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  532. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  533. if (!qdf_mem_get_dma_addr(soc->osdev,
  534. &ipa_res->tx_alt_comp_ring.mem_info))
  535. return QDF_STATUS_E_FAILURE;
  536. return QDF_STATUS_SUCCESS;
  537. }
  538. static void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  539. {
  540. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  541. struct hal_srng *hal_srng;
  542. struct hal_srng_params srng_params;
  543. unsigned long addr_offset, dev_base_paddr;
  544. /* IPA TCL_DATA Alternative Ring - HAL_SRNG_SW2TCL2 */
  545. hal_srng = (struct hal_srng *)
  546. soc->tcl_data_ring[IPA_TX_ALT_RING_IDX].hal_srng;
  547. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  548. hal_srng_to_hal_ring_handle(hal_srng),
  549. &srng_params);
  550. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr =
  551. srng_params.ring_base_paddr;
  552. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr =
  553. srng_params.ring_base_vaddr;
  554. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size =
  555. (srng_params.num_entries * srng_params.entry_size) << 2;
  556. /*
  557. * For the register backed memory addresses, use the scn->mem_pa to
  558. * calculate the physical address of the shadow registers
  559. */
  560. dev_base_paddr =
  561. (unsigned long)
  562. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  563. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  564. (unsigned long)(hal_soc->dev_base_addr);
  565. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr =
  566. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  567. dp_info("IPA TCL_DATA Alt Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  568. (unsigned int)addr_offset,
  569. (unsigned int)dev_base_paddr,
  570. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr),
  571. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  572. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  573. srng_params.num_entries,
  574. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  575. /* IPA TX Alternative COMP Ring - HAL_SRNG_WBM2SW4_RELEASE */
  576. hal_srng = (struct hal_srng *)
  577. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  578. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  579. hal_srng_to_hal_ring_handle(hal_srng),
  580. &srng_params);
  581. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr =
  582. srng_params.ring_base_paddr;
  583. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr =
  584. srng_params.ring_base_vaddr;
  585. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size =
  586. (srng_params.num_entries * srng_params.entry_size) << 2;
  587. soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr =
  588. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  589. hal_srng_to_hal_ring_handle(hal_srng));
  590. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  591. (unsigned long)(hal_soc->dev_base_addr);
  592. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr =
  593. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  594. dp_info("IPA TX Alt COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  595. (unsigned int)addr_offset,
  596. (unsigned int)dev_base_paddr,
  597. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr),
  598. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  599. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  600. srng_params.num_entries,
  601. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  602. }
  603. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  604. {
  605. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  606. uint32_t rx_ready_doorbell_dmaaddr;
  607. uint32_t tx_comp_doorbell_dmaaddr;
  608. struct dp_soc *soc = pdev->soc;
  609. int ret = 0;
  610. if (ipa_res->is_db_ddr_mapped)
  611. ipa_res->tx_comp_doorbell_vaddr =
  612. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  613. else
  614. ipa_res->tx_comp_doorbell_vaddr =
  615. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  616. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  617. ret = pld_smmu_map(soc->osdev->dev,
  618. ipa_res->tx_comp_doorbell_paddr,
  619. &tx_comp_doorbell_dmaaddr,
  620. sizeof(uint32_t));
  621. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  622. qdf_assert_always(!ret);
  623. ret = pld_smmu_map(soc->osdev->dev,
  624. ipa_res->rx_ready_doorbell_paddr,
  625. &rx_ready_doorbell_dmaaddr,
  626. sizeof(uint32_t));
  627. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  628. qdf_assert_always(!ret);
  629. }
  630. /* Setup for alternative TX pipe */
  631. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  632. return;
  633. if (ipa_res->is_db_ddr_mapped)
  634. ipa_res->tx_alt_comp_doorbell_vaddr =
  635. phys_to_virt(ipa_res->tx_alt_comp_doorbell_paddr);
  636. else
  637. ipa_res->tx_alt_comp_doorbell_vaddr =
  638. ioremap(ipa_res->tx_alt_comp_doorbell_paddr, 4);
  639. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  640. ret = pld_smmu_map(soc->osdev->dev,
  641. ipa_res->tx_alt_comp_doorbell_paddr,
  642. &tx_comp_doorbell_dmaaddr,
  643. sizeof(uint32_t));
  644. ipa_res->tx_alt_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  645. qdf_assert_always(!ret);
  646. }
  647. }
  648. static void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  649. {
  650. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  651. struct dp_soc *soc = pdev->soc;
  652. int ret = 0;
  653. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  654. return;
  655. /* Unmap must be in reverse order of map */
  656. if (ipa_res->tx_alt_comp_doorbell_paddr) {
  657. ret = pld_smmu_unmap(soc->osdev->dev,
  658. ipa_res->tx_alt_comp_doorbell_paddr,
  659. sizeof(uint32_t));
  660. qdf_assert_always(!ret);
  661. }
  662. ret = pld_smmu_unmap(soc->osdev->dev,
  663. ipa_res->rx_ready_doorbell_paddr,
  664. sizeof(uint32_t));
  665. qdf_assert_always(!ret);
  666. ret = pld_smmu_unmap(soc->osdev->dev,
  667. ipa_res->tx_comp_doorbell_paddr,
  668. sizeof(uint32_t));
  669. qdf_assert_always(!ret);
  670. }
  671. static QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  672. struct dp_pdev *pdev,
  673. bool create, const char *func,
  674. uint32_t line)
  675. {
  676. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  677. struct ipa_dp_tx_rsc *rsc;
  678. uint32_t tx_buffer_cnt;
  679. uint32_t buf_len;
  680. qdf_nbuf_t nbuf;
  681. uint32_t index;
  682. if (!ipa_is_ready()) {
  683. dp_info("IPA is not READY");
  684. return QDF_STATUS_SUCCESS;
  685. }
  686. rsc = &soc->ipa_uc_tx_rsc_alt;
  687. tx_buffer_cnt = rsc->alloc_tx_buf_cnt;
  688. for (index = 0; index < tx_buffer_cnt; index++) {
  689. nbuf = (qdf_nbuf_t)rsc->tx_buf_pool_vaddr_unaligned[index];
  690. if (!nbuf)
  691. continue;
  692. buf_len = qdf_nbuf_get_data_len(nbuf);
  693. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  694. create, func, line);
  695. }
  696. return ret;
  697. }
  698. static void dp_ipa_wdi_tx_alt_pipe_params(struct dp_soc *soc,
  699. struct dp_ipa_resources *ipa_res,
  700. qdf_ipa_wdi_pipe_setup_info_t *tx)
  701. {
  702. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS1;
  703. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  704. qdf_mem_get_dma_addr(soc->osdev,
  705. &ipa_res->tx_alt_comp_ring.mem_info);
  706. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  707. qdf_mem_get_dma_size(soc->osdev,
  708. &ipa_res->tx_alt_comp_ring.mem_info);
  709. /* WBM Tail Pointer Address */
  710. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  711. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  712. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  713. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  714. qdf_mem_get_dma_addr(soc->osdev,
  715. &ipa_res->tx_alt_ring.mem_info);
  716. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  717. qdf_mem_get_dma_size(soc->osdev,
  718. &ipa_res->tx_alt_ring.mem_info);
  719. /* TCL Head Pointer Address */
  720. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  721. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  722. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  723. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  724. ipa_res->tx_alt_ring_num_alloc_buffer;
  725. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  726. dp_ipa_setup_tx_params_bank_id(soc, tx);
  727. }
  728. static void
  729. dp_ipa_wdi_tx_alt_pipe_smmu_params(struct dp_soc *soc,
  730. struct dp_ipa_resources *ipa_res,
  731. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  732. {
  733. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) = IPA_CLIENT_WLAN2_CONS1;
  734. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  735. &ipa_res->tx_alt_comp_ring.sgtable,
  736. sizeof(sgtable_t));
  737. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  738. qdf_mem_get_dma_size(soc->osdev,
  739. &ipa_res->tx_alt_comp_ring.mem_info);
  740. /* WBM Tail Pointer Address */
  741. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  742. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  743. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  744. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  745. &ipa_res->tx_alt_ring.sgtable,
  746. sizeof(sgtable_t));
  747. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  748. qdf_mem_get_dma_size(soc->osdev,
  749. &ipa_res->tx_alt_ring.mem_info);
  750. /* TCL Head Pointer Address */
  751. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  752. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  753. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  754. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  755. ipa_res->tx_alt_ring_num_alloc_buffer;
  756. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  757. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  758. }
  759. static void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc,
  760. struct dp_ipa_resources *res,
  761. qdf_ipa_wdi_conn_in_params_t *in)
  762. {
  763. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu = NULL;
  764. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  765. qdf_ipa_ep_cfg_t *tx_cfg;
  766. QDF_IPA_WDI_CONN_IN_PARAMS_IS_TX1_USED(in) = true;
  767. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  768. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE_SMMU(in);
  769. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  770. dp_ipa_wdi_tx_alt_pipe_smmu_params(soc, res, tx_smmu);
  771. } else {
  772. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE(in);
  773. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx);
  774. dp_ipa_wdi_tx_alt_pipe_params(soc, res, tx);
  775. }
  776. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  777. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  778. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  779. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  780. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  781. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  782. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  783. }
  784. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  785. qdf_ipa_wdi_conn_out_params_t *out)
  786. {
  787. res->tx_comp_doorbell_paddr =
  788. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  789. res->rx_ready_doorbell_paddr =
  790. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  791. res->tx_alt_comp_doorbell_paddr =
  792. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_ALT_DB_PA(out);
  793. }
  794. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  795. uint8_t session_id)
  796. {
  797. bool is_2g_iface = session_id & IPA_SESSION_ID_SHIFT;
  798. session_id = session_id >> IPA_SESSION_ID_SHIFT;
  799. dp_debug("session_id %u is_2g_iface %d", session_id, is_2g_iface);
  800. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  801. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_TX1_USED(in) = is_2g_iface;
  802. }
  803. static void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  804. struct dp_ipa_resources *res)
  805. {
  806. struct hal_srng *wbm_srng;
  807. /* Init first TX comp ring */
  808. wbm_srng = (struct hal_srng *)
  809. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  810. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  811. res->tx_comp_doorbell_vaddr);
  812. /* Init the alternate TX comp ring */
  813. wbm_srng = (struct hal_srng *)
  814. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  815. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  816. res->tx_alt_comp_doorbell_vaddr);
  817. }
  818. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  819. struct dp_ipa_resources *ipa_res)
  820. {
  821. struct hal_srng *wbm_srng;
  822. wbm_srng = (struct hal_srng *)
  823. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  824. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  825. ipa_res->tx_comp_doorbell_paddr);
  826. dp_info("paddr %pK vaddr %pK",
  827. (void *)ipa_res->tx_comp_doorbell_paddr,
  828. (void *)ipa_res->tx_comp_doorbell_vaddr);
  829. /* Setup for alternative TX comp ring */
  830. wbm_srng = (struct hal_srng *)
  831. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  832. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  833. ipa_res->tx_alt_comp_doorbell_paddr);
  834. dp_info("paddr %pK vaddr %pK",
  835. (void *)ipa_res->tx_alt_comp_doorbell_paddr,
  836. (void *)ipa_res->tx_alt_comp_doorbell_vaddr);
  837. }
  838. #ifdef IPA_SET_RESET_TX_DB_PA
  839. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  840. struct dp_ipa_resources *ipa_res)
  841. {
  842. hal_ring_handle_t wbm_srng;
  843. qdf_dma_addr_t hp_addr;
  844. wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  845. if (!wbm_srng)
  846. return QDF_STATUS_E_FAILURE;
  847. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  848. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  849. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  850. /* Reset alternative TX comp ring */
  851. wbm_srng = soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  852. if (!wbm_srng)
  853. return QDF_STATUS_E_FAILURE;
  854. hp_addr = soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr;
  855. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  856. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  857. return QDF_STATUS_SUCCESS;
  858. }
  859. #endif /* IPA_SET_RESET_TX_DB_PA */
  860. #else /* !IPA_WDI3_TX_TWO_PIPES */
  861. static inline
  862. void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  863. {
  864. }
  865. static inline void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  866. {
  867. }
  868. static inline int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  869. {
  870. return 0;
  871. }
  872. static inline QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  873. {
  874. return QDF_STATUS_SUCCESS;
  875. }
  876. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  877. {
  878. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  879. uint32_t rx_ready_doorbell_dmaaddr;
  880. uint32_t tx_comp_doorbell_dmaaddr;
  881. struct dp_soc *soc = pdev->soc;
  882. int ret = 0;
  883. if (ipa_res->is_db_ddr_mapped)
  884. ipa_res->tx_comp_doorbell_vaddr =
  885. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  886. else
  887. ipa_res->tx_comp_doorbell_vaddr =
  888. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  889. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  890. ret = pld_smmu_map(soc->osdev->dev,
  891. ipa_res->tx_comp_doorbell_paddr,
  892. &tx_comp_doorbell_dmaaddr,
  893. sizeof(uint32_t));
  894. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  895. qdf_assert_always(!ret);
  896. ret = pld_smmu_map(soc->osdev->dev,
  897. ipa_res->rx_ready_doorbell_paddr,
  898. &rx_ready_doorbell_dmaaddr,
  899. sizeof(uint32_t));
  900. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  901. qdf_assert_always(!ret);
  902. }
  903. }
  904. static inline void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  905. {
  906. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  907. struct dp_soc *soc = pdev->soc;
  908. int ret = 0;
  909. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  910. return;
  911. ret = pld_smmu_unmap(soc->osdev->dev,
  912. ipa_res->rx_ready_doorbell_paddr,
  913. sizeof(uint32_t));
  914. qdf_assert_always(!ret);
  915. ret = pld_smmu_unmap(soc->osdev->dev,
  916. ipa_res->tx_comp_doorbell_paddr,
  917. sizeof(uint32_t));
  918. qdf_assert_always(!ret);
  919. }
  920. static inline QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  921. struct dp_pdev *pdev,
  922. bool create,
  923. const char *func,
  924. uint32_t line)
  925. {
  926. return QDF_STATUS_SUCCESS;
  927. }
  928. static inline
  929. void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc, struct dp_ipa_resources *res,
  930. qdf_ipa_wdi_conn_in_params_t *in)
  931. {
  932. }
  933. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  934. qdf_ipa_wdi_conn_out_params_t *out)
  935. {
  936. res->tx_comp_doorbell_paddr =
  937. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  938. res->rx_ready_doorbell_paddr =
  939. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  940. }
  941. #ifdef IPA_WDS_EASYMESH_FEATURE
  942. /**
  943. * dp_ipa_setup_iface_session_id - Pass vdev id to IPA
  944. * @in: ipa in params
  945. * @session_id: vdev id
  946. *
  947. * Pass Vdev id to IPA, IPA metadata order is changed and vdev id
  948. * is stored at higher nibble so, no shift is required.
  949. *
  950. * Return: none
  951. */
  952. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  953. uint8_t session_id)
  954. {
  955. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id);
  956. }
  957. #else
  958. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  959. uint8_t session_id)
  960. {
  961. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  962. }
  963. #endif
  964. static inline void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  965. struct dp_ipa_resources *res)
  966. {
  967. struct hal_srng *wbm_srng = (struct hal_srng *)
  968. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  969. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  970. res->tx_comp_doorbell_vaddr);
  971. }
  972. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  973. struct dp_ipa_resources *ipa_res)
  974. {
  975. struct hal_srng *wbm_srng = (struct hal_srng *)
  976. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  977. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  978. ipa_res->tx_comp_doorbell_paddr);
  979. dp_info("paddr %pK vaddr %pK",
  980. (void *)ipa_res->tx_comp_doorbell_paddr,
  981. (void *)ipa_res->tx_comp_doorbell_vaddr);
  982. }
  983. #ifdef IPA_SET_RESET_TX_DB_PA
  984. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  985. struct dp_ipa_resources *ipa_res)
  986. {
  987. hal_ring_handle_t wbm_srng =
  988. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  989. qdf_dma_addr_t hp_addr;
  990. if (!wbm_srng)
  991. return QDF_STATUS_E_FAILURE;
  992. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  993. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  994. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  995. return QDF_STATUS_SUCCESS;
  996. }
  997. #endif /* IPA_SET_RESET_TX_DB_PA */
  998. #endif /* IPA_WDI3_TX_TWO_PIPES */
  999. /**
  1000. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  1001. * @soc: data path instance
  1002. * @pdev: core txrx pdev context
  1003. *
  1004. * Free allocated TX buffers with WBM SRNG
  1005. *
  1006. * Return: none
  1007. */
  1008. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1009. {
  1010. int idx;
  1011. qdf_nbuf_t nbuf;
  1012. struct dp_ipa_resources *ipa_res;
  1013. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  1014. nbuf = (qdf_nbuf_t)
  1015. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx];
  1016. if (!nbuf)
  1017. continue;
  1018. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  1019. qdf_mem_dp_tx_skb_cnt_dec();
  1020. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  1021. qdf_nbuf_free(nbuf);
  1022. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
  1023. (void *)NULL;
  1024. }
  1025. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1026. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1027. ipa_res = &pdev->ipa_resource;
  1028. qdf_mem_free_sgtable(&ipa_res->tx_ring.sgtable);
  1029. qdf_mem_free_sgtable(&ipa_res->tx_comp_ring.sgtable);
  1030. }
  1031. /**
  1032. * dp_rx_ipa_uc_detach - free autonomy RX resources
  1033. * @soc: data path instance
  1034. * @pdev: core txrx pdev context
  1035. *
  1036. * This function will detach DP RX into main device context
  1037. * will free DP Rx resources.
  1038. *
  1039. * Return: none
  1040. */
  1041. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1042. {
  1043. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1044. qdf_mem_free_sgtable(&ipa_res->rx_rdy_ring.sgtable);
  1045. qdf_mem_free_sgtable(&ipa_res->rx_refill_ring.sgtable);
  1046. }
  1047. /*
  1048. * dp_rx_alt_ipa_uc_detach - free autonomy RX resources
  1049. * @soc: data path instance
  1050. * @pdev: core txrx pdev context
  1051. *
  1052. * This function will detach DP RX into main device context
  1053. * will free DP Rx resources.
  1054. *
  1055. * Return: none
  1056. */
  1057. #ifdef IPA_WDI3_VLAN_SUPPORT
  1058. static void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1059. {
  1060. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1061. if (!wlan_ipa_is_vlan_enabled())
  1062. return;
  1063. qdf_mem_free_sgtable(&ipa_res->rx_alt_rdy_ring.sgtable);
  1064. qdf_mem_free_sgtable(&ipa_res->rx_alt_refill_ring.sgtable);
  1065. }
  1066. #else
  1067. static inline
  1068. void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1069. { }
  1070. #endif
  1071. int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1072. {
  1073. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1074. return QDF_STATUS_SUCCESS;
  1075. /* TX resource detach */
  1076. dp_tx_ipa_uc_detach(soc, pdev);
  1077. /* Cleanup 2nd TX pipe resources */
  1078. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1079. /* RX resource detach */
  1080. dp_rx_ipa_uc_detach(soc, pdev);
  1081. /* Cleanup 2nd RX pipe resources */
  1082. dp_rx_alt_ipa_uc_detach(soc, pdev);
  1083. return QDF_STATUS_SUCCESS; /* success */
  1084. }
  1085. /**
  1086. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  1087. * @soc: data path instance
  1088. * @pdev: Physical device handle
  1089. *
  1090. * Allocate TX buffer from non-cacheable memory
  1091. * Attach allocated TX buffers with WBM SRNG
  1092. *
  1093. * Return: int
  1094. */
  1095. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1096. {
  1097. uint32_t tx_buffer_count;
  1098. uint32_t ring_base_align = 8;
  1099. qdf_dma_addr_t buffer_paddr;
  1100. struct hal_srng *wbm_srng = (struct hal_srng *)
  1101. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1102. struct hal_srng_params srng_params;
  1103. void *ring_entry;
  1104. int num_entries;
  1105. qdf_nbuf_t nbuf;
  1106. int retval = QDF_STATUS_SUCCESS;
  1107. int max_alloc_count = 0;
  1108. uint32_t wbm_bm_id;
  1109. /*
  1110. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  1111. * unsigned int uc_tx_buf_sz =
  1112. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  1113. */
  1114. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  1115. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  1116. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  1117. IPA_TCL_DATA_RING_IDX);
  1118. hal_get_srng_params(soc->hal_soc, hal_srng_to_hal_ring_handle(wbm_srng),
  1119. &srng_params);
  1120. num_entries = srng_params.num_entries;
  1121. max_alloc_count =
  1122. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  1123. if (max_alloc_count <= 0) {
  1124. dp_err("incorrect value for buffer count %u", max_alloc_count);
  1125. return -EINVAL;
  1126. }
  1127. dp_info("requested %d buffers to be posted to wbm ring",
  1128. max_alloc_count);
  1129. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned =
  1130. qdf_mem_malloc(num_entries *
  1131. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned));
  1132. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned) {
  1133. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  1134. return -ENOMEM;
  1135. }
  1136. hal_srng_access_start_unlocked(soc->hal_soc,
  1137. hal_srng_to_hal_ring_handle(wbm_srng));
  1138. /*
  1139. * Allocate Tx buffers as many as possible.
  1140. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  1141. * Populate Tx buffers into WBM2IPA ring
  1142. * This initial buffer population will simulate H/W as source ring,
  1143. * and update HP
  1144. */
  1145. for (tx_buffer_count = 0;
  1146. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  1147. nbuf = qdf_nbuf_alloc(soc->osdev, alloc_size, 0, 256, FALSE);
  1148. if (!nbuf)
  1149. break;
  1150. ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
  1151. hal_srng_to_hal_ring_handle(wbm_srng));
  1152. if (!ring_entry) {
  1153. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1154. "%s: Failed to get WBM ring entry",
  1155. __func__);
  1156. qdf_nbuf_free(nbuf);
  1157. break;
  1158. }
  1159. qdf_nbuf_map_single(soc->osdev, nbuf,
  1160. QDF_DMA_BIDIRECTIONAL);
  1161. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1162. qdf_mem_dp_tx_skb_cnt_inc();
  1163. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  1164. /*
  1165. * TODO - KIWI code can directly call the be handler
  1166. * instead of hal soc ops.
  1167. */
  1168. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  1169. buffer_paddr, 0, wbm_bm_id);
  1170. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
  1171. = (void *)nbuf;
  1172. }
  1173. hal_srng_access_end_unlocked(soc->hal_soc,
  1174. hal_srng_to_hal_ring_handle(wbm_srng));
  1175. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  1176. if (tx_buffer_count) {
  1177. dp_info("IPA WDI TX buffer: %d allocated", tx_buffer_count);
  1178. } else {
  1179. dp_err("No IPA WDI TX buffer allocated!");
  1180. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1181. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1182. retval = -ENOMEM;
  1183. }
  1184. return retval;
  1185. }
  1186. /**
  1187. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  1188. * @soc: data path instance
  1189. * @pdev: core txrx pdev context
  1190. *
  1191. * This function will attach a DP RX instance into the main
  1192. * device (SOC) context.
  1193. *
  1194. * Return: QDF_STATUS_SUCCESS: success
  1195. * QDF_STATUS_E_RESOURCES: Error return
  1196. */
  1197. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1198. {
  1199. return QDF_STATUS_SUCCESS;
  1200. }
  1201. int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1202. {
  1203. int error;
  1204. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1205. return QDF_STATUS_SUCCESS;
  1206. /* TX resource attach */
  1207. error = dp_tx_ipa_uc_attach(soc, pdev);
  1208. if (error) {
  1209. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1210. "%s: DP IPA UC TX attach fail code %d",
  1211. __func__, error);
  1212. return error;
  1213. }
  1214. /* Setup 2nd TX pipe */
  1215. error = dp_ipa_tx_alt_pool_attach(soc);
  1216. if (error) {
  1217. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1218. "%s: DP IPA TX pool2 attach fail code %d",
  1219. __func__, error);
  1220. dp_tx_ipa_uc_detach(soc, pdev);
  1221. return error;
  1222. }
  1223. /* RX resource attach */
  1224. error = dp_rx_ipa_uc_attach(soc, pdev);
  1225. if (error) {
  1226. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1227. "%s: DP IPA UC RX attach fail code %d",
  1228. __func__, error);
  1229. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1230. dp_tx_ipa_uc_detach(soc, pdev);
  1231. return error;
  1232. }
  1233. return QDF_STATUS_SUCCESS; /* success */
  1234. }
  1235. #ifdef IPA_WDI3_VLAN_SUPPORT
  1236. /*
  1237. * dp_ipa_rx_alt_ring_resource_setup() - setup IPA 2nd RX ring resources
  1238. * @soc: data path SoC handle
  1239. * @pdev: data path pdev handle
  1240. *
  1241. * Return: none
  1242. */
  1243. static
  1244. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1245. {
  1246. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1247. struct hal_srng *hal_srng;
  1248. struct hal_srng_params srng_params;
  1249. unsigned long addr_offset, dev_base_paddr;
  1250. qdf_dma_addr_t hp_addr;
  1251. if (!wlan_ipa_is_vlan_enabled())
  1252. return;
  1253. dev_base_paddr =
  1254. (unsigned long)
  1255. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1256. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW3 */
  1257. hal_srng = (struct hal_srng *)
  1258. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1259. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1260. hal_srng_to_hal_ring_handle(hal_srng),
  1261. &srng_params);
  1262. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr =
  1263. srng_params.ring_base_paddr;
  1264. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr =
  1265. srng_params.ring_base_vaddr;
  1266. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size =
  1267. (srng_params.num_entries * srng_params.entry_size) << 2;
  1268. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1269. (unsigned long)(hal_soc->dev_base_addr);
  1270. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr =
  1271. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1272. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1273. (unsigned int)addr_offset,
  1274. (unsigned int)dev_base_paddr,
  1275. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr),
  1276. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1277. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1278. srng_params.num_entries,
  1279. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1280. hal_srng = (struct hal_srng *)
  1281. pdev->rx_refill_buf_ring3.hal_srng;
  1282. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1283. hal_srng_to_hal_ring_handle(hal_srng),
  1284. &srng_params);
  1285. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr =
  1286. srng_params.ring_base_paddr;
  1287. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr =
  1288. srng_params.ring_base_vaddr;
  1289. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size =
  1290. (srng_params.num_entries * srng_params.entry_size) << 2;
  1291. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1292. hal_srng_to_hal_ring_handle(hal_srng));
  1293. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr =
  1294. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1295. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1296. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr),
  1297. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1298. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1299. srng_params.num_entries,
  1300. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1301. }
  1302. #else
  1303. static inline
  1304. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1305. { }
  1306. #endif
  1307. /*
  1308. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1309. * @soc: data path SoC handle
  1310. *
  1311. * Return: none
  1312. */
  1313. int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1314. struct dp_pdev *pdev)
  1315. {
  1316. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1317. struct hal_srng *hal_srng;
  1318. struct hal_srng_params srng_params;
  1319. qdf_dma_addr_t hp_addr;
  1320. unsigned long addr_offset, dev_base_paddr;
  1321. uint32_t ix0;
  1322. uint8_t ix0_map[8];
  1323. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1324. return QDF_STATUS_SUCCESS;
  1325. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL3 */
  1326. hal_srng = (struct hal_srng *)
  1327. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1328. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1329. hal_srng_to_hal_ring_handle(hal_srng),
  1330. &srng_params);
  1331. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1332. srng_params.ring_base_paddr;
  1333. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1334. srng_params.ring_base_vaddr;
  1335. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1336. (srng_params.num_entries * srng_params.entry_size) << 2;
  1337. /*
  1338. * For the register backed memory addresses, use the scn->mem_pa to
  1339. * calculate the physical address of the shadow registers
  1340. */
  1341. dev_base_paddr =
  1342. (unsigned long)
  1343. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1344. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  1345. (unsigned long)(hal_soc->dev_base_addr);
  1346. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr =
  1347. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1348. dp_info("IPA TCL_DATA Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1349. (unsigned int)addr_offset,
  1350. (unsigned int)dev_base_paddr,
  1351. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr),
  1352. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1353. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1354. srng_params.num_entries,
  1355. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1356. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW2_RELEASE */
  1357. hal_srng = (struct hal_srng *)
  1358. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1359. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1360. hal_srng_to_hal_ring_handle(hal_srng),
  1361. &srng_params);
  1362. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1363. srng_params.ring_base_paddr;
  1364. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1365. srng_params.ring_base_vaddr;
  1366. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1367. (srng_params.num_entries * srng_params.entry_size) << 2;
  1368. soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr =
  1369. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1370. hal_srng_to_hal_ring_handle(hal_srng));
  1371. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1372. (unsigned long)(hal_soc->dev_base_addr);
  1373. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr =
  1374. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1375. dp_info("IPA TX COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  1376. (unsigned int)addr_offset,
  1377. (unsigned int)dev_base_paddr,
  1378. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr),
  1379. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1380. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1381. srng_params.num_entries,
  1382. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1383. dp_ipa_tx_alt_ring_resource_setup(soc);
  1384. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1385. hal_srng = (struct hal_srng *)
  1386. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1387. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1388. hal_srng_to_hal_ring_handle(hal_srng),
  1389. &srng_params);
  1390. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1391. srng_params.ring_base_paddr;
  1392. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1393. srng_params.ring_base_vaddr;
  1394. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1395. (srng_params.num_entries * srng_params.entry_size) << 2;
  1396. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1397. (unsigned long)(hal_soc->dev_base_addr);
  1398. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr =
  1399. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1400. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1401. (unsigned int)addr_offset,
  1402. (unsigned int)dev_base_paddr,
  1403. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr),
  1404. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1405. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1406. srng_params.num_entries,
  1407. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1408. hal_srng = (struct hal_srng *)
  1409. pdev->rx_refill_buf_ring2.hal_srng;
  1410. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1411. hal_srng_to_hal_ring_handle(hal_srng),
  1412. &srng_params);
  1413. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1414. srng_params.ring_base_paddr;
  1415. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1416. srng_params.ring_base_vaddr;
  1417. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1418. (srng_params.num_entries * srng_params.entry_size) << 2;
  1419. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1420. hal_srng_to_hal_ring_handle(hal_srng));
  1421. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr =
  1422. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1423. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1424. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr),
  1425. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1426. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1427. srng_params.num_entries,
  1428. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1429. /*
  1430. * Set DEST_RING_MAPPING_4 to SW2 as default value for
  1431. * DESTINATION_RING_CTRL_IX_0.
  1432. */
  1433. ix0_map[0] = REO_REMAP_SW1;
  1434. ix0_map[1] = REO_REMAP_SW1;
  1435. ix0_map[2] = REO_REMAP_SW2;
  1436. ix0_map[3] = REO_REMAP_SW3;
  1437. ix0_map[4] = REO_REMAP_SW2;
  1438. ix0_map[5] = REO_REMAP_RELEASE;
  1439. ix0_map[6] = REO_REMAP_FW;
  1440. ix0_map[7] = REO_REMAP_FW;
  1441. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1442. ix0_map);
  1443. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL, NULL, NULL);
  1444. dp_ipa_rx_alt_ring_resource_setup(soc, pdev);
  1445. return 0;
  1446. }
  1447. #ifdef IPA_WDI3_VLAN_SUPPORT
  1448. /*
  1449. * dp_ipa_rx_alt_ring_get_resource() - get IPA 2nd RX ring resources
  1450. * @pdev: data path pdev handle
  1451. *
  1452. * Return: Success if resourece is found
  1453. */
  1454. static QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1455. {
  1456. struct dp_soc *soc = pdev->soc;
  1457. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1458. if (!wlan_ipa_is_vlan_enabled())
  1459. return QDF_STATUS_SUCCESS;
  1460. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_alt_rdy_ring,
  1461. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1462. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1463. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1464. dp_ipa_get_shared_mem_info(
  1465. soc->osdev, &ipa_res->rx_alt_refill_ring,
  1466. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1467. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1468. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1469. if (!qdf_mem_get_dma_addr(soc->osdev,
  1470. &ipa_res->rx_alt_rdy_ring.mem_info) ||
  1471. !qdf_mem_get_dma_addr(soc->osdev,
  1472. &ipa_res->rx_alt_refill_ring.mem_info))
  1473. return QDF_STATUS_E_FAILURE;
  1474. return QDF_STATUS_SUCCESS;
  1475. }
  1476. #else
  1477. static inline QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1478. {
  1479. return QDF_STATUS_SUCCESS;
  1480. }
  1481. #endif
  1482. QDF_STATUS dp_ipa_get_resource(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1483. {
  1484. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1485. struct dp_pdev *pdev =
  1486. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1487. struct dp_ipa_resources *ipa_res;
  1488. if (!pdev) {
  1489. dp_err("Invalid instance");
  1490. return QDF_STATUS_E_FAILURE;
  1491. }
  1492. ipa_res = &pdev->ipa_resource;
  1493. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1494. return QDF_STATUS_SUCCESS;
  1495. ipa_res->tx_num_alloc_buffer =
  1496. (uint32_t)soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  1497. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_ring,
  1498. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1499. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1500. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1501. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_comp_ring,
  1502. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1503. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1504. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1505. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_rdy_ring,
  1506. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1507. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1508. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1509. dp_ipa_get_shared_mem_info(
  1510. soc->osdev, &ipa_res->rx_refill_ring,
  1511. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1512. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1513. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1514. if (!qdf_mem_get_dma_addr(soc->osdev, &ipa_res->tx_ring.mem_info) ||
  1515. !qdf_mem_get_dma_addr(soc->osdev,
  1516. &ipa_res->tx_comp_ring.mem_info) ||
  1517. !qdf_mem_get_dma_addr(soc->osdev, &ipa_res->rx_rdy_ring.mem_info) ||
  1518. !qdf_mem_get_dma_addr(soc->osdev,
  1519. &ipa_res->rx_refill_ring.mem_info))
  1520. return QDF_STATUS_E_FAILURE;
  1521. if (dp_ipa_tx_alt_ring_get_resource(pdev))
  1522. return QDF_STATUS_E_FAILURE;
  1523. if (dp_ipa_rx_alt_ring_get_resource(pdev))
  1524. return QDF_STATUS_E_FAILURE;
  1525. return QDF_STATUS_SUCCESS;
  1526. }
  1527. #ifdef IPA_SET_RESET_TX_DB_PA
  1528. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res)
  1529. #else
  1530. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res) \
  1531. dp_ipa_set_tx_doorbell_paddr(soc, ipa_res)
  1532. #endif
  1533. #ifdef IPA_WDI3_VLAN_SUPPORT
  1534. /*
  1535. * dp_ipa_map_rx_alt_ring_doorbell_paddr() - Map 2nd rx ring doorbell paddr
  1536. * @pdev: data path pdev handle
  1537. *
  1538. * Return: none
  1539. */
  1540. static void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1541. {
  1542. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1543. uint32_t rx_ready_doorbell_dmaaddr;
  1544. struct dp_soc *soc = pdev->soc;
  1545. struct hal_srng *reo_srng = (struct hal_srng *)
  1546. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1547. int ret = 0;
  1548. if (!wlan_ipa_is_vlan_enabled())
  1549. return;
  1550. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1551. ret = pld_smmu_map(soc->osdev->dev,
  1552. ipa_res->rx_alt_ready_doorbell_paddr,
  1553. &rx_ready_doorbell_dmaaddr,
  1554. sizeof(uint32_t));
  1555. ipa_res->rx_alt_ready_doorbell_paddr =
  1556. rx_ready_doorbell_dmaaddr;
  1557. qdf_assert_always(!ret);
  1558. }
  1559. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1560. ipa_res->rx_alt_ready_doorbell_paddr);
  1561. }
  1562. /*
  1563. * dp_ipa_unmap_rx_alt_ring_doorbell_paddr() - Unmap 2nd rx ring doorbell paddr
  1564. * @pdev: data path pdev handle
  1565. *
  1566. * Return: none
  1567. */
  1568. static void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1569. {
  1570. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1571. struct dp_soc *soc = pdev->soc;
  1572. int ret = 0;
  1573. if (!wlan_ipa_is_vlan_enabled())
  1574. return;
  1575. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  1576. return;
  1577. ret = pld_smmu_unmap(soc->osdev->dev,
  1578. ipa_res->rx_alt_ready_doorbell_paddr,
  1579. sizeof(uint32_t));
  1580. qdf_assert_always(!ret);
  1581. }
  1582. #else
  1583. static inline void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1584. { }
  1585. static inline void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1586. { }
  1587. #endif
  1588. QDF_STATUS dp_ipa_set_doorbell_paddr(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1589. {
  1590. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1591. struct dp_pdev *pdev =
  1592. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1593. struct dp_ipa_resources *ipa_res;
  1594. struct hal_srng *reo_srng = (struct hal_srng *)
  1595. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1596. if (!pdev) {
  1597. dp_err("Invalid instance");
  1598. return QDF_STATUS_E_FAILURE;
  1599. }
  1600. ipa_res = &pdev->ipa_resource;
  1601. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1602. return QDF_STATUS_SUCCESS;
  1603. dp_ipa_map_ring_doorbell_paddr(pdev);
  1604. dp_ipa_map_rx_alt_ring_doorbell_paddr(pdev);
  1605. DP_IPA_SET_TX_DB_PADDR(soc, ipa_res);
  1606. /*
  1607. * For RX, REO module on Napier/Hastings does reordering on incoming
  1608. * Ethernet packets and writes one or more descriptors to REO2IPA Rx
  1609. * ring.It then updates the ring’s Write/Head ptr and rings a doorbell
  1610. * to IPA.
  1611. * Set the doorbell addr for the REO ring.
  1612. */
  1613. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1614. ipa_res->rx_ready_doorbell_paddr);
  1615. return QDF_STATUS_SUCCESS;
  1616. }
  1617. QDF_STATUS dp_ipa_iounmap_doorbell_vaddr(struct cdp_soc_t *soc_hdl,
  1618. uint8_t pdev_id)
  1619. {
  1620. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1621. struct dp_pdev *pdev =
  1622. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1623. struct dp_ipa_resources *ipa_res;
  1624. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1625. return QDF_STATUS_SUCCESS;
  1626. if (!pdev) {
  1627. dp_err("Invalid instance");
  1628. return QDF_STATUS_E_FAILURE;
  1629. }
  1630. ipa_res = &pdev->ipa_resource;
  1631. if (!ipa_res->is_db_ddr_mapped)
  1632. iounmap(ipa_res->tx_comp_doorbell_vaddr);
  1633. return QDF_STATUS_SUCCESS;
  1634. }
  1635. QDF_STATUS dp_ipa_op_response(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1636. uint8_t *op_msg)
  1637. {
  1638. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1639. struct dp_pdev *pdev =
  1640. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1641. if (!pdev) {
  1642. dp_err("Invalid instance");
  1643. return QDF_STATUS_E_FAILURE;
  1644. }
  1645. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1646. return QDF_STATUS_SUCCESS;
  1647. if (pdev->ipa_uc_op_cb) {
  1648. pdev->ipa_uc_op_cb(op_msg, pdev->usr_ctxt);
  1649. } else {
  1650. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1651. "%s: IPA callback function is not registered", __func__);
  1652. qdf_mem_free(op_msg);
  1653. return QDF_STATUS_E_FAILURE;
  1654. }
  1655. return QDF_STATUS_SUCCESS;
  1656. }
  1657. QDF_STATUS dp_ipa_register_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1658. ipa_uc_op_cb_type op_cb,
  1659. void *usr_ctxt)
  1660. {
  1661. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1662. struct dp_pdev *pdev =
  1663. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1664. if (!pdev) {
  1665. dp_err("Invalid instance");
  1666. return QDF_STATUS_E_FAILURE;
  1667. }
  1668. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1669. return QDF_STATUS_SUCCESS;
  1670. pdev->ipa_uc_op_cb = op_cb;
  1671. pdev->usr_ctxt = usr_ctxt;
  1672. return QDF_STATUS_SUCCESS;
  1673. }
  1674. void dp_ipa_deregister_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1675. {
  1676. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1677. struct dp_pdev *pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1678. if (!pdev) {
  1679. dp_err("Invalid instance");
  1680. return;
  1681. }
  1682. dp_debug("Deregister OP handler callback");
  1683. pdev->ipa_uc_op_cb = NULL;
  1684. pdev->usr_ctxt = NULL;
  1685. }
  1686. QDF_STATUS dp_ipa_get_stat(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1687. {
  1688. /* TBD */
  1689. return QDF_STATUS_SUCCESS;
  1690. }
  1691. /**
  1692. * dp_tx_send_ipa_data_frame() - send IPA data frame
  1693. * @soc_hdl: datapath soc handle
  1694. * @vdev_id: id of the virtual device
  1695. * @skb: skb to transmit
  1696. *
  1697. * Return: skb/ NULL is for success
  1698. */
  1699. qdf_nbuf_t dp_tx_send_ipa_data_frame(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1700. qdf_nbuf_t skb)
  1701. {
  1702. qdf_nbuf_t ret;
  1703. /* Terminate the (single-element) list of tx frames */
  1704. qdf_nbuf_set_next(skb, NULL);
  1705. ret = dp_tx_send(soc_hdl, vdev_id, skb);
  1706. if (ret) {
  1707. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1708. "%s: Failed to tx", __func__);
  1709. return ret;
  1710. }
  1711. return NULL;
  1712. }
  1713. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  1714. /**
  1715. * dp_ipa_is_target_ready() - check if target is ready or not
  1716. * @soc: datapath soc handle
  1717. *
  1718. * Return: true if target is ready
  1719. */
  1720. static inline
  1721. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1722. {
  1723. if (hif_get_target_status(soc->hif_handle) == TARGET_STATUS_RESET)
  1724. return false;
  1725. else
  1726. return true;
  1727. }
  1728. #else
  1729. static inline
  1730. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1731. {
  1732. return true;
  1733. }
  1734. #endif
  1735. QDF_STATUS dp_ipa_enable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1736. {
  1737. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1738. struct dp_pdev *pdev =
  1739. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1740. uint32_t ix0;
  1741. uint32_t ix2;
  1742. uint8_t ix_map[8];
  1743. if (!pdev) {
  1744. dp_err("Invalid instance");
  1745. return QDF_STATUS_E_FAILURE;
  1746. }
  1747. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1748. return QDF_STATUS_SUCCESS;
  1749. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1750. return QDF_STATUS_E_AGAIN;
  1751. if (!dp_ipa_is_target_ready(soc))
  1752. return QDF_STATUS_E_AGAIN;
  1753. /* Call HAL API to remap REO rings to REO2IPA ring */
  1754. ix_map[0] = REO_REMAP_SW1;
  1755. ix_map[1] = REO_REMAP_SW4;
  1756. ix_map[2] = REO_REMAP_SW1;
  1757. if (wlan_ipa_is_vlan_enabled())
  1758. ix_map[3] = REO_REMAP_SW3;
  1759. else
  1760. ix_map[3] = REO_REMAP_SW4;
  1761. ix_map[4] = REO_REMAP_SW4;
  1762. ix_map[5] = REO_REMAP_RELEASE;
  1763. ix_map[6] = REO_REMAP_FW;
  1764. ix_map[7] = REO_REMAP_FW;
  1765. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1766. ix_map);
  1767. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1768. ix_map[0] = REO_REMAP_SW4;
  1769. ix_map[1] = REO_REMAP_SW4;
  1770. ix_map[2] = REO_REMAP_SW4;
  1771. ix_map[3] = REO_REMAP_SW4;
  1772. ix_map[4] = REO_REMAP_SW4;
  1773. ix_map[5] = REO_REMAP_SW4;
  1774. ix_map[6] = REO_REMAP_SW4;
  1775. ix_map[7] = REO_REMAP_SW4;
  1776. ix2 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX2,
  1777. ix_map);
  1778. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1779. &ix2, &ix2);
  1780. dp_ipa_reo_remap_history_add(ix0, ix2, ix2);
  1781. } else {
  1782. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1783. NULL, NULL);
  1784. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1785. }
  1786. return QDF_STATUS_SUCCESS;
  1787. }
  1788. QDF_STATUS dp_ipa_disable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1789. {
  1790. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1791. struct dp_pdev *pdev =
  1792. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1793. uint8_t ix0_map[8];
  1794. uint32_t ix0;
  1795. uint32_t ix1;
  1796. uint32_t ix2;
  1797. uint32_t ix3;
  1798. if (!pdev) {
  1799. dp_err("Invalid instance");
  1800. return QDF_STATUS_E_FAILURE;
  1801. }
  1802. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1803. return QDF_STATUS_SUCCESS;
  1804. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1805. return QDF_STATUS_E_AGAIN;
  1806. if (!dp_ipa_is_target_ready(soc))
  1807. return QDF_STATUS_E_AGAIN;
  1808. ix0_map[0] = REO_REMAP_SW1;
  1809. ix0_map[1] = REO_REMAP_SW1;
  1810. ix0_map[2] = REO_REMAP_SW2;
  1811. ix0_map[3] = REO_REMAP_SW3;
  1812. ix0_map[4] = REO_REMAP_SW2;
  1813. ix0_map[5] = REO_REMAP_RELEASE;
  1814. ix0_map[6] = REO_REMAP_FW;
  1815. ix0_map[7] = REO_REMAP_FW;
  1816. /* Call HAL API to remap REO rings to REO2IPA ring */
  1817. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1818. ix0_map);
  1819. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1820. dp_reo_remap_config(soc, &ix1, &ix2, &ix3);
  1821. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1822. &ix2, &ix3);
  1823. dp_ipa_reo_remap_history_add(ix0, ix2, ix3);
  1824. } else {
  1825. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1826. NULL, NULL);
  1827. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1828. }
  1829. return QDF_STATUS_SUCCESS;
  1830. }
  1831. /* This should be configurable per H/W configuration enable status */
  1832. #define L3_HEADER_PADDING 2
  1833. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  1834. defined(CONFIG_IPA_WDI_UNIFIED_API)
  1835. #if !defined(QCA_LL_TX_FLOW_CONTROL_V2) && !defined(QCA_IPA_LL_TX_FLOW_CONTROL)
  1836. static inline void dp_setup_mcc_sys_pipes(
  1837. qdf_ipa_sys_connect_params_t *sys_in,
  1838. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  1839. {
  1840. int i = 0;
  1841. /* Setup MCC sys pipe */
  1842. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) =
  1843. DP_IPA_MAX_IFACE;
  1844. for (i = 0; i < DP_IPA_MAX_IFACE; i++)
  1845. memcpy(&QDF_IPA_WDI_CONN_IN_PARAMS_SYS_IN(pipe_in)[i],
  1846. &sys_in[i], sizeof(qdf_ipa_sys_connect_params_t));
  1847. }
  1848. #else
  1849. static inline void dp_setup_mcc_sys_pipes(
  1850. qdf_ipa_sys_connect_params_t *sys_in,
  1851. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  1852. {
  1853. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) = 0;
  1854. }
  1855. #endif
  1856. static void dp_ipa_wdi_tx_params(struct dp_soc *soc,
  1857. struct dp_ipa_resources *ipa_res,
  1858. qdf_ipa_wdi_pipe_setup_info_t *tx,
  1859. bool over_gsi)
  1860. {
  1861. if (over_gsi)
  1862. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS;
  1863. else
  1864. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  1865. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  1866. qdf_mem_get_dma_addr(soc->osdev,
  1867. &ipa_res->tx_comp_ring.mem_info);
  1868. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  1869. qdf_mem_get_dma_size(soc->osdev,
  1870. &ipa_res->tx_comp_ring.mem_info);
  1871. /* WBM Tail Pointer Address */
  1872. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  1873. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  1874. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  1875. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  1876. qdf_mem_get_dma_addr(soc->osdev,
  1877. &ipa_res->tx_ring.mem_info);
  1878. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  1879. qdf_mem_get_dma_size(soc->osdev,
  1880. &ipa_res->tx_ring.mem_info);
  1881. /* TCL Head Pointer Address */
  1882. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  1883. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  1884. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  1885. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  1886. ipa_res->tx_num_alloc_buffer;
  1887. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  1888. dp_ipa_setup_tx_params_bank_id(soc, tx);
  1889. }
  1890. static void dp_ipa_wdi_rx_params(struct dp_soc *soc,
  1891. struct dp_ipa_resources *ipa_res,
  1892. qdf_ipa_wdi_pipe_setup_info_t *rx,
  1893. bool over_gsi)
  1894. {
  1895. if (over_gsi)
  1896. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  1897. IPA_CLIENT_WLAN2_PROD;
  1898. else
  1899. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  1900. IPA_CLIENT_WLAN1_PROD;
  1901. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  1902. qdf_mem_get_dma_addr(soc->osdev,
  1903. &ipa_res->rx_rdy_ring.mem_info);
  1904. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  1905. qdf_mem_get_dma_size(soc->osdev,
  1906. &ipa_res->rx_rdy_ring.mem_info);
  1907. /* REO Tail Pointer Address */
  1908. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  1909. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  1910. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  1911. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  1912. qdf_mem_get_dma_addr(soc->osdev,
  1913. &ipa_res->rx_refill_ring.mem_info);
  1914. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  1915. qdf_mem_get_dma_size(soc->osdev,
  1916. &ipa_res->rx_refill_ring.mem_info);
  1917. /* FW Head Pointer Address */
  1918. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  1919. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  1920. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  1921. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  1922. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  1923. }
  1924. static void
  1925. dp_ipa_wdi_tx_smmu_params(struct dp_soc *soc,
  1926. struct dp_ipa_resources *ipa_res,
  1927. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu,
  1928. bool over_gsi,
  1929. qdf_ipa_wdi_hdl_t hdl)
  1930. {
  1931. if (over_gsi) {
  1932. if (hdl == DP_IPA_HDL_FIRST)
  1933. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  1934. IPA_CLIENT_WLAN2_CONS;
  1935. else if (hdl == DP_IPA_HDL_SECOND)
  1936. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  1937. IPA_CLIENT_WLAN4_CONS;
  1938. } else {
  1939. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  1940. IPA_CLIENT_WLAN1_CONS;
  1941. }
  1942. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  1943. &ipa_res->tx_comp_ring.sgtable,
  1944. sizeof(sgtable_t));
  1945. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  1946. qdf_mem_get_dma_size(soc->osdev,
  1947. &ipa_res->tx_comp_ring.mem_info);
  1948. /* WBM Tail Pointer Address */
  1949. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  1950. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  1951. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  1952. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  1953. &ipa_res->tx_ring.sgtable,
  1954. sizeof(sgtable_t));
  1955. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  1956. qdf_mem_get_dma_size(soc->osdev,
  1957. &ipa_res->tx_ring.mem_info);
  1958. /* TCL Head Pointer Address */
  1959. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  1960. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  1961. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  1962. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  1963. ipa_res->tx_num_alloc_buffer;
  1964. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  1965. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  1966. }
  1967. static void
  1968. dp_ipa_wdi_rx_smmu_params(struct dp_soc *soc,
  1969. struct dp_ipa_resources *ipa_res,
  1970. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  1971. bool over_gsi,
  1972. qdf_ipa_wdi_hdl_t hdl)
  1973. {
  1974. if (over_gsi) {
  1975. if (hdl == DP_IPA_HDL_FIRST)
  1976. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  1977. IPA_CLIENT_WLAN2_PROD;
  1978. else if (hdl == DP_IPA_HDL_SECOND)
  1979. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  1980. IPA_CLIENT_WLAN3_PROD;
  1981. } else {
  1982. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  1983. IPA_CLIENT_WLAN1_PROD;
  1984. }
  1985. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  1986. &ipa_res->rx_rdy_ring.sgtable,
  1987. sizeof(sgtable_t));
  1988. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  1989. qdf_mem_get_dma_size(soc->osdev,
  1990. &ipa_res->rx_rdy_ring.mem_info);
  1991. /* REO Tail Pointer Address */
  1992. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  1993. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  1994. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  1995. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  1996. &ipa_res->rx_refill_ring.sgtable,
  1997. sizeof(sgtable_t));
  1998. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  1999. qdf_mem_get_dma_size(soc->osdev,
  2000. &ipa_res->rx_refill_ring.mem_info);
  2001. /* FW Head Pointer Address */
  2002. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2003. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2004. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2005. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2006. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2007. }
  2008. #ifdef IPA_WDI3_VLAN_SUPPORT
  2009. /*
  2010. * dp_ipa_wdi_rx_alt_pipe_smmu_params() - Setup 2nd rx pipe smmu params
  2011. * @soc: data path soc handle
  2012. * @ipa_res: ipa resource pointer
  2013. * @rx_smmu: smmu pipe info handle
  2014. * @over_gsi: flag for IPA offload over gsi
  2015. * @hdl: ipa registered handle
  2016. *
  2017. * Return: none
  2018. */
  2019. static void
  2020. dp_ipa_wdi_rx_alt_pipe_smmu_params(struct dp_soc *soc,
  2021. struct dp_ipa_resources *ipa_res,
  2022. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2023. bool over_gsi,
  2024. qdf_ipa_wdi_hdl_t hdl)
  2025. {
  2026. if (!wlan_ipa_is_vlan_enabled())
  2027. return;
  2028. if (over_gsi) {
  2029. if (hdl == DP_IPA_HDL_FIRST)
  2030. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2031. IPA_CLIENT_WLAN2_PROD1;
  2032. else if (hdl == DP_IPA_HDL_SECOND)
  2033. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2034. IPA_CLIENT_WLAN3_PROD1;
  2035. } else {
  2036. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2037. IPA_CLIENT_WLAN1_PROD;
  2038. }
  2039. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2040. &ipa_res->rx_alt_rdy_ring.sgtable,
  2041. sizeof(sgtable_t));
  2042. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2043. qdf_mem_get_dma_size(soc->osdev,
  2044. &ipa_res->rx_alt_rdy_ring.mem_info);
  2045. /* REO Tail Pointer Address */
  2046. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2047. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2048. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  2049. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2050. &ipa_res->rx_alt_refill_ring.sgtable,
  2051. sizeof(sgtable_t));
  2052. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2053. qdf_mem_get_dma_size(soc->osdev,
  2054. &ipa_res->rx_alt_refill_ring.mem_info);
  2055. /* FW Head Pointer Address */
  2056. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2057. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2058. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2059. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2060. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2061. }
  2062. /*
  2063. * dp_ipa_wdi_rx_alt_pipe_smmu_params() - Setup 2nd rx pipe params
  2064. * @soc: data path soc handle
  2065. * @ipa_res: ipa resource pointer
  2066. * @rx: pipe info handle
  2067. * @over_gsi: flag for IPA offload over gsi
  2068. * @hdl: ipa registered handle
  2069. *
  2070. * Return: none
  2071. */
  2072. static void dp_ipa_wdi_rx_alt_pipe_params(struct dp_soc *soc,
  2073. struct dp_ipa_resources *ipa_res,
  2074. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2075. bool over_gsi,
  2076. qdf_ipa_wdi_hdl_t hdl)
  2077. {
  2078. if (!wlan_ipa_is_vlan_enabled())
  2079. return;
  2080. if (over_gsi) {
  2081. if (hdl == DP_IPA_HDL_FIRST)
  2082. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2083. IPA_CLIENT_WLAN2_PROD1;
  2084. else if (hdl == DP_IPA_HDL_SECOND)
  2085. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2086. IPA_CLIENT_WLAN3_PROD1;
  2087. } else {
  2088. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2089. IPA_CLIENT_WLAN1_PROD;
  2090. }
  2091. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2092. qdf_mem_get_dma_addr(soc->osdev,
  2093. &ipa_res->rx_alt_rdy_ring.mem_info);
  2094. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2095. qdf_mem_get_dma_size(soc->osdev,
  2096. &ipa_res->rx_alt_rdy_ring.mem_info);
  2097. /* REO Tail Pointer Address */
  2098. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2099. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2100. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2101. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2102. qdf_mem_get_dma_addr(soc->osdev,
  2103. &ipa_res->rx_alt_refill_ring.mem_info);
  2104. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2105. qdf_mem_get_dma_size(soc->osdev,
  2106. &ipa_res->rx_alt_refill_ring.mem_info);
  2107. /* FW Head Pointer Address */
  2108. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2109. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2110. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2111. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2112. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2113. }
  2114. /*
  2115. * dp_ipa_setup_rx_alt_pipe() - Setup 2nd rx pipe for IPA offload
  2116. * @soc: data path soc handle
  2117. * @res: ipa resource pointer
  2118. * @in: pipe in handle
  2119. * @over_gsi: flag for IPA offload over gsi
  2120. * @hdl: ipa registered handle
  2121. *
  2122. * Return: none
  2123. */
  2124. static void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2125. struct dp_ipa_resources *res,
  2126. qdf_ipa_wdi_conn_in_params_t *in,
  2127. bool over_gsi,
  2128. qdf_ipa_wdi_hdl_t hdl)
  2129. {
  2130. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2131. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2132. qdf_ipa_ep_cfg_t *rx_cfg;
  2133. if (!wlan_ipa_is_vlan_enabled())
  2134. return;
  2135. QDF_IPA_WDI_CONN_IN_PARAMS_IS_RX1_USED(in) = true;
  2136. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  2137. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT_SMMU(in);
  2138. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2139. dp_ipa_wdi_rx_alt_pipe_smmu_params(soc, res, rx_smmu,
  2140. over_gsi, hdl);
  2141. } else {
  2142. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT(in);
  2143. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx);
  2144. dp_ipa_wdi_rx_alt_pipe_params(soc, res, rx, over_gsi, hdl);
  2145. }
  2146. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2147. /* Update with wds len(96) + 4 if wds support is enabled */
  2148. if (ucfg_ipa_is_wds_enabled())
  2149. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST_VLAN;
  2150. else
  2151. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2152. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2153. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2154. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2155. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2156. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2157. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2158. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2159. }
  2160. /*
  2161. * dp_ipa_set_rx_alt_pipe_db() - Setup 2nd rx pipe doorbell
  2162. * @res: ipa resource pointer
  2163. * @out: pipe out handle
  2164. *
  2165. * Return: none
  2166. */
  2167. static void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2168. qdf_ipa_wdi_conn_out_params_t *out)
  2169. {
  2170. if (!wlan_ipa_is_vlan_enabled())
  2171. return;
  2172. res->rx_alt_ready_doorbell_paddr =
  2173. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_ALT_UC_DB_PA(out);
  2174. dp_debug("Setting DB 0x%x for RX alt pipe",
  2175. res->rx_alt_ready_doorbell_paddr);
  2176. }
  2177. #else
  2178. static inline
  2179. void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2180. struct dp_ipa_resources *res,
  2181. qdf_ipa_wdi_conn_in_params_t *in,
  2182. bool over_gsi,
  2183. qdf_ipa_wdi_hdl_t hdl)
  2184. { }
  2185. static inline
  2186. void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2187. qdf_ipa_wdi_conn_out_params_t *out)
  2188. { }
  2189. #endif
  2190. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2191. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2192. void *ipa_wdi_meter_notifier_cb,
  2193. uint32_t ipa_desc_size, void *ipa_priv,
  2194. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2195. uint32_t *rx_pipe_handle, bool is_smmu_enabled,
  2196. qdf_ipa_sys_connect_params_t *sys_in, bool over_gsi,
  2197. qdf_ipa_wdi_hdl_t hdl, qdf_ipa_wdi_hdl_t id,
  2198. void *ipa_ast_notify_cb)
  2199. {
  2200. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2201. struct dp_pdev *pdev =
  2202. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2203. struct dp_ipa_resources *ipa_res;
  2204. qdf_ipa_ep_cfg_t *tx_cfg;
  2205. qdf_ipa_ep_cfg_t *rx_cfg;
  2206. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  2207. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2208. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu;
  2209. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2210. qdf_ipa_wdi_conn_in_params_t *pipe_in = NULL;
  2211. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2212. int ret;
  2213. if (!pdev) {
  2214. dp_err("Invalid instance");
  2215. return QDF_STATUS_E_FAILURE;
  2216. }
  2217. ipa_res = &pdev->ipa_resource;
  2218. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2219. return QDF_STATUS_SUCCESS;
  2220. pipe_in = qdf_mem_malloc(sizeof(*pipe_in));
  2221. if (!pipe_in)
  2222. return QDF_STATUS_E_NOMEM;
  2223. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2224. if (is_smmu_enabled)
  2225. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = true;
  2226. else
  2227. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = false;
  2228. dp_setup_mcc_sys_pipes(sys_in, pipe_in);
  2229. /* TX PIPE */
  2230. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2231. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_SMMU(pipe_in);
  2232. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  2233. } else {
  2234. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(pipe_in);
  2235. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(tx);
  2236. }
  2237. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  2238. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2239. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  2240. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  2241. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  2242. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  2243. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  2244. /**
  2245. * Transfer Ring: WBM Ring
  2246. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2247. * Event Ring: TCL ring
  2248. * Event Ring Doorbell PA: TCL Head Pointer Address
  2249. */
  2250. if (is_smmu_enabled)
  2251. dp_ipa_wdi_tx_smmu_params(soc, ipa_res, tx_smmu, over_gsi, id);
  2252. else
  2253. dp_ipa_wdi_tx_params(soc, ipa_res, tx, over_gsi);
  2254. dp_ipa_setup_tx_alt_pipe(soc, ipa_res, pipe_in);
  2255. /* RX PIPE */
  2256. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2257. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_SMMU(pipe_in);
  2258. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2259. } else {
  2260. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(pipe_in);
  2261. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(rx);
  2262. }
  2263. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2264. if (ucfg_ipa_is_wds_enabled())
  2265. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST;
  2266. else
  2267. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2268. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2269. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2270. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2271. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2272. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2273. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2274. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2275. /**
  2276. * Transfer Ring: REO Ring
  2277. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2278. * Event Ring: FW ring
  2279. * Event Ring Doorbell PA: FW Head Pointer Address
  2280. */
  2281. if (is_smmu_enabled)
  2282. dp_ipa_wdi_rx_smmu_params(soc, ipa_res, rx_smmu, over_gsi, id);
  2283. else
  2284. dp_ipa_wdi_rx_params(soc, ipa_res, rx, over_gsi);
  2285. /* setup 2nd rx pipe */
  2286. dp_ipa_setup_rx_alt_pipe(soc, ipa_res, pipe_in, over_gsi, id);
  2287. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(pipe_in) = ipa_w2i_cb;
  2288. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(pipe_in) = ipa_priv;
  2289. QDF_IPA_WDI_CONN_IN_PARAMS_HANDLE(pipe_in) = hdl;
  2290. dp_ipa_ast_notify_cb(pipe_in, ipa_ast_notify_cb);
  2291. /* Connect WDI IPA PIPEs */
  2292. ret = qdf_ipa_wdi_conn_pipes(pipe_in, &pipe_out);
  2293. if (ret) {
  2294. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2295. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2296. __func__, ret);
  2297. qdf_mem_free(pipe_in);
  2298. return QDF_STATUS_E_FAILURE;
  2299. }
  2300. /* IPA uC Doorbell registers */
  2301. dp_info("Tx DB PA=0x%x, Rx DB PA=0x%x",
  2302. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2303. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2304. dp_ipa_set_pipe_db(ipa_res, &pipe_out);
  2305. dp_ipa_set_rx_alt_pipe_db(ipa_res, &pipe_out);
  2306. ipa_res->is_db_ddr_mapped =
  2307. QDF_IPA_WDI_CONN_OUT_PARAMS_IS_DB_DDR_MAPPED(&pipe_out);
  2308. soc->ipa_first_tx_db_access = true;
  2309. qdf_mem_free(pipe_in);
  2310. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2311. soc->ipa_rx_buf_map_lock_initialized = true;
  2312. return QDF_STATUS_SUCCESS;
  2313. }
  2314. #ifdef IPA_WDI3_VLAN_SUPPORT
  2315. /*
  2316. * dp_ipa_set_rx1_used() - Set rx1 used flag for 2nd rx offload ring
  2317. * @in: pipe in handle
  2318. *
  2319. * Return: none
  2320. */
  2321. static inline
  2322. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2323. {
  2324. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_RX1_USED(in) = true;
  2325. }
  2326. /*
  2327. * dp_ipa_set_v4_vlan_hdr() - Set v4 vlan hdr
  2328. * @in: pipe in handle
  2329. * hdr: pointer to hdr
  2330. *
  2331. * Return: none
  2332. */
  2333. static inline
  2334. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2335. qdf_ipa_wdi_hdr_info_t *hdr)
  2336. {
  2337. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v4_VLAN]),
  2338. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2339. }
  2340. /*
  2341. * dp_ipa_set_v6_vlan_hdr() - Set v6 vlan hdr
  2342. * @in: pipe in handle
  2343. * hdr: pointer to hdr
  2344. *
  2345. * Return: none
  2346. */
  2347. static inline
  2348. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2349. qdf_ipa_wdi_hdr_info_t *hdr)
  2350. {
  2351. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v6_VLAN]),
  2352. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2353. }
  2354. #else
  2355. static inline
  2356. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2357. { }
  2358. static inline
  2359. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2360. qdf_ipa_wdi_hdr_info_t *hdr)
  2361. { }
  2362. static inline
  2363. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2364. qdf_ipa_wdi_hdr_info_t *hdr)
  2365. { }
  2366. #endif
  2367. #ifdef IPA_WDS_EASYMESH_FEATURE
  2368. /**
  2369. * dp_ipa_set_wdi_hdr_type() - Set wdi hdr type for IPA
  2370. * @hdr_info: Header info
  2371. *
  2372. * Return: None
  2373. */
  2374. static inline void
  2375. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2376. {
  2377. if (ucfg_ipa_is_wds_enabled())
  2378. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2379. IPA_HDR_L2_ETHERNET_II_AST;
  2380. else
  2381. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2382. IPA_HDR_L2_ETHERNET_II;
  2383. }
  2384. #else
  2385. static inline void
  2386. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2387. {
  2388. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2389. }
  2390. #endif
  2391. #ifdef IPA_WDI3_VLAN_SUPPORT
  2392. /**
  2393. * dp_ipa_set_wdi_vlan_hdr_type() - Set wdi vlan hdr type for IPA
  2394. * @hdr_info: Header info
  2395. *
  2396. * Return: None
  2397. */
  2398. static inline void
  2399. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2400. {
  2401. if (ucfg_ipa_is_wds_enabled())
  2402. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2403. IPA_HDR_L2_802_1Q_AST;
  2404. else
  2405. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2406. IPA_HDR_L2_802_1Q;
  2407. }
  2408. #else
  2409. static inline void
  2410. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2411. { }
  2412. #endif
  2413. /**
  2414. * dp_ipa_setup_iface() - Setup IPA header and register interface
  2415. * @ifname: Interface name
  2416. * @mac_addr: Interface MAC address
  2417. * @prod_client: IPA prod client type
  2418. * @cons_client: IPA cons client type
  2419. * @session_id: Session ID
  2420. * @is_ipv6_enabled: Is IPV6 enabled or not
  2421. * @hdl: IPA handle
  2422. *
  2423. * Return: QDF_STATUS
  2424. */
  2425. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2426. qdf_ipa_client_type_t prod_client,
  2427. qdf_ipa_client_type_t cons_client,
  2428. uint8_t session_id, bool is_ipv6_enabled,
  2429. qdf_ipa_wdi_hdl_t hdl)
  2430. {
  2431. qdf_ipa_wdi_reg_intf_in_params_t in;
  2432. qdf_ipa_wdi_hdr_info_t hdr_info;
  2433. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2434. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2435. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr;
  2436. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr_v6;
  2437. int ret = -EINVAL;
  2438. qdf_mem_zero(&in, sizeof(qdf_ipa_wdi_reg_intf_in_params_t));
  2439. dp_debug("Add Partial hdr: %s, "QDF_MAC_ADDR_FMT, ifname,
  2440. QDF_MAC_ADDR_REF(mac_addr));
  2441. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2442. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2443. /* IPV4 header */
  2444. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2445. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2446. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2447. dp_ipa_set_wdi_hdr_type(&hdr_info);
  2448. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2449. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2450. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2451. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2452. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2453. QDF_IPA_WDI_REG_INTF_IN_PARAMS_ALT_DST_PIPE(&in) = cons_client;
  2454. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2455. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = WLAN_IPA_META_DATA_MASK;
  2456. QDF_IPA_WDI_REG_INTF_IN_PARAMS_HANDLE(&in) = hdl;
  2457. dp_ipa_setup_iface_session_id(&in, session_id);
  2458. dp_debug("registering for session_id: %u", session_id);
  2459. /* IPV6 header */
  2460. if (is_ipv6_enabled) {
  2461. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2462. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2463. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2464. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2465. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2466. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2467. }
  2468. if (wlan_ipa_is_vlan_enabled()) {
  2469. /* Add vlan specific headers if vlan supporti is enabled */
  2470. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2471. dp_ipa_set_rx1_used(&in);
  2472. qdf_ether_addr_copy(uc_tx_vlan_hdr.eth.h_source, mac_addr);
  2473. /* IPV4 Vlan header */
  2474. uc_tx_vlan_hdr.eth.h_vlan_proto = qdf_htons(ETH_P_8021Q);
  2475. uc_tx_vlan_hdr.eth.h_vlan_encapsulated_proto = qdf_htons(ETH_P_IP);
  2476. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2477. (uint8_t *)&uc_tx_vlan_hdr;
  2478. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) =
  2479. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2480. dp_ipa_set_wdi_vlan_hdr_type(&hdr_info);
  2481. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2482. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2483. dp_ipa_set_v4_vlan_hdr(&in, &hdr_info);
  2484. /* IPV6 Vlan header */
  2485. if (is_ipv6_enabled) {
  2486. qdf_mem_copy(&uc_tx_vlan_hdr_v6, &uc_tx_vlan_hdr,
  2487. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN);
  2488. uc_tx_vlan_hdr_v6.eth.h_vlan_proto =
  2489. qdf_htons(ETH_P_8021Q);
  2490. uc_tx_vlan_hdr_v6.eth.h_vlan_encapsulated_proto =
  2491. qdf_htons(ETH_P_IPV6);
  2492. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2493. (uint8_t *)&uc_tx_vlan_hdr_v6;
  2494. dp_ipa_set_v6_vlan_hdr(&in, &hdr_info);
  2495. }
  2496. }
  2497. ret = qdf_ipa_wdi_reg_intf(&in);
  2498. if (ret) {
  2499. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2500. "%s: ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2501. __func__, ret);
  2502. return QDF_STATUS_E_FAILURE;
  2503. }
  2504. return QDF_STATUS_SUCCESS;
  2505. }
  2506. #else /* !CONFIG_IPA_WDI_UNIFIED_API */
  2507. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2508. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2509. void *ipa_wdi_meter_notifier_cb,
  2510. uint32_t ipa_desc_size, void *ipa_priv,
  2511. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2512. uint32_t *rx_pipe_handle)
  2513. {
  2514. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2515. struct dp_pdev *pdev =
  2516. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2517. struct dp_ipa_resources *ipa_res;
  2518. qdf_ipa_wdi_pipe_setup_info_t *tx;
  2519. qdf_ipa_wdi_pipe_setup_info_t *rx;
  2520. qdf_ipa_wdi_conn_in_params_t pipe_in;
  2521. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2522. struct tcl_data_cmd *tcl_desc_ptr;
  2523. uint8_t *desc_addr;
  2524. uint32_t desc_size;
  2525. int ret;
  2526. if (!pdev) {
  2527. dp_err("Invalid instance");
  2528. return QDF_STATUS_E_FAILURE;
  2529. }
  2530. ipa_res = &pdev->ipa_resource;
  2531. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2532. return QDF_STATUS_SUCCESS;
  2533. qdf_mem_zero(&tx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2534. qdf_mem_zero(&rx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2535. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  2536. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2537. /* TX PIPE */
  2538. /**
  2539. * Transfer Ring: WBM Ring
  2540. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2541. * Event Ring: TCL ring
  2542. * Event Ring Doorbell PA: TCL Head Pointer Address
  2543. */
  2544. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  2545. QDF_IPA_WDI_SETUP_INFO_NAT_EN(tx) = IPA_BYPASS_NAT;
  2546. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(tx) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2547. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(tx) = 0;
  2548. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(tx) = 0;
  2549. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(tx) = 0;
  2550. QDF_IPA_WDI_SETUP_INFO_MODE(tx) = IPA_BASIC;
  2551. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(tx) = true;
  2552. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2553. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2554. ipa_res->tx_comp_ring_base_paddr;
  2555. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2556. ipa_res->tx_comp_ring_size;
  2557. /* WBM Tail Pointer Address */
  2558. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2559. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2560. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2561. ipa_res->tx_ring_base_paddr;
  2562. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) = ipa_res->tx_ring_size;
  2563. /* TCL Head Pointer Address */
  2564. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2565. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2566. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2567. ipa_res->tx_num_alloc_buffer;
  2568. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2569. /* Preprogram TCL descriptor */
  2570. desc_addr =
  2571. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  2572. desc_size = sizeof(struct tcl_data_cmd);
  2573. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  2574. tcl_desc_ptr = (struct tcl_data_cmd *)
  2575. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  2576. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  2577. HAL_RX_BUF_RBM_SW2_BM;
  2578. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  2579. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  2580. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  2581. /* RX PIPE */
  2582. /**
  2583. * Transfer Ring: REO Ring
  2584. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2585. * Event Ring: FW ring
  2586. * Event Ring Doorbell PA: FW Head Pointer Address
  2587. */
  2588. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  2589. QDF_IPA_WDI_SETUP_INFO_NAT_EN(rx) = IPA_BYPASS_NAT;
  2590. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(rx) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2591. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(rx) = 0;
  2592. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(rx) = 0;
  2593. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(rx) = 0;
  2594. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_METADATA_VALID(rx) = 0;
  2595. QDF_IPA_WDI_SETUP_INFO_HDR_METADATA_REG_VALID(rx) = 1;
  2596. QDF_IPA_WDI_SETUP_INFO_MODE(rx) = IPA_BASIC;
  2597. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(rx) = true;
  2598. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) = IPA_CLIENT_WLAN1_PROD;
  2599. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2600. ipa_res->rx_rdy_ring_base_paddr;
  2601. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2602. ipa_res->rx_rdy_ring_size;
  2603. /* REO Tail Pointer Address */
  2604. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2605. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2606. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2607. ipa_res->rx_refill_ring_base_paddr;
  2608. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2609. ipa_res->rx_refill_ring_size;
  2610. /* FW Head Pointer Address */
  2611. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2612. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2613. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) = soc->rx_pkt_tlv_size +
  2614. L3_HEADER_PADDING;
  2615. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  2616. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  2617. /* Connect WDI IPA PIPE */
  2618. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  2619. if (ret) {
  2620. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2621. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2622. __func__, ret);
  2623. return QDF_STATUS_E_FAILURE;
  2624. }
  2625. /* IPA uC Doorbell registers */
  2626. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2627. "%s: Tx DB PA=0x%x, Rx DB PA=0x%x",
  2628. __func__,
  2629. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2630. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2631. ipa_res->tx_comp_doorbell_paddr =
  2632. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  2633. ipa_res->tx_comp_doorbell_vaddr =
  2634. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_VA(&pipe_out);
  2635. ipa_res->rx_ready_doorbell_paddr =
  2636. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  2637. soc->ipa_first_tx_db_access = true;
  2638. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2639. soc->ipa_rx_buf_map_lock_initialized = true;
  2640. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2641. "%s: Tx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2642. __func__,
  2643. "transfer_ring_base_pa",
  2644. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx),
  2645. "transfer_ring_size",
  2646. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx),
  2647. "transfer_ring_doorbell_pa",
  2648. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx),
  2649. "event_ring_base_pa",
  2650. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx),
  2651. "event_ring_size",
  2652. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx),
  2653. "event_ring_doorbell_pa",
  2654. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx),
  2655. "num_pkt_buffers",
  2656. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx),
  2657. "tx_comp_doorbell_paddr",
  2658. (void *)ipa_res->tx_comp_doorbell_paddr);
  2659. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2660. "%s: Rx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2661. __func__,
  2662. "transfer_ring_base_pa",
  2663. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx),
  2664. "transfer_ring_size",
  2665. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx),
  2666. "transfer_ring_doorbell_pa",
  2667. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx),
  2668. "event_ring_base_pa",
  2669. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx),
  2670. "event_ring_size",
  2671. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx),
  2672. "event_ring_doorbell_pa",
  2673. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx),
  2674. "num_pkt_buffers",
  2675. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(rx),
  2676. "tx_comp_doorbell_paddr",
  2677. (void *)ipa_res->rx_ready_doorbell_paddr);
  2678. return QDF_STATUS_SUCCESS;
  2679. }
  2680. /**
  2681. * dp_ipa_setup_iface() - Setup IPA header and register interface
  2682. * @ifname: Interface name
  2683. * @mac_addr: Interface MAC address
  2684. * @prod_client: IPA prod client type
  2685. * @cons_client: IPA cons client type
  2686. * @session_id: Session ID
  2687. * @is_ipv6_enabled: Is IPV6 enabled or not
  2688. * @hdl: IPA handle
  2689. *
  2690. * Return: QDF_STATUS
  2691. */
  2692. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2693. qdf_ipa_client_type_t prod_client,
  2694. qdf_ipa_client_type_t cons_client,
  2695. uint8_t session_id, bool is_ipv6_enabled,
  2696. qdf_ipa_wdi_hdl_t hdl)
  2697. {
  2698. qdf_ipa_wdi_reg_intf_in_params_t in;
  2699. qdf_ipa_wdi_hdr_info_t hdr_info;
  2700. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2701. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2702. int ret = -EINVAL;
  2703. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2704. "%s: Add Partial hdr: %s, "QDF_MAC_ADDR_FMT,
  2705. __func__, ifname, QDF_MAC_ADDR_REF(mac_addr));
  2706. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2707. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2708. /* IPV4 header */
  2709. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2710. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2711. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2712. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2713. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2714. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2715. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2716. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2717. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2718. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2719. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  2720. htonl(session_id << 16);
  2721. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  2722. /* IPV6 header */
  2723. if (is_ipv6_enabled) {
  2724. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2725. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2726. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2727. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2728. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2729. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2730. }
  2731. ret = qdf_ipa_wdi_reg_intf(&in);
  2732. if (ret) {
  2733. dp_err("ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2734. ret);
  2735. return QDF_STATUS_E_FAILURE;
  2736. }
  2737. return QDF_STATUS_SUCCESS;
  2738. }
  2739. #endif /* CONFIG_IPA_WDI_UNIFIED_API */
  2740. /**
  2741. * dp_ipa_cleanup() - Disconnect IPA pipes
  2742. * @soc_hdl: dp soc handle
  2743. * @pdev_id: dp pdev id
  2744. * @tx_pipe_handle: Tx pipe handle
  2745. * @rx_pipe_handle: Rx pipe handle
  2746. * @hdl: IPA handle
  2747. *
  2748. * Return: QDF_STATUS
  2749. */
  2750. QDF_STATUS dp_ipa_cleanup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2751. uint32_t tx_pipe_handle, uint32_t rx_pipe_handle,
  2752. qdf_ipa_wdi_hdl_t hdl)
  2753. {
  2754. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2755. QDF_STATUS status = QDF_STATUS_SUCCESS;
  2756. struct dp_pdev *pdev;
  2757. int ret;
  2758. ret = qdf_ipa_wdi_disconn_pipes(hdl);
  2759. if (ret) {
  2760. dp_err("ipa_wdi_disconn_pipes: IPA pipe cleanup failed: ret=%d",
  2761. ret);
  2762. status = QDF_STATUS_E_FAILURE;
  2763. }
  2764. if (soc->ipa_rx_buf_map_lock_initialized) {
  2765. qdf_spinlock_destroy(&soc->ipa_rx_buf_map_lock);
  2766. soc->ipa_rx_buf_map_lock_initialized = false;
  2767. }
  2768. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2769. if (qdf_unlikely(!pdev)) {
  2770. dp_err_rl("Invalid pdev for pdev_id %d", pdev_id);
  2771. status = QDF_STATUS_E_FAILURE;
  2772. goto exit;
  2773. }
  2774. dp_ipa_unmap_ring_doorbell_paddr(pdev);
  2775. dp_ipa_unmap_rx_alt_ring_doorbell_paddr(pdev);
  2776. exit:
  2777. return status;
  2778. }
  2779. /**
  2780. * dp_ipa_cleanup_iface() - Cleanup IPA header and deregister interface
  2781. * @ifname: Interface name
  2782. * @is_ipv6_enabled: Is IPV6 enabled or not
  2783. * @hdl: IPA handle
  2784. *
  2785. * Return: QDF_STATUS
  2786. */
  2787. QDF_STATUS dp_ipa_cleanup_iface(char *ifname, bool is_ipv6_enabled,
  2788. qdf_ipa_wdi_hdl_t hdl)
  2789. {
  2790. int ret;
  2791. ret = qdf_ipa_wdi_dereg_intf(ifname, hdl);
  2792. if (ret) {
  2793. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2794. "%s: ipa_wdi_dereg_intf: IPA pipe deregistration failed: ret=%d",
  2795. __func__, ret);
  2796. return QDF_STATUS_E_FAILURE;
  2797. }
  2798. return QDF_STATUS_SUCCESS;
  2799. }
  2800. #ifdef IPA_SET_RESET_TX_DB_PA
  2801. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res) \
  2802. dp_ipa_set_tx_doorbell_paddr((soc), (ipa_res))
  2803. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res) \
  2804. dp_ipa_reset_tx_doorbell_pa((soc), (ipa_res))
  2805. #else
  2806. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res)
  2807. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res)
  2808. #endif
  2809. QDF_STATUS dp_ipa_enable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2810. qdf_ipa_wdi_hdl_t hdl)
  2811. {
  2812. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2813. struct dp_pdev *pdev =
  2814. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2815. struct dp_ipa_resources *ipa_res;
  2816. QDF_STATUS result;
  2817. if (!pdev) {
  2818. dp_err("Invalid instance");
  2819. return QDF_STATUS_E_FAILURE;
  2820. }
  2821. ipa_res = &pdev->ipa_resource;
  2822. qdf_atomic_set(&soc->ipa_pipes_enabled, 1);
  2823. DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res);
  2824. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, true,
  2825. __func__, __LINE__);
  2826. result = qdf_ipa_wdi_enable_pipes(hdl);
  2827. if (result) {
  2828. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2829. "%s: Enable WDI PIPE fail, code %d",
  2830. __func__, result);
  2831. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  2832. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  2833. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false,
  2834. __func__, __LINE__);
  2835. return QDF_STATUS_E_FAILURE;
  2836. }
  2837. if (soc->ipa_first_tx_db_access) {
  2838. dp_ipa_tx_comp_ring_init_hp(soc, ipa_res);
  2839. soc->ipa_first_tx_db_access = false;
  2840. }
  2841. return QDF_STATUS_SUCCESS;
  2842. }
  2843. QDF_STATUS dp_ipa_disable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2844. qdf_ipa_wdi_hdl_t hdl)
  2845. {
  2846. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2847. struct dp_pdev *pdev =
  2848. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2849. QDF_STATUS result;
  2850. struct dp_ipa_resources *ipa_res;
  2851. if (!pdev) {
  2852. dp_err("Invalid instance");
  2853. return QDF_STATUS_E_FAILURE;
  2854. }
  2855. ipa_res = &pdev->ipa_resource;
  2856. qdf_sleep(TX_COMP_DRAIN_WAIT_TIMEOUT_MS);
  2857. /*
  2858. * Reset the tx completion doorbell address before invoking IPA disable
  2859. * pipes API to ensure that there is no access to IPA tx doorbell
  2860. * address post disable pipes.
  2861. */
  2862. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  2863. result = qdf_ipa_wdi_disable_pipes(hdl);
  2864. if (result) {
  2865. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2866. "%s: Disable WDI PIPE fail, code %d",
  2867. __func__, result);
  2868. qdf_assert_always(0);
  2869. return QDF_STATUS_E_FAILURE;
  2870. }
  2871. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  2872. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false,
  2873. __func__, __LINE__);
  2874. return result ? QDF_STATUS_E_FAILURE : QDF_STATUS_SUCCESS;
  2875. }
  2876. /**
  2877. * dp_ipa_set_perf_level() - Set IPA clock bandwidth based on data rates
  2878. * @client: Client type
  2879. * @max_supported_bw_mbps: Maximum bandwidth needed (in Mbps)
  2880. * @hdl: IPA handle
  2881. *
  2882. * Return: QDF_STATUS
  2883. */
  2884. QDF_STATUS dp_ipa_set_perf_level(int client, uint32_t max_supported_bw_mbps,
  2885. qdf_ipa_wdi_hdl_t hdl)
  2886. {
  2887. qdf_ipa_wdi_perf_profile_t profile;
  2888. QDF_STATUS result;
  2889. profile.client = client;
  2890. profile.max_supported_bw_mbps = max_supported_bw_mbps;
  2891. result = qdf_ipa_wdi_set_perf_profile(hdl, &profile);
  2892. if (result) {
  2893. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2894. "%s: ipa_wdi_set_perf_profile fail, code %d",
  2895. __func__, result);
  2896. return QDF_STATUS_E_FAILURE;
  2897. }
  2898. return QDF_STATUS_SUCCESS;
  2899. }
  2900. /**
  2901. * dp_ipa_intrabss_send - send IPA RX intra-bss frames
  2902. * @pdev: pdev
  2903. * @vdev: vdev
  2904. * @nbuf: skb
  2905. *
  2906. * Return: nbuf if TX fails and NULL if TX succeeds
  2907. */
  2908. static qdf_nbuf_t dp_ipa_intrabss_send(struct dp_pdev *pdev,
  2909. struct dp_vdev *vdev,
  2910. qdf_nbuf_t nbuf)
  2911. {
  2912. struct dp_peer *vdev_peer;
  2913. uint16_t len;
  2914. vdev_peer = dp_vdev_bss_peer_ref_n_get(pdev->soc, vdev, DP_MOD_ID_IPA);
  2915. if (qdf_unlikely(!vdev_peer))
  2916. return nbuf;
  2917. if (qdf_unlikely(!vdev_peer->txrx_peer)) {
  2918. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  2919. return nbuf;
  2920. }
  2921. qdf_mem_zero(nbuf->cb, sizeof(nbuf->cb));
  2922. len = qdf_nbuf_len(nbuf);
  2923. if (dp_tx_send((struct cdp_soc_t *)pdev->soc, vdev->vdev_id, nbuf)) {
  2924. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  2925. rx.intra_bss.fail, 1, len);
  2926. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  2927. return nbuf;
  2928. }
  2929. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  2930. rx.intra_bss.pkts, 1, len);
  2931. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  2932. return NULL;
  2933. }
  2934. #ifdef IPA_WDS_EASYMESH_FEATURE
  2935. /**
  2936. * dp_ipa_peer_check() - Check for peer for given mac
  2937. * @soc: dp soc object
  2938. * @peer_mac_addr: peer mac address
  2939. * @vdev_id: vdev id
  2940. *
  2941. * Return: true if peer is found, else false
  2942. */
  2943. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  2944. uint8_t *peer_mac_addr, uint8_t vdev_id)
  2945. {
  2946. struct dp_ast_entry *ast_entry = NULL;
  2947. struct dp_peer *peer = NULL;
  2948. qdf_spin_lock_bh(&soc->ast_lock);
  2949. ast_entry = dp_peer_ast_hash_find_soc(soc, peer_mac_addr);
  2950. if ((!ast_entry) ||
  2951. (ast_entry->delete_in_progress && !ast_entry->callback)) {
  2952. qdf_spin_unlock_bh(&soc->ast_lock);
  2953. return false;
  2954. }
  2955. peer = dp_peer_get_ref_by_id(soc, ast_entry->peer_id,
  2956. DP_MOD_ID_AST);
  2957. if (!peer) {
  2958. qdf_spin_unlock_bh(&soc->ast_lock);
  2959. return false;
  2960. } else {
  2961. if (peer->vdev->vdev_id == vdev_id) {
  2962. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  2963. qdf_spin_unlock_bh(&soc->ast_lock);
  2964. return true;
  2965. }
  2966. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  2967. qdf_spin_unlock_bh(&soc->ast_lock);
  2968. return false;
  2969. }
  2970. }
  2971. #else
  2972. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  2973. uint8_t *peer_mac_addr, uint8_t vdev_id)
  2974. {
  2975. struct dp_peer *peer = NULL;
  2976. peer = dp_peer_find_hash_find(soc, peer_mac_addr, 0, vdev_id,
  2977. DP_MOD_ID_IPA);
  2978. if (!peer) {
  2979. return false;
  2980. } else {
  2981. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  2982. return true;
  2983. }
  2984. }
  2985. #endif
  2986. bool dp_ipa_rx_intrabss_fwd(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2987. qdf_nbuf_t nbuf, bool *fwd_success)
  2988. {
  2989. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2990. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2991. DP_MOD_ID_IPA);
  2992. struct dp_pdev *pdev;
  2993. qdf_nbuf_t nbuf_copy;
  2994. uint8_t da_is_bcmc;
  2995. struct ethhdr *eh;
  2996. bool status = false;
  2997. *fwd_success = false; /* set default as failure */
  2998. /*
  2999. * WDI 3.0 skb->cb[] info from IPA driver
  3000. * skb->cb[0] = vdev_id
  3001. * skb->cb[1].bit#1 = da_is_bcmc
  3002. */
  3003. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3004. if (qdf_unlikely(!vdev))
  3005. return false;
  3006. pdev = vdev->pdev;
  3007. if (qdf_unlikely(!pdev))
  3008. goto out;
  3009. /* no fwd for station mode and just pass up to stack */
  3010. if (vdev->opmode == wlan_op_mode_sta)
  3011. goto out;
  3012. if (da_is_bcmc) {
  3013. nbuf_copy = qdf_nbuf_copy(nbuf);
  3014. if (!nbuf_copy)
  3015. goto out;
  3016. if (dp_ipa_intrabss_send(pdev, vdev, nbuf_copy))
  3017. qdf_nbuf_free(nbuf_copy);
  3018. else
  3019. *fwd_success = true;
  3020. /* return false to pass original pkt up to stack */
  3021. goto out;
  3022. }
  3023. eh = (struct ethhdr *)qdf_nbuf_data(nbuf);
  3024. if (!qdf_mem_cmp(eh->h_dest, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  3025. goto out;
  3026. if (!dp_ipa_peer_check(soc, eh->h_dest, vdev->vdev_id))
  3027. goto out;
  3028. if (!dp_ipa_peer_check(soc, eh->h_source, vdev->vdev_id))
  3029. goto out;
  3030. /*
  3031. * In intra-bss forwarding scenario, skb is allocated by IPA driver.
  3032. * Need to add skb to internal tracking table to avoid nbuf memory
  3033. * leak check for unallocated skb.
  3034. */
  3035. qdf_net_buf_debug_acquire_skb(nbuf, __FILE__, __LINE__);
  3036. if (dp_ipa_intrabss_send(pdev, vdev, nbuf))
  3037. qdf_nbuf_free(nbuf);
  3038. else
  3039. *fwd_success = true;
  3040. status = true;
  3041. out:
  3042. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3043. return status;
  3044. }
  3045. #ifdef MDM_PLATFORM
  3046. bool dp_ipa_is_mdm_platform(void)
  3047. {
  3048. return true;
  3049. }
  3050. #else
  3051. bool dp_ipa_is_mdm_platform(void)
  3052. {
  3053. return false;
  3054. }
  3055. #endif
  3056. /**
  3057. * dp_ipa_frag_nbuf_linearize - linearize nbuf for IPA
  3058. * @soc: soc
  3059. * @nbuf: source skb
  3060. *
  3061. * Return: new nbuf if success and otherwise NULL
  3062. */
  3063. static qdf_nbuf_t dp_ipa_frag_nbuf_linearize(struct dp_soc *soc,
  3064. qdf_nbuf_t nbuf)
  3065. {
  3066. uint8_t *src_nbuf_data;
  3067. uint8_t *dst_nbuf_data;
  3068. qdf_nbuf_t dst_nbuf;
  3069. qdf_nbuf_t temp_nbuf = nbuf;
  3070. uint32_t nbuf_len = qdf_nbuf_len(nbuf);
  3071. bool is_nbuf_head = true;
  3072. uint32_t copy_len = 0;
  3073. dst_nbuf = qdf_nbuf_alloc(soc->osdev, RX_DATA_BUFFER_SIZE,
  3074. RX_BUFFER_RESERVATION,
  3075. RX_DATA_BUFFER_ALIGNMENT, FALSE);
  3076. if (!dst_nbuf) {
  3077. dp_err_rl("nbuf allocate fail");
  3078. return NULL;
  3079. }
  3080. if ((nbuf_len + L3_HEADER_PADDING) > RX_DATA_BUFFER_SIZE) {
  3081. qdf_nbuf_free(dst_nbuf);
  3082. dp_err_rl("nbuf is jumbo data");
  3083. return NULL;
  3084. }
  3085. /* prepeare to copy all data into new skb */
  3086. dst_nbuf_data = qdf_nbuf_data(dst_nbuf);
  3087. while (temp_nbuf) {
  3088. src_nbuf_data = qdf_nbuf_data(temp_nbuf);
  3089. /* first head nbuf */
  3090. if (is_nbuf_head) {
  3091. qdf_mem_copy(dst_nbuf_data, src_nbuf_data,
  3092. soc->rx_pkt_tlv_size);
  3093. /* leave extra 2 bytes L3_HEADER_PADDING */
  3094. dst_nbuf_data += (soc->rx_pkt_tlv_size +
  3095. L3_HEADER_PADDING);
  3096. src_nbuf_data += soc->rx_pkt_tlv_size;
  3097. copy_len = qdf_nbuf_headlen(temp_nbuf) -
  3098. soc->rx_pkt_tlv_size;
  3099. temp_nbuf = qdf_nbuf_get_ext_list(temp_nbuf);
  3100. is_nbuf_head = false;
  3101. } else {
  3102. copy_len = qdf_nbuf_len(temp_nbuf);
  3103. temp_nbuf = qdf_nbuf_queue_next(temp_nbuf);
  3104. }
  3105. qdf_mem_copy(dst_nbuf_data, src_nbuf_data, copy_len);
  3106. dst_nbuf_data += copy_len;
  3107. }
  3108. qdf_nbuf_set_len(dst_nbuf, nbuf_len);
  3109. /* copy is done, free original nbuf */
  3110. qdf_nbuf_free(nbuf);
  3111. return dst_nbuf;
  3112. }
  3113. /**
  3114. * dp_ipa_handle_rx_reo_reinject - Handle RX REO reinject skb buffer
  3115. * @soc: soc
  3116. * @nbuf: skb
  3117. *
  3118. * Return: nbuf if success and otherwise NULL
  3119. */
  3120. qdf_nbuf_t dp_ipa_handle_rx_reo_reinject(struct dp_soc *soc, qdf_nbuf_t nbuf)
  3121. {
  3122. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  3123. return nbuf;
  3124. /* WLAN IPA is run-time disabled */
  3125. if (!qdf_atomic_read(&soc->ipa_pipes_enabled))
  3126. return nbuf;
  3127. if (!qdf_nbuf_is_frag(nbuf))
  3128. return nbuf;
  3129. /* linearize skb for IPA */
  3130. return dp_ipa_frag_nbuf_linearize(soc, nbuf);
  3131. }
  3132. QDF_STATUS dp_ipa_tx_buf_smmu_mapping(
  3133. struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3134. const char *func, uint32_t line)
  3135. {
  3136. QDF_STATUS ret;
  3137. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3138. struct dp_pdev *pdev =
  3139. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3140. if (!pdev) {
  3141. dp_err("%s invalid instance", __func__);
  3142. return QDF_STATUS_E_FAILURE;
  3143. }
  3144. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3145. dp_debug("SMMU S1 disabled");
  3146. return QDF_STATUS_SUCCESS;
  3147. }
  3148. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, true, func, line);
  3149. if (ret)
  3150. return ret;
  3151. ret = dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, true, func, line);
  3152. if (ret)
  3153. __dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line);
  3154. return ret;
  3155. }
  3156. QDF_STATUS dp_ipa_tx_buf_smmu_unmapping(
  3157. struct cdp_soc_t *soc_hdl, uint8_t pdev_id, const char *func,
  3158. uint32_t line)
  3159. {
  3160. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3161. struct dp_pdev *pdev =
  3162. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3163. if (!pdev) {
  3164. dp_err("%s invalid instance", __func__);
  3165. return QDF_STATUS_E_FAILURE;
  3166. }
  3167. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3168. dp_debug("SMMU S1 disabled");
  3169. return QDF_STATUS_SUCCESS;
  3170. }
  3171. if (__dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line) ||
  3172. dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, false, func, line))
  3173. return QDF_STATUS_E_FAILURE;
  3174. return QDF_STATUS_SUCCESS;
  3175. }
  3176. #ifdef IPA_WDS_EASYMESH_FEATURE
  3177. QDF_STATUS dp_ipa_ast_create(struct cdp_soc_t *soc_hdl,
  3178. qdf_ipa_ast_info_type_t *data)
  3179. {
  3180. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3181. uint8_t *rx_tlv_hdr;
  3182. struct dp_peer *peer;
  3183. struct hal_rx_msdu_metadata msdu_metadata;
  3184. qdf_ipa_ast_info_type_t *ast_info;
  3185. if (!data) {
  3186. dp_err("Data is NULL !!!");
  3187. return QDF_STATUS_E_FAILURE;
  3188. }
  3189. ast_info = data;
  3190. rx_tlv_hdr = qdf_nbuf_data(ast_info->skb);
  3191. peer = dp_peer_get_ref_by_id(soc, ast_info->ta_peer_id,
  3192. DP_MOD_ID_IPA);
  3193. if (!peer) {
  3194. dp_err("Peer is NULL !!!!");
  3195. return QDF_STATUS_E_FAILURE;
  3196. }
  3197. hal_rx_msdu_metadata_get(soc->hal_soc, rx_tlv_hdr, &msdu_metadata);
  3198. dp_rx_ipa_wds_srcport_learn(soc, peer, ast_info->skb, msdu_metadata,
  3199. ast_info->mac_addr_ad4_valid,
  3200. ast_info->first_msdu_in_mpdu_flag);
  3201. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3202. return QDF_STATUS_SUCCESS;
  3203. }
  3204. #endif
  3205. #endif