dp_be.c 58 KB

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  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include <dp_htt.h>
  22. #include "dp_be.h"
  23. #include "dp_be_tx.h"
  24. #include "dp_be_rx.h"
  25. #ifdef WIFI_MONITOR_SUPPORT
  26. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  27. #include "dp_mon_2.0.h"
  28. #endif
  29. #include "dp_mon.h"
  30. #endif
  31. #include <hal_be_api.h>
  32. #ifdef WLAN_SUPPORT_PPEDS
  33. #include "be/dp_ppeds.h"
  34. #endif
  35. /* Generic AST entry aging timer value */
  36. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  37. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  38. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  39. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  40. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  41. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  42. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  43. #ifdef QCA_WIFI_KIWI_V2
  44. {3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
  45. {4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
  46. #else
  47. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  48. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  49. #endif
  50. };
  51. #else
  52. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  53. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  54. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  55. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  56. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  57. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  58. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  59. };
  60. #endif
  61. #ifdef WLAN_SUPPORT_PPEDS
  62. static struct cdp_ppe_txrx_ops dp_ops_ppe_be = {
  63. .ppeds_entry_attach = dp_ppeds_attach_vdev_be,
  64. .ppeds_entry_detach = dp_ppeds_detach_vdev_be,
  65. .ppeds_set_int_pri2tid = dp_ppeds_set_int_pri2tid_be,
  66. .ppeds_update_int_pri2tid = dp_ppeds_update_int_pri2tid_be,
  67. .ppeds_entry_dump = dp_ppeds_dump_ppe_vp_tbl_be,
  68. .ppeds_enable_pri2tid = dp_ppeds_vdev_enable_pri2tid_be,
  69. };
  70. static void dp_ppeds_rings_status(struct dp_soc *soc)
  71. {
  72. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  73. dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE);
  74. dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL);
  75. }
  76. #endif
  77. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  78. {
  79. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  80. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  81. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  82. /* this is used only when dmac mode is enabled */
  83. soc->num_rx_refill_buf_rings = 1;
  84. soc->wlan_cfg_ctx->notify_frame_support =
  85. DP_MARK_NOTIFY_FRAME_SUPPORT;
  86. }
  87. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  88. {
  89. switch (context_type) {
  90. case DP_CONTEXT_TYPE_SOC:
  91. return sizeof(struct dp_soc_be);
  92. case DP_CONTEXT_TYPE_PDEV:
  93. return sizeof(struct dp_pdev_be);
  94. case DP_CONTEXT_TYPE_VDEV:
  95. return sizeof(struct dp_vdev_be);
  96. case DP_CONTEXT_TYPE_PEER:
  97. return sizeof(struct dp_peer_be);
  98. default:
  99. return 0;
  100. }
  101. }
  102. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  103. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  104. /**
  105. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  106. per wbm2sw ring
  107. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  108. *
  109. * Return: None
  110. */
  111. static inline
  112. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  113. {
  114. cc_cfg->wbm2sw6_cc_en = 1;
  115. cc_cfg->wbm2sw5_cc_en = 1;
  116. cc_cfg->wbm2sw4_cc_en = 1;
  117. cc_cfg->wbm2sw3_cc_en = 1;
  118. cc_cfg->wbm2sw2_cc_en = 1;
  119. /* disable wbm2sw1 hw cc as it's for FW */
  120. cc_cfg->wbm2sw1_cc_en = 0;
  121. cc_cfg->wbm2sw0_cc_en = 1;
  122. cc_cfg->wbm2fw_cc_en = 0;
  123. }
  124. #else
  125. static inline
  126. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  127. {
  128. cc_cfg->wbm2sw6_cc_en = 1;
  129. cc_cfg->wbm2sw5_cc_en = 1;
  130. cc_cfg->wbm2sw4_cc_en = 1;
  131. cc_cfg->wbm2sw3_cc_en = 1;
  132. cc_cfg->wbm2sw2_cc_en = 1;
  133. cc_cfg->wbm2sw1_cc_en = 1;
  134. cc_cfg->wbm2sw0_cc_en = 1;
  135. cc_cfg->wbm2fw_cc_en = 0;
  136. }
  137. #endif
  138. #if defined(WLAN_SUPPORT_RX_FISA)
  139. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  140. {
  141. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  142. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  143. /* get CMEM for cookie conversion */
  144. if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
  145. dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
  146. return QDF_STATUS_E_NOMEM;
  147. }
  148. soc->fst_cmem_size = DP_CMEM_FST_SIZE;
  149. soc->fst_cmem_base = soc->cmem_base +
  150. (soc->cmem_total_size - soc->cmem_avail_size);
  151. soc->cmem_avail_size -= soc->fst_cmem_size;
  152. dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
  153. soc->fst_cmem_base, soc->fst_cmem_size);
  154. return QDF_STATUS_SUCCESS;
  155. }
  156. #else /* !WLAN_SUPPORT_RX_FISA */
  157. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  158. {
  159. return QDF_STATUS_SUCCESS;
  160. }
  161. #endif
  162. /**
  163. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  164. conversion register
  165. * @soc: SOC handle
  166. * @is_4k_align: page address 4k aligned
  167. *
  168. * Return: None
  169. */
  170. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  171. bool is_4k_align)
  172. {
  173. struct hal_hw_cc_config cc_cfg = { 0 };
  174. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  175. if (soc->cdp_soc.ol_ops->get_con_mode &&
  176. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  177. return;
  178. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  179. dp_info("INI skip HW CC register setting");
  180. return;
  181. }
  182. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  183. cc_cfg.cc_global_en = true;
  184. cc_cfg.page_4k_align = is_4k_align;
  185. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  186. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  187. /* 36th bit should be 1 then HW know this is CMEM address */
  188. cc_cfg.lut_base_addr_39_32 = 0x10;
  189. cc_cfg.error_path_cookie_conv_en = true;
  190. cc_cfg.release_path_cookie_conv_en = true;
  191. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  192. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  193. }
  194. /**
  195. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  196. * @hal_soc_hdl: HAL SOC handle
  197. * @offset: CMEM address
  198. * @value: value to write
  199. *
  200. * Return: None.
  201. */
  202. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  203. uint32_t offset,
  204. uint32_t value)
  205. {
  206. hal_cmem_write(hal_soc_hdl, offset, value);
  207. }
  208. /**
  209. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  210. HW cookie conversion
  211. * @soc: SOC handle
  212. * @cc_ctx: cookie conversion context pointer
  213. *
  214. * Return: 0 in case of success, else error value
  215. */
  216. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  217. {
  218. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  219. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  220. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  221. /* get CMEM for cookie conversion */
  222. if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
  223. dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
  224. return QDF_STATUS_E_RESOURCES;
  225. }
  226. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  227. DP_CC_MEM_OFFSET_IN_CMEM);
  228. soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
  229. dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
  230. be_soc->cc_cmem_base, soc->cmem_avail_size);
  231. return QDF_STATUS_SUCCESS;
  232. }
  233. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  234. uint8_t for_feature)
  235. {
  236. QDF_STATUS status = QDF_STATUS_E_NOMEM;
  237. switch (for_feature) {
  238. case COOKIE_CONVERSION:
  239. status = dp_hw_cc_cmem_addr_init(soc);
  240. break;
  241. case FISA_FST:
  242. status = dp_fisa_fst_cmem_addr_init(soc);
  243. break;
  244. default:
  245. dp_err("Invalid CMEM request");
  246. }
  247. return status;
  248. }
  249. #else
  250. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  251. bool is_4k_align) {}
  252. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  253. uint32_t offset,
  254. uint32_t value)
  255. { }
  256. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  257. {
  258. return QDF_STATUS_SUCCESS;
  259. }
  260. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  261. uint8_t for_feature)
  262. {
  263. return QDF_STATUS_SUCCESS;
  264. }
  265. #endif
  266. QDF_STATUS
  267. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  268. struct dp_hw_cookie_conversion_t *cc_ctx,
  269. uint32_t num_descs,
  270. enum dp_desc_type desc_type,
  271. uint8_t desc_pool_id)
  272. {
  273. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  274. uint32_t num_spt_pages, i = 0;
  275. struct dp_spt_page_desc *spt_desc;
  276. struct qdf_mem_dma_page_t *dma_page;
  277. uint8_t chip_id;
  278. /* estimate how many SPT DDR pages needed */
  279. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  280. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  281. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  282. dp_info("num_spt_pages needed %d", num_spt_pages);
  283. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  284. &cc_ctx->page_pool, qdf_page_size,
  285. num_spt_pages, 0, false);
  286. if (!cc_ctx->page_pool.dma_pages) {
  287. dp_err("spt ddr pages allocation failed");
  288. return QDF_STATUS_E_RESOURCES;
  289. }
  290. cc_ctx->page_desc_base = qdf_mem_malloc(
  291. num_spt_pages * sizeof(struct dp_spt_page_desc));
  292. if (!cc_ctx->page_desc_base) {
  293. dp_err("spt page descs allocation failed");
  294. goto fail_0;
  295. }
  296. chip_id = dp_mlo_get_chip_id(soc);
  297. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  298. desc_type);
  299. /* initial page desc */
  300. spt_desc = cc_ctx->page_desc_base;
  301. dma_page = cc_ctx->page_pool.dma_pages;
  302. while (i < num_spt_pages) {
  303. /* check if page address 4K aligned */
  304. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  305. dp_err("non-4k aligned pages addr %pK",
  306. (void *)dma_page[i].page_p_addr);
  307. goto fail_1;
  308. }
  309. spt_desc[i].page_v_addr =
  310. dma_page[i].page_v_addr_start;
  311. spt_desc[i].page_p_addr =
  312. dma_page[i].page_p_addr;
  313. i++;
  314. }
  315. cc_ctx->total_page_num = num_spt_pages;
  316. qdf_spinlock_create(&cc_ctx->cc_lock);
  317. return QDF_STATUS_SUCCESS;
  318. fail_1:
  319. qdf_mem_free(cc_ctx->page_desc_base);
  320. fail_0:
  321. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  322. &cc_ctx->page_pool, 0, false);
  323. return QDF_STATUS_E_FAILURE;
  324. }
  325. QDF_STATUS
  326. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  327. struct dp_hw_cookie_conversion_t *cc_ctx)
  328. {
  329. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  330. qdf_mem_free(cc_ctx->page_desc_base);
  331. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  332. &cc_ctx->page_pool, 0, false);
  333. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  334. return QDF_STATUS_SUCCESS;
  335. }
  336. QDF_STATUS
  337. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  338. struct dp_hw_cookie_conversion_t *cc_ctx)
  339. {
  340. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  341. uint32_t i = 0;
  342. struct dp_spt_page_desc *spt_desc;
  343. uint32_t ppt_index;
  344. uint32_t ppt_id_start;
  345. if (!cc_ctx->total_page_num) {
  346. dp_err("total page num is 0");
  347. return QDF_STATUS_E_INVAL;
  348. }
  349. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  350. spt_desc = cc_ctx->page_desc_base;
  351. while (i < cc_ctx->total_page_num) {
  352. /* write page PA to CMEM */
  353. dp_hw_cc_cmem_write(soc->hal_soc,
  354. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  355. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  356. (spt_desc[i].page_p_addr >>
  357. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  358. ppt_index = ppt_id_start + i;
  359. if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
  360. qdf_assert_always(0);
  361. spt_desc[i].ppt_index = ppt_index;
  362. be_soc->page_desc_base[ppt_index].page_v_addr =
  363. spt_desc[i].page_v_addr;
  364. i++;
  365. }
  366. return QDF_STATUS_SUCCESS;
  367. }
  368. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  369. QDF_STATUS
  370. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  371. struct dp_hw_cookie_conversion_t *cc_ctx)
  372. {
  373. uint32_t ppt_index;
  374. struct dp_spt_page_desc *spt_desc;
  375. int i = 0;
  376. spt_desc = cc_ctx->page_desc_base;
  377. while (i < cc_ctx->total_page_num) {
  378. ppt_index = spt_desc[i].ppt_index;
  379. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  380. i++;
  381. }
  382. return QDF_STATUS_SUCCESS;
  383. }
  384. #else
  385. QDF_STATUS
  386. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  387. struct dp_hw_cookie_conversion_t *cc_ctx)
  388. {
  389. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  390. uint32_t ppt_index;
  391. struct dp_spt_page_desc *spt_desc;
  392. int i = 0;
  393. spt_desc = cc_ctx->page_desc_base;
  394. while (i < cc_ctx->total_page_num) {
  395. /* reset PA in CMEM to NULL */
  396. dp_hw_cc_cmem_write(soc->hal_soc,
  397. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  398. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  399. 0);
  400. ppt_index = spt_desc[i].ppt_index;
  401. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  402. i++;
  403. }
  404. return QDF_STATUS_SUCCESS;
  405. }
  406. #endif
  407. #ifdef WLAN_SUPPORT_PPEDS
  408. static QDF_STATUS dp_soc_ppe_attach_be(struct dp_soc *soc)
  409. {
  410. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  411. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  412. /*
  413. * Check if PPE DS is enabled.
  414. */
  415. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc->wlan_cfg_ctx))
  416. return QDF_STATUS_SUCCESS;
  417. if (dp_ppeds_attach_soc_be(be_soc) != QDF_STATUS_SUCCESS)
  418. return QDF_STATUS_SUCCESS;
  419. cdp_ops->ppe_ops = &dp_ops_ppe_be;
  420. return QDF_STATUS_SUCCESS;
  421. }
  422. static QDF_STATUS dp_soc_ppe_detach_be(struct dp_soc *soc)
  423. {
  424. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  425. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  426. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc->wlan_cfg_ctx))
  427. return QDF_STATUS_E_FAILURE;
  428. dp_ppeds_detach_soc_be(be_soc);
  429. cdp_ops->ppe_ops = NULL;
  430. return QDF_STATUS_SUCCESS;
  431. }
  432. #else
  433. static QDF_STATUS dp_ppeds_init_soc_be(struct dp_soc *soc)
  434. {
  435. return QDF_STATUS_SUCCESS;
  436. }
  437. static QDF_STATUS dp_ppeds_deinit_soc_be(struct dp_soc *soc)
  438. {
  439. return QDF_STATUS_SUCCESS;
  440. }
  441. static inline QDF_STATUS dp_soc_ppe_attach_be(struct dp_soc *soc)
  442. {
  443. return QDF_STATUS_SUCCESS;
  444. }
  445. static inline QDF_STATUS dp_soc_ppe_detach_be(struct dp_soc *soc)
  446. {
  447. return QDF_STATUS_SUCCESS;
  448. }
  449. #endif /* WLAN_SUPPORT_PPEDS */
  450. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  451. {
  452. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  453. int i = 0;
  454. dp_soc_ppe_detach_be(soc);
  455. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  456. dp_hw_cookie_conversion_detach(be_soc,
  457. &be_soc->tx_cc_ctx[i]);
  458. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  459. dp_hw_cookie_conversion_detach(be_soc,
  460. &be_soc->rx_cc_ctx[i]);
  461. qdf_mem_free(be_soc->page_desc_base);
  462. be_soc->page_desc_base = NULL;
  463. return QDF_STATUS_SUCCESS;
  464. }
  465. #ifdef WLAN_MLO_MULTI_CHIP
  466. #ifdef WLAN_MCAST_MLO
  467. static inline void
  468. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  469. {
  470. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  471. be_vdev->mcast_primary = false;
  472. be_vdev->seq_num = 0;
  473. dp_tx_mcast_mlo_reinject_routing_set(soc,
  474. (void *)&be_vdev->mcast_primary);
  475. if (vdev->opmode == wlan_op_mode_ap) {
  476. if (vdev->mlo_vdev)
  477. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  478. vdev->vdev_id,
  479. HAL_TX_MCAST_CTRL_DROP);
  480. else
  481. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  482. vdev->vdev_id,
  483. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  484. }
  485. }
  486. static inline void
  487. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  488. {
  489. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  490. be_vdev->seq_num = 0;
  491. be_vdev->mcast_primary = false;
  492. vdev->mlo_vdev = false;
  493. }
  494. #else
  495. static inline void
  496. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  497. {
  498. }
  499. static inline void
  500. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  501. {
  502. }
  503. #endif
  504. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  505. {
  506. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  507. qdf_mem_set(be_vdev->partner_vdev_list,
  508. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  509. CDP_INVALID_VDEV_ID);
  510. }
  511. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  512. struct cdp_lro_hash_config *lro_hash)
  513. {
  514. dp_mlo_get_rx_hash_key(soc, lro_hash);
  515. }
  516. #else
  517. static inline void
  518. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  519. {
  520. }
  521. static inline void
  522. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  523. {
  524. }
  525. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  526. {
  527. }
  528. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  529. struct cdp_lro_hash_config *lro_hash)
  530. {
  531. dp_get_rx_hash_key_bytes(lro_hash);
  532. }
  533. #endif
  534. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  535. struct cdp_soc_attach_params *params)
  536. {
  537. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  538. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  539. uint32_t max_tx_rx_desc_num, num_spt_pages;
  540. uint32_t num_entries;
  541. int i = 0;
  542. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  543. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS +
  544. WLAN_CFG_NUM_PPEDS_TX_DESC_MAX * MAX_PPE_TXDESC_POOLS;
  545. /* estimate how many SPT DDR pages needed */
  546. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  547. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  548. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  549. be_soc->page_desc_base = qdf_mem_malloc(
  550. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  551. if (!be_soc->page_desc_base) {
  552. dp_err("spt page descs allocation failed");
  553. return QDF_STATUS_E_NOMEM;
  554. }
  555. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  556. qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
  557. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  558. goto fail;
  559. dp_soc_mlo_fill_params(soc, params);
  560. qdf_status = dp_soc_ppe_attach_be(soc);
  561. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  562. goto fail;
  563. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  564. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  565. qdf_status =
  566. dp_hw_cookie_conversion_attach(be_soc,
  567. &be_soc->tx_cc_ctx[i],
  568. num_entries,
  569. DP_TX_DESC_TYPE, i);
  570. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  571. goto fail;
  572. }
  573. qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
  574. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  575. goto fail;
  576. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  577. num_entries =
  578. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  579. qdf_status =
  580. dp_hw_cookie_conversion_attach(be_soc,
  581. &be_soc->rx_cc_ctx[i],
  582. num_entries,
  583. DP_RX_DESC_BUF_TYPE, i);
  584. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  585. goto fail;
  586. }
  587. return qdf_status;
  588. fail:
  589. dp_soc_detach_be(soc);
  590. return qdf_status;
  591. }
  592. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  593. {
  594. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  595. int i = 0;
  596. dp_tx_deinit_bank_profiles(be_soc);
  597. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  598. dp_hw_cookie_conversion_deinit(be_soc,
  599. &be_soc->tx_cc_ctx[i]);
  600. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  601. dp_hw_cookie_conversion_deinit(be_soc,
  602. &be_soc->rx_cc_ctx[i]);
  603. dp_ppeds_deinit_soc_be(soc);
  604. return QDF_STATUS_SUCCESS;
  605. }
  606. static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
  607. {
  608. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  609. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  610. int i = 0;
  611. dp_ppeds_init_soc_be(soc);
  612. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  613. qdf_status =
  614. dp_hw_cookie_conversion_init(be_soc,
  615. &be_soc->tx_cc_ctx[i]);
  616. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  617. goto fail;
  618. }
  619. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  620. qdf_status =
  621. dp_hw_cookie_conversion_init(be_soc,
  622. &be_soc->rx_cc_ctx[i]);
  623. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  624. goto fail;
  625. }
  626. /* route vdev_id mismatch notification via FW completion */
  627. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  628. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  629. qdf_status = dp_tx_init_bank_profiles(be_soc);
  630. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  631. goto fail;
  632. /* write WBM/REO cookie conversion CFG register */
  633. dp_cc_reg_cfg_init(soc, true);
  634. return qdf_status;
  635. fail:
  636. dp_soc_deinit_be(soc);
  637. return qdf_status;
  638. }
  639. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  640. struct cdp_pdev_attach_params *params)
  641. {
  642. dp_pdev_mlo_fill_params(pdev, params);
  643. dp_mlo_update_link_to_pdev_map(pdev->soc, pdev);
  644. return QDF_STATUS_SUCCESS;
  645. }
  646. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  647. {
  648. dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
  649. return QDF_STATUS_SUCCESS;
  650. }
  651. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  652. {
  653. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  654. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  655. struct dp_pdev *pdev = vdev->pdev;
  656. if (vdev->opmode == wlan_op_mode_monitor)
  657. return QDF_STATUS_SUCCESS;
  658. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  659. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  660. vdev->bank_id = be_vdev->bank_id;
  661. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  662. QDF_BUG(0);
  663. return QDF_STATUS_E_FAULT;
  664. }
  665. if (vdev->opmode == wlan_op_mode_sta) {
  666. if (soc->cdp_soc.ol_ops->set_mec_timer)
  667. soc->cdp_soc.ol_ops->set_mec_timer(
  668. soc->ctrl_psoc,
  669. vdev->vdev_id,
  670. DP_AST_AGING_TIMER_DEFAULT_MS);
  671. if (pdev->isolation)
  672. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  673. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  674. else
  675. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  676. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  677. }
  678. dp_mlo_mcast_init(soc, vdev);
  679. dp_mlo_init_ptnr_list(vdev);
  680. return QDF_STATUS_SUCCESS;
  681. }
  682. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  683. {
  684. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  685. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  686. if (vdev->opmode == wlan_op_mode_monitor)
  687. return QDF_STATUS_SUCCESS;
  688. if (vdev->opmode == wlan_op_mode_ap)
  689. dp_mlo_mcast_deinit(soc, vdev);
  690. dp_tx_put_bank_profile(be_soc, be_vdev);
  691. dp_clr_mlo_ptnr_list(soc, vdev);
  692. return QDF_STATUS_SUCCESS;
  693. }
  694. qdf_size_t dp_get_soc_context_size_be(void)
  695. {
  696. return sizeof(struct dp_soc_be);
  697. }
  698. #ifdef CONFIG_WORD_BASED_TLV
  699. /**
  700. * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
  701. * @soc: Common DP soc handle
  702. * @htt_tlv_filter: Rx SRNG TLV and filter setting
  703. *
  704. * Return: none
  705. */
  706. static inline void
  707. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  708. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  709. {
  710. htt_tlv_filter->rx_msdu_end_wmask =
  711. hal_rx_msdu_end_wmask_get(soc->hal_soc);
  712. htt_tlv_filter->rx_mpdu_start_wmask =
  713. hal_rx_mpdu_start_wmask_get(soc->hal_soc);
  714. }
  715. #else
  716. static inline void
  717. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  718. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  719. {
  720. }
  721. #endif
  722. #ifdef NO_RX_PKT_HDR_TLV
  723. /**
  724. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  725. * @soc: Common DP soc handle
  726. *
  727. * Return: QDF_STATUS
  728. */
  729. static QDF_STATUS
  730. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  731. {
  732. int i;
  733. int mac_id;
  734. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  735. struct dp_srng *rx_mac_srng;
  736. QDF_STATUS status = QDF_STATUS_SUCCESS;
  737. /*
  738. * In Beryllium chipset msdu_start, mpdu_end
  739. * and rx_attn are part of msdu_end/mpdu_start
  740. */
  741. htt_tlv_filter.msdu_start = 0;
  742. htt_tlv_filter.mpdu_end = 0;
  743. htt_tlv_filter.attention = 0;
  744. htt_tlv_filter.mpdu_start = 1;
  745. htt_tlv_filter.msdu_end = 1;
  746. htt_tlv_filter.packet = 1;
  747. htt_tlv_filter.packet_header = 0;
  748. htt_tlv_filter.ppdu_start = 0;
  749. htt_tlv_filter.ppdu_end = 0;
  750. htt_tlv_filter.ppdu_end_user_stats = 0;
  751. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  752. htt_tlv_filter.ppdu_end_status_done = 0;
  753. htt_tlv_filter.enable_fp = 1;
  754. htt_tlv_filter.enable_md = 0;
  755. htt_tlv_filter.enable_md = 0;
  756. htt_tlv_filter.enable_mo = 0;
  757. htt_tlv_filter.fp_mgmt_filter = 0;
  758. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  759. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  760. FILTER_DATA_MCAST |
  761. FILTER_DATA_DATA);
  762. htt_tlv_filter.mo_mgmt_filter = 0;
  763. htt_tlv_filter.mo_ctrl_filter = 0;
  764. htt_tlv_filter.mo_data_filter = 0;
  765. htt_tlv_filter.md_data_filter = 0;
  766. htt_tlv_filter.offset_valid = true;
  767. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  768. htt_tlv_filter.rx_mpdu_end_offset = 0;
  769. htt_tlv_filter.rx_msdu_start_offset = 0;
  770. htt_tlv_filter.rx_attn_offset = 0;
  771. /*
  772. * For monitor mode, the packet hdr tlv is enabled later during
  773. * filter update
  774. */
  775. if (soc->cdp_soc.ol_ops->get_con_mode &&
  776. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  777. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  778. else
  779. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  780. /*Not subscribing rx_pkt_header*/
  781. htt_tlv_filter.rx_header_offset = 0;
  782. htt_tlv_filter.rx_mpdu_start_offset =
  783. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  784. htt_tlv_filter.rx_msdu_end_offset =
  785. hal_rx_msdu_end_offset_get(soc->hal_soc);
  786. dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
  787. for (i = 0; i < MAX_PDEV_CNT; i++) {
  788. struct dp_pdev *pdev = soc->pdev_list[i];
  789. if (!pdev)
  790. continue;
  791. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  792. int mac_for_pdev =
  793. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  794. /*
  795. * Obtain lmac id from pdev to access the LMAC ring
  796. * in soc context
  797. */
  798. int lmac_id =
  799. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  800. pdev->pdev_id);
  801. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  802. if (!rx_mac_srng->hal_srng)
  803. continue;
  804. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  805. rx_mac_srng->hal_srng,
  806. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  807. &htt_tlv_filter);
  808. }
  809. }
  810. return status;
  811. }
  812. #else
  813. /**
  814. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  815. * @soc: Common DP soc handle
  816. *
  817. * Return: QDF_STATUS
  818. */
  819. static QDF_STATUS
  820. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  821. {
  822. int i;
  823. int mac_id;
  824. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  825. struct dp_srng *rx_mac_srng;
  826. QDF_STATUS status = QDF_STATUS_SUCCESS;
  827. /*
  828. * In Beryllium chipset msdu_start, mpdu_end
  829. * and rx_attn are part of msdu_end/mpdu_start
  830. */
  831. htt_tlv_filter.msdu_start = 0;
  832. htt_tlv_filter.mpdu_end = 0;
  833. htt_tlv_filter.attention = 0;
  834. htt_tlv_filter.mpdu_start = 1;
  835. htt_tlv_filter.msdu_end = 1;
  836. htt_tlv_filter.packet = 1;
  837. htt_tlv_filter.packet_header = 1;
  838. htt_tlv_filter.ppdu_start = 0;
  839. htt_tlv_filter.ppdu_end = 0;
  840. htt_tlv_filter.ppdu_end_user_stats = 0;
  841. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  842. htt_tlv_filter.ppdu_end_status_done = 0;
  843. htt_tlv_filter.enable_fp = 1;
  844. htt_tlv_filter.enable_md = 0;
  845. htt_tlv_filter.enable_md = 0;
  846. htt_tlv_filter.enable_mo = 0;
  847. htt_tlv_filter.fp_mgmt_filter = 0;
  848. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  849. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  850. FILTER_DATA_MCAST |
  851. FILTER_DATA_DATA);
  852. htt_tlv_filter.mo_mgmt_filter = 0;
  853. htt_tlv_filter.mo_ctrl_filter = 0;
  854. htt_tlv_filter.mo_data_filter = 0;
  855. htt_tlv_filter.md_data_filter = 0;
  856. htt_tlv_filter.offset_valid = true;
  857. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  858. htt_tlv_filter.rx_mpdu_end_offset = 0;
  859. htt_tlv_filter.rx_msdu_start_offset = 0;
  860. htt_tlv_filter.rx_attn_offset = 0;
  861. /*
  862. * For monitor mode, the packet hdr tlv is enabled later during
  863. * filter update
  864. */
  865. if (soc->cdp_soc.ol_ops->get_con_mode &&
  866. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  867. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  868. else
  869. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  870. htt_tlv_filter.rx_header_offset =
  871. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  872. htt_tlv_filter.rx_mpdu_start_offset =
  873. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  874. htt_tlv_filter.rx_msdu_end_offset =
  875. hal_rx_msdu_end_offset_get(soc->hal_soc);
  876. dp_info("TLV subscription\n"
  877. "msdu_start %d, mpdu_end %d, attention %d"
  878. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  879. "TLV offsets\n"
  880. "msdu_start %d, mpdu_end %d, attention %d"
  881. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  882. htt_tlv_filter.msdu_start,
  883. htt_tlv_filter.mpdu_end,
  884. htt_tlv_filter.attention,
  885. htt_tlv_filter.mpdu_start,
  886. htt_tlv_filter.msdu_end,
  887. htt_tlv_filter.packet_header,
  888. htt_tlv_filter.packet,
  889. htt_tlv_filter.rx_msdu_start_offset,
  890. htt_tlv_filter.rx_mpdu_end_offset,
  891. htt_tlv_filter.rx_attn_offset,
  892. htt_tlv_filter.rx_mpdu_start_offset,
  893. htt_tlv_filter.rx_msdu_end_offset,
  894. htt_tlv_filter.rx_header_offset,
  895. htt_tlv_filter.rx_packet_offset);
  896. for (i = 0; i < MAX_PDEV_CNT; i++) {
  897. struct dp_pdev *pdev = soc->pdev_list[i];
  898. if (!pdev)
  899. continue;
  900. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  901. int mac_for_pdev =
  902. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  903. /*
  904. * Obtain lmac id from pdev to access the LMAC ring
  905. * in soc context
  906. */
  907. int lmac_id =
  908. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  909. pdev->pdev_id);
  910. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  911. if (!rx_mac_srng->hal_srng)
  912. continue;
  913. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  914. rx_mac_srng->hal_srng,
  915. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  916. &htt_tlv_filter);
  917. }
  918. }
  919. return status;
  920. }
  921. #endif
  922. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  923. /**
  924. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  925. * near-full IRQs.
  926. * @soc: Datapath SoC handle
  927. * @int_ctx: Interrupt context
  928. * @dp_budget: Budget of the work that can be done in the bottom half
  929. *
  930. * Return: work done in the handler
  931. */
  932. static uint32_t
  933. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  934. uint32_t dp_budget)
  935. {
  936. int ring = 0;
  937. int budget = dp_budget;
  938. uint32_t work_done = 0;
  939. uint32_t remaining_quota = dp_budget;
  940. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  941. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  942. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  943. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  944. int rx_near_full_mask = rx_near_full_grp_1_mask |
  945. rx_near_full_grp_2_mask;
  946. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  947. rx_near_full_mask,
  948. tx_ring_near_full_mask);
  949. if (rx_near_full_mask) {
  950. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  951. if (!(rx_near_full_mask & (1 << ring)))
  952. continue;
  953. work_done = dp_rx_nf_process(int_ctx,
  954. soc->reo_dest_ring[ring].hal_srng,
  955. ring, remaining_quota);
  956. if (work_done) {
  957. intr_stats->num_rx_ring_near_full_masks[ring]++;
  958. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  959. rx_near_full_mask, ring,
  960. work_done,
  961. budget);
  962. budget -= work_done;
  963. if (budget <= 0)
  964. goto budget_done;
  965. remaining_quota = budget;
  966. }
  967. }
  968. }
  969. if (tx_ring_near_full_mask) {
  970. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  971. if (!(tx_ring_near_full_mask & (1 << ring)))
  972. continue;
  973. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  974. soc->tx_comp_ring[ring].hal_srng,
  975. ring, remaining_quota);
  976. if (work_done) {
  977. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  978. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  979. tx_ring_near_full_mask, ring,
  980. work_done, budget);
  981. budget -= work_done;
  982. if (budget <= 0)
  983. break;
  984. remaining_quota = budget;
  985. }
  986. }
  987. }
  988. intr_stats->num_near_full_masks++;
  989. budget_done:
  990. return dp_budget - budget;
  991. }
  992. /**
  993. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  994. * state and set the reap_limit appropriately
  995. * as per the near full state
  996. * @soc: Datapath soc handle
  997. * @dp_srng: Datapath handle for SRNG
  998. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  999. * the srng near-full state
  1000. *
  1001. * Return: 1, if the srng is in near-full state
  1002. * 0, if the srng is not in near-full state
  1003. */
  1004. static int
  1005. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  1006. struct dp_srng *dp_srng,
  1007. int *max_reap_limit)
  1008. {
  1009. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  1010. }
  1011. /**
  1012. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  1013. * near full IRQ handling operations.
  1014. * @arch_ops: arch ops handle
  1015. *
  1016. * Return: none
  1017. */
  1018. static inline void
  1019. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1020. {
  1021. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  1022. arch_ops->dp_srng_test_and_update_nf_params =
  1023. dp_srng_test_and_update_nf_params_be;
  1024. }
  1025. #else
  1026. static inline void
  1027. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1028. {
  1029. }
  1030. #endif
  1031. #ifdef WLAN_SUPPORT_PPEDS
  1032. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  1033. {
  1034. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1035. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1036. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1037. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  1038. return;
  1039. dp_srng_deinit(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0);
  1040. wlan_minidump_remove(be_soc->ppe_release_ring.base_vaddr_unaligned,
  1041. be_soc->ppe_release_ring.alloc_size,
  1042. soc->ctrl_psoc,
  1043. WLAN_MD_DP_SRNG_PPE_RELEASE,
  1044. "ppe_release_ring");
  1045. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  1046. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1047. be_soc->ppe2tcl_ring.alloc_size,
  1048. soc->ctrl_psoc,
  1049. WLAN_MD_DP_SRNG_PPE2TCL,
  1050. "ppe2tcl_ring");
  1051. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  1052. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1053. be_soc->reo2ppe_ring.alloc_size,
  1054. soc->ctrl_psoc,
  1055. WLAN_MD_DP_SRNG_REO2PPE,
  1056. "reo2ppe_ring");
  1057. }
  1058. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  1059. {
  1060. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1061. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1062. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1063. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  1064. return;
  1065. dp_srng_free(soc, &be_soc->ppe_release_ring);
  1066. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  1067. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  1068. }
  1069. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  1070. {
  1071. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1072. uint32_t entries;
  1073. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1074. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1075. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  1076. return QDF_STATUS_SUCCESS;
  1077. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  1078. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  1079. entries, 0)) {
  1080. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  1081. goto fail;
  1082. }
  1083. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  1084. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  1085. entries, 0)) {
  1086. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  1087. goto fail;
  1088. }
  1089. entries = wlan_cfg_get_dp_soc_ppe_release_ring_size(soc_cfg_ctx);
  1090. if (dp_srng_alloc(soc, &be_soc->ppe_release_ring, PPE_RELEASE,
  1091. entries, 0)) {
  1092. dp_err("%pK: dp_srng_alloc failed for ppe_release_ring", soc);
  1093. goto fail;
  1094. }
  1095. return QDF_STATUS_SUCCESS;
  1096. fail:
  1097. dp_soc_ppe_srng_free(soc);
  1098. return QDF_STATUS_E_NOMEM;
  1099. }
  1100. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  1101. {
  1102. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1103. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1104. hal_soc_handle_t hal_soc = soc->hal_soc;
  1105. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1106. if (!wlan_cfg_get_dp_soc_is_ppe_enabled(soc_cfg_ctx))
  1107. return QDF_STATUS_SUCCESS;
  1108. if (dp_srng_init(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0)) {
  1109. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  1110. goto fail;
  1111. }
  1112. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1113. be_soc->reo2ppe_ring.alloc_size,
  1114. soc->ctrl_psoc,
  1115. WLAN_MD_DP_SRNG_REO2PPE,
  1116. "reo2ppe_ring");
  1117. hal_reo_config_reo2ppe_dest_info(hal_soc);
  1118. if (dp_srng_init(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0)) {
  1119. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  1120. goto fail;
  1121. }
  1122. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1123. be_soc->ppe2tcl_ring.alloc_size,
  1124. soc->ctrl_psoc,
  1125. WLAN_MD_DP_SRNG_PPE2TCL,
  1126. "ppe2tcl_ring");
  1127. if (dp_srng_init(soc, &be_soc->ppe_release_ring, PPE_RELEASE, 0, 0)) {
  1128. dp_err("%pK: dp_srng_init failed for ppe_release_ring", soc);
  1129. goto fail;
  1130. }
  1131. wlan_minidump_log(be_soc->ppe_release_ring.base_vaddr_unaligned,
  1132. be_soc->ppe_release_ring.alloc_size,
  1133. soc->ctrl_psoc,
  1134. WLAN_MD_DP_SRNG_PPE_RELEASE,
  1135. "ppe_release_ring");
  1136. #ifdef WLAN_SUPPORT_PPEDS
  1137. if (dp_ppeds_register_soc_be(be_soc)) {
  1138. dp_err("%pK: ppeds registration failed", soc);
  1139. goto fail;
  1140. }
  1141. #endif
  1142. return QDF_STATUS_SUCCESS;
  1143. fail:
  1144. dp_soc_ppe_srng_deinit(soc);
  1145. return QDF_STATUS_E_NOMEM;
  1146. }
  1147. #else
  1148. static void dp_soc_ppe_srng_deinit(struct dp_soc *soc)
  1149. {
  1150. }
  1151. static void dp_soc_ppe_srng_free(struct dp_soc *soc)
  1152. {
  1153. }
  1154. static QDF_STATUS dp_soc_ppe_srng_alloc(struct dp_soc *soc)
  1155. {
  1156. return QDF_STATUS_SUCCESS;
  1157. }
  1158. static QDF_STATUS dp_soc_ppe_srng_init(struct dp_soc *soc)
  1159. {
  1160. return QDF_STATUS_SUCCESS;
  1161. }
  1162. #endif
  1163. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1164. {
  1165. uint32_t i;
  1166. dp_soc_ppe_srng_deinit(soc);
  1167. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1168. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1169. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1170. RXDMA_BUF, 0);
  1171. }
  1172. }
  1173. }
  1174. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1175. {
  1176. uint32_t i;
  1177. dp_soc_ppe_srng_free(soc);
  1178. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1179. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1180. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1181. }
  1182. }
  1183. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1184. {
  1185. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1186. uint32_t ring_size;
  1187. uint32_t i;
  1188. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1189. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1190. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1191. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1192. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1193. RXDMA_BUF, ring_size, 0)) {
  1194. dp_err("%pK: dp_srng_alloc failed refill ring",
  1195. soc);
  1196. goto fail;
  1197. }
  1198. }
  1199. }
  1200. if (dp_soc_ppe_srng_alloc(soc)) {
  1201. dp_err("%pK: ppe rings alloc failed",
  1202. soc);
  1203. goto fail;
  1204. }
  1205. return QDF_STATUS_SUCCESS;
  1206. fail:
  1207. dp_soc_srng_free_be(soc);
  1208. return QDF_STATUS_E_NOMEM;
  1209. }
  1210. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1211. {
  1212. int i = 0;
  1213. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1214. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1215. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1216. RXDMA_BUF, 0, 0)) {
  1217. dp_err("%pK: dp_srng_init failed refill ring",
  1218. soc);
  1219. goto fail;
  1220. }
  1221. }
  1222. }
  1223. if (dp_soc_ppe_srng_init(soc)) {
  1224. dp_err("%pK: ppe rings init failed",
  1225. soc);
  1226. goto fail;
  1227. }
  1228. return QDF_STATUS_SUCCESS;
  1229. fail:
  1230. dp_soc_srng_deinit_be(soc);
  1231. return QDF_STATUS_E_NOMEM;
  1232. }
  1233. #ifdef WLAN_FEATURE_11BE_MLO
  1234. static inline unsigned
  1235. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1236. union dp_align_mac_addr *mac_addr)
  1237. {
  1238. uint32_t index;
  1239. index =
  1240. mac_addr->align2.bytes_ab ^
  1241. mac_addr->align2.bytes_cd ^
  1242. mac_addr->align2.bytes_ef;
  1243. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1244. index &= mld_hash_obj->mld_peer_hash.mask;
  1245. return index;
  1246. }
  1247. QDF_STATUS
  1248. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1249. int hash_elems)
  1250. {
  1251. int i, log2;
  1252. if (!mld_hash_obj)
  1253. return QDF_STATUS_E_FAILURE;
  1254. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1255. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1256. log2 = dp_log2_ceil(hash_elems);
  1257. hash_elems = 1 << log2;
  1258. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1259. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1260. /* allocate an array of TAILQ peer object lists */
  1261. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1262. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1263. if (!mld_hash_obj->mld_peer_hash.bins)
  1264. return QDF_STATUS_E_NOMEM;
  1265. for (i = 0; i < hash_elems; i++)
  1266. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1267. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1268. return QDF_STATUS_SUCCESS;
  1269. }
  1270. void
  1271. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1272. {
  1273. if (!mld_hash_obj)
  1274. return;
  1275. if (mld_hash_obj->mld_peer_hash.bins) {
  1276. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1277. mld_hash_obj->mld_peer_hash.bins = NULL;
  1278. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1279. }
  1280. }
  1281. #ifdef WLAN_MLO_MULTI_CHIP
  1282. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1283. {
  1284. /* In case of MULTI chip MLO peer hash table when MLO global object
  1285. * is created, avoid from SOC attach path
  1286. */
  1287. return QDF_STATUS_SUCCESS;
  1288. }
  1289. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1290. {
  1291. }
  1292. #else
  1293. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1294. {
  1295. dp_mld_peer_hash_obj_t mld_hash_obj;
  1296. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1297. if (!mld_hash_obj)
  1298. return QDF_STATUS_E_FAILURE;
  1299. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1300. }
  1301. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1302. {
  1303. dp_mld_peer_hash_obj_t mld_hash_obj;
  1304. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1305. if (!mld_hash_obj)
  1306. return;
  1307. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1308. }
  1309. #endif
  1310. static struct dp_peer *
  1311. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1312. uint8_t *peer_mac_addr,
  1313. int mac_addr_is_aligned,
  1314. enum dp_mod_id mod_id,
  1315. uint8_t vdev_id)
  1316. {
  1317. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1318. uint32_t index;
  1319. struct dp_peer *peer;
  1320. struct dp_vdev *vdev;
  1321. dp_mld_peer_hash_obj_t mld_hash_obj;
  1322. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1323. if (!mld_hash_obj)
  1324. return NULL;
  1325. if (!mld_hash_obj->mld_peer_hash.bins)
  1326. return NULL;
  1327. if (mac_addr_is_aligned) {
  1328. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1329. } else {
  1330. qdf_mem_copy(
  1331. &local_mac_addr_aligned.raw[0],
  1332. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1333. mac_addr = &local_mac_addr_aligned;
  1334. }
  1335. if (vdev_id != DP_VDEV_ALL) {
  1336. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1337. if (!vdev) {
  1338. dp_err("vdev is null\n");
  1339. return NULL;
  1340. }
  1341. } else {
  1342. vdev = NULL;
  1343. }
  1344. /* search mld peer table if no link peer for given mac address */
  1345. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1346. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1347. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1348. hash_list_elem) {
  1349. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1350. if ((vdev_id == DP_VDEV_ALL) || (
  1351. dp_peer_find_mac_addr_cmp(
  1352. &peer->vdev->mld_mac_addr,
  1353. &vdev->mld_mac_addr) == 0)) {
  1354. /* take peer reference before returning */
  1355. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1356. QDF_STATUS_SUCCESS)
  1357. peer = NULL;
  1358. if (vdev)
  1359. dp_vdev_unref_delete(soc, vdev, mod_id);
  1360. qdf_spin_unlock_bh(
  1361. &mld_hash_obj->mld_peer_hash_lock);
  1362. return peer;
  1363. }
  1364. }
  1365. }
  1366. if (vdev)
  1367. dp_vdev_unref_delete(soc, vdev, mod_id);
  1368. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1369. return NULL; /* failure */
  1370. }
  1371. static void
  1372. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1373. {
  1374. uint32_t index;
  1375. struct dp_peer *tmppeer = NULL;
  1376. int found = 0;
  1377. dp_mld_peer_hash_obj_t mld_hash_obj;
  1378. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1379. if (!mld_hash_obj)
  1380. return;
  1381. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1382. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1383. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1384. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1385. hash_list_elem) {
  1386. if (tmppeer == peer) {
  1387. found = 1;
  1388. break;
  1389. }
  1390. }
  1391. QDF_ASSERT(found);
  1392. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1393. hash_list_elem);
  1394. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1395. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1396. }
  1397. static void
  1398. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1399. {
  1400. uint32_t index;
  1401. dp_mld_peer_hash_obj_t mld_hash_obj;
  1402. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1403. if (!mld_hash_obj)
  1404. return;
  1405. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1406. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1407. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1408. DP_MOD_ID_CONFIG))) {
  1409. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1410. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1411. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1412. return;
  1413. }
  1414. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1415. hash_list_elem);
  1416. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1417. }
  1418. void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
  1419. {
  1420. uint32_t index;
  1421. struct dp_peer *peer;
  1422. dp_mld_peer_hash_obj_t mld_hash_obj;
  1423. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1424. if (!mld_hash_obj)
  1425. return;
  1426. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1427. for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
  1428. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1429. hash_list_elem) {
  1430. dp_print_peer_ast_entries(soc, peer, NULL);
  1431. }
  1432. }
  1433. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1434. }
  1435. #endif
  1436. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1437. static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
  1438. struct dp_vdev *vdev)
  1439. {
  1440. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1441. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1442. hal_soc_handle_t hal_soc = soc->hal_soc;
  1443. uint8_t vdev_id = vdev->vdev_id;
  1444. if (vdev->opmode == wlan_op_mode_sta) {
  1445. if (vdev->pdev->isolation)
  1446. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1447. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1448. else
  1449. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1450. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  1451. } else if (vdev->opmode == wlan_op_mode_ap) {
  1452. if (vdev->mlo_vdev) {
  1453. if (be_vdev->mcast_primary) {
  1454. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1455. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1456. hal_tx_vdev_mcast_ctrl_set(hal_soc,
  1457. vdev_id + 128,
  1458. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1459. dp_mcast_mlo_iter_ptnr_soc(be_soc,
  1460. dp_tx_mcast_mlo_reinject_routing_set,
  1461. (void *)&be_vdev->mcast_primary);
  1462. } else {
  1463. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1464. HAL_TX_MCAST_CTRL_DROP);
  1465. }
  1466. } else {
  1467. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  1468. vdev_id,
  1469. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1470. }
  1471. }
  1472. }
  1473. static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
  1474. {
  1475. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1476. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1477. union hal_tx_bank_config *bank_config;
  1478. if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
  1479. return;
  1480. bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
  1481. hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
  1482. be_vdev->bank_id);
  1483. }
  1484. #endif
  1485. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1486. defined(WLAN_MCAST_MLO)
  1487. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1488. struct dp_vdev_be *be_vdev,
  1489. cdp_config_param_type val)
  1490. {
  1491. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1492. be_vdev->vdev.pdev->soc);
  1493. hal_soc_handle_t hal_soc = be_vdev->vdev.pdev->soc->hal_soc;
  1494. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  1495. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1496. if (be_vdev->mcast_primary) {
  1497. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1498. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1499. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id + 128,
  1500. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1501. dp_mcast_mlo_iter_ptnr_soc(be_soc,
  1502. dp_tx_mcast_mlo_reinject_routing_set,
  1503. (void *)&be_vdev->mcast_primary);
  1504. } else {
  1505. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1506. HAL_TX_MCAST_CTRL_DROP);
  1507. }
  1508. }
  1509. #else
  1510. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1511. struct dp_vdev_be *be_vdev,
  1512. cdp_config_param_type val)
  1513. {
  1514. }
  1515. #endif
  1516. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  1517. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1518. uint8_t tx_ring_id,
  1519. uint8_t bm_id)
  1520. {
  1521. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1522. soc->tcl_data_ring[tx_ring_id].hal_srng,
  1523. bm_id);
  1524. }
  1525. #else
  1526. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  1527. uint8_t tx_ring_id,
  1528. uint8_t bm_id)
  1529. {
  1530. }
  1531. #endif
  1532. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  1533. struct dp_vdev *vdev,
  1534. enum cdp_vdev_param_type param,
  1535. cdp_config_param_type val)
  1536. {
  1537. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1538. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1539. switch (param) {
  1540. case CDP_TX_ENCAP_TYPE:
  1541. case CDP_UPDATE_DSCP_TO_TID_MAP:
  1542. case CDP_UPDATE_TDLS_FLAGS:
  1543. dp_tx_update_bank_profile(be_soc, be_vdev);
  1544. break;
  1545. case CDP_ENABLE_CIPHER:
  1546. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  1547. dp_tx_update_bank_profile(be_soc, be_vdev);
  1548. break;
  1549. case CDP_SET_MCAST_VDEV:
  1550. dp_txrx_set_mlo_mcast_primary_vdev_param_be(be_vdev, val);
  1551. break;
  1552. default:
  1553. dp_warn("invalid param %d", param);
  1554. break;
  1555. }
  1556. return QDF_STATUS_SUCCESS;
  1557. }
  1558. #ifdef WLAN_FEATURE_11BE_MLO
  1559. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  1560. static inline void
  1561. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1562. {
  1563. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  1564. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  1565. /*
  1566. * Double the peers since we use ML indication bit
  1567. * alongwith peer_id to find peers.
  1568. */
  1569. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  1570. }
  1571. #else
  1572. static inline void
  1573. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1574. {
  1575. soc->max_peer_id =
  1576. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  1577. }
  1578. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  1579. #else
  1580. static inline void
  1581. dp_soc_max_peer_id_set(struct dp_soc *soc)
  1582. {
  1583. soc->max_peer_id = soc->max_peers;
  1584. }
  1585. #endif /* WLAN_FEATURE_11BE_MLO */
  1586. static void dp_peer_map_detach_be(struct dp_soc *soc)
  1587. {
  1588. if (soc->host_ast_db_enable)
  1589. dp_peer_ast_hash_detach(soc);
  1590. }
  1591. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  1592. {
  1593. QDF_STATUS status;
  1594. if (soc->host_ast_db_enable) {
  1595. status = dp_peer_ast_hash_attach(soc);
  1596. if (QDF_IS_STATUS_ERROR(status))
  1597. return status;
  1598. }
  1599. dp_soc_max_peer_id_set(soc);
  1600. return QDF_STATUS_SUCCESS;
  1601. }
  1602. static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
  1603. uint8_t *dest_mac,
  1604. uint8_t vdev_id)
  1605. {
  1606. struct dp_peer *peer = NULL;
  1607. struct dp_peer *tgt_peer = NULL;
  1608. struct dp_ast_entry *ast_entry = NULL;
  1609. uint16_t peer_id;
  1610. qdf_spin_lock_bh(&soc->ast_lock);
  1611. ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac);
  1612. if (!ast_entry) {
  1613. qdf_spin_unlock_bh(&soc->ast_lock);
  1614. dp_err("NULL ast entry");
  1615. return NULL;
  1616. }
  1617. peer_id = ast_entry->peer_id;
  1618. qdf_spin_unlock_bh(&soc->ast_lock);
  1619. if (peer_id == HTT_INVALID_PEER)
  1620. return NULL;
  1621. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF);
  1622. if (!peer) {
  1623. dp_err("NULL peer for peer_id:%d", peer_id);
  1624. return NULL;
  1625. }
  1626. tgt_peer = dp_get_tgt_peer_from_peer(peer);
  1627. /*
  1628. * Once tgt_peer is obtained,
  1629. * release the ref taken for original peer.
  1630. */
  1631. dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF);
  1632. dp_peer_unref_delete(peer, DP_MOD_ID_SAWF);
  1633. return tgt_peer;
  1634. }
  1635. #ifdef WLAN_FEATURE_11BE_MLO
  1636. #ifdef WLAN_MCAST_MLO
  1637. static inline void
  1638. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1639. {
  1640. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  1641. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  1642. }
  1643. #else /* WLAN_MCAST_MLO */
  1644. static inline void
  1645. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  1646. {
  1647. }
  1648. #endif /* WLAN_MCAST_MLO */
  1649. #ifdef WLAN_MLO_MULTI_CHIP
  1650. static inline void
  1651. dp_initialize_arch_ops_be_mlo_ptnr_chip(struct dp_arch_ops *arch_ops)
  1652. {
  1653. arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
  1654. arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
  1655. }
  1656. #else
  1657. static inline void
  1658. dp_initialize_arch_ops_be_mlo_ptnr_chip(struct dp_arch_ops *arch_ops)
  1659. {
  1660. }
  1661. #endif
  1662. static inline void
  1663. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1664. {
  1665. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  1666. dp_initialize_arch_ops_be_mlo_ptnr_chip(arch_ops);
  1667. arch_ops->mlo_peer_find_hash_detach =
  1668. dp_mlo_peer_find_hash_detach_wrapper;
  1669. arch_ops->mlo_peer_find_hash_attach =
  1670. dp_mlo_peer_find_hash_attach_wrapper;
  1671. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  1672. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  1673. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  1674. }
  1675. #else /* WLAN_FEATURE_11BE_MLO */
  1676. static inline void
  1677. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  1678. {
  1679. }
  1680. #endif /* WLAN_FEATURE_11BE_MLO */
  1681. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  1682. #define DP_LMAC_PEER_ID_MSB_LEGACY 2
  1683. #define DP_LMAC_PEER_ID_MSB_MLO 3
  1684. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1685. struct cdp_peer_setup_info *setup_info,
  1686. enum cdp_host_reo_dest_ring *reo_dest,
  1687. bool *hash_based,
  1688. uint8_t *lmac_peer_id_msb)
  1689. {
  1690. struct dp_soc *soc = vdev->pdev->soc;
  1691. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1692. if (!be_soc->mlo_enabled)
  1693. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  1694. hash_based);
  1695. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  1696. *reo_dest = vdev->pdev->reo_dest;
  1697. /* Not a ML link peer use non-mlo */
  1698. if (!setup_info) {
  1699. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  1700. return;
  1701. }
  1702. /* For STA ML VAP we do not have num links info at this point
  1703. * use MLO case always
  1704. */
  1705. if (vdev->opmode == wlan_op_mode_sta) {
  1706. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  1707. return;
  1708. }
  1709. /* For AP ML VAP consider the peer as ML only it associates with
  1710. * multiple links
  1711. */
  1712. if (setup_info->num_links == 1) {
  1713. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  1714. return;
  1715. }
  1716. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  1717. }
  1718. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1719. uint32_t *remap0,
  1720. uint32_t *remap1,
  1721. uint32_t *remap2)
  1722. {
  1723. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1724. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  1725. uint32_t reo_mlo_config =
  1726. wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
  1727. if (!be_soc->mlo_enabled)
  1728. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1729. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  1730. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
  1731. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  1732. return true;
  1733. }
  1734. #else
  1735. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  1736. struct cdp_peer_setup_info *setup_info,
  1737. enum cdp_host_reo_dest_ring *reo_dest,
  1738. bool *hash_based,
  1739. uint8_t *lmac_peer_id_msb)
  1740. {
  1741. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  1742. }
  1743. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  1744. uint32_t *remap0,
  1745. uint32_t *remap1,
  1746. uint32_t *remap2)
  1747. {
  1748. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  1749. }
  1750. #endif
  1751. #ifdef IPA_OFFLOAD
  1752. static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc)
  1753. {
  1754. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1755. return be_soc->ipa_bank_id;
  1756. }
  1757. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  1758. {
  1759. arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be;
  1760. }
  1761. #else /* !IPA_OFFLOAD */
  1762. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  1763. {
  1764. }
  1765. #endif /* IPA_OFFLOAD */
  1766. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  1767. {
  1768. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1769. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  1770. arch_ops->dp_rx_process = dp_rx_process_be;
  1771. arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
  1772. arch_ops->tx_comp_get_params_from_hal_desc =
  1773. dp_tx_comp_get_params_from_hal_desc_be;
  1774. arch_ops->dp_tx_process_htt_completion =
  1775. dp_tx_process_htt_completion_be;
  1776. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  1777. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  1778. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  1779. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  1780. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  1781. dp_wbm_get_rx_desc_from_hal_desc_be;
  1782. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
  1783. #endif
  1784. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  1785. #ifdef WIFI_MONITOR_SUPPORT
  1786. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  1787. #endif
  1788. arch_ops->dp_rx_desc_cookie_2_va =
  1789. dp_rx_desc_cookie_2_va_be;
  1790. arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
  1791. arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
  1792. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  1793. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  1794. arch_ops->txrx_soc_init = dp_soc_init_be;
  1795. arch_ops->txrx_soc_deinit = dp_soc_deinit_be;
  1796. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  1797. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  1798. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  1799. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  1800. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  1801. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  1802. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  1803. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  1804. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  1805. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  1806. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  1807. arch_ops->dp_rx_peer_metadata_peer_id_get =
  1808. dp_rx_peer_metadata_peer_id_get_be;
  1809. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  1810. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  1811. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  1812. dp_initialize_arch_ops_be_mlo(arch_ops);
  1813. arch_ops->dp_peer_rx_reorder_queue_setup =
  1814. dp_peer_rx_reorder_queue_setup_be;
  1815. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  1816. arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
  1817. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1818. arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
  1819. arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
  1820. dp_reconfig_tx_vdev_mcast_ctrl_be;
  1821. arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
  1822. #endif
  1823. #ifdef WLAN_SUPPORT_PPEDS
  1824. arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status;
  1825. arch_ops->txrx_soc_ppeds_start = dp_ppeds_start_soc_be;
  1826. arch_ops->txrx_soc_ppeds_stop = dp_ppeds_stop_soc_be;
  1827. #else
  1828. arch_ops->dp_txrx_ppeds_rings_status = NULL;
  1829. arch_ops->txrx_soc_ppeds_start = NULL;
  1830. arch_ops->txrx_soc_ppeds_stop = NULL;
  1831. #endif
  1832. dp_init_near_full_arch_ops_be(arch_ops);
  1833. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
  1834. arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
  1835. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  1836. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  1837. dp_initialize_arch_ops_be_ipa(arch_ops);
  1838. }