hal_srng.c 54 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "hal_hw_headers.h"
  20. #include "hal_api.h"
  21. #include "hal_reo.h"
  22. #include "target_type.h"
  23. #include "qdf_module.h"
  24. #include "wcss_version.h"
  25. #include <qdf_tracepoint.h>
  26. #include "qdf_ssr_driver_dump.h"
  27. struct tcl_data_cmd gtcl_data_symbol __attribute__((used));
  28. #ifdef QCA_WIFI_QCA8074
  29. void hal_qca6290_attach(struct hal_soc *hal);
  30. #endif
  31. #ifdef QCA_WIFI_QCA8074
  32. void hal_qca8074_attach(struct hal_soc *hal);
  33. #endif
  34. #if defined(QCA_WIFI_QCA8074V2) || defined(QCA_WIFI_QCA6018) || \
  35. defined(QCA_WIFI_QCA9574)
  36. void hal_qca8074v2_attach(struct hal_soc *hal);
  37. #endif
  38. #ifdef QCA_WIFI_QCA6390
  39. void hal_qca6390_attach(struct hal_soc *hal);
  40. #endif
  41. #ifdef QCA_WIFI_QCA6490
  42. void hal_qca6490_attach(struct hal_soc *hal);
  43. #endif
  44. #ifdef QCA_WIFI_QCN9000
  45. void hal_qcn9000_attach(struct hal_soc *hal);
  46. #endif
  47. #ifdef QCA_WIFI_QCN9224
  48. void hal_qcn9224v2_attach(struct hal_soc *hal);
  49. #endif
  50. #if defined(QCA_WIFI_QCN6122) || defined(QCA_WIFI_QCN9160)
  51. void hal_qcn6122_attach(struct hal_soc *hal);
  52. #endif
  53. #ifdef QCA_WIFI_QCN6432
  54. void hal_qcn6432_attach(struct hal_soc *hal);
  55. #endif
  56. #ifdef QCA_WIFI_QCA6750
  57. void hal_qca6750_attach(struct hal_soc *hal);
  58. #endif
  59. #ifdef QCA_WIFI_QCA5018
  60. void hal_qca5018_attach(struct hal_soc *hal);
  61. #endif
  62. #ifdef QCA_WIFI_QCA5332
  63. void hal_qca5332_attach(struct hal_soc *hal);
  64. #endif
  65. #ifdef QCA_WIFI_KIWI
  66. void hal_kiwi_attach(struct hal_soc *hal);
  67. #endif
  68. #ifdef ENABLE_VERBOSE_DEBUG
  69. bool is_hal_verbose_debug_enabled;
  70. #endif
  71. #define HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x4)
  72. #define HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x8)
  73. #define HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc)
  74. #define HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10)
  75. #ifdef ENABLE_HAL_REG_WR_HISTORY
  76. struct hal_reg_write_fail_history hal_reg_wr_hist;
  77. void hal_reg_wr_fail_history_add(struct hal_soc *hal_soc,
  78. uint32_t offset,
  79. uint32_t wr_val, uint32_t rd_val)
  80. {
  81. struct hal_reg_write_fail_entry *record;
  82. int idx;
  83. idx = hal_history_get_next_index(&hal_soc->reg_wr_fail_hist->index,
  84. HAL_REG_WRITE_HIST_SIZE);
  85. record = &hal_soc->reg_wr_fail_hist->record[idx];
  86. record->timestamp = qdf_get_log_timestamp();
  87. record->reg_offset = offset;
  88. record->write_val = wr_val;
  89. record->read_val = rd_val;
  90. }
  91. static void hal_reg_write_fail_history_init(struct hal_soc *hal)
  92. {
  93. hal->reg_wr_fail_hist = &hal_reg_wr_hist;
  94. qdf_atomic_set(&hal->reg_wr_fail_hist->index, -1);
  95. }
  96. #else
  97. static void hal_reg_write_fail_history_init(struct hal_soc *hal)
  98. {
  99. }
  100. #endif
  101. /**
  102. * hal_get_srng_ring_id() - get the ring id of a described ring
  103. * @hal: hal_soc data structure
  104. * @ring_type: type enum describing the ring
  105. * @ring_num: which ring of the ring type
  106. * @mac_id: which mac does the ring belong to (or 0 for non-lmac rings)
  107. *
  108. * Return: the ring id or -EINVAL if the ring does not exist.
  109. */
  110. static int hal_get_srng_ring_id(struct hal_soc *hal, int ring_type,
  111. int ring_num, int mac_id)
  112. {
  113. struct hal_hw_srng_config *ring_config =
  114. HAL_SRNG_CONFIG(hal, ring_type);
  115. int ring_id;
  116. if (ring_num >= ring_config->max_rings) {
  117. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO,
  118. "%s: ring_num exceeded maximum no. of supported rings",
  119. __func__);
  120. /* TODO: This is a programming error. Assert if this happens */
  121. return -EINVAL;
  122. }
  123. /*
  124. * Some DMAC rings share a common source ring, hence don't provide them
  125. * with separate ring IDs per LMAC.
  126. */
  127. if (ring_config->lmac_ring && !ring_config->dmac_cmn_ring) {
  128. ring_id = (ring_config->start_ring_id + ring_num +
  129. (mac_id * HAL_MAX_RINGS_PER_LMAC));
  130. } else {
  131. ring_id = ring_config->start_ring_id + ring_num;
  132. }
  133. return ring_id;
  134. }
  135. static struct hal_srng *hal_get_srng(struct hal_soc *hal, int ring_id)
  136. {
  137. /* TODO: Should we allocate srng structures dynamically? */
  138. return &(hal->srng_list[ring_id]);
  139. }
  140. #ifndef SHADOW_REG_CONFIG_DISABLED
  141. #define HP_OFFSET_IN_REG_START 1
  142. #define OFFSET_FROM_HP_TO_TP 4
  143. static void hal_update_srng_hp_tp_address(struct hal_soc *hal_soc,
  144. int shadow_config_index,
  145. int ring_type,
  146. int ring_num)
  147. {
  148. struct hal_srng *srng;
  149. int ring_id;
  150. struct hal_hw_srng_config *ring_config =
  151. HAL_SRNG_CONFIG(hal_soc, ring_type);
  152. ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, 0);
  153. if (ring_id < 0)
  154. return;
  155. srng = hal_get_srng(hal_soc, ring_id);
  156. if (ring_config->ring_dir == HAL_SRNG_DST_RING) {
  157. srng->u.dst_ring.tp_addr = SHADOW_REGISTER(shadow_config_index)
  158. + hal_soc->dev_base_addr;
  159. hal_debug("tp_addr=%pK dev base addr %pK index %u",
  160. srng->u.dst_ring.tp_addr, hal_soc->dev_base_addr,
  161. shadow_config_index);
  162. } else {
  163. srng->u.src_ring.hp_addr = SHADOW_REGISTER(shadow_config_index)
  164. + hal_soc->dev_base_addr;
  165. hal_debug("hp_addr=%pK dev base addr %pK index %u",
  166. srng->u.src_ring.hp_addr,
  167. hal_soc->dev_base_addr, shadow_config_index);
  168. }
  169. }
  170. #endif
  171. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  172. void hal_set_one_target_reg_config(struct hal_soc *hal,
  173. uint32_t target_reg_offset,
  174. int list_index)
  175. {
  176. int i = list_index;
  177. qdf_assert_always(i < MAX_GENERIC_SHADOW_REG);
  178. hal->list_shadow_reg_config[i].target_register =
  179. target_reg_offset;
  180. hal->num_generic_shadow_regs_configured++;
  181. }
  182. qdf_export_symbol(hal_set_one_target_reg_config);
  183. #define REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET 0x4
  184. #define MAX_REO_REMAP_SHADOW_REGS 4
  185. QDF_STATUS hal_set_shadow_regs(void *hal_soc)
  186. {
  187. uint32_t target_reg_offset;
  188. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  189. int i;
  190. struct hal_hw_srng_config *srng_config =
  191. &hal->hw_srng_table[WBM2SW_RELEASE];
  192. uint32_t reo_reg_base;
  193. reo_reg_base = hal_get_reo_reg_base_offset(hal_soc);
  194. target_reg_offset =
  195. HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(reo_reg_base);
  196. for (i = 0; i < MAX_REO_REMAP_SHADOW_REGS; i++) {
  197. hal_set_one_target_reg_config(hal, target_reg_offset, i);
  198. target_reg_offset += REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET;
  199. }
  200. target_reg_offset = srng_config->reg_start[HP_OFFSET_IN_REG_START];
  201. target_reg_offset += (srng_config->reg_size[HP_OFFSET_IN_REG_START]
  202. * HAL_IPA_TX_COMP_RING_IDX);
  203. hal_set_one_target_reg_config(hal, target_reg_offset, i);
  204. return QDF_STATUS_SUCCESS;
  205. }
  206. qdf_export_symbol(hal_set_shadow_regs);
  207. QDF_STATUS hal_construct_shadow_regs(void *hal_soc)
  208. {
  209. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  210. int shadow_config_index = hal->num_shadow_registers_configured;
  211. int i;
  212. int num_regs = hal->num_generic_shadow_regs_configured;
  213. for (i = 0; i < num_regs; i++) {
  214. qdf_assert_always(shadow_config_index < MAX_SHADOW_REGISTERS);
  215. hal->shadow_config[shadow_config_index].addr =
  216. hal->list_shadow_reg_config[i].target_register;
  217. hal->list_shadow_reg_config[i].shadow_config_index =
  218. shadow_config_index;
  219. hal->list_shadow_reg_config[i].va =
  220. SHADOW_REGISTER(shadow_config_index) +
  221. (uintptr_t)hal->dev_base_addr;
  222. hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x",
  223. hal->shadow_config[shadow_config_index].addr,
  224. SHADOW_REGISTER(shadow_config_index),
  225. shadow_config_index);
  226. shadow_config_index++;
  227. hal->num_shadow_registers_configured++;
  228. }
  229. return QDF_STATUS_SUCCESS;
  230. }
  231. qdf_export_symbol(hal_construct_shadow_regs);
  232. #endif
  233. #ifndef SHADOW_REG_CONFIG_DISABLED
  234. QDF_STATUS hal_set_one_shadow_config(void *hal_soc,
  235. int ring_type,
  236. int ring_num)
  237. {
  238. uint32_t target_register;
  239. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  240. struct hal_hw_srng_config *srng_config = &hal->hw_srng_table[ring_type];
  241. int shadow_config_index = hal->num_shadow_registers_configured;
  242. if (shadow_config_index >= MAX_SHADOW_REGISTERS) {
  243. QDF_ASSERT(0);
  244. return QDF_STATUS_E_RESOURCES;
  245. }
  246. hal->num_shadow_registers_configured++;
  247. target_register = srng_config->reg_start[HP_OFFSET_IN_REG_START];
  248. target_register += (srng_config->reg_size[HP_OFFSET_IN_REG_START]
  249. *ring_num);
  250. /* if the ring is a dst ring, we need to shadow the tail pointer */
  251. if (srng_config->ring_dir == HAL_SRNG_DST_RING)
  252. target_register += OFFSET_FROM_HP_TO_TP;
  253. hal->shadow_config[shadow_config_index].addr = target_register;
  254. /* update hp/tp addr in the hal_soc structure*/
  255. hal_update_srng_hp_tp_address(hal_soc, shadow_config_index, ring_type,
  256. ring_num);
  257. hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x, ring_type %d, ring num %d",
  258. target_register,
  259. SHADOW_REGISTER(shadow_config_index),
  260. shadow_config_index,
  261. ring_type, ring_num);
  262. return QDF_STATUS_SUCCESS;
  263. }
  264. qdf_export_symbol(hal_set_one_shadow_config);
  265. QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc)
  266. {
  267. int ring_type, ring_num;
  268. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  269. for (ring_type = 0; ring_type < MAX_RING_TYPES; ring_type++) {
  270. struct hal_hw_srng_config *srng_config =
  271. &hal->hw_srng_table[ring_type];
  272. if (ring_type == CE_SRC ||
  273. ring_type == CE_DST ||
  274. ring_type == CE_DST_STATUS)
  275. continue;
  276. if (srng_config->lmac_ring)
  277. continue;
  278. for (ring_num = 0; ring_num < srng_config->max_rings;
  279. ring_num++)
  280. hal_set_one_shadow_config(hal_soc, ring_type, ring_num);
  281. }
  282. return QDF_STATUS_SUCCESS;
  283. }
  284. qdf_export_symbol(hal_construct_srng_shadow_regs);
  285. #else
  286. QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc)
  287. {
  288. return QDF_STATUS_SUCCESS;
  289. }
  290. qdf_export_symbol(hal_construct_srng_shadow_regs);
  291. QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type,
  292. int ring_num)
  293. {
  294. return QDF_STATUS_SUCCESS;
  295. }
  296. qdf_export_symbol(hal_set_one_shadow_config);
  297. #endif
  298. void hal_get_shadow_config(void *hal_soc,
  299. struct pld_shadow_reg_v2_cfg **shadow_config,
  300. int *num_shadow_registers_configured)
  301. {
  302. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  303. *shadow_config = &hal->shadow_config[0].v2;
  304. *num_shadow_registers_configured =
  305. hal->num_shadow_registers_configured;
  306. }
  307. qdf_export_symbol(hal_get_shadow_config);
  308. #ifdef CONFIG_SHADOW_V3
  309. void hal_get_shadow_v3_config(void *hal_soc,
  310. struct pld_shadow_reg_v3_cfg **shadow_config,
  311. int *num_shadow_registers_configured)
  312. {
  313. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  314. *shadow_config = &hal->shadow_config[0].v3;
  315. *num_shadow_registers_configured =
  316. hal->num_shadow_registers_configured;
  317. }
  318. qdf_export_symbol(hal_get_shadow_v3_config);
  319. #endif
  320. static bool hal_validate_shadow_register(struct hal_soc *hal,
  321. uint32_t *destination,
  322. uint32_t *shadow_address)
  323. {
  324. unsigned int index;
  325. uint32_t *shadow_0_offset = SHADOW_REGISTER(0) + hal->dev_base_addr;
  326. int destination_ba_offset =
  327. ((char *)destination) - (char *)hal->dev_base_addr;
  328. index = shadow_address - shadow_0_offset;
  329. if (index >= MAX_SHADOW_REGISTERS) {
  330. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  331. "%s: index %x out of bounds", __func__, index);
  332. goto error;
  333. } else if (hal->shadow_config[index].addr != destination_ba_offset) {
  334. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  335. "%s: sanity check failure, expected %x, found %x",
  336. __func__, destination_ba_offset,
  337. hal->shadow_config[index].addr);
  338. goto error;
  339. }
  340. return true;
  341. error:
  342. qdf_print("baddr %pK, destination %pK, shadow_address %pK s0offset %pK index %x",
  343. hal->dev_base_addr, destination, shadow_address,
  344. shadow_0_offset, index);
  345. QDF_BUG(0);
  346. return false;
  347. }
  348. static void hal_target_based_configure(struct hal_soc *hal)
  349. {
  350. /*
  351. * Indicate Initialization of srngs to avoid force wake
  352. * as umac power collapse is not enabled yet
  353. */
  354. hal->init_phase = true;
  355. switch (hal->target_type) {
  356. #ifdef QCA_WIFI_QCA6290
  357. case TARGET_TYPE_QCA6290:
  358. hal->use_register_windowing = true;
  359. hal_qca6290_attach(hal);
  360. break;
  361. #endif
  362. #ifdef QCA_WIFI_QCA6390
  363. case TARGET_TYPE_QCA6390:
  364. hal->use_register_windowing = true;
  365. hal_qca6390_attach(hal);
  366. break;
  367. #endif
  368. #ifdef QCA_WIFI_QCA6490
  369. case TARGET_TYPE_QCA6490:
  370. hal->use_register_windowing = true;
  371. hal_qca6490_attach(hal);
  372. break;
  373. #endif
  374. #ifdef QCA_WIFI_QCA6750
  375. case TARGET_TYPE_QCA6750:
  376. hal->use_register_windowing = true;
  377. hal->static_window_map = true;
  378. hal_qca6750_attach(hal);
  379. break;
  380. #endif
  381. #ifdef QCA_WIFI_KIWI
  382. case TARGET_TYPE_KIWI:
  383. case TARGET_TYPE_MANGO:
  384. case TARGET_TYPE_PEACH:
  385. hal->use_register_windowing = true;
  386. hal_kiwi_attach(hal);
  387. break;
  388. #endif
  389. #if defined(QCA_WIFI_QCA8074) && defined(WIFI_TARGET_TYPE_3_0)
  390. case TARGET_TYPE_QCA8074:
  391. hal_qca8074_attach(hal);
  392. break;
  393. #endif
  394. #if defined(QCA_WIFI_QCA8074V2)
  395. case TARGET_TYPE_QCA8074V2:
  396. hal_qca8074v2_attach(hal);
  397. break;
  398. #endif
  399. #if defined(QCA_WIFI_QCA6018)
  400. case TARGET_TYPE_QCA6018:
  401. hal_qca8074v2_attach(hal);
  402. break;
  403. #endif
  404. #if defined(QCA_WIFI_QCA9574)
  405. case TARGET_TYPE_QCA9574:
  406. hal_qca8074v2_attach(hal);
  407. break;
  408. #endif
  409. #if defined(QCA_WIFI_QCN6122)
  410. case TARGET_TYPE_QCN6122:
  411. hal->use_register_windowing = true;
  412. /*
  413. * Static window map is enabled for qcn9000 to use 2mb bar
  414. * size and use multiple windows to write into registers.
  415. */
  416. hal->static_window_map = true;
  417. hal_qcn6122_attach(hal);
  418. break;
  419. #endif
  420. #if defined(QCA_WIFI_QCN9160)
  421. case TARGET_TYPE_QCN9160:
  422. hal->use_register_windowing = true;
  423. /*
  424. * Static window map is enabled for qcn9160 to use 2mb bar
  425. * size and use multiple windows to write into registers.
  426. */
  427. hal->static_window_map = true;
  428. hal_qcn6122_attach(hal);
  429. break;
  430. #endif
  431. #if defined(QCA_WIFI_QCN6432)
  432. case TARGET_TYPE_QCN6432:
  433. hal->use_register_windowing = true;
  434. /*
  435. * Static window map is enabled for qcn6432 to use 2mb bar
  436. * size and use multiple windows to write into registers.
  437. */
  438. hal->static_window_map = true;
  439. hal_qcn6432_attach(hal);
  440. break;
  441. #endif
  442. #ifdef QCA_WIFI_QCN9000
  443. case TARGET_TYPE_QCN9000:
  444. hal->use_register_windowing = true;
  445. /*
  446. * Static window map is enabled for qcn9000 to use 2mb bar
  447. * size and use multiple windows to write into registers.
  448. */
  449. hal->static_window_map = true;
  450. hal_qcn9000_attach(hal);
  451. break;
  452. #endif
  453. #ifdef QCA_WIFI_QCA5018
  454. case TARGET_TYPE_QCA5018:
  455. hal->use_register_windowing = true;
  456. hal->static_window_map = true;
  457. hal_qca5018_attach(hal);
  458. break;
  459. #endif
  460. #ifdef QCA_WIFI_QCN9224
  461. case TARGET_TYPE_QCN9224:
  462. hal->use_register_windowing = true;
  463. hal->static_window_map = true;
  464. if (hal->version == 1)
  465. qdf_assert_always(0);
  466. else
  467. hal_qcn9224v2_attach(hal);
  468. break;
  469. #endif
  470. #ifdef QCA_WIFI_QCA5332
  471. case TARGET_TYPE_QCA5332:
  472. hal->use_register_windowing = true;
  473. hal->static_window_map = true;
  474. hal_qca5332_attach(hal);
  475. break;
  476. #endif
  477. #ifdef QCA_WIFI_WCN6450
  478. case TARGET_TYPE_WCN6450:
  479. hal->use_register_windowing = true;
  480. hal->static_window_map = true;
  481. hal_wcn6450_attach(hal);
  482. break;
  483. #endif
  484. default:
  485. break;
  486. }
  487. }
  488. uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl)
  489. {
  490. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  491. struct hif_target_info *tgt_info =
  492. hif_get_target_info_handle(hal_soc->hif_handle);
  493. return tgt_info->target_type;
  494. }
  495. qdf_export_symbol(hal_get_target_type);
  496. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  497. /**
  498. * hal_is_reg_write_tput_level_high() - throughput level for delayed reg writes
  499. * @hal: hal_soc pointer
  500. *
  501. * Return: true if throughput is high, else false.
  502. */
  503. static inline bool hal_is_reg_write_tput_level_high(struct hal_soc *hal)
  504. {
  505. int bw_level = hif_get_bandwidth_level(hal->hif_handle);
  506. return (bw_level >= PLD_BUS_WIDTH_MEDIUM) ? true : false;
  507. }
  508. static inline
  509. char *hal_fill_reg_write_srng_stats(struct hal_srng *srng,
  510. char *buf, qdf_size_t size)
  511. {
  512. qdf_scnprintf(buf, size, "enq %u deq %u coal %u direct %u",
  513. srng->wstats.enqueues, srng->wstats.dequeues,
  514. srng->wstats.coalesces, srng->wstats.direct);
  515. return buf;
  516. }
  517. /* bytes for local buffer */
  518. #define HAL_REG_WRITE_SRNG_STATS_LEN 100
  519. #ifndef WLAN_SOFTUMAC_SUPPORT
  520. void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
  521. {
  522. struct hal_srng *srng;
  523. char buf[HAL_REG_WRITE_SRNG_STATS_LEN];
  524. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  525. srng = hal_get_srng(hal, HAL_SRNG_SW2TCL1);
  526. hal_debug("SW2TCL1: %s",
  527. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  528. srng = hal_get_srng(hal, HAL_SRNG_WBM2SW0_RELEASE);
  529. hal_debug("WBM2SW0: %s",
  530. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  531. srng = hal_get_srng(hal, HAL_SRNG_REO2SW1);
  532. hal_debug("REO2SW1: %s",
  533. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  534. srng = hal_get_srng(hal, HAL_SRNG_REO2SW2);
  535. hal_debug("REO2SW2: %s",
  536. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  537. srng = hal_get_srng(hal, HAL_SRNG_REO2SW3);
  538. hal_debug("REO2SW3: %s",
  539. hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
  540. }
  541. #else
  542. void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
  543. {
  544. }
  545. #endif
  546. void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl)
  547. {
  548. uint32_t *hist;
  549. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  550. hist = hal->stats.wstats.sched_delay;
  551. hal_debug("wstats: enq %u deq %u coal %u direct %u q_depth %u max_q %u sched-delay hist %u %u %u %u",
  552. qdf_atomic_read(&hal->stats.wstats.enqueues),
  553. hal->stats.wstats.dequeues,
  554. qdf_atomic_read(&hal->stats.wstats.coalesces),
  555. qdf_atomic_read(&hal->stats.wstats.direct),
  556. qdf_atomic_read(&hal->stats.wstats.q_depth),
  557. hal->stats.wstats.max_q_depth,
  558. hist[REG_WRITE_SCHED_DELAY_SUB_100us],
  559. hist[REG_WRITE_SCHED_DELAY_SUB_1000us],
  560. hist[REG_WRITE_SCHED_DELAY_SUB_5000us],
  561. hist[REG_WRITE_SCHED_DELAY_GT_5000us]);
  562. }
  563. int hal_get_reg_write_pending_work(void *hal_soc)
  564. {
  565. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  566. return qdf_atomic_read(&hal->active_work_cnt);
  567. }
  568. #endif
  569. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  570. #ifdef MEMORY_DEBUG
  571. /*
  572. * Length of the queue(array) used to hold delayed register writes.
  573. * Must be a multiple of 2.
  574. */
  575. #define HAL_REG_WRITE_QUEUE_LEN 128
  576. #else
  577. #define HAL_REG_WRITE_QUEUE_LEN 32
  578. #endif
  579. /**
  580. * hal_process_reg_write_q_elem() - process a register write queue element
  581. * @hal: hal_soc pointer
  582. * @q_elem: pointer to hal register write queue element
  583. *
  584. * Return: The value which was written to the address
  585. */
  586. static uint32_t
  587. hal_process_reg_write_q_elem(struct hal_soc *hal,
  588. struct hal_reg_write_q_elem *q_elem)
  589. {
  590. struct hal_srng *srng = q_elem->srng;
  591. uint32_t write_val;
  592. SRNG_LOCK(&srng->lock);
  593. srng->reg_write_in_progress = false;
  594. srng->wstats.dequeues++;
  595. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  596. q_elem->dequeue_val = srng->u.src_ring.hp;
  597. hal_write_address_32_mb(hal,
  598. srng->u.src_ring.hp_addr,
  599. srng->u.src_ring.hp, false);
  600. write_val = srng->u.src_ring.hp;
  601. } else {
  602. q_elem->dequeue_val = srng->u.dst_ring.tp;
  603. hal_write_address_32_mb(hal,
  604. srng->u.dst_ring.tp_addr,
  605. srng->u.dst_ring.tp, false);
  606. write_val = srng->u.dst_ring.tp;
  607. }
  608. hal_srng_reg_his_add(srng, write_val);
  609. q_elem->valid = 0;
  610. srng->last_dequeue_time = q_elem->dequeue_time;
  611. SRNG_UNLOCK(&srng->lock);
  612. return write_val;
  613. }
  614. /**
  615. * hal_reg_write_fill_sched_delay_hist() - fill reg write delay histogram in hal
  616. * @hal: hal_soc pointer
  617. * @delay_us: delay in us
  618. *
  619. * Return: None
  620. */
  621. static inline void hal_reg_write_fill_sched_delay_hist(struct hal_soc *hal,
  622. uint64_t delay_us)
  623. {
  624. uint32_t *hist;
  625. hist = hal->stats.wstats.sched_delay;
  626. if (delay_us < 100)
  627. hist[REG_WRITE_SCHED_DELAY_SUB_100us]++;
  628. else if (delay_us < 1000)
  629. hist[REG_WRITE_SCHED_DELAY_SUB_1000us]++;
  630. else if (delay_us < 5000)
  631. hist[REG_WRITE_SCHED_DELAY_SUB_5000us]++;
  632. else
  633. hist[REG_WRITE_SCHED_DELAY_GT_5000us]++;
  634. }
  635. #ifdef SHADOW_WRITE_DELAY
  636. #define SHADOW_WRITE_MIN_DELTA_US 5
  637. #define SHADOW_WRITE_DELAY_US 50
  638. /*
  639. * Never add those srngs which are performance relate.
  640. * The delay itself will hit performance heavily.
  641. */
  642. #define IS_SRNG_MATCH(s) ((s)->ring_id == HAL_SRNG_CE_1_DST_STATUS || \
  643. (s)->ring_id == HAL_SRNG_CE_1_DST)
  644. static inline bool hal_reg_write_need_delay(struct hal_reg_write_q_elem *elem)
  645. {
  646. struct hal_srng *srng = elem->srng;
  647. struct hal_soc *hal;
  648. qdf_time_t now;
  649. qdf_iomem_t real_addr;
  650. if (qdf_unlikely(!srng))
  651. return false;
  652. hal = srng->hal_soc;
  653. if (qdf_unlikely(!hal))
  654. return false;
  655. /* Check if it is target srng, and valid shadow reg */
  656. if (qdf_likely(!IS_SRNG_MATCH(srng)))
  657. return false;
  658. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  659. real_addr = SRNG_SRC_ADDR(srng, HP);
  660. else
  661. real_addr = SRNG_DST_ADDR(srng, TP);
  662. if (!hal_validate_shadow_register(hal, real_addr, elem->addr))
  663. return false;
  664. /* Check the time delta from last write of same srng */
  665. now = qdf_get_log_timestamp();
  666. if (qdf_log_timestamp_to_usecs(now - srng->last_dequeue_time) >
  667. SHADOW_WRITE_MIN_DELTA_US)
  668. return false;
  669. /* Delay dequeue, and record */
  670. qdf_udelay(SHADOW_WRITE_DELAY_US);
  671. srng->wstats.dequeue_delay++;
  672. hal->stats.wstats.dequeue_delay++;
  673. return true;
  674. }
  675. #else
  676. static inline bool hal_reg_write_need_delay(struct hal_reg_write_q_elem *elem)
  677. {
  678. return false;
  679. }
  680. #endif
  681. /**
  682. * hal_reg_write_work() - Worker to process delayed writes
  683. * @arg: hal_soc pointer
  684. *
  685. * Return: None
  686. */
  687. static void hal_reg_write_work(void *arg)
  688. {
  689. int32_t q_depth, write_val;
  690. struct hal_soc *hal = arg;
  691. struct hal_reg_write_q_elem *q_elem;
  692. uint64_t delta_us;
  693. uint8_t ring_id;
  694. uint32_t *addr;
  695. uint32_t num_processed = 0;
  696. q_elem = &hal->reg_write_queue[(hal->read_idx)];
  697. q_elem->work_scheduled_time = qdf_get_log_timestamp();
  698. q_elem->cpu_id = qdf_get_cpu();
  699. /* Make sure q_elem consistent in the memory for multi-cores */
  700. qdf_rmb();
  701. if (!q_elem->valid)
  702. return;
  703. q_depth = qdf_atomic_read(&hal->stats.wstats.q_depth);
  704. if (q_depth > hal->stats.wstats.max_q_depth)
  705. hal->stats.wstats.max_q_depth = q_depth;
  706. if (hif_prevent_link_low_power_states(hal->hif_handle)) {
  707. hal->stats.wstats.prevent_l1_fails++;
  708. return;
  709. }
  710. while (true) {
  711. qdf_rmb();
  712. if (!q_elem->valid)
  713. break;
  714. q_elem->dequeue_time = qdf_get_log_timestamp();
  715. ring_id = q_elem->srng->ring_id;
  716. addr = q_elem->addr;
  717. delta_us = qdf_log_timestamp_to_usecs(q_elem->dequeue_time -
  718. q_elem->enqueue_time);
  719. hal_reg_write_fill_sched_delay_hist(hal, delta_us);
  720. hal->stats.wstats.dequeues++;
  721. qdf_atomic_dec(&hal->stats.wstats.q_depth);
  722. if (hal_reg_write_need_delay(q_elem))
  723. hal_verbose_debug("Delay reg writer for srng 0x%x, addr 0x%pK",
  724. q_elem->srng->ring_id, q_elem->addr);
  725. write_val = hal_process_reg_write_q_elem(hal, q_elem);
  726. hal_verbose_debug("read_idx %u srng 0x%x, addr 0x%pK dequeue_val %u sched delay %llu us",
  727. hal->read_idx, ring_id, addr, write_val, delta_us);
  728. qdf_trace_dp_del_reg_write(ring_id, q_elem->enqueue_val,
  729. q_elem->dequeue_val,
  730. q_elem->enqueue_time,
  731. q_elem->dequeue_time);
  732. num_processed++;
  733. hal->read_idx = (hal->read_idx + 1) &
  734. (HAL_REG_WRITE_QUEUE_LEN - 1);
  735. q_elem = &hal->reg_write_queue[(hal->read_idx)];
  736. }
  737. hif_allow_link_low_power_states(hal->hif_handle);
  738. /*
  739. * Decrement active_work_cnt by the number of elements dequeued after
  740. * hif_allow_link_low_power_states.
  741. * This makes sure that hif_try_complete_tasks will wait till we make
  742. * the bus access in hif_allow_link_low_power_states. This will avoid
  743. * race condition between delayed register worker and bus suspend
  744. * (system suspend or runtime suspend).
  745. *
  746. * The following decrement should be done at the end!
  747. */
  748. qdf_atomic_sub(num_processed, &hal->active_work_cnt);
  749. }
  750. static void __hal_flush_reg_write_work(struct hal_soc *hal)
  751. {
  752. qdf_flush_work(&hal->reg_write_work);
  753. qdf_disable_work(&hal->reg_write_work);
  754. }
  755. void hal_flush_reg_write_work(hal_soc_handle_t hal_handle)
  756. { __hal_flush_reg_write_work((struct hal_soc *)hal_handle);
  757. }
  758. /**
  759. * hal_reg_write_enqueue() - enqueue register writes into kworker
  760. * @hal_soc: hal_soc pointer
  761. * @srng: srng pointer
  762. * @addr: iomem address of register
  763. * @value: value to be written to iomem address
  764. *
  765. * This function executes from within the SRNG LOCK
  766. *
  767. * Return: None
  768. */
  769. static void hal_reg_write_enqueue(struct hal_soc *hal_soc,
  770. struct hal_srng *srng,
  771. void __iomem *addr,
  772. uint32_t value)
  773. {
  774. struct hal_reg_write_q_elem *q_elem;
  775. uint32_t write_idx;
  776. if (srng->reg_write_in_progress) {
  777. hal_verbose_debug("Already in progress srng ring id 0x%x addr 0x%pK val %u",
  778. srng->ring_id, addr, value);
  779. qdf_atomic_inc(&hal_soc->stats.wstats.coalesces);
  780. srng->wstats.coalesces++;
  781. return;
  782. }
  783. write_idx = qdf_atomic_inc_return(&hal_soc->write_idx);
  784. write_idx = write_idx & (HAL_REG_WRITE_QUEUE_LEN - 1);
  785. q_elem = &hal_soc->reg_write_queue[write_idx];
  786. if (q_elem->valid) {
  787. hal_err("queue full");
  788. QDF_BUG(0);
  789. return;
  790. }
  791. qdf_atomic_inc(&hal_soc->stats.wstats.enqueues);
  792. srng->wstats.enqueues++;
  793. qdf_atomic_inc(&hal_soc->stats.wstats.q_depth);
  794. q_elem->srng = srng;
  795. q_elem->addr = addr;
  796. q_elem->enqueue_val = value;
  797. q_elem->enqueue_time = qdf_get_log_timestamp();
  798. /*
  799. * Before the valid flag is set to true, all the other
  800. * fields in the q_elem needs to be updated in memory.
  801. * Else there is a chance that the dequeuing worker thread
  802. * might read stale entries and process incorrect srng.
  803. */
  804. qdf_wmb();
  805. q_elem->valid = true;
  806. /*
  807. * After all other fields in the q_elem has been updated
  808. * in memory successfully, the valid flag needs to be updated
  809. * in memory in time too.
  810. * Else there is a chance that the dequeuing worker thread
  811. * might read stale valid flag and the work will be bypassed
  812. * for this round. And if there is no other work scheduled
  813. * later, this hal register writing won't be updated any more.
  814. */
  815. qdf_wmb();
  816. srng->reg_write_in_progress = true;
  817. qdf_atomic_inc(&hal_soc->active_work_cnt);
  818. hal_verbose_debug("write_idx %u srng ring id 0x%x addr 0x%pK val %u",
  819. write_idx, srng->ring_id, addr, value);
  820. qdf_queue_work(hal_soc->qdf_dev, hal_soc->reg_write_wq,
  821. &hal_soc->reg_write_work);
  822. }
  823. /**
  824. * hal_delayed_reg_write_init() - Initialization function for delayed reg writes
  825. * @hal: hal_soc pointer
  826. *
  827. * Initialize main data structures to process register writes in a delayed
  828. * workqueue.
  829. *
  830. * Return: QDF_STATUS_SUCCESS on success else a QDF error.
  831. */
  832. static QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal)
  833. {
  834. hal->reg_write_wq =
  835. qdf_alloc_high_prior_ordered_workqueue("hal_register_write_wq");
  836. qdf_create_work(0, &hal->reg_write_work, hal_reg_write_work, hal);
  837. hal->reg_write_queue = qdf_mem_malloc(HAL_REG_WRITE_QUEUE_LEN *
  838. sizeof(*hal->reg_write_queue));
  839. if (!hal->reg_write_queue) {
  840. hal_err("unable to allocate memory");
  841. QDF_BUG(0);
  842. return QDF_STATUS_E_NOMEM;
  843. }
  844. /* Initial value of indices */
  845. hal->read_idx = 0;
  846. qdf_atomic_set(&hal->write_idx, -1);
  847. return QDF_STATUS_SUCCESS;
  848. }
  849. /**
  850. * hal_delayed_reg_write_deinit() - De-Initialize delayed reg write processing
  851. * @hal: hal_soc pointer
  852. *
  853. * De-initialize main data structures to process register writes in a delayed
  854. * workqueue.
  855. *
  856. * Return: None
  857. */
  858. static void hal_delayed_reg_write_deinit(struct hal_soc *hal)
  859. {
  860. __hal_flush_reg_write_work(hal);
  861. qdf_flush_workqueue(0, hal->reg_write_wq);
  862. qdf_destroy_workqueue(0, hal->reg_write_wq);
  863. qdf_mem_free(hal->reg_write_queue);
  864. }
  865. #else
  866. static inline QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal)
  867. {
  868. return QDF_STATUS_SUCCESS;
  869. }
  870. static inline void hal_delayed_reg_write_deinit(struct hal_soc *hal)
  871. {
  872. }
  873. #endif
  874. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  875. #ifdef HAL_RECORD_SUSPEND_WRITE
  876. static struct hal_suspend_write_history
  877. g_hal_suspend_write_history[HAL_SUSPEND_WRITE_HISTORY_MAX];
  878. static
  879. void hal_event_suspend_record(uint8_t ring_id, uint32_t value, uint32_t count)
  880. {
  881. uint32_t index = qdf_atomic_read(g_hal_suspend_write_history.index) &
  882. (HAL_SUSPEND_WRITE_HISTORY_MAX - 1);
  883. struct hal_suspend_write_record *cur_event =
  884. &hal_suspend_write_event.record[index];
  885. cur_event->ts = qdf_get_log_timestamp();
  886. cur_event->ring_id = ring_id;
  887. cur_event->value = value;
  888. cur_event->direct_wcount = count;
  889. qdf_atomic_inc(g_hal_suspend_write_history.index);
  890. }
  891. static inline
  892. void hal_record_suspend_write(uint8_t ring_id, uint32_t value, uint32_t count)
  893. {
  894. if (hif_rtpm_get_state() >= HIF_RTPM_STATE_SUSPENDING)
  895. hal_event_suspend_record(ring_id, value, count);
  896. }
  897. #else
  898. static inline
  899. void hal_record_suspend_write(uint8_t ring_id, uint32_t value, uint32_t count)
  900. {
  901. }
  902. #endif
  903. #ifdef QCA_WIFI_QCA6750
  904. void hal_delayed_reg_write(struct hal_soc *hal_soc,
  905. struct hal_srng *srng,
  906. void __iomem *addr,
  907. uint32_t value)
  908. {
  909. uint8_t vote_access;
  910. switch (srng->ring_type) {
  911. case CE_SRC:
  912. case CE_DST:
  913. case CE_DST_STATUS:
  914. vote_access = hif_get_ep_vote_access(hal_soc->hif_handle,
  915. HIF_EP_VOTE_NONDP_ACCESS);
  916. if ((vote_access == HIF_EP_VOTE_ACCESS_DISABLE) ||
  917. (vote_access == HIF_EP_VOTE_INTERMEDIATE_ACCESS &&
  918. PLD_MHI_STATE_L0 ==
  919. pld_get_mhi_state(hal_soc->qdf_dev->dev))) {
  920. hal_write_address_32_mb(hal_soc, addr, value, false);
  921. hal_srng_reg_his_add(srng, value);
  922. qdf_atomic_inc(&hal_soc->stats.wstats.direct);
  923. srng->wstats.direct++;
  924. } else {
  925. hal_reg_write_enqueue(hal_soc, srng, addr, value);
  926. }
  927. break;
  928. default:
  929. if (hif_get_ep_vote_access(hal_soc->hif_handle,
  930. HIF_EP_VOTE_DP_ACCESS) ==
  931. HIF_EP_VOTE_ACCESS_DISABLE ||
  932. hal_is_reg_write_tput_level_high(hal_soc) ||
  933. PLD_MHI_STATE_L0 ==
  934. pld_get_mhi_state(hal_soc->qdf_dev->dev)) {
  935. hal_write_address_32_mb(hal_soc, addr, value, false);
  936. hal_srng_reg_his_add(srng, value);
  937. qdf_atomic_inc(&hal_soc->stats.wstats.direct);
  938. srng->wstats.direct++;
  939. } else {
  940. hal_reg_write_enqueue(hal_soc, srng, addr, value);
  941. }
  942. break;
  943. }
  944. }
  945. #else
  946. void hal_delayed_reg_write(struct hal_soc *hal_soc,
  947. struct hal_srng *srng,
  948. void __iomem *addr,
  949. uint32_t value)
  950. {
  951. if (hal_is_reg_write_tput_level_high(hal_soc) ||
  952. pld_is_device_awake(hal_soc->qdf_dev->dev)) {
  953. qdf_atomic_inc(&hal_soc->stats.wstats.direct);
  954. srng->wstats.direct++;
  955. hal_write_address_32_mb(hal_soc, addr, value, false);
  956. hal_srng_reg_his_add(srng, value);
  957. } else {
  958. hal_reg_write_enqueue(hal_soc, srng, addr, value);
  959. }
  960. hal_record_suspend_write(srng->ring_id, value, srng->wstats.direct);
  961. }
  962. #endif
  963. #endif
  964. void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev)
  965. {
  966. struct hal_soc *hal;
  967. int i;
  968. hal = qdf_mem_common_alloc(sizeof(*hal));
  969. if (!hal) {
  970. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  971. "%s: hal_soc allocation failed", __func__);
  972. goto fail0;
  973. }
  974. hal->hif_handle = hif_handle;
  975. hal->dev_base_addr = hif_get_dev_ba(hif_handle); /* UMAC */
  976. hal->dev_base_addr_ce = hif_get_dev_ba_ce(hif_handle); /* CE */
  977. hal->dev_base_addr_cmem = hif_get_dev_ba_cmem(hif_handle); /* CMEM */
  978. hal->dev_base_addr_pmm = hif_get_dev_ba_pmm(hif_handle); /* PMM */
  979. hal->qdf_dev = qdf_dev;
  980. hal->shadow_rdptr_mem_vaddr = (uint32_t *)qdf_mem_alloc_consistent(
  981. qdf_dev, qdf_dev->dev, sizeof(*(hal->shadow_rdptr_mem_vaddr)) *
  982. HAL_SRNG_ID_MAX, &(hal->shadow_rdptr_mem_paddr));
  983. if (!hal->shadow_rdptr_mem_paddr) {
  984. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  985. "%s: hal->shadow_rdptr_mem_paddr allocation failed",
  986. __func__);
  987. goto fail1;
  988. }
  989. qdf_mem_zero(hal->shadow_rdptr_mem_vaddr,
  990. sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX);
  991. hal->shadow_wrptr_mem_vaddr =
  992. (uint32_t *)qdf_mem_alloc_consistent(qdf_dev, qdf_dev->dev,
  993. sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS,
  994. &(hal->shadow_wrptr_mem_paddr));
  995. if (!hal->shadow_wrptr_mem_vaddr) {
  996. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  997. "%s: hal->shadow_wrptr_mem_vaddr allocation failed",
  998. __func__);
  999. goto fail2;
  1000. }
  1001. qdf_mem_zero(hal->shadow_wrptr_mem_vaddr,
  1002. sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS);
  1003. for (i = 0; i < HAL_SRNG_ID_MAX; i++) {
  1004. hal->srng_list[i].initialized = 0;
  1005. hal->srng_list[i].ring_id = i;
  1006. }
  1007. qdf_spinlock_create(&hal->register_access_lock);
  1008. hal->register_window = 0;
  1009. hal->target_type = hal_get_target_type(hal_soc_to_hal_soc_handle(hal));
  1010. hal->version = hif_get_soc_version(hif_handle);
  1011. hal->ops = qdf_mem_malloc(sizeof(*hal->ops));
  1012. if (!hal->ops) {
  1013. hal_err("unable to allocable memory for HAL ops");
  1014. goto fail3;
  1015. }
  1016. hal_target_based_configure(hal);
  1017. hal_reg_write_fail_history_init(hal);
  1018. qdf_minidump_log(hal, sizeof(*hal), "hal_soc");
  1019. qdf_ssr_driver_dump_register_region("hal_soc", hal, sizeof(*hal));
  1020. qdf_atomic_init(&hal->active_work_cnt);
  1021. if (hal_delayed_reg_write_init(hal) != QDF_STATUS_SUCCESS) {
  1022. hal_err("unable to initialize delayed reg write");
  1023. goto fail4;
  1024. }
  1025. hif_rtpm_register(HIF_RTPM_ID_HAL_REO_CMD, NULL);
  1026. return (void *)hal;
  1027. fail4:
  1028. qdf_ssr_driver_dump_unregister_region("hal_soc");
  1029. qdf_minidump_remove(hal, sizeof(*hal), "hal_soc");
  1030. qdf_mem_free(hal->ops);
  1031. fail3:
  1032. qdf_mem_free_consistent(qdf_dev, qdf_dev->dev,
  1033. sizeof(*hal->shadow_wrptr_mem_vaddr) *
  1034. HAL_MAX_LMAC_RINGS,
  1035. hal->shadow_wrptr_mem_vaddr,
  1036. hal->shadow_wrptr_mem_paddr, 0);
  1037. fail2:
  1038. qdf_mem_free_consistent(qdf_dev, qdf_dev->dev,
  1039. sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX,
  1040. hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0);
  1041. fail1:
  1042. qdf_mem_common_free(hal);
  1043. fail0:
  1044. return NULL;
  1045. }
  1046. qdf_export_symbol(hal_attach);
  1047. void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem)
  1048. {
  1049. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  1050. mem->dev_base_addr = (void *)hal->dev_base_addr;
  1051. mem->shadow_rdptr_mem_vaddr = (void *)hal->shadow_rdptr_mem_vaddr;
  1052. mem->shadow_wrptr_mem_vaddr = (void *)hal->shadow_wrptr_mem_vaddr;
  1053. mem->shadow_rdptr_mem_paddr = (void *)hal->shadow_rdptr_mem_paddr;
  1054. mem->shadow_wrptr_mem_paddr = (void *)hal->shadow_wrptr_mem_paddr;
  1055. hif_read_phy_mem_base((void *)hal->hif_handle,
  1056. (qdf_dma_addr_t *)&mem->dev_base_paddr);
  1057. mem->lmac_srng_start_id = HAL_SRNG_LMAC1_ID_START;
  1058. return;
  1059. }
  1060. qdf_export_symbol(hal_get_meminfo);
  1061. void hal_detach(void *hal_soc)
  1062. {
  1063. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1064. hif_rtpm_deregister(HIF_RTPM_ID_HAL_REO_CMD);
  1065. hal_delayed_reg_write_deinit(hal);
  1066. hal_reo_shared_qaddr_detach((hal_soc_handle_t)hal);
  1067. qdf_ssr_driver_dump_unregister_region("hal_soc");
  1068. qdf_minidump_remove(hal, sizeof(*hal), "hal_soc");
  1069. qdf_mem_free(hal->ops);
  1070. qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev,
  1071. sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX,
  1072. hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0);
  1073. qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev,
  1074. sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS,
  1075. hal->shadow_wrptr_mem_vaddr, hal->shadow_wrptr_mem_paddr, 0);
  1076. qdf_mem_common_free(hal);
  1077. return;
  1078. }
  1079. qdf_export_symbol(hal_detach);
  1080. #define HAL_CE_CHANNEL_DST_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
  1081. #define HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0x0000ffff
  1082. #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
  1083. #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
  1084. /**
  1085. * hal_ce_dst_setup() - Initialize CE destination ring registers
  1086. * @hal: HAL SOC handle
  1087. * @srng: SRNG ring pointer
  1088. * @ring_num: ring number
  1089. */
  1090. static inline void hal_ce_dst_setup(struct hal_soc *hal, struct hal_srng *srng,
  1091. int ring_num)
  1092. {
  1093. uint32_t reg_val = 0;
  1094. uint32_t reg_addr;
  1095. struct hal_hw_srng_config *ring_config =
  1096. HAL_SRNG_CONFIG(hal, CE_DST);
  1097. /* set DEST_MAX_LENGTH according to ce assignment */
  1098. reg_addr = HAL_CE_CHANNEL_DST_DEST_CTRL_ADDR(
  1099. ring_config->reg_start[R0_INDEX] +
  1100. (ring_num * ring_config->reg_size[R0_INDEX]));
  1101. reg_val = HAL_REG_READ(hal, reg_addr);
  1102. reg_val &= ~HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK;
  1103. reg_val |= srng->u.dst_ring.max_buffer_length &
  1104. HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK;
  1105. HAL_REG_WRITE(hal, reg_addr, reg_val);
  1106. if (srng->prefetch_timer) {
  1107. reg_addr = HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(
  1108. ring_config->reg_start[R0_INDEX] +
  1109. (ring_num * ring_config->reg_size[R0_INDEX]));
  1110. reg_val = HAL_REG_READ(hal, reg_addr);
  1111. reg_val &= ~HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK;
  1112. reg_val |= srng->prefetch_timer;
  1113. HAL_REG_WRITE(hal, reg_addr, reg_val);
  1114. reg_val = HAL_REG_READ(hal, reg_addr);
  1115. }
  1116. }
  1117. void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read,
  1118. uint32_t *ix0, uint32_t *ix1,
  1119. uint32_t *ix2, uint32_t *ix3)
  1120. {
  1121. uint32_t reg_offset;
  1122. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  1123. uint32_t reo_reg_base;
  1124. reo_reg_base = hal_get_reo_reg_base_offset(hal_soc_hdl);
  1125. if (read) {
  1126. if (ix0) {
  1127. reg_offset =
  1128. HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(
  1129. reo_reg_base);
  1130. *ix0 = HAL_REG_READ(hal, reg_offset);
  1131. }
  1132. if (ix1) {
  1133. reg_offset =
  1134. HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR(
  1135. reo_reg_base);
  1136. *ix1 = HAL_REG_READ(hal, reg_offset);
  1137. }
  1138. if (ix2) {
  1139. reg_offset =
  1140. HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR(
  1141. reo_reg_base);
  1142. *ix2 = HAL_REG_READ(hal, reg_offset);
  1143. }
  1144. if (ix3) {
  1145. reg_offset =
  1146. HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR(
  1147. reo_reg_base);
  1148. *ix3 = HAL_REG_READ(hal, reg_offset);
  1149. }
  1150. } else {
  1151. if (ix0) {
  1152. reg_offset =
  1153. HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(
  1154. reo_reg_base);
  1155. HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset,
  1156. *ix0, true);
  1157. }
  1158. if (ix1) {
  1159. reg_offset =
  1160. HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR(
  1161. reo_reg_base);
  1162. HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset,
  1163. *ix1, true);
  1164. }
  1165. if (ix2) {
  1166. reg_offset =
  1167. HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR(
  1168. reo_reg_base);
  1169. HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset,
  1170. *ix2, true);
  1171. }
  1172. if (ix3) {
  1173. reg_offset =
  1174. HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR(
  1175. reo_reg_base);
  1176. HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset,
  1177. *ix3, true);
  1178. }
  1179. }
  1180. }
  1181. qdf_export_symbol(hal_reo_read_write_ctrl_ix);
  1182. void hal_srng_dst_set_hp_paddr_confirm(struct hal_srng *srng, uint64_t paddr)
  1183. {
  1184. SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_LSB, paddr & 0xffffffff);
  1185. SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_MSB, paddr >> 32);
  1186. }
  1187. qdf_export_symbol(hal_srng_dst_set_hp_paddr_confirm);
  1188. void hal_srng_dst_init_hp(struct hal_soc_handle *hal_soc,
  1189. struct hal_srng *srng,
  1190. uint32_t *vaddr)
  1191. {
  1192. uint32_t reg_offset;
  1193. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1194. if (!srng)
  1195. return;
  1196. srng->u.dst_ring.hp_addr = vaddr;
  1197. reg_offset = SRNG_DST_ADDR(srng, HP) - hal->dev_base_addr;
  1198. HAL_REG_WRITE_CONFIRM_RETRY(
  1199. hal, reg_offset, srng->u.dst_ring.cached_hp, true);
  1200. if (vaddr) {
  1201. *srng->u.dst_ring.hp_addr = srng->u.dst_ring.cached_hp;
  1202. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1203. "hp_addr=%pK, cached_hp=%d",
  1204. (void *)srng->u.dst_ring.hp_addr,
  1205. srng->u.dst_ring.cached_hp);
  1206. }
  1207. }
  1208. qdf_export_symbol(hal_srng_dst_init_hp);
  1209. /**
  1210. * hal_srng_hw_init - Private function to initialize SRNG HW
  1211. * @hal: HAL SOC handle
  1212. * @srng: SRNG ring pointer
  1213. * @idle_check: Check if ring is idle
  1214. * @idx: ring index
  1215. */
  1216. static inline void hal_srng_hw_init(struct hal_soc *hal,
  1217. struct hal_srng *srng, bool idle_check, uint32_t idx)
  1218. {
  1219. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1220. hal_srng_src_hw_init(hal, srng, idle_check, idx);
  1221. else
  1222. hal_srng_dst_hw_init(hal, srng, idle_check, idx);
  1223. }
  1224. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1225. bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc,
  1226. int ring_type, int ring_num)
  1227. {
  1228. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1229. struct hal_hw_srng_config *ring_config =
  1230. HAL_SRNG_CONFIG(hal, ring_type);
  1231. return ring_config->nf_irq_support;
  1232. }
  1233. /**
  1234. * hal_srng_set_msi2_params() - Set MSI2 params to SRNG data structure from
  1235. * ring params
  1236. * @srng: SRNG handle
  1237. * @ring_params: ring params for this SRNG
  1238. *
  1239. * Return: None
  1240. */
  1241. static inline void
  1242. hal_srng_set_msi2_params(struct hal_srng *srng,
  1243. struct hal_srng_params *ring_params)
  1244. {
  1245. srng->msi2_addr = ring_params->msi2_addr;
  1246. srng->msi2_data = ring_params->msi2_data;
  1247. }
  1248. /**
  1249. * hal_srng_get_nf_params() - Get the near full MSI2 params from srng
  1250. * @srng: SRNG handle
  1251. * @ring_params: ring params for this SRNG
  1252. *
  1253. * Return: None
  1254. */
  1255. static inline void
  1256. hal_srng_get_nf_params(struct hal_srng *srng,
  1257. struct hal_srng_params *ring_params)
  1258. {
  1259. ring_params->msi2_addr = srng->msi2_addr;
  1260. ring_params->msi2_data = srng->msi2_data;
  1261. }
  1262. /**
  1263. * hal_srng_set_nf_thresholds() - Set the near full thresholds in SRNG
  1264. * @srng: SRNG handle where the params are to be set
  1265. * @ring_params: ring params, from where threshold is to be fetched
  1266. *
  1267. * Return: None
  1268. */
  1269. static inline void
  1270. hal_srng_set_nf_thresholds(struct hal_srng *srng,
  1271. struct hal_srng_params *ring_params)
  1272. {
  1273. srng->u.dst_ring.nf_irq_support = ring_params->nf_irq_support;
  1274. srng->u.dst_ring.high_thresh = ring_params->high_thresh;
  1275. }
  1276. #else
  1277. static inline void
  1278. hal_srng_set_msi2_params(struct hal_srng *srng,
  1279. struct hal_srng_params *ring_params)
  1280. {
  1281. }
  1282. static inline void
  1283. hal_srng_get_nf_params(struct hal_srng *srng,
  1284. struct hal_srng_params *ring_params)
  1285. {
  1286. }
  1287. static inline void
  1288. hal_srng_set_nf_thresholds(struct hal_srng *srng,
  1289. struct hal_srng_params *ring_params)
  1290. {
  1291. }
  1292. #endif
  1293. #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
  1294. /**
  1295. * hal_srng_last_desc_cleared_init - Initialize SRNG last_desc_cleared ptr
  1296. * @srng: Source ring pointer
  1297. *
  1298. * Return: None
  1299. */
  1300. static inline
  1301. void hal_srng_last_desc_cleared_init(struct hal_srng *srng)
  1302. {
  1303. srng->last_desc_cleared = srng->ring_size - srng->entry_size;
  1304. }
  1305. #else
  1306. static inline
  1307. void hal_srng_last_desc_cleared_init(struct hal_srng *srng)
  1308. {
  1309. }
  1310. #endif /* CLEAR_SW2TCL_CONSUMED_DESC */
  1311. #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING
  1312. static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng)
  1313. {
  1314. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_90_to_100] =
  1315. ((srng->num_entries * 90) / 100);
  1316. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_80_to_90] =
  1317. ((srng->num_entries * 80) / 100);
  1318. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_70_to_80] =
  1319. ((srng->num_entries * 70) / 100);
  1320. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_60_to_70] =
  1321. ((srng->num_entries * 60) / 100);
  1322. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_50_to_60] =
  1323. ((srng->num_entries * 50) / 100);
  1324. /* Below 50% threshold is not needed */
  1325. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT] = 0;
  1326. hal_info("ring_id: %u, wm_thresh- <50:%u, 50-60:%u, 60-70:%u, 70-80:%u, 80-90:%u, 90-100:%u",
  1327. srng->ring_id,
  1328. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT],
  1329. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_50_to_60],
  1330. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_60_to_70],
  1331. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_70_to_80],
  1332. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_80_to_90],
  1333. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_90_to_100]);
  1334. }
  1335. #else
  1336. static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng)
  1337. {
  1338. }
  1339. #endif
  1340. void *hal_srng_setup_idx(void *hal_soc, int ring_type, int ring_num, int mac_id,
  1341. struct hal_srng_params *ring_params, bool idle_check,
  1342. uint32_t idx)
  1343. {
  1344. int ring_id;
  1345. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1346. hal_soc_handle_t hal_hdl = (hal_soc_handle_t)hal;
  1347. struct hal_srng *srng;
  1348. struct hal_hw_srng_config *ring_config =
  1349. HAL_SRNG_CONFIG(hal, ring_type);
  1350. void *dev_base_addr;
  1351. int i;
  1352. ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, mac_id);
  1353. if (ring_id < 0)
  1354. return NULL;
  1355. hal_verbose_debug("mac_id %d ring_id %d", mac_id, ring_id);
  1356. srng = hal_get_srng(hal_soc, ring_id);
  1357. if (srng->initialized) {
  1358. hal_verbose_debug("Ring (ring_type, ring_num) already initialized");
  1359. return NULL;
  1360. }
  1361. hal_srng_reg_his_init(srng);
  1362. dev_base_addr = hal->dev_base_addr;
  1363. srng->ring_id = ring_id;
  1364. srng->ring_type = ring_type;
  1365. srng->ring_dir = ring_config->ring_dir;
  1366. srng->ring_base_paddr = ring_params->ring_base_paddr;
  1367. srng->ring_base_vaddr = ring_params->ring_base_vaddr;
  1368. srng->entry_size = ring_config->entry_size;
  1369. srng->num_entries = ring_params->num_entries;
  1370. srng->ring_size = srng->num_entries * srng->entry_size;
  1371. srng->ring_size_mask = srng->ring_size - 1;
  1372. srng->ring_vaddr_end = srng->ring_base_vaddr + srng->ring_size;
  1373. srng->msi_addr = ring_params->msi_addr;
  1374. srng->msi_data = ring_params->msi_data;
  1375. srng->intr_timer_thres_us = ring_params->intr_timer_thres_us;
  1376. srng->intr_batch_cntr_thres_entries =
  1377. ring_params->intr_batch_cntr_thres_entries;
  1378. srng->pointer_timer_threshold =
  1379. ring_params->pointer_timer_threshold;
  1380. srng->pointer_num_threshold =
  1381. ring_params->pointer_num_threshold;
  1382. if (!idle_check)
  1383. srng->prefetch_timer = ring_params->prefetch_timer;
  1384. srng->hal_soc = hal_soc;
  1385. hal_srng_set_msi2_params(srng, ring_params);
  1386. hal_srng_update_high_wm_thresholds(srng);
  1387. for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++) {
  1388. srng->hwreg_base[i] = dev_base_addr + ring_config->reg_start[i]
  1389. + (ring_num * ring_config->reg_size[i]);
  1390. }
  1391. /* Zero out the entire ring memory */
  1392. qdf_mem_zero(srng->ring_base_vaddr, (srng->entry_size *
  1393. srng->num_entries) << 2);
  1394. srng->flags = ring_params->flags;
  1395. /* For cached descriptors flush and invalidate the memory*/
  1396. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  1397. qdf_nbuf_dma_clean_range(
  1398. srng->ring_base_vaddr,
  1399. srng->ring_base_vaddr +
  1400. ((srng->entry_size * srng->num_entries)));
  1401. qdf_nbuf_dma_inv_range(
  1402. srng->ring_base_vaddr,
  1403. srng->ring_base_vaddr +
  1404. ((srng->entry_size * srng->num_entries)));
  1405. }
  1406. #ifdef BIG_ENDIAN_HOST
  1407. /* TODO: See if we should we get these flags from caller */
  1408. srng->flags |= HAL_SRNG_DATA_TLV_SWAP;
  1409. srng->flags |= HAL_SRNG_MSI_SWAP;
  1410. srng->flags |= HAL_SRNG_RING_PTR_SWAP;
  1411. #endif
  1412. hal_srng_last_desc_cleared_init(srng);
  1413. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1414. srng->u.src_ring.hp = 0;
  1415. srng->u.src_ring.reap_hp = srng->ring_size -
  1416. srng->entry_size;
  1417. srng->u.src_ring.tp_addr =
  1418. &(hal->shadow_rdptr_mem_vaddr[ring_id]);
  1419. srng->u.src_ring.low_threshold =
  1420. ring_params->low_threshold * srng->entry_size;
  1421. if (srng->u.src_ring.tp_addr)
  1422. qdf_mem_zero(srng->u.src_ring.tp_addr,
  1423. sizeof(*hal->shadow_rdptr_mem_vaddr));
  1424. if (ring_config->lmac_ring) {
  1425. /* For LMAC rings, head pointer updates will be done
  1426. * through FW by writing to a shared memory location
  1427. */
  1428. srng->u.src_ring.hp_addr =
  1429. &(hal->shadow_wrptr_mem_vaddr[ring_id -
  1430. HAL_SRNG_LMAC1_ID_START]);
  1431. srng->flags |= HAL_SRNG_LMAC_RING;
  1432. if (srng->u.src_ring.hp_addr)
  1433. qdf_mem_zero(srng->u.src_ring.hp_addr,
  1434. sizeof(*hal->shadow_wrptr_mem_vaddr));
  1435. } else if (ignore_shadow || (srng->u.src_ring.hp_addr == 0)) {
  1436. srng->u.src_ring.hp_addr =
  1437. hal_get_window_address(hal,
  1438. SRNG_SRC_ADDR(srng, HP));
  1439. if (CHECK_SHADOW_REGISTERS) {
  1440. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1441. QDF_TRACE_LEVEL_ERROR,
  1442. "%s: Ring (%d, %d) missing shadow config",
  1443. __func__, ring_type, ring_num);
  1444. }
  1445. } else {
  1446. hal_validate_shadow_register(hal,
  1447. SRNG_SRC_ADDR(srng, HP),
  1448. srng->u.src_ring.hp_addr);
  1449. }
  1450. } else {
  1451. /* During initialization loop count in all the descriptors
  1452. * will be set to zero, and HW will set it to 1 on completing
  1453. * descriptor update in first loop, and increments it by 1 on
  1454. * subsequent loops (loop count wraps around after reaching
  1455. * 0xffff). The 'loop_cnt' in SW ring state is the expected
  1456. * loop count in descriptors updated by HW (to be processed
  1457. * by SW).
  1458. */
  1459. hal_srng_set_nf_thresholds(srng, ring_params);
  1460. srng->u.dst_ring.loop_cnt = 1;
  1461. srng->u.dst_ring.tp = 0;
  1462. srng->u.dst_ring.hp_addr =
  1463. &(hal->shadow_rdptr_mem_vaddr[ring_id]);
  1464. if (srng->u.dst_ring.hp_addr)
  1465. qdf_mem_zero(srng->u.dst_ring.hp_addr,
  1466. sizeof(*hal->shadow_rdptr_mem_vaddr));
  1467. if (ring_config->lmac_ring) {
  1468. /* For LMAC rings, tail pointer updates will be done
  1469. * through FW by writing to a shared memory location
  1470. */
  1471. srng->u.dst_ring.tp_addr =
  1472. &(hal->shadow_wrptr_mem_vaddr[ring_id -
  1473. HAL_SRNG_LMAC1_ID_START]);
  1474. srng->flags |= HAL_SRNG_LMAC_RING;
  1475. if (srng->u.dst_ring.tp_addr)
  1476. qdf_mem_zero(srng->u.dst_ring.tp_addr,
  1477. sizeof(*hal->shadow_wrptr_mem_vaddr));
  1478. } else if (ignore_shadow || srng->u.dst_ring.tp_addr == 0) {
  1479. srng->u.dst_ring.tp_addr =
  1480. hal_get_window_address(hal,
  1481. SRNG_DST_ADDR(srng, TP));
  1482. if (CHECK_SHADOW_REGISTERS) {
  1483. QDF_TRACE(QDF_MODULE_ID_TXRX,
  1484. QDF_TRACE_LEVEL_ERROR,
  1485. "%s: Ring (%d, %d) missing shadow config",
  1486. __func__, ring_type, ring_num);
  1487. }
  1488. } else {
  1489. hal_validate_shadow_register(hal,
  1490. SRNG_DST_ADDR(srng, TP),
  1491. srng->u.dst_ring.tp_addr);
  1492. }
  1493. }
  1494. if (!(ring_config->lmac_ring)) {
  1495. /*
  1496. * UMAC reset has idle check enabled.
  1497. * During UMAC reset Tx ring halt is set
  1498. * by Wi-Fi FW during pre-reset stage,
  1499. * avoid Tx ring halt again.
  1500. */
  1501. if (idle_check && idx) {
  1502. if (!hal->ops->hal_tx_ring_halt_get(hal_hdl)) {
  1503. qdf_print("\nTx ring halt not set:Ring(%d, %d)",
  1504. ring_type, ring_num);
  1505. qdf_assert_always(0);
  1506. }
  1507. hal_srng_hw_init(hal, srng, idle_check, idx);
  1508. goto ce_setup;
  1509. }
  1510. if (idx) {
  1511. hal->ops->hal_tx_ring_halt_set(hal_hdl);
  1512. do {
  1513. hal_info("Waiting for ring reset\n");
  1514. } while (!(hal->ops->hal_tx_ring_halt_poll(hal_hdl)));
  1515. }
  1516. hal_srng_hw_init(hal, srng, idle_check, idx);
  1517. if (idx) {
  1518. hal->ops->hal_tx_ring_halt_reset(hal_hdl);
  1519. }
  1520. ce_setup:
  1521. if (ring_type == CE_DST) {
  1522. srng->u.dst_ring.max_buffer_length = ring_params->max_buffer_length;
  1523. hal_ce_dst_setup(hal, srng, ring_num);
  1524. }
  1525. }
  1526. SRNG_LOCK_INIT(&srng->lock);
  1527. srng->srng_event = 0;
  1528. srng->initialized = true;
  1529. return (void *)srng;
  1530. }
  1531. qdf_export_symbol(hal_srng_setup_idx);
  1532. /**
  1533. * hal_srng_setup - Initialize HW SRNG ring.
  1534. * @hal_soc: Opaque HAL SOC handle
  1535. * @ring_type: one of the types from hal_ring_type
  1536. * @ring_num: Ring number if there are multiple rings of same type (staring
  1537. * from 0)
  1538. * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings
  1539. * @ring_params: SRNG ring params in hal_srng_params structure.
  1540. * @idle_check: Check if ring is idle
  1541. *
  1542. * Callers are expected to allocate contiguous ring memory of size
  1543. * 'num_entries * entry_size' bytes and pass the physical and virtual base
  1544. * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in
  1545. * hal_srng_params structure. Ring base address should be 8 byte aligned
  1546. * and size of each ring entry should be queried using the API
  1547. * hal_srng_get_entrysize
  1548. *
  1549. * Return: Opaque pointer to ring on success
  1550. * NULL on failure (if given ring is not available)
  1551. */
  1552. void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
  1553. int mac_id, struct hal_srng_params *ring_params,
  1554. bool idle_check)
  1555. {
  1556. return hal_srng_setup_idx(hal_soc, ring_type, ring_num, mac_id,
  1557. ring_params, idle_check, 0);
  1558. }
  1559. qdf_export_symbol(hal_srng_setup);
  1560. void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl,
  1561. bool umac_reset_inprogress)
  1562. {
  1563. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1564. SRNG_LOCK_DESTROY(&srng->lock);
  1565. srng->initialized = 0;
  1566. if (umac_reset_inprogress)
  1567. hal_srng_hw_disable(hal_soc, srng);
  1568. }
  1569. qdf_export_symbol(hal_srng_cleanup);
  1570. uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type)
  1571. {
  1572. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1573. struct hal_hw_srng_config *ring_config =
  1574. HAL_SRNG_CONFIG(hal, ring_type);
  1575. return ring_config->entry_size << 2;
  1576. }
  1577. qdf_export_symbol(hal_srng_get_entrysize);
  1578. uint32_t hal_srng_max_entries(void *hal_soc, int ring_type)
  1579. {
  1580. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1581. struct hal_hw_srng_config *ring_config =
  1582. HAL_SRNG_CONFIG(hal, ring_type);
  1583. return ring_config->max_size / ring_config->entry_size;
  1584. }
  1585. qdf_export_symbol(hal_srng_max_entries);
  1586. enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type)
  1587. {
  1588. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  1589. struct hal_hw_srng_config *ring_config =
  1590. HAL_SRNG_CONFIG(hal, ring_type);
  1591. return ring_config->ring_dir;
  1592. }
  1593. void hal_srng_dump(struct hal_srng *srng)
  1594. {
  1595. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1596. hal_debug("=== SRC RING %d ===", srng->ring_id);
  1597. hal_debug("hp %u, reap_hp %u, tp %u, cached tp %u",
  1598. srng->u.src_ring.hp,
  1599. srng->u.src_ring.reap_hp,
  1600. *srng->u.src_ring.tp_addr,
  1601. srng->u.src_ring.cached_tp);
  1602. } else {
  1603. hal_debug("=== DST RING %d ===", srng->ring_id);
  1604. hal_debug("tp %u, hp %u, cached tp %u, loop_cnt %u",
  1605. srng->u.dst_ring.tp,
  1606. *srng->u.dst_ring.hp_addr,
  1607. srng->u.dst_ring.cached_hp,
  1608. srng->u.dst_ring.loop_cnt);
  1609. }
  1610. }
  1611. void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl,
  1612. hal_ring_handle_t hal_ring_hdl,
  1613. struct hal_srng_params *ring_params)
  1614. {
  1615. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1616. int i =0;
  1617. ring_params->ring_id = srng->ring_id;
  1618. ring_params->ring_dir = srng->ring_dir;
  1619. ring_params->entry_size = srng->entry_size;
  1620. ring_params->ring_base_paddr = srng->ring_base_paddr;
  1621. ring_params->ring_base_vaddr = srng->ring_base_vaddr;
  1622. ring_params->num_entries = srng->num_entries;
  1623. ring_params->msi_addr = srng->msi_addr;
  1624. ring_params->msi_data = srng->msi_data;
  1625. ring_params->intr_timer_thres_us = srng->intr_timer_thres_us;
  1626. ring_params->intr_batch_cntr_thres_entries =
  1627. srng->intr_batch_cntr_thres_entries;
  1628. ring_params->low_threshold = srng->u.src_ring.low_threshold;
  1629. ring_params->flags = srng->flags;
  1630. ring_params->ring_id = srng->ring_id;
  1631. for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++)
  1632. ring_params->hwreg_base[i] = srng->hwreg_base[i];
  1633. hal_srng_get_nf_params(srng, ring_params);
  1634. }
  1635. qdf_export_symbol(hal_get_srng_params);
  1636. void hal_set_low_threshold(hal_ring_handle_t hal_ring_hdl,
  1637. uint32_t low_threshold)
  1638. {
  1639. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1640. srng->u.src_ring.low_threshold = low_threshold * srng->entry_size;
  1641. }
  1642. qdf_export_symbol(hal_set_low_threshold);
  1643. #ifdef FEATURE_RUNTIME_PM
  1644. void
  1645. hal_srng_rtpm_access_end(hal_soc_handle_t hal_soc_hdl,
  1646. hal_ring_handle_t hal_ring_hdl,
  1647. uint32_t rtpm_id)
  1648. {
  1649. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1650. if (qdf_unlikely(!hal_ring_hdl)) {
  1651. qdf_print("Error: Invalid hal_ring\n");
  1652. return;
  1653. }
  1654. if (hif_rtpm_get(HIF_RTPM_GET_ASYNC, rtpm_id) == 0) {
  1655. if (hif_system_pm_state_check(hal_soc->hif_handle)) {
  1656. hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
  1657. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1658. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1659. } else {
  1660. hal_srng_access_end(hal_soc_hdl, hal_ring_hdl);
  1661. }
  1662. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, rtpm_id);
  1663. } else {
  1664. hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
  1665. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1666. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1667. }
  1668. }
  1669. qdf_export_symbol(hal_srng_rtpm_access_end);
  1670. #endif /* FEATURE_RUNTIME_PM */
  1671. #ifdef FORCE_WAKE
  1672. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase)
  1673. {
  1674. struct hal_soc *hal_soc = (struct hal_soc *)soc;
  1675. hal_soc->init_phase = init_phase;
  1676. }
  1677. #endif /* FORCE_WAKE */