hal_rx.h 88 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_RX_H_
  20. #define _HAL_RX_H_
  21. #include <hal_api.h>
  22. #include "hal_rx_hw_defines.h"
  23. #include "hal_hw_headers.h"
  24. /*************************************
  25. * Ring desc offset/shift/masks
  26. *************************************/
  27. #define HAL_INVALID_PPDU_ID 0xFFFFFFFF
  28. #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET
  29. #define HAL_RX_LSB(block, field) block##_##field##_LSB
  30. #define HAL_RX_MASK(block, field) block##_##field##_MASK
  31. #define HAL_RX_TLV_L3_TYPE_INVALID 0xFFFF
  32. #define HAL_RX_GET(_ptr, block, field) \
  33. (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \
  34. HAL_RX_MASK(block, field)) >> \
  35. HAL_RX_LSB(block, field))
  36. #define HAL_RX_GET_64(_ptr, block, field) \
  37. (((*((volatile uint64_t *)(_ptr) + \
  38. (HAL_RX_OFFSET(block, field) >> 3))) & \
  39. HAL_RX_MASK(block, field)) >> \
  40. HAL_RX_LSB(block, field))
  41. #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \
  42. (*(uint32_t *)(((uint8_t *)_ptr) + \
  43. _wrd ## _ ## _field ## _OFFSET) |= \
  44. (((_val) << _wrd ## _ ## _field ## _LSB) & \
  45. _wrd ## _ ## _field ## _MASK))
  46. /* BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */
  47. #ifndef RX_DATA_BUFFER_SIZE
  48. #define RX_DATA_BUFFER_SIZE 2048
  49. #endif
  50. #ifndef RX_MONITOR_BUFFER_SIZE
  51. #define RX_MONITOR_BUFFER_SIZE 2048
  52. #endif
  53. #define RXDMA_OPTIMIZATION
  54. /* MONITOR STATUS BUFFER SIZE = 1408 data bytes, buffer allocation of 2k bytes
  55. * including buffer reservation, buffer alignment and skb shared info size.
  56. */
  57. #define RX_MON_STATUS_BASE_BUF_SIZE 2048
  58. #define RX_MON_STATUS_BUF_ALIGN 128
  59. #define RX_MON_STATUS_BUF_RESERVATION 128
  60. #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \
  61. (RX_MON_STATUS_BUF_RESERVATION + \
  62. RX_MON_STATUS_BUF_ALIGN + QDF_SHINFO_SIZE))
  63. #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
  64. /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */
  65. #define HAL_RX_NON_QOS_TID 16
  66. enum {
  67. HAL_HW_RX_DECAP_FORMAT_RAW = 0,
  68. HAL_HW_RX_DECAP_FORMAT_NWIFI,
  69. HAL_HW_RX_DECAP_FORMAT_ETH2,
  70. HAL_HW_RX_DECAP_FORMAT_8023,
  71. };
  72. /**
  73. * struct hal_wbm_err_desc_info - structure to hold wbm error codes and reasons
  74. *
  75. * @reo_psh_rsn: REO push reason
  76. * @reo_err_code: REO Error code
  77. * @rxdma_psh_rsn: RXDMA push reason
  78. * @rxdma_err_code: RXDMA Error code
  79. * @reserved_1: Reserved bits
  80. * @wbm_err_src: WBM error source
  81. * @pool_id: pool ID, indicates which rxdma pool
  82. * @msdu_continued: Is the MSDU continued
  83. * @reserved_2: Reserved bits
  84. */
  85. struct hal_wbm_err_desc_info {
  86. uint16_t reo_psh_rsn:2,
  87. reo_err_code:5,
  88. rxdma_psh_rsn:2,
  89. rxdma_err_code:5,
  90. reserved_1:2;
  91. uint8_t wbm_err_src:3,
  92. pool_id:2,
  93. msdu_continued:1,
  94. reserved_2:2;
  95. };
  96. /**
  97. * struct hal_rx_mon_dest_buf_info - Structure to hold rx mon dest buffer info
  98. * @first_buffer: First buffer of MSDU
  99. * @last_buffer: Last buffer of MSDU
  100. * @is_decap_raw: Is RAW Frame
  101. * @mpdu_len_err: Is there an MPDU length error
  102. * @l2_hdr_pad: Amount of layer 2 header padding
  103. * @reserved_1: Reserved
  104. *
  105. * MSDU with continuation:
  106. * -----------------------------------------------------------
  107. * | first_buffer:1 | first_buffer: 0 | ... | first_buffer: 0 |
  108. * | last_buffer :0 | last_buffer : 0 | ... | last_buffer : 0 |
  109. * | is_decap_raw:1/0 | Same as earlier | Same as earlier|
  110. * -----------------------------------------------------------
  111. *
  112. * Single buffer MSDU:
  113. * ------------------
  114. * | first_buffer:1 |
  115. * | last_buffer :1 |
  116. * | is_decap_raw:1/0 |
  117. * ------------------
  118. */
  119. struct hal_rx_mon_dest_buf_info {
  120. uint8_t first_buffer:1,
  121. last_buffer:1,
  122. is_decap_raw:1,
  123. mpdu_len_err:1,
  124. l2_hdr_pad:2,
  125. reserved_1:2;
  126. };
  127. /**
  128. * struct hal_rx_msdu_metadata - Structure to hold rx fast path information.
  129. *
  130. * @l3_hdr_pad: l3 header padding
  131. * @reserved: Reserved bits
  132. * @sa_sw_peer_id: sa sw peer id
  133. * @sa_idx: sa index
  134. * @da_idx: da index
  135. */
  136. struct hal_rx_msdu_metadata {
  137. uint32_t l3_hdr_pad:16,
  138. sa_sw_peer_id:16;
  139. uint32_t sa_idx:16,
  140. da_idx:16;
  141. };
  142. struct hal_proto_params {
  143. uint8_t tcp_proto;
  144. uint8_t udp_proto;
  145. uint8_t ipv6_proto;
  146. };
  147. /**
  148. * enum hal_reo_error_status - Enum which encapsulates "reo_push_reason"
  149. *
  150. * @HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected
  151. * @HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing
  152. */
  153. enum hal_reo_error_status {
  154. HAL_REO_ERROR_DETECTED = 0,
  155. HAL_REO_ROUTING_INSTRUCTION = 1,
  156. };
  157. /**
  158. * struct hal_rx_msdu_desc_info - RX MSDU Descriptor
  159. * @msdu_flags: [0] first_msdu_in_mpdu
  160. * [1] last_msdu_in_mpdu
  161. * [2] msdu_continuation - MSDU spread across buffers
  162. * [23] sa_is_valid - SA match in peer table
  163. * [24] sa_idx_timeout - Timeout while searching for SA match
  164. * [25] da_is_valid - Used to identtify intra-bss forwarding
  165. * [26] da_is_MCBC
  166. * [27] da_idx_timeout - Timeout while searching for DA match
  167. * @msdu_len: length of the MSDU (14 bits of length)
  168. *
  169. */
  170. struct hal_rx_msdu_desc_info {
  171. uint32_t msdu_flags;
  172. uint16_t msdu_len;
  173. };
  174. /**
  175. * enum hal_rx_msdu_desc_flags - Enum for flags in MSDU_DESC_INFO
  176. *
  177. * @HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU
  178. * @HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU
  179. * @HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation
  180. * @HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST
  181. * @HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out
  182. * @HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST
  183. * @HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address
  184. * @HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out
  185. * @HAL_MSDU_F_INTRA_BSS: This is an intrabss packet
  186. */
  187. enum hal_rx_msdu_desc_flags {
  188. HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0),
  189. HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1),
  190. HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2),
  191. HAL_MSDU_F_SA_IS_VALID = (0x1 << 23),
  192. HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24),
  193. HAL_MSDU_F_DA_IS_VALID = (0x1 << 25),
  194. HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26),
  195. HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27),
  196. HAL_MSDU_F_INTRA_BSS = (0x1 << 28),
  197. };
  198. /**
  199. * struct hal_rx_mpdu_desc_info - RX MPDU descriptor
  200. * @msdu_count: no. of msdus in the MPDU
  201. * @mpdu_seq: MPDU sequence number
  202. * @mpdu_flags: [0] Fragment flag
  203. * [1] MPDU_retry_bit
  204. * [2] AMPDU flag
  205. * [3] raw_ampdu
  206. * @peer_meta_data: Upper bits containing peer id, vdev id
  207. * @bar_frame: indicates if received frame is a bar frame
  208. * @tid: tid value of received MPDU
  209. * @reserved: spare bits
  210. */
  211. struct hal_rx_mpdu_desc_info {
  212. uint16_t msdu_count;
  213. uint16_t mpdu_seq; /* 12 bits for length */
  214. uint32_t mpdu_flags;
  215. uint32_t peer_meta_data; /* sw programmed meta-data:MAC Id & peer Id */
  216. uint16_t bar_frame;
  217. uint8_t tid:4,
  218. reserved:4;
  219. };
  220. /**
  221. * enum hal_rx_mpdu_desc_flags - Enum for flags in MPDU_DESC_INFO
  222. *
  223. * @HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation)
  224. * @HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU
  225. * @HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU
  226. * @HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU
  227. * @HAL_MPDU_F_QOS_CONTROL_VALID: MPDU has a QoS control field
  228. */
  229. enum hal_rx_mpdu_desc_flags {
  230. HAL_MPDU_F_FRAGMENT = (0x1 << 20),
  231. HAL_MPDU_F_RETRY_BIT = (0x1 << 21),
  232. HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22),
  233. HAL_MPDU_F_RAW_AMPDU = (0x1 << 30),
  234. HAL_MPDU_F_QOS_CONTROL_VALID = (0x1 << 31)
  235. };
  236. /* Return Buffer manager ID */
  237. #define HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST 0
  238. #define HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST 1
  239. #define HAL_RX_BUF_RBM_WBM_CHIP1_IDLE_DESC_LIST 2
  240. #define HAL_RX_BUF_RBM_WBM_CHIP2_IDLE_DESC_LIST 3
  241. #define HAL_RX_BUF_RBM_SW0_BM(sw0_bm_id) (sw0_bm_id)
  242. #define HAL_RX_BUF_RBM_SW1_BM(sw0_bm_id) (sw0_bm_id + 1)
  243. #define HAL_RX_BUF_RBM_SW2_BM(sw0_bm_id) (sw0_bm_id + 2)
  244. #define HAL_RX_BUF_RBM_SW3_BM(sw0_bm_id) (sw0_bm_id + 3)
  245. #define HAL_RX_BUF_RBM_SW4_BM(sw0_bm_id) (sw0_bm_id + 4)
  246. #define HAL_RX_BUF_RBM_SW5_BM(sw0_bm_id) (sw0_bm_id + 5)
  247. #define HAL_RX_BUF_RBM_SW6_BM(sw0_bm_id) (sw0_bm_id + 6)
  248. #define HAL_RX_BUF_RBM_SW_BM(sw0_bm_id, wbm2sw_id) (sw0_bm_id + wbm2sw_id)
  249. #define HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET 0x8
  250. #define HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB 0
  251. #define HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK 0x000000ff
  252. #define HAL_RX_REO_DESC_MSDU_COUNT_GET(reo_desc) \
  253. (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \
  254. HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET)), \
  255. HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK, \
  256. HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB))
  257. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0
  258. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  259. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  260. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x4
  261. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
  262. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
  263. /*
  264. * macro to set the LSW of the nbuf data physical address
  265. * to the rxdma ring entry
  266. */
  267. #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \
  268. ((*(((unsigned int *) buff_addr_info) + \
  269. (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET >> 2))) = \
  270. (paddr_lo << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB) & \
  271. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK)
  272. /*
  273. * macro to set the LSB of MSW of the nbuf data physical address
  274. * to the rxdma ring entry
  275. */
  276. #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \
  277. ((*(((unsigned int *) buff_addr_info) + \
  278. (HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET >> 2))) = \
  279. (paddr_hi << HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB) & \
  280. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK)
  281. #ifdef DP_RX_DESC_COOKIE_INVALIDATE
  282. #define HAL_RX_COOKIE_INVALID_MASK 0x80000000
  283. /*
  284. * macro to get the invalid bit for sw cookie
  285. */
  286. #define HAL_RX_BUF_COOKIE_INVALID_GET(buff_addr_info) \
  287. ((*(((unsigned int *)buff_addr_info) + \
  288. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \
  289. HAL_RX_COOKIE_INVALID_MASK)
  290. /*
  291. * macro to set the invalid bit for sw cookie
  292. */
  293. #define HAL_RX_BUF_COOKIE_INVALID_SET(buff_addr_info) \
  294. ((*(((unsigned int *)buff_addr_info) + \
  295. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  296. HAL_RX_COOKIE_INVALID_MASK)
  297. /*
  298. * macro to reset the invalid bit for sw cookie
  299. */
  300. #define HAL_RX_BUF_COOKIE_INVALID_RESET(buff_addr_info) \
  301. ((*(((unsigned int *)buff_addr_info) + \
  302. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \
  303. ~HAL_RX_COOKIE_INVALID_MASK)
  304. #define HAL_RX_REO_BUF_COOKIE_INVALID_GET(reo_desc) \
  305. (HAL_RX_BUF_COOKIE_INVALID_GET(& \
  306. (((struct reo_destination_ring *) \
  307. reo_desc)->buf_or_link_desc_addr_info)))
  308. #define HAL_RX_REO_BUF_COOKIE_INVALID_SET(reo_desc) \
  309. (HAL_RX_BUF_COOKIE_INVALID_SET(& \
  310. (((struct reo_destination_ring *) \
  311. reo_desc)->buf_or_link_desc_addr_info)))
  312. #define HAL_RX_LINK_COOKIE_INVALID_MASK 0x40000000
  313. #define HAL_RX_BUF_LINK_COOKIE_INVALID_GET(buff_addr_info) \
  314. ((*(((unsigned int *)buff_addr_info) + \
  315. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) & \
  316. HAL_RX_LINK_COOKIE_INVALID_MASK)
  317. #define HAL_RX_BUF_LINK_COOKIE_INVALID_SET(buff_addr_info) \
  318. ((*(((unsigned int *)buff_addr_info) + \
  319. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  320. HAL_RX_LINK_COOKIE_INVALID_MASK)
  321. #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_GET(reo_desc) \
  322. (HAL_RX_BUF_LINK_COOKIE_INVALID_GET(& \
  323. (((struct reo_destination_ring *) \
  324. reo_desc)->buf_or_link_desc_addr_info)))
  325. #define HAL_RX_REO_BUF_LINK_COOKIE_INVALID_SET(reo_desc) \
  326. (HAL_RX_BUF_LINK_COOKIE_INVALID_SET(& \
  327. (((struct reo_destination_ring *) \
  328. reo_desc)->buf_or_link_desc_addr_info)))
  329. #endif
  330. /* TODO: Convert the following structure fields accesseses to offsets */
  331. #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \
  332. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  333. (((struct reo_destination_ring *) \
  334. reo_desc)->buf_or_link_desc_addr_info)))
  335. #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \
  336. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  337. (((struct reo_destination_ring *) \
  338. reo_desc)->buf_or_link_desc_addr_info)))
  339. #define HAL_RX_REO_BUF_COOKIE_INVALID_RESET(reo_desc) \
  340. (HAL_RX_BUF_COOKIE_INVALID_RESET(& \
  341. (((struct reo_destination_ring *) \
  342. reo_desc)->buf_or_link_desc_addr_info)))
  343. #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \
  344. HAL_RX_FLD_SET(_rx_msdu_link, HAL_UNIFORM_DESCRIPTOR_HEADER, \
  345. _field, _val)
  346. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x0
  347. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
  348. #define HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
  349. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  350. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  351. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \
  352. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \
  353. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB))
  354. #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \
  355. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  356. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \
  357. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \
  358. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB))
  359. #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x0
  360. #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
  361. #define HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
  362. #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x0
  363. #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1
  364. #define HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
  365. #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \
  366. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  367. HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \
  368. (val << HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \
  369. HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK)
  370. #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \
  371. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  372. HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) |= \
  373. (val << HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB) & \
  374. HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK)
  375. #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \
  376. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  377. HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \
  378. HAL_RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK)
  379. #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \
  380. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  381. HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \
  382. HAL_RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK)
  383. #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x0
  384. #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3
  385. #define HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8
  386. #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \
  387. (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  388. HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET)), \
  389. HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK, \
  390. HAL_RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB))
  391. static inline uint32_t
  392. hal_rx_msdu_flags_get(hal_soc_handle_t hal_soc_hdl,
  393. rx_msdu_desc_info_t msdu_desc_info_hdl)
  394. {
  395. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  396. return hal_soc->ops->hal_rx_msdu_flags_get(msdu_desc_info_hdl);
  397. }
  398. /*
  399. * Structures & Macros to obtain fields from the TLV's in the Rx packet
  400. * pre-header.
  401. */
  402. static inline uint8_t *hal_rx_desc_get_80211_hdr(hal_soc_handle_t hal_soc_hdl,
  403. void *hw_desc_addr)
  404. {
  405. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  406. return hal_soc->ops->hal_rx_desc_get_80211_hdr(hw_desc_addr);
  407. }
  408. /**
  409. * hal_rx_mpdu_desc_info_get() - Get MDPU desc info params
  410. * @hal_soc_hdl: hal soc handle
  411. * @desc_addr: ring descriptor
  412. * @mpdu_desc_info: Buffer to fill the mpdu desc info params
  413. *
  414. * Return: None
  415. */
  416. static inline void
  417. hal_rx_mpdu_desc_info_get(hal_soc_handle_t hal_soc_hdl, void *desc_addr,
  418. struct hal_rx_mpdu_desc_info *mpdu_desc_info)
  419. {
  420. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  421. return hal_soc->ops->hal_rx_mpdu_desc_info_get(desc_addr,
  422. mpdu_desc_info);
  423. }
  424. #define HAL_RX_NUM_MSDU_DESC 6
  425. #define HAL_RX_MAX_SAVED_RING_DESC 16
  426. /* TODO: rework the structure */
  427. struct hal_rx_msdu_list {
  428. struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
  429. uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC];
  430. uint8_t rbm[HAL_RX_NUM_MSDU_DESC];
  431. /* physical address of the msdu */
  432. uint64_t paddr[HAL_RX_NUM_MSDU_DESC];
  433. };
  434. struct hal_buf_info {
  435. uint64_t paddr;
  436. uint32_t sw_cookie;
  437. uint8_t rbm;
  438. };
  439. /* This special cookie value will be used to indicate FW allocated buffers
  440. * received through RXDMA2SW ring for RXDMA WARs
  441. */
  442. #define HAL_RX_COOKIE_SPECIAL 0x1fffff
  443. /**
  444. * enum hal_rx_reo_buf_type - Indicates that type of buffer or descriptor
  445. *
  446. * @HAL_RX_REO_MSDU_BUF_ADDR_TYPE: Reo buffer address points to the MSDU buffer
  447. * @HAL_RX_REO_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link
  448. * descriptor
  449. */
  450. enum hal_rx_reo_buf_type {
  451. HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0,
  452. HAL_RX_REO_MSDU_LINK_DESC_TYPE,
  453. };
  454. /**
  455. * enum hal_reo_error_code - Error code describing the type of error detected
  456. *
  457. * @HAL_REO_ERR_QUEUE_DESC_ADDR_0: Reo queue descriptor provided in the
  458. * REO_ENTRANCE ring is set to 0
  459. * @HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set
  460. * @HAL_REO_ERR_AMPDU_IN_NON_BA: AMPDU frame received without BA session
  461. * having been setup
  462. * @HAL_REO_ERR_NON_BA_DUPLICATE: Non-BA session, SN equal to SSN,
  463. * Retry bit set: duplicate frame
  464. * @HAL_REO_ERR_BA_DUPLICATE: BA session, duplicate frame
  465. * @HAL_REO_ERR_REGULAR_FRAME_2K_JUMP: A normal (management/data frame)
  466. * received with 2K jump in SN
  467. * @HAL_REO_ERR_BAR_FRAME_2K_JUMP: A bar received with 2K jump in SSN
  468. * @HAL_REO_ERR_REGULAR_FRAME_OOR: A normal (management/data frame) received
  469. * with SN falling within the OOR window
  470. * @HAL_REO_ERR_BAR_FRAME_OOR: A bar received with SSN falling within the
  471. * OOR window
  472. * @HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION: A bar received without a BA session
  473. * @HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN: A bar received with SSN equal to SN
  474. * @HAL_REO_ERR_PN_CHECK_FAILED: PN Check Failed packet
  475. * @HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET: Frame is forwarded as a result
  476. * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor
  477. * @HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET: Frame is forwarded as a result
  478. * of the pn_error_detected_flag been set in the REO Queue descriptor
  479. * @HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET: Frame is forwarded as a result of
  480. * the queue descriptor(address) being blocked as SW/FW seems to be currently
  481. * in the process of making updates to this descriptor
  482. * @HAL_REO_ERR_MAX: count of number of enumerators
  483. */
  484. enum hal_reo_error_code {
  485. HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0,
  486. HAL_REO_ERR_QUEUE_DESC_INVALID,
  487. HAL_REO_ERR_AMPDU_IN_NON_BA,
  488. HAL_REO_ERR_NON_BA_DUPLICATE,
  489. HAL_REO_ERR_BA_DUPLICATE,
  490. HAL_REO_ERR_REGULAR_FRAME_2K_JUMP,
  491. HAL_REO_ERR_BAR_FRAME_2K_JUMP,
  492. HAL_REO_ERR_REGULAR_FRAME_OOR,
  493. HAL_REO_ERR_BAR_FRAME_OOR,
  494. HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION,
  495. HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN,
  496. HAL_REO_ERR_PN_CHECK_FAILED,
  497. HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET,
  498. HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET,
  499. HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET,
  500. HAL_REO_ERR_MAX
  501. };
  502. /**
  503. * enum hal_rxdma_error_code - Code describing the type of RxDMA error detected
  504. *
  505. * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow
  506. * @HAL_RXDMA_ERR_MPDU_LENGTH: MPDU frame is not complete due to receiving
  507. * incomplete MPDU from the PHY
  508. * @HAL_RXDMA_ERR_FCS: FCS check on the MPDU frame failed
  509. * @HAL_RXDMA_ERR_DECRYPT: Decryption error
  510. * @HAL_RXDMA_ERR_TKIP_MIC: TKIP MIC error
  511. * @HAL_RXDMA_ERR_UNENCRYPTED: Received a frame that was expected to be
  512. * encrypted but wasn’t
  513. * @HAL_RXDMA_ERR_MSDU_LEN: MSDU related length error
  514. * @HAL_RXDMA_ERR_MSDU_LIMIT: Number of MSDUs in the MPDUs exceeded
  515. * the max allowed
  516. * @HAL_RXDMA_ERR_WIFI_PARSE: wifi parsing error
  517. * @HAL_RXDMA_ERR_AMSDU_PARSE: Amsdu parsing error
  518. * @HAL_RXDMA_ERR_SA_TIMEOUT: Source Address search timeout
  519. * @HAL_RXDMA_ERR_DA_TIMEOUT: Destination Address search timeout
  520. * @HAL_RXDMA_ERR_FLOW_TIMEOUT: Flow Search Timeout
  521. * @HAL_RXDMA_ERR_FLUSH_REQUEST: RxDMA FIFO Flush request
  522. * @HAL_RXDMA_AMSDU_FRAGMENT: Rx PCU reported A-MSDU
  523. * present as well as a fragmented MPDU
  524. * @HAL_RXDMA_MULTICAST_ECHO: RX OLE reported a multicast echo
  525. * @HAL_RXDMA_AMSDU_ADDR_MISMATCH: RX OLE reported AMSDU address mismatch
  526. * @HAL_RXDMA_UNAUTHORIZED_WDS: RX PCU reported unauthorized wds
  527. * @HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS: RX PCU reported group cast AMSDU or WDS
  528. * @HAL_RXDMA_ERR_WAR: RxDMA WAR dummy errors
  529. * @HAL_RXDMA_ERR_MAX: count of number of enumerators
  530. */
  531. enum hal_rxdma_error_code {
  532. HAL_RXDMA_ERR_OVERFLOW = 0,
  533. HAL_RXDMA_ERR_MPDU_LENGTH,
  534. HAL_RXDMA_ERR_FCS,
  535. HAL_RXDMA_ERR_DECRYPT,
  536. HAL_RXDMA_ERR_TKIP_MIC,
  537. HAL_RXDMA_ERR_UNENCRYPTED,
  538. HAL_RXDMA_ERR_MSDU_LEN,
  539. HAL_RXDMA_ERR_MSDU_LIMIT,
  540. HAL_RXDMA_ERR_WIFI_PARSE,
  541. HAL_RXDMA_ERR_AMSDU_PARSE,
  542. HAL_RXDMA_ERR_SA_TIMEOUT,
  543. HAL_RXDMA_ERR_DA_TIMEOUT,
  544. HAL_RXDMA_ERR_FLOW_TIMEOUT,
  545. HAL_RXDMA_ERR_FLUSH_REQUEST,
  546. HAL_RXDMA_AMSDU_FRAGMENT,
  547. HAL_RXDMA_MULTICAST_ECHO,
  548. HAL_RXDMA_AMSDU_ADDR_MISMATCH,
  549. HAL_RXDMA_UNAUTHORIZED_WDS,
  550. HAL_RXDMA_GROUPCAST_AMSDU_OR_WDS,
  551. HAL_RXDMA_ERR_WAR = 31,
  552. HAL_RXDMA_ERR_MAX
  553. };
  554. /*
  555. * HW BM action settings in WBM release ring
  556. */
  557. #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0
  558. #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1
  559. /**
  560. * enum hal_rx_wbm_error_source - Indicates which module initiated the
  561. * release of this buffer or descriptor
  562. *
  563. * @HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor
  564. * @HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor
  565. * @HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor
  566. * @HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor
  567. * @HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor
  568. */
  569. enum hal_rx_wbm_error_source {
  570. HAL_RX_WBM_ERR_SRC_TQM = 0,
  571. HAL_RX_WBM_ERR_SRC_RXDMA,
  572. HAL_RX_WBM_ERR_SRC_REO,
  573. HAL_RX_WBM_ERR_SRC_FW,
  574. HAL_RX_WBM_ERR_SRC_SW,
  575. };
  576. /**
  577. * enum hal_rx_wbm_buf_type - Indicates that type of buffer or descriptor
  578. * released
  579. *
  580. * @HAL_RX_WBM_BUF_TYPE_REL_BUF:
  581. * @HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC:
  582. * @HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC:
  583. * @HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC:
  584. * @HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC:
  585. */
  586. enum hal_rx_wbm_buf_type {
  587. HAL_RX_WBM_BUF_TYPE_REL_BUF = 0,
  588. HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC,
  589. HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC,
  590. HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC,
  591. HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC,
  592. };
  593. #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING)
  594. /**
  595. * hal_rx_msdu_is_wlan_mcast() - Check if the buffer is for multicast address
  596. * @hal_soc_hdl: hal soc handle
  597. * @nbuf: Network buffer
  598. *
  599. * Return: flag to indicate whether the nbuf has MC/BC address
  600. */
  601. static inline uint32_t
  602. hal_rx_msdu_is_wlan_mcast(hal_soc_handle_t hal_soc_hdl,
  603. qdf_nbuf_t nbuf)
  604. {
  605. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  606. return hal_soc->ops->hal_rx_msdu_is_wlan_mcast(nbuf);
  607. }
  608. /**
  609. * hal_rx_priv_info_set_in_tlv() - Save the private info to
  610. * the reserved bytes of rx_tlv_hdr
  611. * @hal_soc_hdl: hal soc handle
  612. * @buf: start of rx_tlv_hdr
  613. * @priv_data: private info to store
  614. * @len: length of @priv_data
  615. *
  616. * Return: void
  617. */
  618. static inline void
  619. hal_rx_priv_info_set_in_tlv(hal_soc_handle_t hal_soc_hdl,
  620. uint8_t *buf, uint8_t *priv_data,
  621. uint32_t len)
  622. {
  623. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  624. return hal_soc->ops->hal_rx_priv_info_set_in_tlv(buf,
  625. priv_data,
  626. len);
  627. }
  628. /**
  629. * hal_rx_reo_ent_rxdma_push_reason_get() - Retrieves RXDMA push reason from
  630. * reo_entrance_ring descriptor
  631. *
  632. * @reo_ent_desc: reo_entrance_ring descriptor
  633. *
  634. * Return: value of rxdma_push_reason
  635. */
  636. static inline
  637. uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc)
  638. {
  639. return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc,
  640. HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET)),
  641. HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK,
  642. HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB);
  643. }
  644. /**
  645. * hal_rx_reo_ent_rxdma_error_code_get() - Retrieves RXDMA error code from
  646. * reo_entrance_ring descriptor
  647. * @reo_ent_desc: reo_entrance_ring descriptor
  648. *
  649. * Return: value of rxdma_error_code
  650. */
  651. static inline
  652. uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc)
  653. {
  654. return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc,
  655. HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET)),
  656. HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK,
  657. HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB);
  658. }
  659. /**
  660. * hal_rx_priv_info_get_from_tlv() - retrieve the private data from
  661. * the reserved bytes of rx_tlv_hdr.
  662. * @hal_soc_hdl: hal soc handle
  663. * @buf: start of rx_tlv_hdr
  664. * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter.
  665. * @len: length of the buffer
  666. *
  667. * Return: void
  668. */
  669. static inline void
  670. hal_rx_priv_info_get_from_tlv(hal_soc_handle_t hal_soc_hdl,
  671. uint8_t *buf, uint8_t *wbm_er_info,
  672. uint32_t len)
  673. {
  674. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  675. return hal_soc->ops->hal_rx_priv_info_get_from_tlv(buf,
  676. wbm_er_info,
  677. len);
  678. }
  679. static inline void
  680. hal_rx_get_tlv_size(hal_soc_handle_t hal_soc_hdl, uint16_t *rx_pkt_tlv_size,
  681. uint16_t *rx_mon_pkt_tlv_size)
  682. {
  683. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  684. return hal_soc->ops->hal_rx_get_tlv_size(rx_pkt_tlv_size,
  685. rx_mon_pkt_tlv_size);
  686. }
  687. /**
  688. * hal_rx_encryption_info_valid() - Returns encryption type.
  689. * @hal_soc_hdl: hal soc handle
  690. * @buf: rx_tlv_hdr of the received packet
  691. *
  692. * Return: encryption type
  693. */
  694. static inline uint32_t
  695. hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  696. {
  697. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  698. return hal_soc->ops->hal_rx_encryption_info_valid(buf);
  699. }
  700. /**
  701. * hal_rx_print_pn() - Prints the PN of rx packet.
  702. * @hal_soc_hdl: hal soc handle
  703. * @buf: rx_tlv_hdr of the received packet
  704. *
  705. * Return: void
  706. */
  707. static inline void
  708. hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  709. {
  710. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  711. hal_soc->ops->hal_rx_print_pn(buf);
  712. }
  713. /**
  714. * hal_rx_msdu_end_l3_hdr_padding_get() - API to get the
  715. * l3_header padding from rx_msdu_end TLV
  716. * @hal_soc_hdl: hal_soc handle
  717. * @buf: pointer to the start of RX PKT TLV headers
  718. *
  719. * Return: number of l3 header padding bytes
  720. */
  721. static inline uint32_t
  722. hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl,
  723. uint8_t *buf)
  724. {
  725. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  726. return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf);
  727. }
  728. /**
  729. * hal_rx_msdu_end_sa_idx_get() - API to get the sa_idx from rx_msdu_end TLV
  730. * @hal_soc_hdl: hal_soc handle
  731. * @buf: pointer to the start of RX PKT TLV headers
  732. *
  733. * Return: sa_idx (SA AST index)
  734. */
  735. static inline uint16_t
  736. hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl,
  737. uint8_t *buf)
  738. {
  739. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  740. return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf);
  741. }
  742. /**
  743. * hal_rx_msdu_end_sa_is_valid_get() - API to get the
  744. * sa_is_valid bit from rx_msdu_end TLV
  745. * @hal_soc_hdl: hal_soc handle
  746. * @buf: pointer to the start of RX PKT TLV headers
  747. *
  748. * Return: sa_is_valid bit
  749. */
  750. static inline uint8_t
  751. hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl,
  752. uint8_t *buf)
  753. {
  754. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  755. return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf);
  756. }
  757. /**
  758. * hal_rx_tlv_msdu_len_set() - API to set the MSDU length from rx_msdu_start TLV
  759. * @hal_soc_hdl: hal_soc handle
  760. * @buf: pointer to the start of RX PKT TLV headers
  761. * @len: msdu length
  762. *
  763. * Return: none
  764. */
  765. static inline void
  766. hal_rx_tlv_msdu_len_set(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  767. uint32_t len)
  768. {
  769. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  770. return hal_soc->ops->hal_rx_tlv_msdu_len_set(buf, len);
  771. }
  772. /**
  773. * enum hal_rx_mpdu_info_sw_frame_group_id_type - Enum for group id in MPDU_INFO
  774. *
  775. * @HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame
  776. * @HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame
  777. * @HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame
  778. * @HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame
  779. * @HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame
  780. * @HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ: probe req frame
  781. * @HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON: beacon frame
  782. * @HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame
  783. * @HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA: NDPA frame
  784. * @HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR: BAR frame
  785. * @HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS: RTS frame
  786. * @HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported
  787. * @HAL_MPDU_SW_FRAME_GROUP_MAX: max limit
  788. */
  789. enum hal_rx_mpdu_info_sw_frame_group_id_type {
  790. HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0,
  791. HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA,
  792. HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA,
  793. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA,
  794. HAL_MPDU_SW_FRAME_GROUP_MGMT,
  795. HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ = 8,
  796. HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12,
  797. HAL_MPDU_SW_FRAME_GROUP_CTRL = 20,
  798. HAL_MPDU_SW_FRAME_GROUP_CTRL_NDPA = 25,
  799. HAL_MPDU_SW_FRAME_GROUP_CTRL_BAR = 28,
  800. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS = 31,
  801. HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36,
  802. HAL_MPDU_SW_FRAME_GROUP_MAX = 37,
  803. };
  804. /**
  805. * hal_rx_mpdu_start_mpdu_qos_control_valid_get() -
  806. * Retrieve qos control valid bit from the tlv.
  807. * @hal_soc_hdl: hal_soc handle
  808. * @buf: pointer to rx pkt TLV.
  809. *
  810. * Return: qos control value.
  811. */
  812. static inline uint32_t
  813. hal_rx_mpdu_start_mpdu_qos_control_valid_get(
  814. hal_soc_handle_t hal_soc_hdl,
  815. uint8_t *buf)
  816. {
  817. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  818. if ((!hal_soc) || (!hal_soc->ops)) {
  819. hal_err("hal handle is NULL");
  820. QDF_BUG(0);
  821. return QDF_STATUS_E_INVAL;
  822. }
  823. if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get)
  824. return hal_soc->ops->
  825. hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf);
  826. return QDF_STATUS_E_INVAL;
  827. }
  828. /**
  829. * hal_rx_is_unicast() - check packet is unicast frame or not.
  830. * @hal_soc_hdl: hal_soc handle
  831. * @buf: pointer to rx pkt TLV.
  832. *
  833. * Return: true on unicast.
  834. */
  835. static inline bool
  836. hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  837. {
  838. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  839. return hal_soc->ops->hal_rx_is_unicast(buf);
  840. }
  841. /**
  842. * hal_rx_tid_get() - get tid based on qos control valid.
  843. * @hal_soc_hdl: hal soc handle
  844. * @buf: pointer to rx pkt TLV.
  845. *
  846. * Return: tid
  847. */
  848. static inline uint32_t
  849. hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  850. {
  851. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  852. return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf);
  853. }
  854. /**
  855. * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id
  856. * @hal_soc_hdl: hal soc handle
  857. * @buf: pointer to rx pkt TLV.
  858. *
  859. * Return: sw peer_id
  860. */
  861. static inline uint32_t
  862. hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl,
  863. uint8_t *buf)
  864. {
  865. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  866. return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf);
  867. }
  868. /**
  869. * hal_rx_tlv_peer_meta_data_get() - Retrieve PEER_META_DATA
  870. * @hal_soc_hdl: hal soc handle
  871. * @buf: pointer to rx pkt TLV.
  872. *
  873. * Return: peer meta data
  874. */
  875. static inline uint32_t
  876. hal_rx_tlv_peer_meta_data_get(hal_soc_handle_t hal_soc_hdl,
  877. uint8_t *buf)
  878. {
  879. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  880. return hal_soc->ops->hal_rx_tlv_peer_meta_data_get(buf);
  881. }
  882. /**
  883. * hal_rx_mpdu_get_to_ds() - API to get the tods info from rx_mpdu_start
  884. * @hal_soc_hdl: hal_soc handle
  885. * @buf: pointer to the start of RX PKT TLV header
  886. *
  887. * Return: uint32_t(to_ds)
  888. */
  889. static inline uint32_t
  890. hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  891. {
  892. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  893. return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf);
  894. }
  895. /**
  896. * hal_rx_mpdu_get_fr_ds() - API to get the from ds info
  897. * from rx_mpdu_start
  898. * @hal_soc_hdl: hal soc handle
  899. * @buf: pointer to the start of RX PKT TLV header
  900. *
  901. * Return: uint32_t(fr_ds)
  902. */
  903. static inline uint32_t
  904. hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  905. {
  906. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  907. return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf);
  908. }
  909. /**
  910. * hal_rx_mpdu_get_addr1() - API to check get address1 of the mpdu
  911. * @hal_soc_hdl: hal soc handle
  912. * @buf: pointer to the start of RX PKT TLV headera
  913. * @mac_addr: pointer to mac address
  914. *
  915. * Return: success/failure
  916. */
  917. static inline
  918. QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl,
  919. uint8_t *buf, uint8_t *mac_addr)
  920. {
  921. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  922. return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr);
  923. }
  924. /**
  925. * hal_rx_mpdu_get_addr2() - API to check get address2 of the mpdu
  926. * in the packet
  927. * @hal_soc_hdl: hal soc handle
  928. * @buf: pointer to the start of RX PKT TLV header
  929. * @mac_addr: pointer to mac address
  930. *
  931. * Return: success/failure
  932. */
  933. static inline
  934. QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl,
  935. uint8_t *buf, uint8_t *mac_addr)
  936. {
  937. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  938. return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr);
  939. }
  940. /**
  941. * hal_rx_mpdu_get_addr3() - API to get address3 of the mpdu
  942. * in the packet
  943. * @hal_soc_hdl: hal soc handle
  944. * @buf: pointer to the start of RX PKT TLV header
  945. * @mac_addr: pointer to mac address
  946. *
  947. * Return: success/failure
  948. */
  949. static inline
  950. QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl,
  951. uint8_t *buf, uint8_t *mac_addr)
  952. {
  953. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  954. return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr);
  955. }
  956. /**
  957. * hal_rx_mpdu_get_addr4() - API to get address4 of the mpdu
  958. * in the packet
  959. * @hal_soc_hdl: hal_soc handle
  960. * @buf: pointer to the start of RX PKT TLV header
  961. * @mac_addr: pointer to mac address
  962. * Return: success/failure
  963. */
  964. static inline
  965. QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl,
  966. uint8_t *buf, uint8_t *mac_addr)
  967. {
  968. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  969. return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr);
  970. }
  971. /**
  972. * hal_rx_msdu_end_da_idx_get() - API to get da_idx from rx_msdu_end TLV
  973. * @hal_soc_hdl: hal_soc handle
  974. * @buf: pointer to the start of RX PKT TLV headers
  975. *
  976. * Return: da index
  977. */
  978. static inline uint16_t
  979. hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  980. {
  981. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  982. return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf);
  983. }
  984. /**
  985. * hal_rx_msdu_end_da_is_valid_get() - API to check if da is valid
  986. * from rx_msdu_end TLV
  987. * @hal_soc_hdl: hal soc handle
  988. * @buf: pointer to the start of RX PKT TLV headers
  989. *
  990. * Return: da_is_valid
  991. */
  992. static inline uint8_t
  993. hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl,
  994. uint8_t *buf)
  995. {
  996. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  997. return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf);
  998. }
  999. /**
  1000. * hal_rx_msdu_end_da_is_mcbc_get() - API to check if pkt is MCBC
  1001. * from rx_msdu_end TLV
  1002. * @hal_soc_hdl: HAL SOC handle
  1003. * @buf: pointer to the start of RX PKT TLV headers
  1004. *
  1005. * Return: da_is_mcbc
  1006. */
  1007. static inline uint8_t
  1008. hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1009. {
  1010. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1011. return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf);
  1012. }
  1013. /**
  1014. * hal_rx_msdu_end_is_tkip_mic_err() - API to check if pkt has mic error
  1015. * from rx_msdu_end TLV
  1016. * @hal_soc_hdl: HAL SOC handle
  1017. * @buf: pointer to the start of RX PKT TLV headers
  1018. *
  1019. * Return: tkip_mic_err
  1020. */
  1021. static inline uint8_t
  1022. hal_rx_msdu_end_is_tkip_mic_err(hal_soc_handle_t hal_soc_hdl,
  1023. uint8_t *buf)
  1024. {
  1025. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1026. if (hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err)
  1027. return hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err(buf);
  1028. else
  1029. return 0;
  1030. }
  1031. /**
  1032. * hal_rx_msdu_end_first_msdu_get() - API to get first msdu status
  1033. * from rx_msdu_end TLV
  1034. * @hal_soc_hdl: hal soc handle
  1035. * @buf: pointer to the start of RX PKT TLV headers
  1036. *
  1037. * Return: first_msdu
  1038. */
  1039. static inline uint8_t
  1040. hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl,
  1041. uint8_t *buf)
  1042. {
  1043. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1044. return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf);
  1045. }
  1046. /**
  1047. * hal_rx_msdu_end_last_msdu_get() - API to get last msdu status
  1048. * from rx_msdu_end TLV
  1049. * @hal_soc_hdl: hal soc handle
  1050. * @buf: pointer to the start of RX PKT TLV headers
  1051. *
  1052. * Return: last_msdu
  1053. */
  1054. static inline uint8_t
  1055. hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl,
  1056. uint8_t *buf)
  1057. {
  1058. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1059. return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf);
  1060. }
  1061. /**
  1062. * hal_rx_msdu_cce_match_get() - API to get CCE match from rx_msdu_end TLV
  1063. * @hal_soc_hdl: HAL SOC handle
  1064. * @buf: pointer to the start of RX PKT TLV headers
  1065. *
  1066. * Return: cce_meta_data
  1067. */
  1068. static inline bool
  1069. hal_rx_msdu_cce_match_get(hal_soc_handle_t hal_soc_hdl,
  1070. uint8_t *buf)
  1071. {
  1072. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1073. return hal_soc->ops->hal_rx_msdu_cce_match_get(buf);
  1074. }
  1075. /**
  1076. * hal_rx_msdu_cce_metadata_get() - API to get CCE metadata
  1077. * from rx_msdu_end TLV
  1078. * @hal_soc_hdl: HAL SOC handle
  1079. * @buf: pointer to the start of RX PKT TLV headers
  1080. *
  1081. * Return: cce_meta_data
  1082. */
  1083. static inline uint16_t
  1084. hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl,
  1085. uint8_t *buf)
  1086. {
  1087. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1088. return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf);
  1089. }
  1090. /*******************************************************************************
  1091. * RX REO ERROR APIS
  1092. ******************************************************************************/
  1093. /**
  1094. * hal_rx_link_desc_msdu0_ptr() - Get pointer to rx_msdu details
  1095. * @msdu_link_ptr: msdu link ptr
  1096. * @hal_soc: pointer to hal_soc
  1097. *
  1098. * Return: Pointer to rx_msdu_details structure
  1099. *
  1100. */
  1101. static inline
  1102. void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr,
  1103. struct hal_soc *hal_soc)
  1104. {
  1105. return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr);
  1106. }
  1107. /**
  1108. * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr
  1109. * @msdu_details_ptr: Pointer to msdu_details_ptr
  1110. * @hal_soc: pointer to hal_soc
  1111. *
  1112. * Return: Pointer to rx_msdu_desc_info structure.
  1113. *
  1114. */
  1115. static inline
  1116. void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr,
  1117. struct hal_soc *hal_soc)
  1118. {
  1119. return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr);
  1120. }
  1121. /**
  1122. * hal_rx_reo_buf_paddr_get() - Gets the physical address and
  1123. * cookie from the REO destination ring element
  1124. * @hal_soc_hdl: HAL SOC handle
  1125. * @rx_desc: the current descriptor
  1126. * @buf_info: structure to return the buffer information
  1127. *
  1128. * Return: void
  1129. */
  1130. static inline
  1131. void hal_rx_reo_buf_paddr_get(hal_soc_handle_t hal_soc_hdl,
  1132. hal_ring_desc_t rx_desc,
  1133. struct hal_buf_info *buf_info)
  1134. {
  1135. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1136. if (hal_soc->ops->hal_rx_reo_buf_paddr_get)
  1137. return hal_soc->ops->hal_rx_reo_buf_paddr_get(
  1138. rx_desc,
  1139. buf_info);
  1140. }
  1141. /**
  1142. * hal_rx_wbm_rel_buf_paddr_get() - Gets the physical address and
  1143. * cookie from the WBM release ring element
  1144. * @hal_soc_hdl: HAL SOC handle
  1145. * @rx_desc: the current descriptor
  1146. * @buf_info: structure to return the buffer information
  1147. *
  1148. * Return: void
  1149. */
  1150. static inline
  1151. void hal_rx_wbm_rel_buf_paddr_get(hal_soc_handle_t hal_soc_hdl,
  1152. hal_ring_desc_t rx_desc,
  1153. struct hal_buf_info *buf_info)
  1154. {
  1155. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1156. if (hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get)
  1157. return hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get(rx_desc,
  1158. buf_info);
  1159. }
  1160. /**
  1161. * hal_rx_buf_cookie_rbm_get() - Gets the physical address and cookie
  1162. * from the REO entrance ring element
  1163. * @hal_soc_hdl: hal soc handle
  1164. * @buf_addr_info: pointer to buf_addr_info structure
  1165. * @buf_info: structure to return the buffer information
  1166. *
  1167. * Return: void
  1168. */
  1169. static inline
  1170. void hal_rx_buf_cookie_rbm_get(hal_soc_handle_t hal_soc_hdl,
  1171. uint32_t *buf_addr_info,
  1172. struct hal_buf_info *buf_info)
  1173. {
  1174. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1175. return hal_soc->ops->hal_rx_buf_cookie_rbm_get(
  1176. buf_addr_info,
  1177. buf_info);
  1178. }
  1179. /**
  1180. * hal_rx_msdu_list_get() - API to get the MSDU information
  1181. * from the MSDU link descriptor
  1182. * @hal_soc_hdl: hal soc handle
  1183. * @msdu_link_desc: Opaque pointer used by HAL to get to the
  1184. * MSDU link descriptor (struct rx_msdu_link)
  1185. * @msdu_list: Return the list of MSDUs contained in this link descriptor
  1186. * @num_msdus: Number of MSDUs in the MPDU
  1187. *
  1188. * Return: void
  1189. */
  1190. static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl,
  1191. void *msdu_link_desc,
  1192. struct hal_rx_msdu_list *msdu_list,
  1193. uint16_t *num_msdus)
  1194. {
  1195. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1196. struct rx_msdu_details *msdu_details;
  1197. struct rx_msdu_desc_info *msdu_desc_info;
  1198. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  1199. int i;
  1200. struct hal_buf_info buf_info;
  1201. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  1202. dp_nofl_debug("[%s][%d] msdu_link=%pK msdu_details=%pK",
  1203. __func__, __LINE__, msdu_link, msdu_details);
  1204. for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
  1205. /* num_msdus received in mpdu descriptor may be incorrect
  1206. * sometimes due to HW issue. Check msdu buffer address also
  1207. */
  1208. if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET(
  1209. &msdu_details[i].buffer_addr_info_details) == 0))
  1210. break;
  1211. if (HAL_RX_BUFFER_ADDR_31_0_GET(
  1212. &msdu_details[i].buffer_addr_info_details) == 0) {
  1213. /* set the last msdu bit in the prev msdu_desc_info */
  1214. msdu_desc_info =
  1215. hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc);
  1216. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1217. break;
  1218. }
  1219. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i],
  1220. hal_soc);
  1221. /* set first MSDU bit or the last MSDU bit */
  1222. if (!i)
  1223. HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1224. else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
  1225. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1226. msdu_list->msdu_info[i].msdu_flags =
  1227. hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info);
  1228. msdu_list->msdu_info[i].msdu_len =
  1229. HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info);
  1230. /* addr field in buf_info will not be valid */
  1231. hal_rx_buf_cookie_rbm_get(
  1232. hal_soc_hdl,
  1233. (uint32_t *)&msdu_details[i].buffer_addr_info_details,
  1234. &buf_info);
  1235. msdu_list->sw_cookie[i] = buf_info.sw_cookie;
  1236. msdu_list->rbm[i] = buf_info.rbm;
  1237. msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET(
  1238. &msdu_details[i].buffer_addr_info_details) |
  1239. (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET(
  1240. &msdu_details[i].buffer_addr_info_details) << 32;
  1241. dp_nofl_debug("[%s][%d] i=%d sw_cookie=%d",
  1242. __func__, __LINE__, i, msdu_list->sw_cookie[i]);
  1243. }
  1244. *num_msdus = i;
  1245. }
  1246. /**
  1247. * hal_rx_reo_is_pn_error() - Indicate if this error was caused by a
  1248. * PN check failure
  1249. * @error_code: error code obtained from ring descriptor.
  1250. *
  1251. * Return: true: error caused by PN check, false: other error
  1252. */
  1253. static inline bool hal_rx_reo_is_pn_error(uint32_t error_code)
  1254. {
  1255. return ((error_code == HAL_REO_ERR_PN_CHECK_FAILED) ||
  1256. (error_code == HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ?
  1257. true : false;
  1258. }
  1259. /**
  1260. * hal_rx_reo_is_2k_jump() - Indicate if this error was caused by a 2K jump in
  1261. * the sequence number
  1262. * @error_code: error code obtained from ring descriptor.
  1263. *
  1264. * Return: true: error caused by 2K jump, false: other error
  1265. */
  1266. static inline bool hal_rx_reo_is_2k_jump(uint32_t error_code)
  1267. {
  1268. return ((error_code == HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) ||
  1269. (error_code == HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ?
  1270. true : false;
  1271. }
  1272. /**
  1273. * hal_rx_reo_is_oor_error() - Indicate if this error was caused by OOR
  1274. * @error_code: error code obtained from ring descriptor.
  1275. *
  1276. * Return: true: error caused by OOR, false: other error
  1277. */
  1278. static inline bool hal_rx_reo_is_oor_error(uint32_t error_code)
  1279. {
  1280. return (error_code == HAL_REO_ERR_REGULAR_FRAME_OOR) ?
  1281. true : false;
  1282. }
  1283. /**
  1284. * hal_rx_reo_is_bar_oor_2k_jump() - Check if the error is 2k-jump or OOR error
  1285. * @error_code: error code obtained from ring descriptor.
  1286. *
  1287. * Return: true, if the error code is 2k-jump or OOR
  1288. * false, for other error codes.
  1289. */
  1290. static inline bool hal_rx_reo_is_bar_oor_2k_jump(uint32_t error_code)
  1291. {
  1292. return ((error_code == HAL_REO_ERR_BAR_FRAME_2K_JUMP) ||
  1293. (error_code == HAL_REO_ERR_BAR_FRAME_OOR)) ?
  1294. true : false;
  1295. }
  1296. /**
  1297. * hal_dump_wbm_rel_desc() - dump wbm release descriptor
  1298. * @src_srng_desc: hardware descriptor pointer
  1299. *
  1300. * This function will print wbm release descriptor
  1301. *
  1302. * Return: none
  1303. */
  1304. static inline void hal_dump_wbm_rel_desc(void *src_srng_desc)
  1305. {
  1306. uint32_t *wbm_comp = (uint32_t *)src_srng_desc;
  1307. uint32_t i;
  1308. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  1309. "Current Rx wbm release descriptor is");
  1310. for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) {
  1311. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  1312. "DWORD[i] = 0x%x", wbm_comp[i]);
  1313. }
  1314. }
  1315. /**
  1316. * hal_rx_msdu_link_desc_set() - Retrieves MSDU Link Descriptor to WBM
  1317. *
  1318. * @hal_soc_hdl: HAL version of the SOC pointer
  1319. * @src_srng_desc: void pointer to the WBM Release Ring descriptor
  1320. * @buf_addr_info: void pointer to the buffer_addr_info
  1321. * @bm_action: put in IDLE list or release to MSDU_LIST
  1322. *
  1323. * Return: void
  1324. */
  1325. /* look at implementation at dp_hw_link_desc_pool_setup()*/
  1326. static inline
  1327. void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl,
  1328. void *src_srng_desc,
  1329. hal_buff_addrinfo_t buf_addr_info,
  1330. uint8_t bm_action)
  1331. {
  1332. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1333. if (hal_soc->ops->hal_rx_msdu_link_desc_set)
  1334. return hal_soc->ops->hal_rx_msdu_link_desc_set(hal_soc_hdl,
  1335. src_srng_desc,
  1336. buf_addr_info,
  1337. bm_action);
  1338. }
  1339. /**
  1340. * HAL_RX_BUF_ADDR_INFO_GET() - Returns the address of the
  1341. * BUFFER_ADDR_INFO, give the RX descriptor
  1342. * (Assumption -- BUFFER_ADDR_INFO is the
  1343. * first field in the descriptor structure)
  1344. * @ring_desc: RX descriptor
  1345. *
  1346. * Return: pointer to buffer addr info
  1347. */
  1348. #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \
  1349. ((hal_link_desc_t)(ring_desc))
  1350. #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET
  1351. #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET
  1352. /*******************************************************************************
  1353. * RX WBM ERROR APIS
  1354. ******************************************************************************/
  1355. #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \
  1356. (WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \
  1357. WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK) >> \
  1358. WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB)
  1359. /**
  1360. * enum hal_rx_wbm_reo_push_reason - Indicates why REO pushed
  1361. * the frame to this release ring
  1362. *
  1363. * @HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this
  1364. * frame to this queue
  1365. * @HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per
  1366. * received routing instructions. No error within REO was detected
  1367. */
  1368. enum hal_rx_wbm_reo_push_reason {
  1369. HAL_RX_WBM_REO_PSH_RSN_ERROR = 0,
  1370. HAL_RX_WBM_REO_PSH_RSN_ROUTE,
  1371. };
  1372. /**
  1373. * enum hal_rx_wbm_rxdma_push_reason - Indicates why REO pushed the frame to
  1374. * this release ring
  1375. *
  1376. * @HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed
  1377. * this frame to this queue
  1378. * @HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue
  1379. * per received routing instructions. No error within RXDMA was detected
  1380. * @HAL_RX_WBM_RXDMA_PSH_RSN_FLUSH:
  1381. */
  1382. enum hal_rx_wbm_rxdma_push_reason {
  1383. HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0,
  1384. HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE,
  1385. HAL_RX_WBM_RXDMA_PSH_RSN_FLUSH,
  1386. };
  1387. static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start,
  1388. uint8_t dbg_level,
  1389. struct hal_soc *hal)
  1390. {
  1391. hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level);
  1392. }
  1393. /**
  1394. * hal_rx_dump_msdu_end_tlv() - dump RX msdu_end TLV in structured
  1395. * human readable format.
  1396. * @hal_soc: HAL soc
  1397. * @msdu_end: pointer the msdu_end TLV in pkt.
  1398. * @dbg_level: log level.
  1399. *
  1400. * Return: void
  1401. */
  1402. static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc,
  1403. struct rx_msdu_end *msdu_end,
  1404. uint8_t dbg_level)
  1405. {
  1406. hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level);
  1407. }
  1408. /**
  1409. * hal_srng_ring_id_get() - API to retrieve ring id from hal ring
  1410. * structure
  1411. * @hal_ring_hdl: handle to hal_srng structure
  1412. *
  1413. * Return: ring_id
  1414. */
  1415. static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl)
  1416. {
  1417. return ((struct hal_srng *)hal_ring_hdl)->ring_id;
  1418. }
  1419. #define DOT11_SEQ_FRAG_MASK 0x000f
  1420. #define DOT11_FC1_MORE_FRAG_OFFSET 0x04
  1421. /**
  1422. * hal_rx_get_rx_fragment_number() - Function to retrieve rx fragment number
  1423. * @hal_soc: HAL soc
  1424. * @buf: Network buffer
  1425. *
  1426. * Return: rx fragment number
  1427. */
  1428. static inline
  1429. uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc,
  1430. uint8_t *buf)
  1431. {
  1432. return hal_soc->ops->hal_rx_get_rx_fragment_number(buf);
  1433. }
  1434. /**
  1435. * hal_rx_get_mpdu_sequence_control_valid() - Get mpdu sequence control valid
  1436. * @hal_soc_hdl: hal soc handle
  1437. * @buf: Network buffer
  1438. *
  1439. * Return: value of sequence control valid field
  1440. */
  1441. static inline
  1442. uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl,
  1443. uint8_t *buf)
  1444. {
  1445. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1446. return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf);
  1447. }
  1448. /**
  1449. * hal_rx_get_mpdu_frame_control_valid() - Retrieves mpdu frame control valid
  1450. * @hal_soc_hdl: hal soc handle
  1451. * @buf: Network buffer
  1452. *
  1453. * Return: value of frame control valid field
  1454. */
  1455. static inline
  1456. uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl,
  1457. uint8_t *buf)
  1458. {
  1459. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1460. return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf);
  1461. }
  1462. /**
  1463. * hal_rx_get_mpdu_mac_ad4_valid() - Retrieves if mpdu 4th addr is valid
  1464. * @hal_soc_hdl: hal soc handle
  1465. * @buf: Network buffer
  1466. *
  1467. * Return: value of mpdu 4th address valid field
  1468. */
  1469. static inline
  1470. bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl,
  1471. uint8_t *buf)
  1472. {
  1473. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1474. return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf);
  1475. }
  1476. /**
  1477. * hal_rx_clear_mpdu_desc_info() - Clears mpdu_desc_info
  1478. * @rx_mpdu_desc_info: HAL view of rx mpdu desc info
  1479. *
  1480. * Return: None
  1481. */
  1482. static inline void
  1483. hal_rx_clear_mpdu_desc_info(struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info)
  1484. {
  1485. qdf_mem_zero(rx_mpdu_desc_info, sizeof(*rx_mpdu_desc_info));
  1486. }
  1487. /**
  1488. * hal_rx_wbm_err_info_get() - Retrieves WBM error code and reason and
  1489. * save it to hal_wbm_err_desc_info structure passed by caller
  1490. * @wbm_desc: wbm ring descriptor
  1491. * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter.
  1492. * @hal_soc_hdl: HAL SOC handle
  1493. *
  1494. * Return: void
  1495. */
  1496. static inline
  1497. void hal_rx_wbm_err_info_get(void *wbm_desc,
  1498. struct hal_wbm_err_desc_info *wbm_er_info,
  1499. hal_soc_handle_t hal_soc_hdl)
  1500. {
  1501. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1502. hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info);
  1503. }
  1504. /**
  1505. * hal_rx_wbm_err_msdu_continuation_get() - Get wbm msdu continuation
  1506. * bit from wbm release ring descriptor
  1507. * @hal_soc_hdl: HAL SOC handle
  1508. * @wbm_desc: wbm ring descriptor
  1509. *
  1510. * Return: uint8_t
  1511. */
  1512. static inline
  1513. uint8_t hal_rx_wbm_err_msdu_continuation_get(hal_soc_handle_t hal_soc_hdl,
  1514. void *wbm_desc)
  1515. {
  1516. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1517. return hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get(wbm_desc);
  1518. }
  1519. /**
  1520. * hal_rx_mon_hw_desc_get_mpdu_status() - Retrieve MPDU status
  1521. * @hal_soc_hdl: HAL SOC handle
  1522. * @hw_desc_addr: Start address of Rx HW TLVs
  1523. * @rs: Status for monitor mode
  1524. *
  1525. * Return: void
  1526. */
  1527. static inline
  1528. void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl,
  1529. void *hw_desc_addr,
  1530. struct mon_rx_status *rs)
  1531. {
  1532. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1533. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs);
  1534. }
  1535. /**
  1536. * hal_rx_get_tlv() - API to get the tlv
  1537. *
  1538. * @hal_soc: HAL version of the SOC pointer
  1539. * @rx_tlv: TLV data extracted from the rx packet
  1540. *
  1541. * Return: uint8_t
  1542. */
  1543. static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv)
  1544. {
  1545. return hal_soc->ops->hal_rx_get_tlv(rx_tlv);
  1546. }
  1547. /**
  1548. * hal_rx_msdu_start_nss_get() - API to get the NSS
  1549. * Interval from rx_msdu_start
  1550. * @hal_soc_hdl: HAL SOC handle
  1551. * @buf: pointer to the start of RX PKT TLV header
  1552. *
  1553. * Return: uint32_t(nss)
  1554. */
  1555. static inline
  1556. uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1557. {
  1558. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1559. return hal_soc->ops->hal_rx_msdu_start_nss_get(buf);
  1560. }
  1561. /**
  1562. * hal_rx_dump_msdu_start_tlv() - dump RX msdu_start TLV in structured
  1563. * human readable format.
  1564. * @hal_soc: HAL SOC
  1565. * @msdu_start: pointer the msdu_start TLV in pkt.
  1566. * @dbg_level: log level.
  1567. *
  1568. * Return: void
  1569. */
  1570. static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc,
  1571. struct rx_msdu_start *msdu_start,
  1572. uint8_t dbg_level)
  1573. {
  1574. hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level);
  1575. }
  1576. /**
  1577. * hal_rx_mpdu_start_tid_get() - Return tid info from the rx mpdu start
  1578. * info details
  1579. * @hal_soc_hdl: HAL SOC handle
  1580. * @buf: Pointer to buffer containing rx pkt tlvs.
  1581. *
  1582. *
  1583. */
  1584. static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl,
  1585. uint8_t *buf)
  1586. {
  1587. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1588. return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf);
  1589. }
  1590. /**
  1591. * hal_rx_msdu_start_reception_type_get() - API to get the reception type
  1592. * Interval from rx_msdu_start
  1593. * @hal_soc_hdl: hal_soc handle
  1594. * @buf: pointer to the start of RX PKT TLV header
  1595. *
  1596. * Return: uint32_t(reception_type)
  1597. */
  1598. static inline
  1599. uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl,
  1600. uint8_t *buf)
  1601. {
  1602. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1603. return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf);
  1604. }
  1605. /**
  1606. * hal_reo_status_get_header() - Process reo desc info
  1607. * @ring_desc: Pointer to reo descriptor
  1608. * @b: tlv type info
  1609. * @h: Pointer to hal_reo_status_header where info to be stored
  1610. * @hal_soc: pointer to hal_soc structure
  1611. *
  1612. * Return: none.
  1613. *
  1614. */
  1615. static inline
  1616. void hal_reo_status_get_header(hal_ring_desc_t ring_desc, int b,
  1617. void *h, struct hal_soc *hal_soc)
  1618. {
  1619. hal_soc->ops->hal_reo_status_get_header(ring_desc, b, h);
  1620. }
  1621. /**
  1622. * hal_rx_desc_is_first_msdu() - Check if first msdu
  1623. *
  1624. * @hal_soc_hdl: hal_soc handle
  1625. * @hw_desc_addr: hardware descriptor address
  1626. *
  1627. * Return: 0 - success/ non-zero failure
  1628. */
  1629. static inline
  1630. uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl,
  1631. void *hw_desc_addr)
  1632. {
  1633. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1634. return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr);
  1635. }
  1636. /**
  1637. * hal_rx_tlv_populate_mpdu_desc_info() - Populate mpdu_desc_info fields from
  1638. * the rx tlv fields.
  1639. * @hal_soc_hdl: HAL SoC handle
  1640. * @buf: rx tlv start address [To be validated by caller]
  1641. * @mpdu_desc_info_hdl: Buffer where the mpdu_desc_info is to be populated.
  1642. *
  1643. * Return: None
  1644. */
  1645. static inline void
  1646. hal_rx_tlv_populate_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
  1647. uint8_t *buf,
  1648. void *mpdu_desc_info_hdl)
  1649. {
  1650. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1651. if (hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info)
  1652. return hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info(buf,
  1653. mpdu_desc_info_hdl);
  1654. }
  1655. static inline uint32_t
  1656. hal_rx_tlv_decap_format_get(hal_soc_handle_t hal_soc_hdl, void *hw_desc_addr)
  1657. {
  1658. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1659. return hal_soc->ops->hal_rx_tlv_decap_format_get(hw_desc_addr);
  1660. }
  1661. static inline
  1662. bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl,
  1663. uint8_t *rx_tlv_hdr)
  1664. {
  1665. uint8_t decap_format;
  1666. if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) {
  1667. decap_format = hal_rx_tlv_decap_format_get(hal_soc_hdl,
  1668. rx_tlv_hdr);
  1669. if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW)
  1670. return true;
  1671. }
  1672. return false;
  1673. }
  1674. /**
  1675. * hal_rx_msdu_fse_metadata_get() - API to get FSE metadata
  1676. * from rx_msdu_end TLV
  1677. * @hal_soc_hdl: HAL SOC handle
  1678. * @buf: pointer to the start of RX PKT TLV headers
  1679. *
  1680. * Return: fse metadata value from MSDU END TLV
  1681. */
  1682. static inline uint32_t
  1683. hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl,
  1684. uint8_t *buf)
  1685. {
  1686. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1687. return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf);
  1688. }
  1689. /**
  1690. * hal_rx_buffer_addr_info_get_paddr() - get paddr/sw_cookie from
  1691. * <struct buffer_addr_info> structure
  1692. * @buf_addr_info: pointer to <struct buffer_addr_info> structure
  1693. * @buf_info: structure to return the buffer information including
  1694. * paddr/cookie
  1695. *
  1696. * Return: None
  1697. */
  1698. static inline
  1699. void hal_rx_buffer_addr_info_get_paddr(void *buf_addr_info,
  1700. struct hal_buf_info *buf_info)
  1701. {
  1702. buf_info->paddr =
  1703. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  1704. ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  1705. }
  1706. /**
  1707. * hal_rx_msdu_flow_idx_get() - API to get flow index from rx_msdu_end TLV
  1708. * @hal_soc_hdl: HAL SOC handle
  1709. * @buf: pointer to the start of RX PKT TLV headers
  1710. *
  1711. * Return: flow index value from MSDU END TLV
  1712. */
  1713. static inline uint32_t
  1714. hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl,
  1715. uint8_t *buf)
  1716. {
  1717. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1718. return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf);
  1719. }
  1720. /**
  1721. * hal_rx_msdu_get_reo_destination_indication() - API to get reo
  1722. * destination index from rx_msdu_end TLV
  1723. * @hal_soc_hdl: HAL SOC handle
  1724. * @buf: pointer to the start of RX PKT TLV headers
  1725. * @reo_destination_indication: pointer to return value of
  1726. * reo_destination_indication
  1727. *
  1728. * Return: reo_destination_indication value from MSDU END TLV
  1729. */
  1730. static inline void
  1731. hal_rx_msdu_get_reo_destination_indication(hal_soc_handle_t hal_soc_hdl,
  1732. uint8_t *buf,
  1733. uint32_t *reo_destination_indication)
  1734. {
  1735. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1736. hal_soc->ops->hal_rx_msdu_get_reo_destination_indication(buf,
  1737. reo_destination_indication);
  1738. }
  1739. /**
  1740. * hal_rx_msdu_flow_idx_timeout() - API to get flow index timeout
  1741. * from rx_msdu_end TLV
  1742. * @hal_soc_hdl: HAL SOC handle
  1743. * @buf: pointer to the start of RX PKT TLV headers
  1744. *
  1745. * Return: flow index timeout value from MSDU END TLV
  1746. */
  1747. static inline bool
  1748. hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl,
  1749. uint8_t *buf)
  1750. {
  1751. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1752. return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf);
  1753. }
  1754. /**
  1755. * hal_rx_msdu_flow_idx_invalid() - API to get flow index invalid
  1756. * from rx_msdu_end TLV
  1757. * @hal_soc_hdl: HAL SOC handle
  1758. * @buf: pointer to the start of RX PKT TLV headers
  1759. *
  1760. * Return: flow index invalid value from MSDU END TLV
  1761. */
  1762. static inline bool
  1763. hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl,
  1764. uint8_t *buf)
  1765. {
  1766. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1767. return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf);
  1768. }
  1769. /**
  1770. * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id
  1771. * @hal_soc_hdl: hal_soc handle
  1772. * @rx_tlv_hdr: Rx_tlv_hdr
  1773. * @rxdma_dst_ring_desc: Rx HW descriptor
  1774. *
  1775. * Return: ppdu id
  1776. */
  1777. static inline
  1778. uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl,
  1779. void *rx_tlv_hdr,
  1780. void *rxdma_dst_ring_desc)
  1781. {
  1782. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1783. return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(rx_tlv_hdr,
  1784. rxdma_dst_ring_desc);
  1785. }
  1786. /**
  1787. * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id
  1788. * @hal_soc_hdl: hal_soc handle
  1789. * @buf: rx tlv address
  1790. *
  1791. * Return: sw peer id
  1792. */
  1793. static inline
  1794. uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl,
  1795. uint8_t *buf)
  1796. {
  1797. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1798. return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf);
  1799. }
  1800. static inline
  1801. void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl,
  1802. void *link_desc_addr)
  1803. {
  1804. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1805. return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr);
  1806. }
  1807. static inline
  1808. void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl,
  1809. void *msdu_addr)
  1810. {
  1811. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1812. return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr);
  1813. }
  1814. static inline
  1815. void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
  1816. void *hw_addr)
  1817. {
  1818. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1819. return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr);
  1820. }
  1821. static inline
  1822. void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
  1823. void *hw_addr)
  1824. {
  1825. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1826. return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr);
  1827. }
  1828. static inline
  1829. uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl,
  1830. uint8_t *buf)
  1831. {
  1832. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1833. return hal_soc->ops->hal_rx_get_fc_valid(buf);
  1834. }
  1835. static inline
  1836. uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1837. {
  1838. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1839. return hal_soc->ops->hal_rx_get_to_ds_flag(buf);
  1840. }
  1841. static inline
  1842. uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl,
  1843. uint8_t *buf)
  1844. {
  1845. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1846. return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf);
  1847. }
  1848. static inline
  1849. uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl,
  1850. uint8_t *buf)
  1851. {
  1852. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1853. return hal_soc->ops->hal_rx_get_filter_category(buf);
  1854. }
  1855. static inline
  1856. uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl,
  1857. uint8_t *buf)
  1858. {
  1859. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1860. return hal_soc->ops->hal_rx_get_ppdu_id(buf);
  1861. }
  1862. /**
  1863. * hal_reo_config() - Set reo config parameters
  1864. * @hal_soc: hal soc handle
  1865. * @reg_val: value to be set
  1866. * @reo_params: reo parameters
  1867. *
  1868. * Return: void
  1869. */
  1870. static inline
  1871. void hal_reo_config(struct hal_soc *hal_soc,
  1872. uint32_t reg_val,
  1873. struct hal_reo_params *reo_params)
  1874. {
  1875. hal_soc->ops->hal_reo_config(hal_soc,
  1876. reg_val,
  1877. reo_params);
  1878. }
  1879. /**
  1880. * hal_rx_msdu_get_flow_params() - API to get flow index,
  1881. * flow index invalid and flow index timeout from rx_msdu_end TLV
  1882. * @hal_soc_hdl: HAL SOC handle
  1883. * @buf: pointer to the start of RX PKT TLV headers
  1884. * @flow_invalid: pointer to return value of flow_idx_valid
  1885. * @flow_timeout: pointer to return value of flow_idx_timeout
  1886. * @flow_index: pointer to return value of flow_idx
  1887. *
  1888. * Return: none
  1889. */
  1890. static inline void
  1891. hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl,
  1892. uint8_t *buf,
  1893. bool *flow_invalid,
  1894. bool *flow_timeout,
  1895. uint32_t *flow_index)
  1896. {
  1897. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1898. hal_soc->ops->hal_rx_msdu_get_flow_params(buf,
  1899. flow_invalid,
  1900. flow_timeout,
  1901. flow_index);
  1902. }
  1903. static inline
  1904. uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl,
  1905. uint8_t *buf)
  1906. {
  1907. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1908. return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf);
  1909. }
  1910. static inline
  1911. uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl,
  1912. uint8_t *buf)
  1913. {
  1914. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1915. return hal_soc->ops->hal_rx_get_rx_sequence(buf);
  1916. }
  1917. static inline void
  1918. hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl,
  1919. void *rx_tlv,
  1920. void *ppdu_info)
  1921. {
  1922. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1923. if (hal_soc->ops->hal_rx_get_bb_info)
  1924. hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info);
  1925. }
  1926. static inline void
  1927. hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl,
  1928. void *rx_tlv,
  1929. void *ppdu_info)
  1930. {
  1931. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1932. if (hal_soc->ops->hal_rx_get_rtt_info)
  1933. hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info);
  1934. }
  1935. /**
  1936. * hal_rx_msdu_metadata_get() - API to get the
  1937. * fast path information from rx_msdu_end TLV
  1938. *
  1939. * @hal_soc_hdl: DP soc handle
  1940. * @buf: pointer to the start of RX PKT TLV headers
  1941. * @msdu_md: Structure to hold msdu end information
  1942. * Return: none
  1943. */
  1944. static inline void
  1945. hal_rx_msdu_metadata_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  1946. struct hal_rx_msdu_metadata *msdu_md)
  1947. {
  1948. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1949. return hal_soc->ops->hal_rx_msdu_packet_metadata_get(buf, msdu_md);
  1950. }
  1951. /**
  1952. * hal_rx_get_fisa_cumulative_l4_checksum() - API to get cumulative_l4_checksum
  1953. * from rx_msdu_end TLV
  1954. * @hal_soc_hdl: HAL SOC handle
  1955. * @buf: pointer to the start of RX PKT TLV headers
  1956. *
  1957. * Return: cumulative_l4_checksum
  1958. */
  1959. static inline uint16_t
  1960. hal_rx_get_fisa_cumulative_l4_checksum(hal_soc_handle_t hal_soc_hdl,
  1961. uint8_t *buf)
  1962. {
  1963. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1964. if (!hal_soc || !hal_soc->ops) {
  1965. hal_err("hal handle is NULL");
  1966. QDF_BUG(0);
  1967. return 0;
  1968. }
  1969. if (!hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum)
  1970. return 0;
  1971. return hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum(buf);
  1972. }
  1973. /**
  1974. * hal_rx_get_fisa_cumulative_ip_length() - API to get cumulative_ip_length
  1975. * from rx_msdu_end TLV
  1976. * @hal_soc_hdl: HAL SOC handle
  1977. * @buf: pointer to the start of RX PKT TLV headers
  1978. *
  1979. * Return: cumulative_ip_length
  1980. */
  1981. static inline uint16_t
  1982. hal_rx_get_fisa_cumulative_ip_length(hal_soc_handle_t hal_soc_hdl,
  1983. uint8_t *buf)
  1984. {
  1985. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1986. if (!hal_soc || !hal_soc->ops) {
  1987. hal_err("hal handle is NULL");
  1988. QDF_BUG(0);
  1989. return 0;
  1990. }
  1991. if (hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length)
  1992. return hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length(buf);
  1993. return 0;
  1994. }
  1995. /**
  1996. * hal_rx_get_udp_proto() - API to get UDP proto field
  1997. * from rx_msdu_start TLV
  1998. * @hal_soc_hdl: HAL SOC handle
  1999. * @buf: pointer to the start of RX PKT TLV headers
  2000. *
  2001. * Return: UDP proto field value
  2002. */
  2003. static inline bool
  2004. hal_rx_get_udp_proto(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2005. {
  2006. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2007. if (!hal_soc || !hal_soc->ops) {
  2008. hal_err("hal handle is NULL");
  2009. QDF_BUG(0);
  2010. return 0;
  2011. }
  2012. if (hal_soc->ops->hal_rx_get_udp_proto)
  2013. return hal_soc->ops->hal_rx_get_udp_proto(buf);
  2014. return 0;
  2015. }
  2016. /**
  2017. * hal_rx_get_fisa_flow_agg_continuation() - API to get fisa
  2018. * flow_agg_continuation from rx_msdu_end TLV
  2019. * @hal_soc_hdl: HAL SOC handle
  2020. * @buf: pointer to the start of RX PKT TLV headers
  2021. *
  2022. * Return: flow_agg_continuation bit field value
  2023. */
  2024. static inline bool
  2025. hal_rx_get_fisa_flow_agg_continuation(hal_soc_handle_t hal_soc_hdl,
  2026. uint8_t *buf)
  2027. {
  2028. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2029. if (!hal_soc || !hal_soc->ops) {
  2030. hal_err("hal handle is NULL");
  2031. QDF_BUG(0);
  2032. return 0;
  2033. }
  2034. if (hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation)
  2035. return hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation(buf);
  2036. return 0;
  2037. }
  2038. /**
  2039. * hal_rx_get_fisa_flow_agg_count() - API to get fisa flow_agg count from
  2040. * rx_msdu_end TLV
  2041. * @hal_soc_hdl: HAL SOC handle
  2042. * @buf: pointer to the start of RX PKT TLV headers
  2043. *
  2044. * Return: flow_agg count value
  2045. */
  2046. static inline uint8_t
  2047. hal_rx_get_fisa_flow_agg_count(hal_soc_handle_t hal_soc_hdl,
  2048. uint8_t *buf)
  2049. {
  2050. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2051. if (!hal_soc || !hal_soc->ops) {
  2052. hal_err("hal handle is NULL");
  2053. QDF_BUG(0);
  2054. return 0;
  2055. }
  2056. if (hal_soc->ops->hal_rx_get_fisa_flow_agg_count)
  2057. return hal_soc->ops->hal_rx_get_fisa_flow_agg_count(buf);
  2058. return 0;
  2059. }
  2060. /**
  2061. * hal_rx_get_fisa_timeout() - API to get fisa time out from rx_msdu_end TLV
  2062. * @hal_soc_hdl: HAL SOC handle
  2063. * @buf: pointer to the start of RX PKT TLV headers
  2064. *
  2065. * Return: fisa flow_agg timeout bit value
  2066. */
  2067. static inline bool
  2068. hal_rx_get_fisa_timeout(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2069. {
  2070. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2071. if (!hal_soc || !hal_soc->ops) {
  2072. hal_err("hal handle is NULL");
  2073. QDF_BUG(0);
  2074. return 0;
  2075. }
  2076. if (hal_soc->ops->hal_rx_get_fisa_timeout)
  2077. return hal_soc->ops->hal_rx_get_fisa_timeout(buf);
  2078. return 0;
  2079. }
  2080. /**
  2081. * hal_rx_mpdu_start_tlv_tag_valid() - API to check if RX_MPDU_START tlv
  2082. * tag is valid
  2083. *
  2084. * @hal_soc_hdl: HAL SOC handle
  2085. * @rx_tlv_hdr: start address of rx_pkt_tlvs
  2086. *
  2087. * Return: true if RX_MPDU_START tlv tag is valid, else false
  2088. */
  2089. static inline uint8_t
  2090. hal_rx_mpdu_start_tlv_tag_valid(hal_soc_handle_t hal_soc_hdl,
  2091. void *rx_tlv_hdr)
  2092. {
  2093. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2094. if (hal->ops->hal_rx_mpdu_start_tlv_tag_valid)
  2095. return hal->ops->hal_rx_mpdu_start_tlv_tag_valid(rx_tlv_hdr);
  2096. return 0;
  2097. }
  2098. /**
  2099. * hal_rx_get_next_msdu_link_desc_buf_addr_info() - get next msdu link desc
  2100. * buffer addr info
  2101. * @link_desc_va: pointer to current msdu link Desc
  2102. * @next_addr_info: buffer to save next msdu link Desc buffer addr info
  2103. *
  2104. * return: None
  2105. */
  2106. static inline void hal_rx_get_next_msdu_link_desc_buf_addr_info(
  2107. void *link_desc_va,
  2108. struct buffer_addr_info *next_addr_info)
  2109. {
  2110. struct rx_msdu_link *msdu_link = link_desc_va;
  2111. if (!msdu_link) {
  2112. qdf_mem_zero(next_addr_info, sizeof(struct buffer_addr_info));
  2113. return;
  2114. }
  2115. *next_addr_info = msdu_link->next_msdu_link_desc_addr_info;
  2116. }
  2117. /**
  2118. * hal_rx_clear_next_msdu_link_desc_buf_addr_info() - clear next msdu link desc
  2119. * buffer addr info
  2120. * @link_desc_va: pointer to current msdu link Desc
  2121. *
  2122. * return: None
  2123. */
  2124. static inline
  2125. void hal_rx_clear_next_msdu_link_desc_buf_addr_info(void *link_desc_va)
  2126. {
  2127. struct rx_msdu_link *msdu_link = link_desc_va;
  2128. if (msdu_link)
  2129. qdf_mem_zero(&msdu_link->next_msdu_link_desc_addr_info,
  2130. sizeof(msdu_link->next_msdu_link_desc_addr_info));
  2131. }
  2132. /**
  2133. * hal_rx_is_buf_addr_info_valid() - check is the buf_addr_info valid
  2134. *
  2135. * @buf_addr_info: pointer to buf_addr_info structure
  2136. *
  2137. * return: true: has valid paddr, false: not.
  2138. */
  2139. static inline
  2140. bool hal_rx_is_buf_addr_info_valid(struct buffer_addr_info *buf_addr_info)
  2141. {
  2142. return (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) == 0) ?
  2143. false : true;
  2144. }
  2145. /**
  2146. * hal_rx_msdu_end_offset_get() - Get the MSDU end offset from
  2147. * rx_pkt_tlvs structure
  2148. *
  2149. * @hal_soc_hdl: HAL SOC handle
  2150. * return: msdu_end_tlv offset value
  2151. */
  2152. static inline
  2153. uint32_t hal_rx_msdu_end_offset_get(hal_soc_handle_t hal_soc_hdl)
  2154. {
  2155. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2156. if (!hal_soc || !hal_soc->ops) {
  2157. hal_err("hal handle is NULL");
  2158. QDF_BUG(0);
  2159. return 0;
  2160. }
  2161. return hal_soc->ops->hal_rx_msdu_end_offset_get();
  2162. }
  2163. /**
  2164. * hal_rx_msdu_start_offset_get() - Get the MSDU start offset from
  2165. * rx_pkt_tlvs structure
  2166. *
  2167. * @hal_soc_hdl: HAL SOC handle
  2168. * return: msdu_start_tlv offset value
  2169. */
  2170. static inline
  2171. uint32_t hal_rx_msdu_start_offset_get(hal_soc_handle_t hal_soc_hdl)
  2172. {
  2173. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2174. if (!hal_soc || !hal_soc->ops) {
  2175. hal_err("hal handle is NULL");
  2176. QDF_BUG(0);
  2177. return 0;
  2178. }
  2179. return hal_soc->ops->hal_rx_msdu_start_offset_get();
  2180. }
  2181. /**
  2182. * hal_rx_mpdu_start_offset_get() - Get the MPDU start offset from
  2183. * rx_pkt_tlvs structure
  2184. *
  2185. * @hal_soc_hdl: HAL SOC handle
  2186. * return: mpdu_start_tlv offset value
  2187. */
  2188. static inline
  2189. uint32_t hal_rx_mpdu_start_offset_get(hal_soc_handle_t hal_soc_hdl)
  2190. {
  2191. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2192. if (!hal_soc || !hal_soc->ops) {
  2193. hal_err("hal handle is NULL");
  2194. QDF_BUG(0);
  2195. return 0;
  2196. }
  2197. return hal_soc->ops->hal_rx_mpdu_start_offset_get();
  2198. }
  2199. static inline
  2200. uint32_t hal_rx_pkt_tlv_offset_get(hal_soc_handle_t hal_soc_hdl)
  2201. {
  2202. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2203. if (!hal_soc || !hal_soc->ops) {
  2204. hal_err("hal handle is NULL");
  2205. QDF_BUG(0);
  2206. return 0;
  2207. }
  2208. return hal_soc->ops->hal_rx_pkt_tlv_offset_get();
  2209. }
  2210. /**
  2211. * hal_rx_mpdu_end_offset_get() - Get the MPDU end offset from
  2212. * rx_pkt_tlvs structure
  2213. *
  2214. * @hal_soc_hdl: HAL SOC handle
  2215. * return: mpdu_end_tlv offset value
  2216. */
  2217. static inline
  2218. uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl)
  2219. {
  2220. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2221. if (!hal_soc || !hal_soc->ops) {
  2222. hal_err("hal handle is NULL");
  2223. QDF_BUG(0);
  2224. return 0;
  2225. }
  2226. return hal_soc->ops->hal_rx_mpdu_end_offset_get();
  2227. }
  2228. #ifdef CONFIG_WORD_BASED_TLV
  2229. /**
  2230. * hal_rx_mpdu_start_wmask_get() - Get the MPDU start word mask
  2231. *
  2232. * @hal_soc_hdl: HAL SOC handle
  2233. * return: mpdu_start_tlv word mask value
  2234. */
  2235. static inline
  2236. uint32_t hal_rx_mpdu_start_wmask_get(hal_soc_handle_t hal_soc_hdl)
  2237. {
  2238. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2239. if (!hal_soc || !hal_soc->ops) {
  2240. hal_err("hal handle is NULL");
  2241. QDF_BUG(0);
  2242. return 0;
  2243. }
  2244. return hal_soc->ops->hal_rx_mpdu_start_wmask_get();
  2245. }
  2246. /**
  2247. * hal_rx_msdu_end_wmask_get() - Get the MSDU END word mask
  2248. *
  2249. * @hal_soc_hdl: HAL SOC handle
  2250. * return: msdu_end_tlv word mask value
  2251. */
  2252. static inline
  2253. uint32_t hal_rx_msdu_end_wmask_get(hal_soc_handle_t hal_soc_hdl)
  2254. {
  2255. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2256. if (!hal_soc || !hal_soc->ops) {
  2257. hal_err("hal handle is NULL");
  2258. QDF_BUG(0);
  2259. return 0;
  2260. }
  2261. return hal_soc->ops->hal_rx_msdu_end_wmask_get();
  2262. }
  2263. #endif
  2264. /**
  2265. * hal_rx_attn_offset_get() - Get the ATTENTION offset from
  2266. * rx_pkt_tlvs structure
  2267. *
  2268. * @hal_soc_hdl: HAL SOC handle
  2269. * return: attn_tlv offset value
  2270. */
  2271. static inline
  2272. uint32_t hal_rx_attn_offset_get(hal_soc_handle_t hal_soc_hdl)
  2273. {
  2274. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2275. if (!hal_soc || !hal_soc->ops) {
  2276. hal_err("hal handle is NULL");
  2277. QDF_BUG(0);
  2278. return 0;
  2279. }
  2280. return hal_soc->ops->hal_rx_attn_offset_get();
  2281. }
  2282. /**
  2283. * hal_rx_msdu_ext_desc_info_get_ptr() - Get msdu extension desc info ptr
  2284. * @msdu_details_ptr: Pointer to msdu_details_ptr
  2285. * @hal_soc: pointer to hal_soc
  2286. *
  2287. * Return: Pointer to rx_msdu_desc_info structure.
  2288. *
  2289. */
  2290. static inline
  2291. void *hal_rx_msdu_ext_desc_info_get_ptr(void *msdu_details_ptr,
  2292. struct hal_soc *hal_soc)
  2293. {
  2294. return hal_soc->ops->hal_rx_msdu_ext_desc_info_get_ptr(
  2295. msdu_details_ptr);
  2296. }
  2297. static inline void
  2298. hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl,
  2299. uint8_t *buf, uint8_t dbg_level)
  2300. {
  2301. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2302. hal_soc->ops->hal_rx_dump_pkt_tlvs(hal_soc_hdl, buf, dbg_level);
  2303. }
  2304. //TODO - Change the names to not include tlv names
  2305. static inline uint16_t
  2306. hal_rx_attn_phy_ppdu_id_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2307. {
  2308. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2309. return hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get(buf);
  2310. }
  2311. static inline uint32_t
  2312. hal_rx_attn_msdu_done_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2313. {
  2314. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2315. return hal_soc->ops->hal_rx_tlv_msdu_done_get(buf);
  2316. }
  2317. static inline uint32_t
  2318. hal_rx_msdu_start_msdu_len_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2319. {
  2320. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2321. return hal_soc->ops->hal_rx_tlv_msdu_len_get(buf);
  2322. }
  2323. static inline uint16_t
  2324. hal_rx_get_frame_ctrl_field(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2325. {
  2326. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2327. return hal_soc->ops->hal_rx_get_frame_ctrl_field(buf);
  2328. }
  2329. static inline int
  2330. hal_rx_tlv_get_offload_info(hal_soc_handle_t hal_soc_hdl,
  2331. uint8_t *rx_pkt_tlv,
  2332. struct hal_offload_info *offload_info)
  2333. {
  2334. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2335. return hal_soc->ops->hal_rx_tlv_get_offload_info(rx_pkt_tlv,
  2336. offload_info);
  2337. }
  2338. static inline int
  2339. hal_rx_get_proto_params(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  2340. void *proto_params)
  2341. {
  2342. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2343. return hal_soc->ops->hal_rx_get_proto_params(buf, proto_params);
  2344. }
  2345. static inline int
  2346. hal_rx_get_l3_l4_offsets(hal_soc_handle_t hal_soc_hdl, uint8_t *buf,
  2347. uint32_t *l3_hdr_offset, uint32_t *l4_hdr_offset)
  2348. {
  2349. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2350. return hal_soc->ops->hal_rx_get_l3_l4_offsets(buf,
  2351. l3_hdr_offset,
  2352. l4_hdr_offset);
  2353. }
  2354. static inline uint32_t
  2355. hal_rx_tlv_mic_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2356. {
  2357. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2358. return hal_soc->ops->hal_rx_tlv_mic_err_get(buf);
  2359. }
  2360. /**
  2361. * hal_rx_tlv_get_pkt_type() - API to get the pkt type
  2362. * from rx_msdu_start
  2363. * @hal_soc_hdl: hal_soc handle
  2364. * @buf: pointer to the start of RX PKT TLV header
  2365. * Return: uint32_t(pkt type)
  2366. */
  2367. static inline uint32_t
  2368. hal_rx_tlv_get_pkt_type(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2369. {
  2370. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2371. return hal_soc->ops->hal_rx_tlv_get_pkt_type(buf);
  2372. }
  2373. static inline void
  2374. hal_rx_tlv_get_pn_num(hal_soc_handle_t hal_soc_hdl,
  2375. uint8_t *buf, uint64_t *pn_num)
  2376. {
  2377. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2378. hal_soc->ops->hal_rx_tlv_get_pn_num(buf, pn_num);
  2379. }
  2380. static inline uint8_t *
  2381. hal_get_reo_ent_desc_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *desc)
  2382. {
  2383. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2384. if (hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr)
  2385. return hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr(desc);
  2386. return NULL;
  2387. }
  2388. static inline uint64_t
  2389. hal_rx_get_qdesc_addr(hal_soc_handle_t hal_soc_hdl, uint8_t *dst_ring_desc,
  2390. uint8_t *buf)
  2391. {
  2392. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2393. if (hal_soc->ops->hal_rx_get_qdesc_addr)
  2394. return hal_soc->ops->hal_rx_get_qdesc_addr(dst_ring_desc, buf);
  2395. return 0;
  2396. }
  2397. static inline void
  2398. hal_set_reo_ent_desc_reo_dest_ind(hal_soc_handle_t hal_soc_hdl,
  2399. uint8_t *desc, uint32_t dst_ind)
  2400. {
  2401. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2402. if (hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind)
  2403. hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind(desc, dst_ind);
  2404. }
  2405. static inline uint32_t
  2406. hal_rx_tlv_get_is_decrypted(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2407. {
  2408. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2409. if (hal_soc->ops->hal_rx_tlv_get_is_decrypted)
  2410. return hal_soc->ops->hal_rx_tlv_get_is_decrypted(buf);
  2411. return 0;
  2412. }
  2413. static inline uint8_t *
  2414. hal_rx_pkt_hdr_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2415. {
  2416. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2417. return hal_soc->ops->hal_rx_pkt_hdr_get(buf);
  2418. }
  2419. static inline uint8_t
  2420. hal_rx_msdu_get_keyid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2421. {
  2422. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2423. if (hal_soc->ops->hal_rx_msdu_get_keyid)
  2424. return hal_soc->ops->hal_rx_msdu_get_keyid(buf);
  2425. return 0;
  2426. }
  2427. static inline uint32_t
  2428. hal_rx_tlv_get_freq(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2429. {
  2430. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2431. if (hal_soc->ops->hal_rx_tlv_get_freq)
  2432. return hal_soc->ops->hal_rx_tlv_get_freq(buf);
  2433. return 0;
  2434. }
  2435. static inline void hal_mpdu_desc_info_set(hal_soc_handle_t hal_soc_hdl,
  2436. void *desc,
  2437. void *mpdu_desc_info,
  2438. uint32_t val)
  2439. {
  2440. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2441. if (hal_soc->ops->hal_mpdu_desc_info_set)
  2442. return hal_soc->ops->hal_mpdu_desc_info_set(
  2443. hal_soc_hdl, desc, mpdu_desc_info, val);
  2444. }
  2445. static inline void hal_msdu_desc_info_set(hal_soc_handle_t hal_soc_hdl,
  2446. void *msdu_desc_info,
  2447. uint32_t val, uint32_t nbuf_len)
  2448. {
  2449. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2450. if (hal_soc->ops->hal_msdu_desc_info_set)
  2451. return hal_soc->ops->hal_msdu_desc_info_set(
  2452. hal_soc_hdl, msdu_desc_info, val, nbuf_len);
  2453. }
  2454. static inline uint32_t
  2455. hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc)
  2456. {
  2457. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2458. if (hal_soc->ops->hal_rx_msdu_reo_dst_ind_get)
  2459. return hal_soc->ops->hal_rx_msdu_reo_dst_ind_get(
  2460. hal_soc_hdl, msdu_link_desc);
  2461. return 0;
  2462. }
  2463. static inline uint32_t
  2464. hal_rx_tlv_sgi_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2465. {
  2466. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2467. return hal_soc->ops->hal_rx_tlv_sgi_get(buf);
  2468. }
  2469. static inline uint32_t
  2470. hal_rx_tlv_rate_mcs_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2471. {
  2472. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2473. return hal_soc->ops->hal_rx_tlv_rate_mcs_get(buf);
  2474. }
  2475. static inline uint32_t
  2476. hal_rx_tlv_decrypt_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2477. {
  2478. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2479. return hal_soc->ops->hal_rx_tlv_decrypt_err_get(buf);
  2480. }
  2481. static inline uint32_t
  2482. hal_rx_tlv_first_mpdu_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2483. {
  2484. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2485. return hal_soc->ops->hal_rx_tlv_first_mpdu_get(buf);
  2486. }
  2487. static inline uint32_t
  2488. hal_rx_tlv_bw_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2489. {
  2490. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2491. return hal_soc->ops->hal_rx_tlv_bw_get(buf);
  2492. }
  2493. static inline uint32_t
  2494. hal_rx_wbm_err_src_get(hal_soc_handle_t hal_soc_hdl,
  2495. hal_ring_desc_t ring_desc)
  2496. {
  2497. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2498. return hal_soc->ops->hal_rx_wbm_err_src_get(ring_desc);
  2499. }
  2500. /**
  2501. * hal_rx_ret_buf_manager_get() - Returns the "return_buffer_manager"
  2502. * from the BUFFER_ADDR_INFO structure
  2503. * given a REO destination ring descriptor.
  2504. * @hal_soc_hdl: hal soc handle
  2505. * @ring_desc: RX(REO/WBM release) destination ring descriptor
  2506. *
  2507. * Return: uint8_t (value of the return_buffer_manager)
  2508. */
  2509. static inline uint8_t
  2510. hal_rx_ret_buf_manager_get(hal_soc_handle_t hal_soc_hdl,
  2511. hal_ring_desc_t ring_desc)
  2512. {
  2513. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2514. return hal_soc->ops->hal_rx_ret_buf_manager_get(ring_desc);
  2515. }
  2516. /**
  2517. * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the
  2518. * rxdma ring entry.
  2519. * @hal_soc_hdl: hal soc handle
  2520. * @rxdma_entry: descriptor entry
  2521. * @paddr: physical address of nbuf data pointer.
  2522. * @cookie: SW cookie used as a index to SW rx desc.
  2523. * @manager: who owns the nbuf (host, NSS, etc...).
  2524. *
  2525. */
  2526. static inline void hal_rxdma_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl,
  2527. void *rxdma_entry,
  2528. qdf_dma_addr_t paddr,
  2529. uint32_t cookie,
  2530. uint8_t manager)
  2531. {
  2532. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2533. return hal_soc->ops->hal_rxdma_buff_addr_info_set(rxdma_entry,
  2534. paddr,
  2535. cookie,
  2536. manager);
  2537. }
  2538. static inline uint32_t
  2539. hal_rx_get_reo_error_code(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc)
  2540. {
  2541. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2542. return hal_soc->ops->hal_rx_get_reo_error_code(rx_desc);
  2543. }
  2544. static inline void
  2545. hal_rx_tlv_csum_err_get(hal_soc_handle_t hal_soc_hdl, uint8_t *rx_tlv_hdr,
  2546. uint32_t *ip_csum_err, uint32_t *tcp_udp_csum_err)
  2547. {
  2548. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2549. return hal_soc->ops->hal_rx_tlv_csum_err_get(rx_tlv_hdr,
  2550. ip_csum_err,
  2551. tcp_udp_csum_err);
  2552. }
  2553. static inline void
  2554. hal_rx_tlv_get_pkt_capture_flags(hal_soc_handle_t hal_soc_hdl,
  2555. uint8_t *rx_tlv_hdr,
  2556. struct hal_rx_pkt_capture_flags *flags)
  2557. {
  2558. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2559. return hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags(rx_tlv_hdr,
  2560. flags);
  2561. }
  2562. static inline uint8_t
  2563. hal_rx_err_status_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc)
  2564. {
  2565. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2566. return hal_soc->ops->hal_rx_err_status_get(rx_desc);
  2567. }
  2568. static inline uint8_t
  2569. hal_rx_reo_buf_type_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t rx_desc)
  2570. {
  2571. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2572. return hal_soc->ops->hal_rx_reo_buf_type_get(rx_desc);
  2573. }
  2574. /**
  2575. * hal_rx_reo_prev_pn_get() - Get the previous pn from ring descriptor.
  2576. * @hal_soc_hdl: HAL SoC handle
  2577. * @ring_desc: REO ring descriptor
  2578. * @prev_pn: Buffer to populate the previous PN
  2579. *
  2580. * Return: None
  2581. */
  2582. static inline void
  2583. hal_rx_reo_prev_pn_get(hal_soc_handle_t hal_soc_hdl, hal_ring_desc_t ring_desc,
  2584. uint64_t *prev_pn)
  2585. {
  2586. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2587. if (hal_soc->ops->hal_rx_reo_prev_pn_get)
  2588. return hal_soc->ops->hal_rx_reo_prev_pn_get(ring_desc, prev_pn);
  2589. }
  2590. /**
  2591. * hal_rx_mpdu_info_ampdu_flag_get() - get ampdu flag bit from rx mpdu info
  2592. * @hal_soc_hdl: hal soc handle
  2593. * @buf: pointer to rx_pkt_tlvs
  2594. *
  2595. * No input validdataion, since this function is supposed to be
  2596. * called from fastpath.
  2597. *
  2598. * Return: ampdu flag
  2599. */
  2600. static inline bool
  2601. hal_rx_mpdu_info_ampdu_flag_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2602. {
  2603. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2604. return hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get(buf);
  2605. }
  2606. #ifdef REO_SHARED_QREF_TABLE_EN
  2607. /**
  2608. * hal_reo_shared_qaddr_write() - Write REo tid queue addr
  2609. * LUT shared by SW and HW at the index given by peer id
  2610. * and tid.
  2611. *
  2612. * @hal_soc_hdl: hal soc handle
  2613. * @peer_id: peer_id
  2614. * @tid: tid queue number
  2615. * @hw_qdesc_paddr: reo queue addr
  2616. */
  2617. static inline void
  2618. hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl,
  2619. uint16_t peer_id,
  2620. int tid,
  2621. qdf_dma_addr_t hw_qdesc_paddr)
  2622. {
  2623. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2624. if (hal_soc->ops->hal_reo_shared_qaddr_write)
  2625. return hal_soc->ops->hal_reo_shared_qaddr_write(hal_soc_hdl,
  2626. peer_id, tid, hw_qdesc_paddr);
  2627. }
  2628. /**
  2629. * hal_reo_shared_qaddr_init() - Initialize reo qref LUT
  2630. * @hal_soc_hdl: Hal soc handle
  2631. * @qref_reset: reset qref LUT
  2632. *
  2633. * Write MLO and Non MLO table start addr to HW reg
  2634. *
  2635. * Return: void
  2636. */
  2637. static inline void
  2638. hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset)
  2639. {
  2640. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2641. if (hal_soc->ops->hal_reo_shared_qaddr_init)
  2642. return hal_soc->ops->hal_reo_shared_qaddr_init(hal_soc_hdl,
  2643. qref_reset);
  2644. }
  2645. /**
  2646. * hal_reo_shared_qaddr_cache_clear() - Set and unset 'clear_qdesc_array'
  2647. * bit in reo reg for shared qref feature. This is done for every MLO
  2648. * connection to clear HW reo internal storage for clearing stale entry
  2649. * of prev peer having same peer id
  2650. *
  2651. * @hal_soc_hdl: Hal soc handle
  2652. *
  2653. * Write MLO and Non MLO table start addr to HW reg
  2654. *
  2655. * Return: void
  2656. */
  2657. static inline void hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl)
  2658. {
  2659. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2660. if (hal_soc->ops->hal_reo_shared_qaddr_cache_clear)
  2661. return hal_soc->ops->hal_reo_shared_qaddr_cache_clear(hal_soc_hdl);
  2662. }
  2663. #else
  2664. static inline void
  2665. hal_reo_shared_qaddr_write(hal_soc_handle_t hal_soc_hdl,
  2666. uint16_t peer_id,
  2667. int tid,
  2668. qdf_dma_addr_t hw_qdesc_paddr) {}
  2669. static inline void
  2670. hal_reo_shared_qaddr_init(hal_soc_handle_t hal_soc_hdl, int qref_reset) {}
  2671. static inline void
  2672. hal_reo_shared_qaddr_cache_clear(hal_soc_handle_t hal_soc_hdl) {}
  2673. #endif /* REO_SHARED_QREF_TABLE_EN */
  2674. static inline uint8_t
  2675. hal_reo_shared_qaddr_is_enable(hal_soc_handle_t hal_soc_hdl)
  2676. {
  2677. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2678. return hal->reo_qref.reo_qref_table_en;
  2679. }
  2680. #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
  2681. static inline uint8_t
  2682. hal_get_first_wow_wakeup_packet(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2683. {
  2684. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2685. return hal_soc->ops->hal_get_first_wow_wakeup_packet(buf);
  2686. }
  2687. #endif
  2688. static inline uint32_t
  2689. hal_rx_tlv_l3_type_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2690. {
  2691. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2692. return hal_soc->ops->hal_rx_tlv_l3_type_get ?
  2693. hal_soc->ops->hal_rx_tlv_l3_type_get(buf) :
  2694. HAL_RX_TLV_L3_TYPE_INVALID;
  2695. }
  2696. /**
  2697. * hal_get_tsf_time() - Get tsf time
  2698. * @hal_soc_hdl: HAL soc handle
  2699. * @tsf_id:
  2700. * @mac_id: mac_id
  2701. * @tsf: pointer to update tsf value
  2702. * @tsf_sync_soc_time: pointer to update tsf sync time
  2703. *
  2704. * Return: None.
  2705. */
  2706. static inline void
  2707. hal_get_tsf_time(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id,
  2708. uint32_t mac_id, uint64_t *tsf,
  2709. uint64_t *tsf_sync_soc_time)
  2710. {
  2711. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2712. if (hal_soc->ops->hal_get_tsf_time)
  2713. hal_soc->ops->hal_get_tsf_time(hal_soc_hdl, tsf_id, mac_id,
  2714. tsf, tsf_sync_soc_time);
  2715. }
  2716. /**
  2717. * hal_rx_en_mcast_fp_data_filter() - Is mcast filter pass enabled
  2718. * @hal_soc_hdl: HAL soc handle
  2719. *
  2720. * Return: false for BE MCC, true for WIN
  2721. */
  2722. static inline
  2723. bool hal_rx_en_mcast_fp_data_filter(hal_soc_handle_t hal_soc_hdl)
  2724. {
  2725. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2726. return hal_soc->ops->hal_rx_en_mcast_fp_data_filter();
  2727. }
  2728. #endif /* _HAL_RX_H */