hal_api.h 99 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_API_H_
  20. #define _HAL_API_H_
  21. #include "qdf_types.h"
  22. #include "qdf_util.h"
  23. #include "qdf_atomic.h"
  24. #include "hal_internal.h"
  25. #include "hif.h"
  26. #include "hif_io32.h"
  27. #include "qdf_platform.h"
  28. #ifdef DUMP_REO_QUEUE_INFO_IN_DDR
  29. #include "hal_hw_headers.h"
  30. #endif
  31. /* Ring index for WBM2SW2 release ring */
  32. #define HAL_IPA_TX_COMP_RING_IDX 2
  33. #if defined(CONFIG_SHADOW_V2) || defined(CONFIG_SHADOW_V3)
  34. #define ignore_shadow false
  35. #define CHECK_SHADOW_REGISTERS true
  36. #else
  37. #define ignore_shadow true
  38. #define CHECK_SHADOW_REGISTERS false
  39. #endif
  40. /* calculate the register address offset from bar0 of shadow register x */
  41. #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \
  42. defined(QCA_WIFI_KIWI)
  43. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x000008FC
  44. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  45. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  46. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  47. #elif defined(QCA_WIFI_QCA6290) || defined(QCA_WIFI_QCN9000)
  48. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x00003024
  49. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  50. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  51. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  52. #elif defined(QCA_WIFI_QCA6750)
  53. #define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x00000504
  54. #define SHADOW_REGISTER_END_ADDRESS_OFFSET \
  55. ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
  56. #define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
  57. #else
  58. #define SHADOW_REGISTER(x) 0
  59. #endif /* QCA_WIFI_QCA6390 || QCA_WIFI_QCA6490 || QCA_WIFI_QCA6750 */
  60. /*
  61. * BAR + 4K is always accessible, any access outside this
  62. * space requires force wake procedure.
  63. * OFFSET = 4K - 32 bytes = 0xFE0
  64. */
  65. #define MAPPED_REF_OFF 0xFE0
  66. #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET
  67. #ifdef ENABLE_VERBOSE_DEBUG
  68. static inline void
  69. hal_set_verbose_debug(bool flag)
  70. {
  71. is_hal_verbose_debug_enabled = flag;
  72. }
  73. #endif
  74. #ifdef ENABLE_HAL_SOC_STATS
  75. #define HAL_STATS_INC(_handle, _field, _delta) \
  76. { \
  77. if (likely(_handle)) \
  78. _handle->stats._field += _delta; \
  79. }
  80. #else
  81. #define HAL_STATS_INC(_handle, _field, _delta)
  82. #endif
  83. #ifdef ENABLE_HAL_REG_WR_HISTORY
  84. #define HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, wr_val, rd_val) \
  85. hal_reg_wr_fail_history_add(hal_soc, offset, wr_val, rd_val)
  86. void hal_reg_wr_fail_history_add(struct hal_soc *hal_soc,
  87. uint32_t offset,
  88. uint32_t wr_val,
  89. uint32_t rd_val);
  90. static inline int hal_history_get_next_index(qdf_atomic_t *table_index,
  91. int array_size)
  92. {
  93. int record_index = qdf_atomic_inc_return(table_index);
  94. return record_index & (array_size - 1);
  95. }
  96. #else
  97. #define HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, wr_val, rd_val) \
  98. hal_err("write failed at reg offset 0x%x, write 0x%x read 0x%x\n", \
  99. offset, \
  100. wr_val, \
  101. rd_val)
  102. #endif
  103. /**
  104. * hal_reg_write_result_check() - check register writing result
  105. * @hal_soc: HAL soc handle
  106. * @offset: register offset to read
  107. * @exp_val: the expected value of register
  108. *
  109. * Return: none
  110. */
  111. static inline void hal_reg_write_result_check(struct hal_soc *hal_soc,
  112. uint32_t offset,
  113. uint32_t exp_val)
  114. {
  115. uint32_t value;
  116. value = qdf_ioread32(hal_soc->dev_base_addr + offset);
  117. if (exp_val != value) {
  118. HAL_REG_WRITE_FAIL_HIST_ADD(hal_soc, offset, exp_val, value);
  119. HAL_STATS_INC(hal_soc, reg_write_fail, 1);
  120. }
  121. }
  122. #ifdef WINDOW_REG_PLD_LOCK_ENABLE
  123. static inline void hal_lock_reg_access(struct hal_soc *soc,
  124. unsigned long *flags)
  125. {
  126. pld_lock_reg_window(soc->qdf_dev->dev, flags);
  127. }
  128. static inline void hal_unlock_reg_access(struct hal_soc *soc,
  129. unsigned long *flags)
  130. {
  131. pld_unlock_reg_window(soc->qdf_dev->dev, flags);
  132. }
  133. #else
  134. static inline void hal_lock_reg_access(struct hal_soc *soc,
  135. unsigned long *flags)
  136. {
  137. qdf_spin_lock_irqsave(&soc->register_access_lock);
  138. }
  139. static inline void hal_unlock_reg_access(struct hal_soc *soc,
  140. unsigned long *flags)
  141. {
  142. qdf_spin_unlock_irqrestore(&soc->register_access_lock);
  143. }
  144. #endif
  145. #ifdef PCIE_REG_WINDOW_LOCAL_NO_CACHE
  146. /**
  147. * hal_select_window_confirm() - write remap window register and
  148. * check writing result
  149. * @hal_soc: hal soc handle
  150. * @offset: offset to write
  151. *
  152. */
  153. static inline void hal_select_window_confirm(struct hal_soc *hal_soc,
  154. uint32_t offset)
  155. {
  156. uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
  157. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  158. WINDOW_ENABLE_BIT | window);
  159. hal_soc->register_window = window;
  160. hal_reg_write_result_check(hal_soc, WINDOW_REG_ADDRESS,
  161. WINDOW_ENABLE_BIT | window);
  162. }
  163. #else
  164. static inline void hal_select_window_confirm(struct hal_soc *hal_soc,
  165. uint32_t offset)
  166. {
  167. uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
  168. if (window != hal_soc->register_window) {
  169. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
  170. WINDOW_ENABLE_BIT | window);
  171. hal_soc->register_window = window;
  172. hal_reg_write_result_check(
  173. hal_soc,
  174. WINDOW_REG_ADDRESS,
  175. WINDOW_ENABLE_BIT | window);
  176. }
  177. }
  178. #endif
  179. static inline qdf_iomem_t hal_get_window_address(struct hal_soc *hal_soc,
  180. qdf_iomem_t addr)
  181. {
  182. return hal_soc->ops->hal_get_window_address(hal_soc, addr);
  183. }
  184. static inline void hal_tx_init_cmd_credit_ring(hal_soc_handle_t hal_soc_hdl,
  185. hal_ring_handle_t hal_ring_hdl)
  186. {
  187. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  188. return hal_soc->ops->hal_tx_init_cmd_credit_ring(hal_soc_hdl,
  189. hal_ring_hdl);
  190. }
  191. /**
  192. * hal_write32_mb() - Access registers to update configuration
  193. * @hal_soc: hal soc handle
  194. * @offset: offset address from the BAR
  195. * @value: value to write
  196. *
  197. * Return: None
  198. *
  199. * Description: Register address space is split below:
  200. * SHADOW REGION UNWINDOWED REGION WINDOWED REGION
  201. * |--------------------|-------------------|------------------|
  202. * BAR NO FORCE WAKE BAR+4K FORCE WAKE BAR+512K FORCE WAKE
  203. *
  204. * 1. Any access to the shadow region, doesn't need force wake
  205. * and windowing logic to access.
  206. * 2. Any access beyond BAR + 4K:
  207. * If init_phase enabled, no force wake is needed and access
  208. * should be based on windowed or unwindowed access.
  209. * If init_phase disabled, force wake is needed and access
  210. * should be based on windowed or unwindowed access.
  211. *
  212. * note1: WINDOW_RANGE_MASK = (1 << WINDOW_SHIFT) -1
  213. * note2: 1 << WINDOW_SHIFT = MAX_UNWINDOWED_ADDRESS
  214. * note3: WINDOW_VALUE_MASK = big enough that trying to write past
  215. * that window would be a bug
  216. */
  217. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) && \
  218. !defined(QCA_WIFI_QCA6750) && !defined(QCA_WIFI_KIWI) && \
  219. !defined(QCA_WIFI_WCN6450)
  220. static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
  221. uint32_t value)
  222. {
  223. unsigned long flags;
  224. qdf_iomem_t new_addr;
  225. if (!hal_soc->use_register_windowing ||
  226. offset < MAX_UNWINDOWED_ADDRESS) {
  227. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  228. } else if (hal_soc->static_window_map) {
  229. new_addr = hal_get_window_address(hal_soc,
  230. hal_soc->dev_base_addr + offset);
  231. qdf_iowrite32(new_addr, value);
  232. } else {
  233. hal_lock_reg_access(hal_soc, &flags);
  234. hal_select_window_confirm(hal_soc, offset);
  235. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  236. (offset & WINDOW_RANGE_MASK), value);
  237. hal_unlock_reg_access(hal_soc, &flags);
  238. }
  239. }
  240. #define hal_write32_mb_confirm(_hal_soc, _offset, _value) \
  241. hal_write32_mb(_hal_soc, _offset, _value)
  242. #define hal_write32_mb_cmem(_hal_soc, _offset, _value)
  243. #else
  244. static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
  245. uint32_t value)
  246. {
  247. int ret;
  248. unsigned long flags;
  249. qdf_iomem_t new_addr;
  250. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  251. hal_soc->hif_handle))) {
  252. hal_err_rl("target access is not allowed");
  253. return;
  254. }
  255. /* Region < BAR + 4K can be directly accessed */
  256. if (offset < MAPPED_REF_OFF) {
  257. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  258. return;
  259. }
  260. /* Region greater than BAR + 4K */
  261. if (!hal_soc->init_phase) {
  262. ret = hif_force_wake_request(hal_soc->hif_handle);
  263. if (ret) {
  264. hal_err_rl("Wake up request failed");
  265. qdf_check_state_before_panic(__func__, __LINE__);
  266. return;
  267. }
  268. }
  269. if (!hal_soc->use_register_windowing ||
  270. offset < MAX_UNWINDOWED_ADDRESS) {
  271. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  272. } else if (hal_soc->static_window_map) {
  273. new_addr = hal_get_window_address(
  274. hal_soc,
  275. hal_soc->dev_base_addr + offset);
  276. qdf_iowrite32(new_addr, value);
  277. } else {
  278. hal_lock_reg_access(hal_soc, &flags);
  279. hal_select_window_confirm(hal_soc, offset);
  280. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  281. (offset & WINDOW_RANGE_MASK), value);
  282. hal_unlock_reg_access(hal_soc, &flags);
  283. }
  284. if (!hal_soc->init_phase) {
  285. ret = hif_force_wake_release(hal_soc->hif_handle);
  286. if (ret) {
  287. hal_err("Wake up release failed");
  288. qdf_check_state_before_panic(__func__, __LINE__);
  289. return;
  290. }
  291. }
  292. }
  293. /**
  294. * hal_write32_mb_confirm() - write register and check writing result
  295. * @hal_soc: hal soc handle
  296. * @offset: I/O memory address to write
  297. * @value: value to write
  298. */
  299. static inline void hal_write32_mb_confirm(struct hal_soc *hal_soc,
  300. uint32_t offset,
  301. uint32_t value)
  302. {
  303. int ret;
  304. unsigned long flags;
  305. qdf_iomem_t new_addr;
  306. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  307. hal_soc->hif_handle))) {
  308. hal_err_rl("target access is not allowed");
  309. return;
  310. }
  311. /* Region < BAR + 4K can be directly accessed */
  312. if (offset < MAPPED_REF_OFF) {
  313. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  314. return;
  315. }
  316. /* Region greater than BAR + 4K */
  317. if (!hal_soc->init_phase) {
  318. ret = hif_force_wake_request(hal_soc->hif_handle);
  319. if (ret) {
  320. hal_err("Wake up request failed");
  321. qdf_check_state_before_panic(__func__, __LINE__);
  322. return;
  323. }
  324. }
  325. if (!hal_soc->use_register_windowing ||
  326. offset < MAX_UNWINDOWED_ADDRESS) {
  327. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  328. hal_reg_write_result_check(hal_soc, offset,
  329. value);
  330. } else if (hal_soc->static_window_map) {
  331. new_addr = hal_get_window_address(
  332. hal_soc,
  333. hal_soc->dev_base_addr + offset);
  334. qdf_iowrite32(new_addr, value);
  335. hal_reg_write_result_check(hal_soc,
  336. new_addr - hal_soc->dev_base_addr,
  337. value);
  338. } else {
  339. hal_lock_reg_access(hal_soc, &flags);
  340. hal_select_window_confirm(hal_soc, offset);
  341. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  342. (offset & WINDOW_RANGE_MASK), value);
  343. hal_reg_write_result_check(
  344. hal_soc,
  345. WINDOW_START + (offset & WINDOW_RANGE_MASK),
  346. value);
  347. hal_unlock_reg_access(hal_soc, &flags);
  348. }
  349. if (!hal_soc->init_phase) {
  350. ret = hif_force_wake_release(hal_soc->hif_handle);
  351. if (ret) {
  352. hal_err("Wake up release failed");
  353. qdf_check_state_before_panic(__func__, __LINE__);
  354. return;
  355. }
  356. }
  357. }
  358. /**
  359. * hal_write32_mb_cmem() - write CMEM
  360. * @hal_soc: hal soc handle
  361. * @offset: offset into CMEM to write
  362. * @value: value to write
  363. */
  364. static inline void hal_write32_mb_cmem(struct hal_soc *hal_soc, uint32_t offset,
  365. uint32_t value)
  366. {
  367. unsigned long flags;
  368. qdf_iomem_t new_addr;
  369. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  370. hal_soc->hif_handle))) {
  371. hal_err_rl("%s: target access is not allowed", __func__);
  372. return;
  373. }
  374. if (!hal_soc->use_register_windowing ||
  375. offset < MAX_UNWINDOWED_ADDRESS) {
  376. qdf_iowrite32(hal_soc->dev_base_addr + offset, value);
  377. } else if (hal_soc->static_window_map) {
  378. new_addr = hal_get_window_address(
  379. hal_soc,
  380. hal_soc->dev_base_addr + offset);
  381. qdf_iowrite32(new_addr, value);
  382. } else {
  383. hal_lock_reg_access(hal_soc, &flags);
  384. hal_select_window_confirm(hal_soc, offset);
  385. qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
  386. (offset & WINDOW_RANGE_MASK), value);
  387. hal_unlock_reg_access(hal_soc, &flags);
  388. }
  389. }
  390. #endif
  391. /**
  392. * hal_write_address_32_mb() - write a value to a register
  393. * @hal_soc: hal soc handle
  394. * @addr: I/O memory address to write
  395. * @value: value to write
  396. * @wr_confirm: true if read back confirmation is required
  397. */
  398. static inline
  399. void hal_write_address_32_mb(struct hal_soc *hal_soc,
  400. qdf_iomem_t addr, uint32_t value, bool wr_confirm)
  401. {
  402. uint32_t offset;
  403. if (!hal_soc->use_register_windowing)
  404. return qdf_iowrite32(addr, value);
  405. offset = addr - hal_soc->dev_base_addr;
  406. if (qdf_unlikely(wr_confirm))
  407. hal_write32_mb_confirm(hal_soc, offset, value);
  408. else
  409. hal_write32_mb(hal_soc, offset, value);
  410. }
  411. #ifdef DP_HAL_MULTIWINDOW_DIRECT_ACCESS
  412. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  413. struct hal_srng *srng,
  414. void __iomem *addr,
  415. uint32_t value)
  416. {
  417. qdf_iowrite32(addr, value);
  418. hal_srng_reg_his_add(srng, value);
  419. }
  420. #elif defined(FEATURE_HAL_DELAYED_REG_WRITE)
  421. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  422. struct hal_srng *srng,
  423. void __iomem *addr,
  424. uint32_t value)
  425. {
  426. hal_delayed_reg_write(hal_soc, srng, addr, value);
  427. }
  428. #else
  429. static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
  430. struct hal_srng *srng,
  431. void __iomem *addr,
  432. uint32_t value)
  433. {
  434. hal_write_address_32_mb(hal_soc, addr, value, false);
  435. hal_srng_reg_his_add(srng, value);
  436. }
  437. #endif
  438. #if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) && \
  439. !defined(QCA_WIFI_QCA6750) && !defined(QCA_WIFI_KIWI) && \
  440. !defined(QCA_WIFI_WCN6450)
  441. /**
  442. * hal_read32_mb() - Access registers to read configuration
  443. * @hal_soc: hal soc handle
  444. * @offset: offset address from the BAR
  445. *
  446. * Description: Register address space is split below:
  447. * SHADOW REGION UNWINDOWED REGION WINDOWED REGION
  448. * |--------------------|-------------------|------------------|
  449. * BAR NO FORCE WAKE BAR+4K FORCE WAKE BAR+512K FORCE WAKE
  450. *
  451. * 1. Any access to the shadow region, doesn't need force wake
  452. * and windowing logic to access.
  453. * 2. Any access beyond BAR + 4K:
  454. * If init_phase enabled, no force wake is needed and access
  455. * should be based on windowed or unwindowed access.
  456. * If init_phase disabled, force wake is needed and access
  457. * should be based on windowed or unwindowed access.
  458. *
  459. * Return: value read
  460. */
  461. static inline uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)
  462. {
  463. uint32_t ret;
  464. unsigned long flags;
  465. qdf_iomem_t new_addr;
  466. if (!hal_soc->use_register_windowing ||
  467. offset < MAX_UNWINDOWED_ADDRESS) {
  468. return qdf_ioread32(hal_soc->dev_base_addr + offset);
  469. } else if (hal_soc->static_window_map) {
  470. new_addr = hal_get_window_address(hal_soc, hal_soc->dev_base_addr + offset);
  471. return qdf_ioread32(new_addr);
  472. }
  473. hal_lock_reg_access(hal_soc, &flags);
  474. hal_select_window_confirm(hal_soc, offset);
  475. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  476. (offset & WINDOW_RANGE_MASK));
  477. hal_unlock_reg_access(hal_soc, &flags);
  478. return ret;
  479. }
  480. #define hal_read32_mb_cmem(_hal_soc, _offset)
  481. #else
  482. static
  483. uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)
  484. {
  485. uint32_t ret;
  486. unsigned long flags;
  487. qdf_iomem_t new_addr;
  488. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  489. hal_soc->hif_handle))) {
  490. hal_err_rl("target access is not allowed");
  491. return 0;
  492. }
  493. /* Region < BAR + 4K can be directly accessed */
  494. if (offset < MAPPED_REF_OFF)
  495. return qdf_ioread32(hal_soc->dev_base_addr + offset);
  496. if ((!hal_soc->init_phase) &&
  497. hif_force_wake_request(hal_soc->hif_handle)) {
  498. hal_err("Wake up request failed");
  499. qdf_check_state_before_panic(__func__, __LINE__);
  500. return 0;
  501. }
  502. if (!hal_soc->use_register_windowing ||
  503. offset < MAX_UNWINDOWED_ADDRESS) {
  504. ret = qdf_ioread32(hal_soc->dev_base_addr + offset);
  505. } else if (hal_soc->static_window_map) {
  506. new_addr = hal_get_window_address(
  507. hal_soc,
  508. hal_soc->dev_base_addr + offset);
  509. ret = qdf_ioread32(new_addr);
  510. } else {
  511. hal_lock_reg_access(hal_soc, &flags);
  512. hal_select_window_confirm(hal_soc, offset);
  513. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  514. (offset & WINDOW_RANGE_MASK));
  515. hal_unlock_reg_access(hal_soc, &flags);
  516. }
  517. if ((!hal_soc->init_phase) &&
  518. hif_force_wake_release(hal_soc->hif_handle)) {
  519. hal_err("Wake up release failed");
  520. qdf_check_state_before_panic(__func__, __LINE__);
  521. return 0;
  522. }
  523. return ret;
  524. }
  525. static inline
  526. uint32_t hal_read32_mb_cmem(struct hal_soc *hal_soc, uint32_t offset)
  527. {
  528. uint32_t ret;
  529. unsigned long flags;
  530. qdf_iomem_t new_addr;
  531. if (!TARGET_ACCESS_ALLOWED(HIF_GET_SOFTC(
  532. hal_soc->hif_handle))) {
  533. hal_err_rl("%s: target access is not allowed", __func__);
  534. return 0;
  535. }
  536. if (!hal_soc->use_register_windowing ||
  537. offset < MAX_UNWINDOWED_ADDRESS) {
  538. ret = qdf_ioread32(hal_soc->dev_base_addr + offset);
  539. } else if (hal_soc->static_window_map) {
  540. new_addr = hal_get_window_address(
  541. hal_soc,
  542. hal_soc->dev_base_addr + offset);
  543. ret = qdf_ioread32(new_addr);
  544. } else {
  545. hal_lock_reg_access(hal_soc, &flags);
  546. hal_select_window_confirm(hal_soc, offset);
  547. ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
  548. (offset & WINDOW_RANGE_MASK));
  549. hal_unlock_reg_access(hal_soc, &flags);
  550. }
  551. return ret;
  552. }
  553. #endif
  554. /* Max times allowed for register writing retry */
  555. #define HAL_REG_WRITE_RETRY_MAX 5
  556. /* Delay milliseconds for each time retry */
  557. #define HAL_REG_WRITE_RETRY_DELAY 1
  558. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  559. /* To check shadow config index range between 0..31 */
  560. #define HAL_SHADOW_REG_INDEX_LOW 32
  561. /* To check shadow config index range between 32..39 */
  562. #define HAL_SHADOW_REG_INDEX_HIGH 40
  563. /* Dirty bit reg offsets corresponding to shadow config index */
  564. #define HAL_SHADOW_REG_DIRTY_BIT_DATA_LOW_OFFSET 0x30C8
  565. #define HAL_SHADOW_REG_DIRTY_BIT_DATA_HIGH_OFFSET 0x30C4
  566. /* PCIE_PCIE_TOP base addr offset */
  567. #define HAL_PCIE_PCIE_TOP_WRAPPER 0x01E00000
  568. /* Max retry attempts to read the dirty bit reg */
  569. #ifdef HAL_CONFIG_SLUB_DEBUG_ON
  570. #define HAL_SHADOW_DIRTY_BIT_POLL_MAX 10000
  571. #else
  572. #define HAL_SHADOW_DIRTY_BIT_POLL_MAX 2000
  573. #endif
  574. /* Delay in usecs for polling dirty bit reg */
  575. #define HAL_SHADOW_DIRTY_BIT_POLL_DELAY 5
  576. /**
  577. * hal_poll_dirty_bit_reg() - Poll dirty register bit to confirm
  578. * write was successful
  579. * @hal: hal soc handle
  580. * @shadow_config_index: index of shadow reg used to confirm
  581. * write
  582. *
  583. * Return: QDF_STATUS_SUCCESS on success
  584. */
  585. static inline QDF_STATUS hal_poll_dirty_bit_reg(struct hal_soc *hal,
  586. int shadow_config_index)
  587. {
  588. uint32_t read_value = 0;
  589. int retry_cnt = 0;
  590. uint32_t reg_offset = 0;
  591. if (shadow_config_index > 0 &&
  592. shadow_config_index < HAL_SHADOW_REG_INDEX_LOW) {
  593. reg_offset =
  594. HAL_SHADOW_REG_DIRTY_BIT_DATA_LOW_OFFSET;
  595. } else if (shadow_config_index >= HAL_SHADOW_REG_INDEX_LOW &&
  596. shadow_config_index < HAL_SHADOW_REG_INDEX_HIGH) {
  597. reg_offset =
  598. HAL_SHADOW_REG_DIRTY_BIT_DATA_HIGH_OFFSET;
  599. } else {
  600. hal_err("Invalid shadow_config_index = %d",
  601. shadow_config_index);
  602. return QDF_STATUS_E_INVAL;
  603. }
  604. while (retry_cnt < HAL_SHADOW_DIRTY_BIT_POLL_MAX) {
  605. read_value = hal_read32_mb(
  606. hal, HAL_PCIE_PCIE_TOP_WRAPPER + reg_offset);
  607. /* Check if dirty bit corresponding to shadow_index is set */
  608. if (read_value & BIT(shadow_config_index)) {
  609. /* Dirty reg bit not reset */
  610. qdf_udelay(HAL_SHADOW_DIRTY_BIT_POLL_DELAY);
  611. retry_cnt++;
  612. } else {
  613. hal_debug("Shadow write: offset 0x%x read val 0x%x",
  614. reg_offset, read_value);
  615. return QDF_STATUS_SUCCESS;
  616. }
  617. }
  618. return QDF_STATUS_E_TIMEOUT;
  619. }
  620. /**
  621. * hal_write32_mb_shadow_confirm() - write to shadow reg and
  622. * poll dirty register bit to confirm write
  623. * @hal: hal soc handle
  624. * @reg_offset: target reg offset address from BAR
  625. * @value: value to write
  626. *
  627. * Return: QDF_STATUS_SUCCESS on success
  628. */
  629. static inline QDF_STATUS hal_write32_mb_shadow_confirm(
  630. struct hal_soc *hal,
  631. uint32_t reg_offset,
  632. uint32_t value)
  633. {
  634. int i;
  635. QDF_STATUS ret;
  636. uint32_t shadow_reg_offset;
  637. int shadow_config_index;
  638. bool is_reg_offset_present = false;
  639. for (i = 0; i < MAX_GENERIC_SHADOW_REG; i++) {
  640. /* Found the shadow config for the reg_offset */
  641. struct shadow_reg_config *hal_shadow_reg_list =
  642. &hal->list_shadow_reg_config[i];
  643. if (hal_shadow_reg_list->target_register ==
  644. reg_offset) {
  645. shadow_config_index =
  646. hal_shadow_reg_list->shadow_config_index;
  647. shadow_reg_offset =
  648. SHADOW_REGISTER(shadow_config_index);
  649. hal_write32_mb_confirm(
  650. hal, shadow_reg_offset, value);
  651. is_reg_offset_present = true;
  652. break;
  653. }
  654. ret = QDF_STATUS_E_FAILURE;
  655. }
  656. if (is_reg_offset_present) {
  657. ret = hal_poll_dirty_bit_reg(hal, shadow_config_index);
  658. hal_info("Shadow write:reg 0x%x val 0x%x ret %d",
  659. reg_offset, value, ret);
  660. if (QDF_IS_STATUS_ERROR(ret)) {
  661. HAL_STATS_INC(hal, shadow_reg_write_fail, 1);
  662. return ret;
  663. }
  664. HAL_STATS_INC(hal, shadow_reg_write_succ, 1);
  665. }
  666. return ret;
  667. }
  668. /**
  669. * hal_write32_mb_confirm_retry() - write register with confirming and
  670. * do retry/recovery if writing failed
  671. * @hal_soc: hal soc handle
  672. * @offset: offset address from the BAR
  673. * @value: value to write
  674. * @recovery: is recovery needed or not.
  675. *
  676. * Write the register value with confirming and read it back, if
  677. * read back value is not as expected, do retry for writing, if
  678. * retry hit max times allowed but still fail, check if recovery
  679. * needed.
  680. *
  681. * Return: None
  682. */
  683. static inline void hal_write32_mb_confirm_retry(struct hal_soc *hal_soc,
  684. uint32_t offset,
  685. uint32_t value,
  686. bool recovery)
  687. {
  688. QDF_STATUS ret;
  689. ret = hal_write32_mb_shadow_confirm(hal_soc, offset, value);
  690. if (QDF_IS_STATUS_ERROR(ret) && recovery)
  691. qdf_trigger_self_recovery(NULL, QDF_HAL_REG_WRITE_FAILURE);
  692. }
  693. #else /* GENERIC_SHADOW_REGISTER_ACCESS_ENABLE */
  694. static inline void hal_write32_mb_confirm_retry(struct hal_soc *hal_soc,
  695. uint32_t offset,
  696. uint32_t value,
  697. bool recovery)
  698. {
  699. uint8_t retry_cnt = 0;
  700. uint32_t read_value;
  701. while (retry_cnt <= HAL_REG_WRITE_RETRY_MAX) {
  702. hal_write32_mb_confirm(hal_soc, offset, value);
  703. read_value = hal_read32_mb(hal_soc, offset);
  704. if (qdf_likely(read_value == value))
  705. break;
  706. /* write failed, do retry */
  707. hal_warn("Retry reg offset 0x%x, value 0x%x, read value 0x%x",
  708. offset, value, read_value);
  709. qdf_mdelay(HAL_REG_WRITE_RETRY_DELAY);
  710. retry_cnt++;
  711. }
  712. if (retry_cnt > HAL_REG_WRITE_RETRY_MAX && recovery)
  713. qdf_trigger_self_recovery(NULL, QDF_HAL_REG_WRITE_FAILURE);
  714. }
  715. #endif /* GENERIC_SHADOW_REGISTER_ACCESS_ENABLE */
  716. #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
  717. /**
  718. * hal_dump_reg_write_srng_stats() - dump SRNG reg write stats
  719. * @hal_soc_hdl: HAL soc handle
  720. *
  721. * Return: none
  722. */
  723. void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl);
  724. /**
  725. * hal_dump_reg_write_stats() - dump reg write stats
  726. * @hal_soc_hdl: HAL soc handle
  727. *
  728. * Return: none
  729. */
  730. void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl);
  731. /**
  732. * hal_get_reg_write_pending_work() - get the number of entries
  733. * pending in the workqueue to be processed.
  734. * @hal_soc: HAL soc handle
  735. *
  736. * Returns: the number of entries pending to be processed
  737. */
  738. int hal_get_reg_write_pending_work(void *hal_soc);
  739. #else
  740. static inline void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
  741. {
  742. }
  743. static inline void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl)
  744. {
  745. }
  746. static inline int hal_get_reg_write_pending_work(void *hal_soc)
  747. {
  748. return 0;
  749. }
  750. #endif
  751. /**
  752. * hal_read_address_32_mb() - Read 32-bit value from the register
  753. * @soc: soc handle
  754. * @addr: register address to read
  755. *
  756. * Return: 32-bit value
  757. */
  758. static inline
  759. uint32_t hal_read_address_32_mb(struct hal_soc *soc,
  760. qdf_iomem_t addr)
  761. {
  762. uint32_t offset;
  763. uint32_t ret;
  764. if (!soc->use_register_windowing)
  765. return qdf_ioread32(addr);
  766. offset = addr - soc->dev_base_addr;
  767. ret = hal_read32_mb(soc, offset);
  768. return ret;
  769. }
  770. /**
  771. * hal_attach() - Initialize HAL layer
  772. * @hif_handle: Opaque HIF handle
  773. * @qdf_dev: QDF device
  774. *
  775. * This function should be called as part of HIF initialization (for accessing
  776. * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle()
  777. *
  778. * Return: Opaque HAL SOC handle
  779. * NULL on failure (if given ring is not available)
  780. */
  781. void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev);
  782. /**
  783. * hal_detach() - Detach HAL layer
  784. * @hal_soc: HAL SOC handle
  785. *
  786. * This function should be called as part of HIF detach
  787. *
  788. */
  789. void hal_detach(void *hal_soc);
  790. #define HAL_SRNG_LMAC_RING 0x80000000
  791. /* SRNG flags passed in hal_srng_params.flags */
  792. #define HAL_SRNG_MSI_SWAP 0x00000008
  793. #define HAL_SRNG_RING_PTR_SWAP 0x00000010
  794. #define HAL_SRNG_DATA_TLV_SWAP 0x00000020
  795. #define HAL_SRNG_LOW_THRES_INTR_ENABLE 0x00010000
  796. #define HAL_SRNG_MSI_INTR 0x00020000
  797. #define HAL_SRNG_CACHED_DESC 0x00040000
  798. #if defined(QCA_WIFI_QCA6490) || defined(QCA_WIFI_KIWI)
  799. #define HAL_SRNG_PREFETCH_TIMER 1
  800. #else
  801. #define HAL_SRNG_PREFETCH_TIMER 0
  802. #endif
  803. #define PN_SIZE_24 0
  804. #define PN_SIZE_48 1
  805. #define PN_SIZE_128 2
  806. #ifdef FORCE_WAKE
  807. /**
  808. * hal_set_init_phase() - Indicate initialization of
  809. * datapath rings
  810. * @soc: hal_soc handle
  811. * @init_phase: flag to indicate datapath rings
  812. * initialization status
  813. *
  814. * Return: None
  815. */
  816. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase);
  817. #else
  818. static inline
  819. void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase)
  820. {
  821. }
  822. #endif /* FORCE_WAKE */
  823. /**
  824. * hal_srng_get_entrysize() - Returns size of ring entry in bytes.
  825. * @hal_soc: Opaque HAL SOC handle
  826. * @ring_type: one of the types from hal_ring_type
  827. *
  828. * Should be used by callers for calculating the size of memory to be
  829. * allocated before calling hal_srng_setup to setup the ring
  830. *
  831. * Return: ring entry size
  832. */
  833. uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type);
  834. /**
  835. * hal_srng_max_entries() - Returns maximum possible number of ring entries
  836. * @hal_soc: Opaque HAL SOC handle
  837. * @ring_type: one of the types from hal_ring_type
  838. *
  839. * Return: Maximum number of entries for the given ring_type
  840. */
  841. uint32_t hal_srng_max_entries(void *hal_soc, int ring_type);
  842. void hal_set_low_threshold(hal_ring_handle_t hal_ring_hdl,
  843. uint32_t low_threshold);
  844. /**
  845. * hal_srng_dump() - Dump ring status
  846. * @srng: hal srng pointer
  847. */
  848. void hal_srng_dump(struct hal_srng *srng);
  849. /**
  850. * hal_srng_get_dir() - Returns the direction of the ring
  851. * @hal_soc: Opaque HAL SOC handle
  852. * @ring_type: one of the types from hal_ring_type
  853. *
  854. * Return: Ring direction
  855. */
  856. enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type);
  857. /* HAL memory information */
  858. struct hal_mem_info {
  859. /* dev base virtual addr */
  860. void *dev_base_addr;
  861. /* dev base physical addr */
  862. void *dev_base_paddr;
  863. /* dev base ce virtual addr - applicable only for qca5018 */
  864. /* In qca5018 CE register are outside wcss block */
  865. /* using a separate address space to access CE registers */
  866. void *dev_base_addr_ce;
  867. /* dev base ce physical addr */
  868. void *dev_base_paddr_ce;
  869. /* Remote virtual pointer memory for HW/FW updates */
  870. void *shadow_rdptr_mem_vaddr;
  871. /* Remote physical pointer memory for HW/FW updates */
  872. void *shadow_rdptr_mem_paddr;
  873. /* Shared memory for ring pointer updates from host to FW */
  874. void *shadow_wrptr_mem_vaddr;
  875. /* Shared physical memory for ring pointer updates from host to FW */
  876. void *shadow_wrptr_mem_paddr;
  877. /* lmac srng start id */
  878. uint8_t lmac_srng_start_id;
  879. };
  880. /* SRNG parameters to be passed to hal_srng_setup */
  881. struct hal_srng_params {
  882. /* Physical base address of the ring */
  883. qdf_dma_addr_t ring_base_paddr;
  884. /* Virtual base address of the ring */
  885. void *ring_base_vaddr;
  886. /* Number of entries in ring */
  887. uint32_t num_entries;
  888. /* max transfer length */
  889. uint16_t max_buffer_length;
  890. /* MSI Address */
  891. qdf_dma_addr_t msi_addr;
  892. /* MSI data */
  893. uint32_t msi_data;
  894. /* Interrupt timer threshold – in micro seconds */
  895. uint32_t intr_timer_thres_us;
  896. /* Interrupt batch counter threshold – in number of ring entries */
  897. uint32_t intr_batch_cntr_thres_entries;
  898. /* Low threshold – in number of ring entries
  899. * (valid for src rings only)
  900. */
  901. uint32_t low_threshold;
  902. /* Misc flags */
  903. uint32_t flags;
  904. /* Unique ring id */
  905. uint8_t ring_id;
  906. /* Source or Destination ring */
  907. enum hal_srng_dir ring_dir;
  908. /* Size of ring entry */
  909. uint32_t entry_size;
  910. /* hw register base address */
  911. void *hwreg_base[MAX_SRNG_REG_GROUPS];
  912. /* prefetch timer config - in micro seconds */
  913. uint32_t prefetch_timer;
  914. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  915. /* Near full IRQ support flag */
  916. uint32_t nf_irq_support;
  917. /* MSI2 Address */
  918. qdf_dma_addr_t msi2_addr;
  919. /* MSI2 data */
  920. uint32_t msi2_data;
  921. /* Critical threshold */
  922. uint16_t crit_thresh;
  923. /* High threshold */
  924. uint16_t high_thresh;
  925. /* Safe threshold */
  926. uint16_t safe_thresh;
  927. #endif
  928. /* Timer threshold to issue ring pointer update - in micro seconds */
  929. uint16_t pointer_timer_threshold;
  930. /* Number threshold of ring entries to issue pointer update */
  931. uint8_t pointer_num_threshold;
  932. };
  933. /**
  934. * hal_construct_srng_shadow_regs() - initialize the shadow
  935. * registers for srngs
  936. * @hal_soc: hal handle
  937. *
  938. * Return: QDF_STATUS_OK on success
  939. */
  940. QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc);
  941. /**
  942. * hal_set_one_shadow_config() - add a config for the specified ring
  943. * @hal_soc: hal handle
  944. * @ring_type: ring type
  945. * @ring_num: ring num
  946. *
  947. * The ring type and ring num uniquely specify the ring. After this call,
  948. * the hp/tp will be added as the next entry int the shadow register
  949. * configuration table. The hal code will use the shadow register address
  950. * in place of the hp/tp address.
  951. *
  952. * This function is exposed, so that the CE module can skip configuring shadow
  953. * registers for unused ring and rings assigned to the firmware.
  954. *
  955. * Return: QDF_STATUS_OK on success
  956. */
  957. QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type,
  958. int ring_num);
  959. /**
  960. * hal_get_shadow_config() - retrieve the config table for shadow cfg v2
  961. * @hal_soc: hal handle
  962. * @shadow_config: will point to the table after
  963. * @num_shadow_registers_configured: will contain the number of valid entries
  964. */
  965. extern void
  966. hal_get_shadow_config(void *hal_soc,
  967. struct pld_shadow_reg_v2_cfg **shadow_config,
  968. int *num_shadow_registers_configured);
  969. #ifdef CONFIG_SHADOW_V3
  970. /**
  971. * hal_get_shadow_v3_config() - retrieve the config table for shadow cfg v3
  972. * @hal_soc: hal handle
  973. * @shadow_config: will point to the table after
  974. * @num_shadow_registers_configured: will contain the number of valid entries
  975. */
  976. extern void
  977. hal_get_shadow_v3_config(void *hal_soc,
  978. struct pld_shadow_reg_v3_cfg **shadow_config,
  979. int *num_shadow_registers_configured);
  980. #endif
  981. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  982. /**
  983. * hal_srng_is_near_full_irq_supported() - Check if srng supports near full irq
  984. * @hal_soc: HAL SoC handle [To be validated by caller]
  985. * @ring_type: srng type
  986. * @ring_num: The index of the srng (of the same type)
  987. *
  988. * Return: true, if srng support near full irq trigger
  989. * false, if the srng does not support near full irq support.
  990. */
  991. bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc,
  992. int ring_type, int ring_num);
  993. #else
  994. static inline
  995. bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc,
  996. int ring_type, int ring_num)
  997. {
  998. return false;
  999. }
  1000. #endif
  1001. /**
  1002. * hal_srng_setup() - Initialize HW SRNG ring.
  1003. * @hal_soc: Opaque HAL SOC handle
  1004. * @ring_type: one of the types from hal_ring_type
  1005. * @ring_num: Ring number if there are multiple rings of
  1006. * same type (staring from 0)
  1007. * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings
  1008. * @ring_params: SRNG ring params in hal_srng_params structure.
  1009. * @idle_check: Check if ring is idle
  1010. *
  1011. * Callers are expected to allocate contiguous ring memory of size
  1012. * 'num_entries * entry_size' bytes and pass the physical and virtual base
  1013. * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in hal_srng_params
  1014. * structure. Ring base address should be 8 byte aligned and size of each ring
  1015. * entry should be queried using the API hal_srng_get_entrysize
  1016. *
  1017. * Return: Opaque pointer to ring on success
  1018. * NULL on failure (if given ring is not available)
  1019. */
  1020. void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
  1021. int mac_id, struct hal_srng_params *ring_params,
  1022. bool idle_check);
  1023. /**
  1024. * hal_srng_setup_idx() - Initialize HW SRNG ring.
  1025. * @hal_soc: Opaque HAL SOC handle
  1026. * @ring_type: one of the types from hal_ring_type
  1027. * @ring_num: Ring number if there are multiple rings of
  1028. * same type (staring from 0)
  1029. * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings
  1030. * @ring_params: SRNG ring params in hal_srng_params structure.
  1031. * @idle_check: Check if ring is idle
  1032. * @idx: Ring index
  1033. *
  1034. * Callers are expected to allocate contiguous ring memory of size
  1035. * 'num_entries * entry_size' bytes and pass the physical and virtual base
  1036. * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in hal_srng_params
  1037. * structure. Ring base address should be 8 byte aligned and size of each ring
  1038. * entry should be queried using the API hal_srng_get_entrysize
  1039. *
  1040. * Return: Opaque pointer to ring on success
  1041. * NULL on failure (if given ring is not available)
  1042. */
  1043. void *hal_srng_setup_idx(void *hal_soc, int ring_type, int ring_num,
  1044. int mac_id, struct hal_srng_params *ring_params,
  1045. bool idle_check, uint32_t idx);
  1046. /* Remapping ids of REO rings */
  1047. #define REO_REMAP_TCL 0
  1048. #define REO_REMAP_SW1 1
  1049. #define REO_REMAP_SW2 2
  1050. #define REO_REMAP_SW3 3
  1051. #define REO_REMAP_SW4 4
  1052. #define REO_REMAP_RELEASE 5
  1053. #define REO_REMAP_FW 6
  1054. /*
  1055. * In Beryllium: 4 bits REO destination ring value is defined as: 0: TCL
  1056. * 1:SW1 2:SW2 3:SW3 4:SW4 5:Release 6:FW(WIFI) 7:SW5
  1057. * 8:SW6 9:SW7 10:SW8 11: NOT_USED.
  1058. *
  1059. */
  1060. #define REO_REMAP_SW5 7
  1061. #define REO_REMAP_SW6 8
  1062. #define REO_REMAP_SW7 9
  1063. #define REO_REMAP_SW8 10
  1064. /*
  1065. * Macro to access HWIO_REO_R0_ERROR_DESTINATION_RING_CTRL_IX_0
  1066. * to map destination to rings
  1067. */
  1068. #define HAL_REO_ERR_REMAP_IX0(_VALUE, _OFFSET) \
  1069. ((_VALUE) << \
  1070. (HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_ ## \
  1071. DESTINATION_RING_ ## _OFFSET ## _SHFT))
  1072. /*
  1073. * Macro to access HWIO_REO_R0_ERROR_DESTINATION_RING_CTRL_IX_1
  1074. * to map destination to rings
  1075. */
  1076. #define HAL_REO_ERR_REMAP_IX1(_VALUE, _OFFSET) \
  1077. ((_VALUE) << \
  1078. (HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_ ## \
  1079. DESTINATION_RING_ ## _OFFSET ## _SHFT))
  1080. /*
  1081. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0
  1082. * to map destination to rings
  1083. */
  1084. #define HAL_REO_REMAP_IX0(_VALUE, _OFFSET) \
  1085. ((_VALUE) << \
  1086. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_ ## \
  1087. _OFFSET ## _SHFT))
  1088. /*
  1089. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1
  1090. * to map destination to rings
  1091. */
  1092. #define HAL_REO_REMAP_IX2(_VALUE, _OFFSET) \
  1093. ((_VALUE) << \
  1094. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_ ## \
  1095. _OFFSET ## _SHFT))
  1096. /*
  1097. * Macro to access HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3
  1098. * to map destination to rings
  1099. */
  1100. #define HAL_REO_REMAP_IX3(_VALUE, _OFFSET) \
  1101. ((_VALUE) << \
  1102. (HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_ ## \
  1103. _OFFSET ## _SHFT))
  1104. /**
  1105. * hal_reo_read_write_ctrl_ix() - Read or write REO_DESTINATION_RING_CTRL_IX
  1106. * @hal_soc_hdl: HAL SOC handle
  1107. * @read: boolean value to indicate if read or write
  1108. * @ix0: pointer to store IX0 reg value
  1109. * @ix1: pointer to store IX1 reg value
  1110. * @ix2: pointer to store IX2 reg value
  1111. * @ix3: pointer to store IX3 reg value
  1112. */
  1113. void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read,
  1114. uint32_t *ix0, uint32_t *ix1,
  1115. uint32_t *ix2, uint32_t *ix3);
  1116. /**
  1117. * hal_srng_dst_set_hp_paddr_confirm() - Set physical address to dest SRNG head
  1118. * pointer and confirm that write went through by reading back the value
  1119. * @sring: sring pointer
  1120. * @paddr: physical address
  1121. *
  1122. * Return: None
  1123. */
  1124. void hal_srng_dst_set_hp_paddr_confirm(struct hal_srng *sring,
  1125. uint64_t paddr);
  1126. /**
  1127. * hal_srng_dst_init_hp() - Initialize head pointer with cached head pointer
  1128. * @hal_soc: hal_soc handle
  1129. * @srng: sring pointer
  1130. * @vaddr: virtual address
  1131. */
  1132. void hal_srng_dst_init_hp(struct hal_soc_handle *hal_soc,
  1133. struct hal_srng *srng,
  1134. uint32_t *vaddr);
  1135. /**
  1136. * hal_srng_cleanup() - Deinitialize HW SRNG ring.
  1137. * @hal_soc: Opaque HAL SOC handle
  1138. * @hal_ring_hdl: Opaque HAL SRNG pointer
  1139. * @umac_reset_inprogress: UMAC reset enabled/disabled.
  1140. */
  1141. void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl,
  1142. bool umac_reset_inprogress);
  1143. static inline bool hal_srng_initialized(hal_ring_handle_t hal_ring_hdl)
  1144. {
  1145. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1146. return !!srng->initialized;
  1147. }
  1148. /**
  1149. * hal_srng_dst_peek() - Check if there are any entries in the ring (peek)
  1150. * @hal_soc_hdl: Opaque HAL SOC handle
  1151. * @hal_ring_hdl: Destination ring pointer
  1152. *
  1153. * Caller takes responsibility for any locking needs.
  1154. *
  1155. * Return: Opaque pointer for next ring entry; NULL on failire
  1156. */
  1157. static inline
  1158. void *hal_srng_dst_peek(hal_soc_handle_t hal_soc_hdl,
  1159. hal_ring_handle_t hal_ring_hdl)
  1160. {
  1161. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1162. if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp)
  1163. return (void *)(&srng->ring_base_vaddr[srng->u.dst_ring.tp]);
  1164. return NULL;
  1165. }
  1166. /**
  1167. * hal_mem_dma_cache_sync() - Cache sync the specified virtual address Range
  1168. * @soc: HAL soc handle
  1169. * @desc: desc start address
  1170. * @entry_size: size of memory to sync
  1171. *
  1172. * Return: void
  1173. */
  1174. #if defined(__LINUX_MIPS32_ARCH__) || defined(__LINUX_MIPS64_ARCH__)
  1175. static inline void hal_mem_dma_cache_sync(struct hal_soc *soc, uint32_t *desc,
  1176. uint32_t entry_size)
  1177. {
  1178. qdf_nbuf_dma_inv_range((void *)desc, (void *)(desc + entry_size));
  1179. }
  1180. #else
  1181. static inline void hal_mem_dma_cache_sync(struct hal_soc *soc, uint32_t *desc,
  1182. uint32_t entry_size)
  1183. {
  1184. qdf_mem_dma_cache_sync(soc->qdf_dev, qdf_mem_virt_to_phys(desc),
  1185. QDF_DMA_FROM_DEVICE,
  1186. (entry_size * sizeof(uint32_t)));
  1187. }
  1188. #endif
  1189. /**
  1190. * hal_srng_access_start_unlocked() - Start ring access (unlocked). Should use
  1191. * hal_srng_access_start() if locked access is required
  1192. * @hal_soc_hdl: Opaque HAL SOC handle
  1193. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1194. *
  1195. * This API doesn't implement any byte-order conversion on reading hp/tp.
  1196. * So, Use API only for those srngs for which the target writes hp/tp values to
  1197. * the DDR in the Host order.
  1198. *
  1199. * Return: 0 on success; error on failire
  1200. */
  1201. static inline int
  1202. hal_srng_access_start_unlocked(hal_soc_handle_t hal_soc_hdl,
  1203. hal_ring_handle_t hal_ring_hdl)
  1204. {
  1205. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1206. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  1207. uint32_t *desc;
  1208. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1209. srng->u.src_ring.cached_tp =
  1210. *(volatile uint32_t *)(srng->u.src_ring.tp_addr);
  1211. else {
  1212. srng->u.dst_ring.cached_hp =
  1213. *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1214. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  1215. desc = hal_srng_dst_peek(hal_soc_hdl, hal_ring_hdl);
  1216. if (qdf_likely(desc)) {
  1217. hal_mem_dma_cache_sync(soc, desc,
  1218. srng->entry_size);
  1219. qdf_prefetch(desc);
  1220. }
  1221. }
  1222. }
  1223. return 0;
  1224. }
  1225. /**
  1226. * hal_le_srng_access_start_unlocked_in_cpu_order() - Start ring access
  1227. * (unlocked) with endianness correction.
  1228. * @hal_soc_hdl: Opaque HAL SOC handle
  1229. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1230. *
  1231. * This API provides same functionally as hal_srng_access_start_unlocked()
  1232. * except that it converts the little-endian formatted hp/tp values to
  1233. * Host order on reading them. So, this API should only be used for those srngs
  1234. * for which the target always writes hp/tp values in little-endian order
  1235. * regardless of Host order.
  1236. *
  1237. * Also, this API doesn't take the lock. For locked access, use
  1238. * hal_srng_access_start/hal_le_srng_access_start_in_cpu_order.
  1239. *
  1240. * Return: 0 on success; error on failire
  1241. */
  1242. static inline int
  1243. hal_le_srng_access_start_unlocked_in_cpu_order(
  1244. hal_soc_handle_t hal_soc_hdl,
  1245. hal_ring_handle_t hal_ring_hdl)
  1246. {
  1247. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1248. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  1249. uint32_t *desc;
  1250. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  1251. srng->u.src_ring.cached_tp =
  1252. qdf_le32_to_cpu(*(volatile uint32_t *)
  1253. (srng->u.src_ring.tp_addr));
  1254. else {
  1255. srng->u.dst_ring.cached_hp =
  1256. qdf_le32_to_cpu(*(volatile uint32_t *)
  1257. (srng->u.dst_ring.hp_addr));
  1258. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  1259. desc = hal_srng_dst_peek(hal_soc_hdl, hal_ring_hdl);
  1260. if (qdf_likely(desc)) {
  1261. hal_mem_dma_cache_sync(soc, desc,
  1262. srng->entry_size);
  1263. qdf_prefetch(desc);
  1264. }
  1265. }
  1266. }
  1267. return 0;
  1268. }
  1269. /**
  1270. * hal_srng_try_access_start() - Try to start (locked) ring access
  1271. * @hal_soc_hdl: Opaque HAL SOC handle
  1272. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1273. *
  1274. * Return: 0 on success; error on failure
  1275. */
  1276. static inline int hal_srng_try_access_start(hal_soc_handle_t hal_soc_hdl,
  1277. hal_ring_handle_t hal_ring_hdl)
  1278. {
  1279. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1280. if (qdf_unlikely(!hal_ring_hdl)) {
  1281. qdf_print("Error: Invalid hal_ring\n");
  1282. return -EINVAL;
  1283. }
  1284. if (!SRNG_TRY_LOCK(&(srng->lock)))
  1285. return -EINVAL;
  1286. return hal_srng_access_start_unlocked(hal_soc_hdl, hal_ring_hdl);
  1287. }
  1288. /**
  1289. * hal_srng_access_start() - Start (locked) ring access
  1290. *
  1291. * @hal_soc_hdl: Opaque HAL SOC handle
  1292. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1293. *
  1294. * This API doesn't implement any byte-order conversion on reading hp/tp.
  1295. * So, Use API only for those srngs for which the target writes hp/tp values to
  1296. * the DDR in the Host order.
  1297. *
  1298. * Return: 0 on success; error on failire
  1299. */
  1300. static inline int hal_srng_access_start(hal_soc_handle_t hal_soc_hdl,
  1301. hal_ring_handle_t hal_ring_hdl)
  1302. {
  1303. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1304. if (qdf_unlikely(!hal_ring_hdl)) {
  1305. qdf_print("Error: Invalid hal_ring\n");
  1306. return -EINVAL;
  1307. }
  1308. SRNG_LOCK(&(srng->lock));
  1309. return hal_srng_access_start_unlocked(hal_soc_hdl, hal_ring_hdl);
  1310. }
  1311. /**
  1312. * hal_le_srng_access_start_in_cpu_order() - Start (locked) ring access with
  1313. * endianness correction
  1314. * @hal_soc_hdl: Opaque HAL SOC handle
  1315. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  1316. *
  1317. * This API provides same functionally as hal_srng_access_start()
  1318. * except that it converts the little-endian formatted hp/tp values to
  1319. * Host order on reading them. So, this API should only be used for those srngs
  1320. * for which the target always writes hp/tp values in little-endian order
  1321. * regardless of Host order.
  1322. *
  1323. * Return: 0 on success; error on failire
  1324. */
  1325. static inline int
  1326. hal_le_srng_access_start_in_cpu_order(
  1327. hal_soc_handle_t hal_soc_hdl,
  1328. hal_ring_handle_t hal_ring_hdl)
  1329. {
  1330. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1331. if (qdf_unlikely(!hal_ring_hdl)) {
  1332. qdf_print("Error: Invalid hal_ring\n");
  1333. return -EINVAL;
  1334. }
  1335. SRNG_LOCK(&(srng->lock));
  1336. return hal_le_srng_access_start_unlocked_in_cpu_order(
  1337. hal_soc_hdl, hal_ring_hdl);
  1338. }
  1339. /**
  1340. * hal_srng_dst_get_next() - Get next entry from a destination ring
  1341. * @hal_soc: Opaque HAL SOC handle
  1342. * @hal_ring_hdl: Destination ring pointer
  1343. *
  1344. * Return: Opaque pointer for next ring entry; NULL on failure
  1345. */
  1346. static inline
  1347. void *hal_srng_dst_get_next(void *hal_soc,
  1348. hal_ring_handle_t hal_ring_hdl)
  1349. {
  1350. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1351. uint32_t *desc;
  1352. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  1353. return NULL;
  1354. desc = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1355. /* TODO: Using % is expensive, but we have to do this since
  1356. * size of some SRNG rings is not power of 2 (due to descriptor
  1357. * sizes). Need to create separate API for rings used
  1358. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1359. * SW2RXDMA and CE rings)
  1360. */
  1361. srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size);
  1362. if (srng->u.dst_ring.tp == srng->ring_size)
  1363. srng->u.dst_ring.tp = 0;
  1364. if (srng->flags & HAL_SRNG_CACHED_DESC) {
  1365. struct hal_soc *soc = (struct hal_soc *)hal_soc;
  1366. uint32_t *desc_next;
  1367. uint32_t tp;
  1368. tp = srng->u.dst_ring.tp;
  1369. desc_next = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1370. hal_mem_dma_cache_sync(soc, desc_next, srng->entry_size);
  1371. qdf_prefetch(desc_next);
  1372. }
  1373. return (void *)desc;
  1374. }
  1375. /**
  1376. * hal_srng_dst_get_next_cached() - Get cached next entry
  1377. * @hal_soc: Opaque HAL SOC handle
  1378. * @hal_ring_hdl: Destination ring pointer
  1379. *
  1380. * Get next entry from a destination ring and move cached tail pointer
  1381. *
  1382. * Return: Opaque pointer for next ring entry; NULL on failure
  1383. */
  1384. static inline
  1385. void *hal_srng_dst_get_next_cached(void *hal_soc,
  1386. hal_ring_handle_t hal_ring_hdl)
  1387. {
  1388. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1389. uint32_t *desc;
  1390. uint32_t *desc_next;
  1391. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  1392. return NULL;
  1393. desc = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1394. /* TODO: Using % is expensive, but we have to do this since
  1395. * size of some SRNG rings is not power of 2 (due to descriptor
  1396. * sizes). Need to create separate API for rings used
  1397. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1398. * SW2RXDMA and CE rings)
  1399. */
  1400. srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size);
  1401. if (srng->u.dst_ring.tp == srng->ring_size)
  1402. srng->u.dst_ring.tp = 0;
  1403. desc_next = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1404. qdf_prefetch(desc_next);
  1405. return (void *)desc;
  1406. }
  1407. /**
  1408. * hal_srng_dst_dec_tp() - decrement the TP of the Dst ring by one entry
  1409. * @hal_soc: Opaque HAL SOC handle
  1410. * @hal_ring_hdl: Destination ring pointer
  1411. *
  1412. * reset the tail pointer in the destination ring by one entry
  1413. *
  1414. */
  1415. static inline
  1416. void hal_srng_dst_dec_tp(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1417. {
  1418. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1419. if (qdf_unlikely(!srng->u.dst_ring.tp))
  1420. srng->u.dst_ring.tp = (srng->ring_size - srng->entry_size);
  1421. else
  1422. srng->u.dst_ring.tp -= srng->entry_size;
  1423. }
  1424. static inline int hal_srng_lock(hal_ring_handle_t hal_ring_hdl)
  1425. {
  1426. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1427. if (qdf_unlikely(!hal_ring_hdl)) {
  1428. qdf_print("error: invalid hal_ring\n");
  1429. return -EINVAL;
  1430. }
  1431. SRNG_LOCK(&(srng->lock));
  1432. return 0;
  1433. }
  1434. static inline int hal_srng_unlock(hal_ring_handle_t hal_ring_hdl)
  1435. {
  1436. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1437. if (qdf_unlikely(!hal_ring_hdl)) {
  1438. qdf_print("error: invalid hal_ring\n");
  1439. return -EINVAL;
  1440. }
  1441. SRNG_UNLOCK(&(srng->lock));
  1442. return 0;
  1443. }
  1444. /**
  1445. * hal_srng_dst_get_next_hp() - Get next entry from a destination ring and move
  1446. * cached head pointer
  1447. * @hal_soc_hdl: Opaque HAL SOC handle
  1448. * @hal_ring_hdl: Destination ring pointer
  1449. *
  1450. * Return: Opaque pointer for next ring entry; NULL on failire
  1451. */
  1452. static inline void *
  1453. hal_srng_dst_get_next_hp(hal_soc_handle_t hal_soc_hdl,
  1454. hal_ring_handle_t hal_ring_hdl)
  1455. {
  1456. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1457. uint32_t *desc;
  1458. /* TODO: Using % is expensive, but we have to do this since
  1459. * size of some SRNG rings is not power of 2 (due to descriptor
  1460. * sizes). Need to create separate API for rings used
  1461. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1462. * SW2RXDMA and CE rings)
  1463. */
  1464. uint32_t next_hp = (srng->u.dst_ring.cached_hp + srng->entry_size) %
  1465. srng->ring_size;
  1466. if (next_hp != srng->u.dst_ring.tp) {
  1467. desc = &(srng->ring_base_vaddr[srng->u.dst_ring.cached_hp]);
  1468. srng->u.dst_ring.cached_hp = next_hp;
  1469. return (void *)desc;
  1470. }
  1471. return NULL;
  1472. }
  1473. /**
  1474. * hal_srng_dst_peek_sync() - Check if there are any entries in the ring (peek)
  1475. * @hal_soc_hdl: Opaque HAL SOC handle
  1476. * @hal_ring_hdl: Destination ring pointer
  1477. *
  1478. * Sync cached head pointer with HW.
  1479. * Caller takes responsibility for any locking needs.
  1480. *
  1481. * Return: Opaque pointer for next ring entry; NULL on failire
  1482. */
  1483. static inline
  1484. void *hal_srng_dst_peek_sync(hal_soc_handle_t hal_soc_hdl,
  1485. hal_ring_handle_t hal_ring_hdl)
  1486. {
  1487. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1488. srng->u.dst_ring.cached_hp =
  1489. *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1490. if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp)
  1491. return (void *)(&(srng->ring_base_vaddr[srng->u.dst_ring.tp]));
  1492. return NULL;
  1493. }
  1494. /**
  1495. * hal_srng_dst_peek_sync_locked() - Peek for any entries in the ring
  1496. * @hal_soc_hdl: Opaque HAL SOC handle
  1497. * @hal_ring_hdl: Destination ring pointer
  1498. *
  1499. * Sync cached head pointer with HW.
  1500. * This function takes up SRNG_LOCK. Should not be called with SRNG lock held.
  1501. *
  1502. * Return: Opaque pointer for next ring entry; NULL on failire
  1503. */
  1504. static inline
  1505. void *hal_srng_dst_peek_sync_locked(hal_soc_handle_t hal_soc_hdl,
  1506. hal_ring_handle_t hal_ring_hdl)
  1507. {
  1508. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1509. void *ring_desc_ptr = NULL;
  1510. if (qdf_unlikely(!hal_ring_hdl)) {
  1511. qdf_print("Error: Invalid hal_ring\n");
  1512. return NULL;
  1513. }
  1514. SRNG_LOCK(&srng->lock);
  1515. ring_desc_ptr = hal_srng_dst_peek_sync(hal_soc_hdl, hal_ring_hdl);
  1516. SRNG_UNLOCK(&srng->lock);
  1517. return ring_desc_ptr;
  1518. }
  1519. #define hal_srng_dst_num_valid_nolock(hal_soc, hal_ring_hdl, sync_hw_ptr) \
  1520. hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, sync_hw_ptr)
  1521. /**
  1522. * hal_srng_dst_num_valid() - Returns number of valid entries (to be processed
  1523. * by SW) in destination ring
  1524. * @hal_soc: Opaque HAL SOC handle
  1525. * @hal_ring_hdl: Destination ring pointer
  1526. * @sync_hw_ptr: Sync cached head pointer with HW
  1527. *
  1528. * Return: number of valid entries
  1529. */
  1530. static inline
  1531. uint32_t hal_srng_dst_num_valid(void *hal_soc,
  1532. hal_ring_handle_t hal_ring_hdl,
  1533. int sync_hw_ptr)
  1534. {
  1535. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1536. uint32_t hp;
  1537. uint32_t tp = srng->u.dst_ring.tp;
  1538. if (sync_hw_ptr) {
  1539. hp = *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1540. srng->u.dst_ring.cached_hp = hp;
  1541. } else {
  1542. hp = srng->u.dst_ring.cached_hp;
  1543. }
  1544. if (hp >= tp)
  1545. return (hp - tp) / srng->entry_size;
  1546. return (srng->ring_size - tp + hp) / srng->entry_size;
  1547. }
  1548. /**
  1549. * hal_srng_dst_inv_cached_descs() - API to invalidate descriptors in batch mode
  1550. * @hal_soc: Opaque HAL SOC handle
  1551. * @hal_ring_hdl: Destination ring pointer
  1552. * @entry_count: call invalidate API if valid entries available
  1553. *
  1554. * Invalidates a set of cached descriptors starting from TP to cached_HP
  1555. *
  1556. * Return: None
  1557. */
  1558. static inline void hal_srng_dst_inv_cached_descs(void *hal_soc,
  1559. hal_ring_handle_t hal_ring_hdl,
  1560. uint32_t entry_count)
  1561. {
  1562. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1563. uint32_t *first_desc;
  1564. uint32_t *last_desc;
  1565. uint32_t last_desc_index;
  1566. /*
  1567. * If SRNG does not have cached descriptors this
  1568. * API call should be a no op
  1569. */
  1570. if (!(srng->flags & HAL_SRNG_CACHED_DESC))
  1571. return;
  1572. if (!entry_count)
  1573. return;
  1574. first_desc = &srng->ring_base_vaddr[srng->u.dst_ring.tp];
  1575. last_desc_index = (srng->u.dst_ring.tp +
  1576. (entry_count * srng->entry_size)) %
  1577. srng->ring_size;
  1578. last_desc = &srng->ring_base_vaddr[last_desc_index];
  1579. if (last_desc > (uint32_t *)first_desc)
  1580. /* invalidate from tp to cached_hp */
  1581. qdf_nbuf_dma_inv_range_no_dsb((void *)first_desc,
  1582. (void *)(last_desc));
  1583. else {
  1584. /* invalidate from tp to end of the ring */
  1585. qdf_nbuf_dma_inv_range_no_dsb((void *)first_desc,
  1586. (void *)srng->ring_vaddr_end);
  1587. /* invalidate from start of ring to cached_hp */
  1588. qdf_nbuf_dma_inv_range_no_dsb((void *)srng->ring_base_vaddr,
  1589. (void *)last_desc);
  1590. }
  1591. qdf_dsb();
  1592. }
  1593. /**
  1594. * hal_srng_dst_num_valid_locked() - Returns num valid entries to be processed
  1595. * @hal_soc: Opaque HAL SOC handle
  1596. * @hal_ring_hdl: Destination ring pointer
  1597. * @sync_hw_ptr: Sync cached head pointer with HW
  1598. *
  1599. * Returns number of valid entries to be processed by the host driver. The
  1600. * function takes up SRNG lock.
  1601. *
  1602. * Return: Number of valid destination entries
  1603. */
  1604. static inline uint32_t
  1605. hal_srng_dst_num_valid_locked(hal_soc_handle_t hal_soc,
  1606. hal_ring_handle_t hal_ring_hdl,
  1607. int sync_hw_ptr)
  1608. {
  1609. uint32_t num_valid;
  1610. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1611. SRNG_LOCK(&srng->lock);
  1612. num_valid = hal_srng_dst_num_valid(hal_soc, hal_ring_hdl, sync_hw_ptr);
  1613. SRNG_UNLOCK(&srng->lock);
  1614. return num_valid;
  1615. }
  1616. /**
  1617. * hal_srng_sync_cachedhp() - sync cachehp pointer from hw hp
  1618. * @hal_soc: Opaque HAL SOC handle
  1619. * @hal_ring_hdl: Destination ring pointer
  1620. *
  1621. */
  1622. static inline
  1623. void hal_srng_sync_cachedhp(void *hal_soc,
  1624. hal_ring_handle_t hal_ring_hdl)
  1625. {
  1626. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1627. uint32_t hp;
  1628. hp = *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  1629. srng->u.dst_ring.cached_hp = hp;
  1630. }
  1631. /**
  1632. * hal_srng_src_reap_next() - Reap next entry from a source ring
  1633. * @hal_soc: Opaque HAL SOC handle
  1634. * @hal_ring_hdl: Source ring pointer
  1635. *
  1636. * Reaps next entry from a source ring and moves reap pointer. This
  1637. * can be used to release any buffers associated with completed ring
  1638. * entries. Note that this should not be used for posting new
  1639. * descriptor entries. Posting of new entries should be done only
  1640. * using hal_srng_src_get_next_reaped() when this function is used for
  1641. * reaping.
  1642. *
  1643. * Return: Opaque pointer for next ring entry; NULL on failire
  1644. */
  1645. static inline void *
  1646. hal_srng_src_reap_next(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1647. {
  1648. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1649. uint32_t *desc;
  1650. /* TODO: Using % is expensive, but we have to do this since
  1651. * size of some SRNG rings is not power of 2 (due to descriptor
  1652. * sizes). Need to create separate API for rings used
  1653. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1654. * SW2RXDMA and CE rings)
  1655. */
  1656. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1657. srng->ring_size;
  1658. if (next_reap_hp != srng->u.src_ring.cached_tp) {
  1659. desc = &(srng->ring_base_vaddr[next_reap_hp]);
  1660. srng->u.src_ring.reap_hp = next_reap_hp;
  1661. return (void *)desc;
  1662. }
  1663. return NULL;
  1664. }
  1665. /**
  1666. * hal_srng_src_get_next_reaped() - Get next reaped entry from a source ring
  1667. * @hal_soc: Opaque HAL SOC handle
  1668. * @hal_ring_hdl: Source ring pointer
  1669. *
  1670. * Gets next entry from a source ring that is already reaped using
  1671. * hal_srng_src_reap_next(), for posting new entries to the ring
  1672. *
  1673. * Return: Opaque pointer for next (reaped) source ring entry; NULL on failire
  1674. */
  1675. static inline void *
  1676. hal_srng_src_get_next_reaped(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1677. {
  1678. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1679. uint32_t *desc;
  1680. if (srng->u.src_ring.hp != srng->u.src_ring.reap_hp) {
  1681. desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]);
  1682. srng->u.src_ring.hp = (srng->u.src_ring.hp + srng->entry_size) %
  1683. srng->ring_size;
  1684. return (void *)desc;
  1685. }
  1686. return NULL;
  1687. }
  1688. /**
  1689. * hal_srng_src_pending_reap_next() - Reap next entry from a source ring
  1690. * @hal_soc: Opaque HAL SOC handle
  1691. * @hal_ring_hdl: Source ring pointer
  1692. *
  1693. * Reaps next entry from a source ring and move reap pointer. This API
  1694. * is used in detach path to release any buffers associated with ring
  1695. * entries which are pending reap.
  1696. *
  1697. * Return: Opaque pointer for next ring entry; NULL on failire
  1698. */
  1699. static inline void *
  1700. hal_srng_src_pending_reap_next(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1701. {
  1702. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1703. uint32_t *desc;
  1704. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1705. srng->ring_size;
  1706. if (next_reap_hp != srng->u.src_ring.hp) {
  1707. desc = &(srng->ring_base_vaddr[next_reap_hp]);
  1708. srng->u.src_ring.reap_hp = next_reap_hp;
  1709. return (void *)desc;
  1710. }
  1711. return NULL;
  1712. }
  1713. /**
  1714. * hal_srng_src_done_val() -
  1715. * @hal_soc: Opaque HAL SOC handle
  1716. * @hal_ring_hdl: Source ring pointer
  1717. *
  1718. * Return: Opaque pointer for next ring entry; NULL on failire
  1719. */
  1720. static inline uint32_t
  1721. hal_srng_src_done_val(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1722. {
  1723. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1724. /* TODO: Using % is expensive, but we have to do this since
  1725. * size of some SRNG rings is not power of 2 (due to descriptor
  1726. * sizes). Need to create separate API for rings used
  1727. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1728. * SW2RXDMA and CE rings)
  1729. */
  1730. uint32_t next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) %
  1731. srng->ring_size;
  1732. if (next_reap_hp == srng->u.src_ring.cached_tp)
  1733. return 0;
  1734. if (srng->u.src_ring.cached_tp > next_reap_hp)
  1735. return (srng->u.src_ring.cached_tp - next_reap_hp) /
  1736. srng->entry_size;
  1737. else
  1738. return ((srng->ring_size - next_reap_hp) +
  1739. srng->u.src_ring.cached_tp) / srng->entry_size;
  1740. }
  1741. /**
  1742. * hal_get_entrysize_from_srng() - Retrieve ring entry size
  1743. * @hal_ring_hdl: Source ring pointer
  1744. *
  1745. * srng->entry_size value is in 4 byte dwords so left shifting
  1746. * this by 2 to return the value of entry_size in bytes.
  1747. *
  1748. * Return: uint8_t
  1749. */
  1750. static inline
  1751. uint8_t hal_get_entrysize_from_srng(hal_ring_handle_t hal_ring_hdl)
  1752. {
  1753. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1754. return srng->entry_size << 2;
  1755. }
  1756. /**
  1757. * hal_get_sw_hptp() - Get SW head and tail pointer location for any ring
  1758. * @hal_soc: Opaque HAL SOC handle
  1759. * @hal_ring_hdl: Source ring pointer
  1760. * @tailp: Tail Pointer
  1761. * @headp: Head Pointer
  1762. *
  1763. * Return: Update tail pointer and head pointer in arguments.
  1764. */
  1765. static inline
  1766. void hal_get_sw_hptp(void *hal_soc, hal_ring_handle_t hal_ring_hdl,
  1767. uint32_t *tailp, uint32_t *headp)
  1768. {
  1769. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1770. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  1771. *headp = srng->u.src_ring.hp;
  1772. *tailp = *srng->u.src_ring.tp_addr;
  1773. } else {
  1774. *tailp = srng->u.dst_ring.tp;
  1775. *headp = *srng->u.dst_ring.hp_addr;
  1776. }
  1777. }
  1778. #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
  1779. /**
  1780. * hal_srng_src_get_next_consumed() - Get the next desc if consumed by HW
  1781. * @hal_soc: Opaque HAL SOC handle
  1782. * @hal_ring_hdl: Source ring pointer
  1783. *
  1784. * Return: pointer to descriptor if consumed by HW, else NULL
  1785. */
  1786. static inline
  1787. void *hal_srng_src_get_next_consumed(void *hal_soc,
  1788. hal_ring_handle_t hal_ring_hdl)
  1789. {
  1790. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1791. uint32_t *desc = NULL;
  1792. /* TODO: Using % is expensive, but we have to do this since
  1793. * size of some SRNG rings is not power of 2 (due to descriptor
  1794. * sizes). Need to create separate API for rings used
  1795. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1796. * SW2RXDMA and CE rings)
  1797. */
  1798. uint32_t next_entry = (srng->last_desc_cleared + srng->entry_size) %
  1799. srng->ring_size;
  1800. if (next_entry != srng->u.src_ring.cached_tp) {
  1801. desc = &srng->ring_base_vaddr[next_entry];
  1802. srng->last_desc_cleared = next_entry;
  1803. }
  1804. return desc;
  1805. }
  1806. #else
  1807. static inline
  1808. void *hal_srng_src_get_next_consumed(void *hal_soc,
  1809. hal_ring_handle_t hal_ring_hdl)
  1810. {
  1811. return NULL;
  1812. }
  1813. #endif /* CLEAR_SW2TCL_CONSUMED_DESC */
  1814. /**
  1815. * hal_srng_src_peek() - get the HP of the SRC ring
  1816. * @hal_soc: Opaque HAL SOC handle
  1817. * @hal_ring_hdl: Source ring pointer
  1818. *
  1819. * get the head pointer in the src ring but do not increment it
  1820. *
  1821. * Return: head descriptor
  1822. */
  1823. static inline
  1824. void *hal_srng_src_peek(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  1825. {
  1826. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1827. uint32_t *desc;
  1828. uint32_t next_hp = (srng->u.src_ring.hp + srng->entry_size) %
  1829. srng->ring_size;
  1830. if (next_hp != srng->u.src_ring.cached_tp) {
  1831. desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]);
  1832. return (void *)desc;
  1833. }
  1834. return NULL;
  1835. }
  1836. /**
  1837. * hal_srng_src_get_next() - Get next entry from a source ring and move cached
  1838. * tail pointer
  1839. * @hal_soc: Opaque HAL SOC handle
  1840. * @hal_ring_hdl: Source ring pointer
  1841. *
  1842. * Return: Opaque pointer for next ring entry; NULL on failure
  1843. */
  1844. static inline
  1845. void *hal_srng_src_get_next(void *hal_soc,
  1846. hal_ring_handle_t hal_ring_hdl)
  1847. {
  1848. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1849. uint32_t *desc;
  1850. /* TODO: Using % is expensive, but we have to do this since
  1851. * size of some SRNG rings is not power of 2 (due to descriptor
  1852. * sizes). Need to create separate API for rings used
  1853. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1854. * SW2RXDMA and CE rings)
  1855. */
  1856. uint32_t next_hp = (srng->u.src_ring.hp + srng->entry_size) %
  1857. srng->ring_size;
  1858. if (next_hp != srng->u.src_ring.cached_tp) {
  1859. desc = &(srng->ring_base_vaddr[srng->u.src_ring.hp]);
  1860. srng->u.src_ring.hp = next_hp;
  1861. /* TODO: Since reap function is not used by all rings, we can
  1862. * remove the following update of reap_hp in this function
  1863. * if we can ensure that only hal_srng_src_get_next_reaped
  1864. * is used for the rings requiring reap functionality
  1865. */
  1866. srng->u.src_ring.reap_hp = next_hp;
  1867. return (void *)desc;
  1868. }
  1869. return NULL;
  1870. }
  1871. /**
  1872. * hal_srng_src_peek_n_get_next() - Get next entry from a ring without
  1873. * moving head pointer.
  1874. * @hal_soc_hdl: Opaque HAL SOC handle
  1875. * @hal_ring_hdl: Source ring pointer
  1876. *
  1877. * hal_srng_src_get_next should be called subsequently to move the head pointer
  1878. *
  1879. * Return: Opaque pointer for next ring entry; NULL on failire
  1880. */
  1881. static inline
  1882. void *hal_srng_src_peek_n_get_next(hal_soc_handle_t hal_soc_hdl,
  1883. hal_ring_handle_t hal_ring_hdl)
  1884. {
  1885. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1886. uint32_t *desc;
  1887. /* TODO: Using % is expensive, but we have to do this since
  1888. * size of some SRNG rings is not power of 2 (due to descriptor
  1889. * sizes). Need to create separate API for rings used
  1890. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1891. * SW2RXDMA and CE rings)
  1892. */
  1893. if (((srng->u.src_ring.hp + srng->entry_size) %
  1894. srng->ring_size) != srng->u.src_ring.cached_tp) {
  1895. desc = &(srng->ring_base_vaddr[(srng->u.src_ring.hp +
  1896. srng->entry_size) %
  1897. srng->ring_size]);
  1898. return (void *)desc;
  1899. }
  1900. return NULL;
  1901. }
  1902. /**
  1903. * hal_srng_src_peek_n_get_next_next() - Get next to next, i.e HP + 2 entry from
  1904. * a ring without moving head pointer.
  1905. * @hal_soc_hdl: Opaque HAL SOC handle
  1906. * @hal_ring_hdl: Source ring pointer
  1907. *
  1908. * Return: Opaque pointer for next to next ring entry; NULL on failire
  1909. */
  1910. static inline
  1911. void *hal_srng_src_peek_n_get_next_next(hal_soc_handle_t hal_soc_hdl,
  1912. hal_ring_handle_t hal_ring_hdl)
  1913. {
  1914. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1915. uint32_t *desc;
  1916. /* TODO: Using % is expensive, but we have to do this since
  1917. * size of some SRNG rings is not power of 2 (due to descriptor
  1918. * sizes). Need to create separate API for rings used
  1919. * per-packet, with sizes power of 2 (TCL2SW, REO2SW,
  1920. * SW2RXDMA and CE rings)
  1921. */
  1922. if ((((srng->u.src_ring.hp + (srng->entry_size)) %
  1923. srng->ring_size) != srng->u.src_ring.cached_tp) &&
  1924. (((srng->u.src_ring.hp + (srng->entry_size * 2)) %
  1925. srng->ring_size) != srng->u.src_ring.cached_tp)) {
  1926. desc = &(srng->ring_base_vaddr[(srng->u.src_ring.hp +
  1927. (srng->entry_size * 2)) %
  1928. srng->ring_size]);
  1929. return (void *)desc;
  1930. }
  1931. return NULL;
  1932. }
  1933. /**
  1934. * hal_srng_src_get_cur_hp_n_move_next() - API returns current hp
  1935. * and move hp to next in src ring
  1936. * @hal_soc_hdl: HAL soc handle
  1937. * @hal_ring_hdl: Source ring pointer
  1938. *
  1939. * This API should only be used at init time replenish.
  1940. */
  1941. static inline void *
  1942. hal_srng_src_get_cur_hp_n_move_next(hal_soc_handle_t hal_soc_hdl,
  1943. hal_ring_handle_t hal_ring_hdl)
  1944. {
  1945. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1946. uint32_t *cur_desc = NULL;
  1947. uint32_t next_hp;
  1948. cur_desc = &srng->ring_base_vaddr[(srng->u.src_ring.hp)];
  1949. next_hp = (srng->u.src_ring.hp + srng->entry_size) %
  1950. srng->ring_size;
  1951. if (next_hp != srng->u.src_ring.cached_tp)
  1952. srng->u.src_ring.hp = next_hp;
  1953. return (void *)cur_desc;
  1954. }
  1955. /**
  1956. * hal_srng_src_num_avail() - Returns number of available entries in src ring
  1957. * @hal_soc: Opaque HAL SOC handle
  1958. * @hal_ring_hdl: Source ring pointer
  1959. * @sync_hw_ptr: Sync cached tail pointer with HW
  1960. *
  1961. * Return: number of available entries
  1962. */
  1963. static inline uint32_t
  1964. hal_srng_src_num_avail(void *hal_soc,
  1965. hal_ring_handle_t hal_ring_hdl, int sync_hw_ptr)
  1966. {
  1967. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1968. uint32_t tp;
  1969. uint32_t hp = srng->u.src_ring.hp;
  1970. if (sync_hw_ptr) {
  1971. tp = *(srng->u.src_ring.tp_addr);
  1972. srng->u.src_ring.cached_tp = tp;
  1973. } else {
  1974. tp = srng->u.src_ring.cached_tp;
  1975. }
  1976. if (tp > hp)
  1977. return ((tp - hp) / srng->entry_size) - 1;
  1978. else
  1979. return ((srng->ring_size - hp + tp) / srng->entry_size) - 1;
  1980. }
  1981. #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING
  1982. /**
  1983. * hal_srng_clear_ring_usage_wm_locked() - Clear SRNG usage watermark stats
  1984. * @hal_soc_hdl: HAL soc handle
  1985. * @hal_ring_hdl: SRNG handle
  1986. *
  1987. * This function tries to acquire SRNG lock, and hence should not be called
  1988. * from a context which has already acquired the SRNG lock.
  1989. *
  1990. * Return: None
  1991. */
  1992. static inline
  1993. void hal_srng_clear_ring_usage_wm_locked(hal_soc_handle_t hal_soc_hdl,
  1994. hal_ring_handle_t hal_ring_hdl)
  1995. {
  1996. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  1997. SRNG_LOCK(&srng->lock);
  1998. srng->high_wm.val = 0;
  1999. srng->high_wm.timestamp = 0;
  2000. qdf_mem_zero(&srng->high_wm.bins[0], sizeof(srng->high_wm.bins[0]) *
  2001. HAL_SRNG_HIGH_WM_BIN_MAX);
  2002. SRNG_UNLOCK(&srng->lock);
  2003. }
  2004. /**
  2005. * hal_srng_update_ring_usage_wm_no_lock() - Update the SRNG usage wm stats
  2006. * @hal_soc_hdl: HAL soc handle
  2007. * @hal_ring_hdl: SRNG handle
  2008. *
  2009. * This function should be called with the SRNG lock held.
  2010. *
  2011. * Return: None
  2012. */
  2013. static inline
  2014. void hal_srng_update_ring_usage_wm_no_lock(hal_soc_handle_t hal_soc_hdl,
  2015. hal_ring_handle_t hal_ring_hdl)
  2016. {
  2017. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2018. uint32_t curr_wm_val = 0;
  2019. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  2020. curr_wm_val = hal_srng_src_num_avail(hal_soc_hdl, hal_ring_hdl,
  2021. 0);
  2022. else
  2023. curr_wm_val = hal_srng_dst_num_valid(hal_soc_hdl, hal_ring_hdl,
  2024. 0);
  2025. if (curr_wm_val > srng->high_wm.val) {
  2026. srng->high_wm.val = curr_wm_val;
  2027. srng->high_wm.timestamp = qdf_get_system_timestamp();
  2028. }
  2029. if (curr_wm_val >=
  2030. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_90_to_100])
  2031. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_90_to_100]++;
  2032. else if (curr_wm_val >=
  2033. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_80_to_90])
  2034. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_80_to_90]++;
  2035. else if (curr_wm_val >=
  2036. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_70_to_80])
  2037. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_70_to_80]++;
  2038. else if (curr_wm_val >=
  2039. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_60_to_70])
  2040. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_60_to_70]++;
  2041. else if (curr_wm_val >=
  2042. srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_50_to_60])
  2043. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_50_to_60]++;
  2044. else
  2045. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT]++;
  2046. }
  2047. static inline
  2048. int hal_dump_srng_high_wm_stats(hal_soc_handle_t hal_soc_hdl,
  2049. hal_ring_handle_t hal_ring_hdl,
  2050. char *buf, int buf_len, int pos)
  2051. {
  2052. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2053. return qdf_scnprintf(buf + pos, buf_len - pos,
  2054. "%8u %7u %12llu %10u %10u %10u %10u %10u %10u",
  2055. srng->ring_id, srng->high_wm.val,
  2056. srng->high_wm.timestamp,
  2057. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT],
  2058. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_50_to_60],
  2059. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_60_to_70],
  2060. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_70_to_80],
  2061. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_80_to_90],
  2062. srng->high_wm.bins[HAL_SRNG_HIGH_WM_BIN_90_to_100]);
  2063. }
  2064. #else
  2065. /**
  2066. * hal_srng_clear_ring_usage_wm_locked() - Clear SRNG usage watermark stats
  2067. * @hal_soc_hdl: HAL soc handle
  2068. * @hal_ring_hdl: SRNG handle
  2069. *
  2070. * This function tries to acquire SRNG lock, and hence should not be called
  2071. * from a context which has already acquired the SRNG lock.
  2072. *
  2073. * Return: None
  2074. */
  2075. static inline
  2076. void hal_srng_clear_ring_usage_wm_locked(hal_soc_handle_t hal_soc_hdl,
  2077. hal_ring_handle_t hal_ring_hdl)
  2078. {
  2079. }
  2080. /**
  2081. * hal_srng_update_ring_usage_wm_no_lock() - Update the SRNG usage wm stats
  2082. * @hal_soc_hdl: HAL soc handle
  2083. * @hal_ring_hdl: SRNG handle
  2084. *
  2085. * This function should be called with the SRNG lock held.
  2086. *
  2087. * Return: None
  2088. */
  2089. static inline
  2090. void hal_srng_update_ring_usage_wm_no_lock(hal_soc_handle_t hal_soc_hdl,
  2091. hal_ring_handle_t hal_ring_hdl)
  2092. {
  2093. }
  2094. static inline
  2095. int hal_dump_srng_high_wm_stats(hal_soc_handle_t hal_soc_hdl,
  2096. hal_ring_handle_t hal_ring_hdl,
  2097. char *buf, int buf_len, int pos)
  2098. {
  2099. return 0;
  2100. }
  2101. #endif
  2102. /**
  2103. * hal_srng_access_end_unlocked() - End ring access (unlocked), update cached
  2104. * ring head/tail pointers to HW.
  2105. * @hal_soc: Opaque HAL SOC handle
  2106. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2107. *
  2108. * The target expects cached head/tail pointer to be updated to the
  2109. * shared location in the little-endian order, This API ensures that.
  2110. * This API should be used only if hal_srng_access_start_unlocked was used to
  2111. * start ring access
  2112. *
  2113. * Return: None
  2114. */
  2115. static inline void
  2116. hal_srng_access_end_unlocked(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  2117. {
  2118. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2119. /* TODO: See if we need a write memory barrier here */
  2120. if (srng->flags & HAL_SRNG_LMAC_RING) {
  2121. /* For LMAC rings, ring pointer updates are done through FW and
  2122. * hence written to a shared memory location that is read by FW
  2123. */
  2124. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  2125. *srng->u.src_ring.hp_addr =
  2126. qdf_cpu_to_le32(srng->u.src_ring.hp);
  2127. } else {
  2128. *srng->u.dst_ring.tp_addr =
  2129. qdf_cpu_to_le32(srng->u.dst_ring.tp);
  2130. }
  2131. } else {
  2132. if (srng->ring_dir == HAL_SRNG_SRC_RING)
  2133. hal_srng_write_address_32_mb(hal_soc,
  2134. srng,
  2135. srng->u.src_ring.hp_addr,
  2136. srng->u.src_ring.hp);
  2137. else
  2138. hal_srng_write_address_32_mb(hal_soc,
  2139. srng,
  2140. srng->u.dst_ring.tp_addr,
  2141. srng->u.dst_ring.tp);
  2142. }
  2143. }
  2144. /* hal_srng_access_end_unlocked already handles endianness conversion,
  2145. * use the same.
  2146. */
  2147. #define hal_le_srng_access_end_unlocked_in_cpu_order \
  2148. hal_srng_access_end_unlocked
  2149. /**
  2150. * hal_srng_access_end() - Unlock ring access and update cached ring head/tail
  2151. * pointers to HW
  2152. * @hal_soc: Opaque HAL SOC handle
  2153. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2154. *
  2155. * The target expects cached head/tail pointer to be updated to the
  2156. * shared location in the little-endian order, This API ensures that.
  2157. * This API should be used only if hal_srng_access_start was used to
  2158. * start ring access
  2159. *
  2160. */
  2161. static inline void
  2162. hal_srng_access_end(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  2163. {
  2164. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2165. if (qdf_unlikely(!hal_ring_hdl)) {
  2166. qdf_print("Error: Invalid hal_ring\n");
  2167. return;
  2168. }
  2169. hal_srng_access_end_unlocked(hal_soc, hal_ring_hdl);
  2170. SRNG_UNLOCK(&(srng->lock));
  2171. }
  2172. #ifdef FEATURE_RUNTIME_PM
  2173. #define hal_srng_access_end_v1 hal_srng_rtpm_access_end
  2174. /**
  2175. * hal_srng_rtpm_access_end() - RTPM aware, Unlock ring access
  2176. * @hal_soc_hdl: Opaque HAL SOC handle
  2177. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2178. * @rtpm_id: RTPM debug id
  2179. *
  2180. * Function updates the HP/TP value to the hardware register.
  2181. * The target expects cached head/tail pointer to be updated to the
  2182. * shared location in the little-endian order, This API ensures that.
  2183. * This API should be used only if hal_srng_access_start was used to
  2184. * start ring access
  2185. *
  2186. * Return: None
  2187. */
  2188. void
  2189. hal_srng_rtpm_access_end(hal_soc_handle_t hal_soc_hdl,
  2190. hal_ring_handle_t hal_ring_hdl,
  2191. uint32_t rtpm_id);
  2192. #else
  2193. #define hal_srng_access_end_v1(hal_soc_hdl, hal_ring_hdl, rtpm_id) \
  2194. hal_srng_access_end(hal_soc_hdl, hal_ring_hdl)
  2195. #endif
  2196. /* hal_srng_access_end already handles endianness conversion, so use the same */
  2197. #define hal_le_srng_access_end_in_cpu_order \
  2198. hal_srng_access_end
  2199. /**
  2200. * hal_srng_access_end_reap() - Unlock ring access
  2201. * @hal_soc: Opaque HAL SOC handle
  2202. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2203. *
  2204. * This should be used only if hal_srng_access_start to start ring access
  2205. * and should be used only while reaping SRC ring completions
  2206. *
  2207. * Return: 0 on success; error on failire
  2208. */
  2209. static inline void
  2210. hal_srng_access_end_reap(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  2211. {
  2212. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2213. SRNG_UNLOCK(&(srng->lock));
  2214. }
  2215. /* TODO: Check if the following definitions is available in HW headers */
  2216. #define WBM_IDLE_SCATTER_BUF_SIZE 32704
  2217. #define NUM_MPDUS_PER_LINK_DESC 6
  2218. #define NUM_MSDUS_PER_LINK_DESC 7
  2219. #define REO_QUEUE_DESC_ALIGN 128
  2220. #define LINK_DESC_ALIGN 128
  2221. #define ADDRESS_MATCH_TAG_VAL 0x5
  2222. /* Number of mpdu link pointers is 9 in case of TX_MPDU_QUEUE_HEAD and 14 in
  2223. * of TX_MPDU_QUEUE_EXT. We are defining a common average count here
  2224. */
  2225. #define NUM_MPDU_LINKS_PER_QUEUE_DESC 12
  2226. /* TODO: Check with HW team on the scatter buffer size supported. As per WBM
  2227. * MLD, scatter_buffer_size in IDLE_LIST_CONTROL register is 9 bits and size
  2228. * should be specified in 16 word units. But the number of bits defined for
  2229. * this field in HW header files is 5.
  2230. */
  2231. #define WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE 8
  2232. /**
  2233. * hal_idle_list_scatter_buf_size() - Get the size of each scatter buffer
  2234. * in an idle list
  2235. * @hal_soc_hdl: Opaque HAL SOC handle
  2236. *
  2237. * Return: scatter buffer size
  2238. */
  2239. static inline
  2240. uint32_t hal_idle_list_scatter_buf_size(hal_soc_handle_t hal_soc_hdl)
  2241. {
  2242. return WBM_IDLE_SCATTER_BUF_SIZE;
  2243. }
  2244. /**
  2245. * hal_get_link_desc_size() - Get the size of each link descriptor
  2246. * @hal_soc_hdl: Opaque HAL SOC handle
  2247. *
  2248. * Return: link descriptor size
  2249. */
  2250. static inline uint32_t hal_get_link_desc_size(hal_soc_handle_t hal_soc_hdl)
  2251. {
  2252. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2253. if (!hal_soc || !hal_soc->ops) {
  2254. qdf_print("Error: Invalid ops\n");
  2255. QDF_BUG(0);
  2256. return -EINVAL;
  2257. }
  2258. if (!hal_soc->ops->hal_get_link_desc_size) {
  2259. qdf_print("Error: Invalid function pointer\n");
  2260. QDF_BUG(0);
  2261. return -EINVAL;
  2262. }
  2263. return hal_soc->ops->hal_get_link_desc_size();
  2264. }
  2265. /**
  2266. * hal_get_link_desc_align() - Get the required start address alignment for
  2267. * link descriptors
  2268. * @hal_soc_hdl: Opaque HAL SOC handle
  2269. *
  2270. * Return: the required alignment
  2271. */
  2272. static inline
  2273. uint32_t hal_get_link_desc_align(hal_soc_handle_t hal_soc_hdl)
  2274. {
  2275. return LINK_DESC_ALIGN;
  2276. }
  2277. /**
  2278. * hal_num_mpdus_per_link_desc() - Get number of mpdus each link desc can hold
  2279. * @hal_soc_hdl: Opaque HAL SOC handle
  2280. *
  2281. * Return: number of MPDUs
  2282. */
  2283. static inline
  2284. uint32_t hal_num_mpdus_per_link_desc(hal_soc_handle_t hal_soc_hdl)
  2285. {
  2286. return NUM_MPDUS_PER_LINK_DESC;
  2287. }
  2288. /**
  2289. * hal_num_msdus_per_link_desc() - Get number of msdus each link desc can hold
  2290. * @hal_soc_hdl: Opaque HAL SOC handle
  2291. *
  2292. * Return: number of MSDUs
  2293. */
  2294. static inline
  2295. uint32_t hal_num_msdus_per_link_desc(hal_soc_handle_t hal_soc_hdl)
  2296. {
  2297. return NUM_MSDUS_PER_LINK_DESC;
  2298. }
  2299. /**
  2300. * hal_num_mpdu_links_per_queue_desc() - Get number of mpdu links each queue
  2301. * descriptor can hold
  2302. * @hal_soc_hdl: Opaque HAL SOC handle
  2303. *
  2304. * Return: number of links per queue descriptor
  2305. */
  2306. static inline
  2307. uint32_t hal_num_mpdu_links_per_queue_desc(hal_soc_handle_t hal_soc_hdl)
  2308. {
  2309. return NUM_MPDU_LINKS_PER_QUEUE_DESC;
  2310. }
  2311. /**
  2312. * hal_idle_scatter_buf_num_entries() - Get the number of link desc entries
  2313. * that the given buffer size
  2314. * @hal_soc_hdl: Opaque HAL SOC handle
  2315. * @scatter_buf_size: Size of scatter buffer
  2316. *
  2317. * Return: number of entries
  2318. */
  2319. static inline
  2320. uint32_t hal_idle_scatter_buf_num_entries(hal_soc_handle_t hal_soc_hdl,
  2321. uint32_t scatter_buf_size)
  2322. {
  2323. return (scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) /
  2324. hal_srng_get_entrysize(hal_soc_hdl, WBM_IDLE_LINK);
  2325. }
  2326. /**
  2327. * hal_idle_list_num_scatter_bufs() - Get the number of scatter buffer
  2328. * each given buffer size
  2329. * @hal_soc_hdl: Opaque HAL SOC handle
  2330. * @total_mem: size of memory to be scattered
  2331. * @scatter_buf_size: Size of scatter buffer
  2332. *
  2333. * Return: number of idle list scatter buffers
  2334. */
  2335. static inline
  2336. uint32_t hal_idle_list_num_scatter_bufs(hal_soc_handle_t hal_soc_hdl,
  2337. uint32_t total_mem,
  2338. uint32_t scatter_buf_size)
  2339. {
  2340. uint8_t rem = (total_mem % (scatter_buf_size -
  2341. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)) ? 1 : 0;
  2342. uint32_t num_scatter_bufs = (total_mem / (scatter_buf_size -
  2343. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)) + rem;
  2344. return num_scatter_bufs;
  2345. }
  2346. enum hal_pn_type {
  2347. HAL_PN_NONE,
  2348. HAL_PN_WPA,
  2349. HAL_PN_WAPI_EVEN,
  2350. HAL_PN_WAPI_UNEVEN,
  2351. };
  2352. #define HAL_RX_BA_WINDOW_256 256
  2353. #define HAL_RX_BA_WINDOW_1024 1024
  2354. /**
  2355. * hal_get_reo_qdesc_align() - Get start address alignment for reo
  2356. * queue descriptors
  2357. * @hal_soc_hdl: Opaque HAL SOC handle
  2358. *
  2359. * Return: required start address alignment
  2360. */
  2361. static inline
  2362. uint32_t hal_get_reo_qdesc_align(hal_soc_handle_t hal_soc_hdl)
  2363. {
  2364. return REO_QUEUE_DESC_ALIGN;
  2365. }
  2366. /**
  2367. * hal_srng_get_hp_addr() - Get head pointer physical address
  2368. * @hal_soc: Opaque HAL SOC handle
  2369. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2370. *
  2371. * Return: head pointer physical address
  2372. */
  2373. static inline qdf_dma_addr_t
  2374. hal_srng_get_hp_addr(void *hal_soc,
  2375. hal_ring_handle_t hal_ring_hdl)
  2376. {
  2377. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2378. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  2379. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  2380. if (srng->flags & HAL_SRNG_LMAC_RING)
  2381. return hal->shadow_wrptr_mem_paddr +
  2382. ((unsigned long)(srng->u.src_ring.hp_addr) -
  2383. (unsigned long)(hal->shadow_wrptr_mem_vaddr));
  2384. else if (ignore_shadow)
  2385. return (qdf_dma_addr_t)srng->u.src_ring.hp_addr;
  2386. else
  2387. return ((struct hif_softc *)hal->hif_handle)->mem_pa +
  2388. ((unsigned long)srng->u.src_ring.hp_addr -
  2389. (unsigned long)hal->dev_base_addr);
  2390. } else {
  2391. return hal->shadow_rdptr_mem_paddr +
  2392. ((unsigned long)(srng->u.dst_ring.hp_addr) -
  2393. (unsigned long)(hal->shadow_rdptr_mem_vaddr));
  2394. }
  2395. }
  2396. /**
  2397. * hal_srng_get_tp_addr() - Get tail pointer physical address
  2398. * @hal_soc: Opaque HAL SOC handle
  2399. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2400. *
  2401. * Return: tail pointer physical address
  2402. */
  2403. static inline qdf_dma_addr_t
  2404. hal_srng_get_tp_addr(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
  2405. {
  2406. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2407. struct hal_soc *hal = (struct hal_soc *)hal_soc;
  2408. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  2409. return hal->shadow_rdptr_mem_paddr +
  2410. ((unsigned long)(srng->u.src_ring.tp_addr) -
  2411. (unsigned long)(hal->shadow_rdptr_mem_vaddr));
  2412. } else {
  2413. if (srng->flags & HAL_SRNG_LMAC_RING)
  2414. return hal->shadow_wrptr_mem_paddr +
  2415. ((unsigned long)(srng->u.dst_ring.tp_addr) -
  2416. (unsigned long)(hal->shadow_wrptr_mem_vaddr));
  2417. else if (ignore_shadow)
  2418. return (qdf_dma_addr_t)srng->u.dst_ring.tp_addr;
  2419. else
  2420. return ((struct hif_softc *)hal->hif_handle)->mem_pa +
  2421. ((unsigned long)srng->u.dst_ring.tp_addr -
  2422. (unsigned long)hal->dev_base_addr);
  2423. }
  2424. }
  2425. /**
  2426. * hal_srng_get_num_entries() - Get total entries in the HAL Srng
  2427. * @hal_soc_hdl: Opaque HAL SOC handle
  2428. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2429. *
  2430. * Return: total number of entries in hal ring
  2431. */
  2432. static inline
  2433. uint32_t hal_srng_get_num_entries(hal_soc_handle_t hal_soc_hdl,
  2434. hal_ring_handle_t hal_ring_hdl)
  2435. {
  2436. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2437. return srng->num_entries;
  2438. }
  2439. /**
  2440. * hal_get_srng_params() - Retrieve SRNG parameters for a given ring from HAL
  2441. * @hal_soc_hdl: Opaque HAL SOC handle
  2442. * @hal_ring_hdl: Ring pointer (Source or Destination ring)
  2443. * @ring_params: SRNG parameters will be returned through this structure
  2444. */
  2445. void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl,
  2446. hal_ring_handle_t hal_ring_hdl,
  2447. struct hal_srng_params *ring_params);
  2448. /**
  2449. * hal_get_meminfo() - Retrieve hal memory base address
  2450. * @hal_soc_hdl: Opaque HAL SOC handle
  2451. * @mem: pointer to structure to be updated with hal mem info
  2452. */
  2453. void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem);
  2454. /**
  2455. * hal_get_target_type() - Return target type
  2456. * @hal_soc_hdl: Opaque HAL SOC handle
  2457. *
  2458. * Return: target type
  2459. */
  2460. uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl);
  2461. /**
  2462. * hal_srng_dst_hw_init() - Private function to initialize SRNG
  2463. * destination ring HW
  2464. * @hal: HAL SOC handle
  2465. * @srng: SRNG ring pointer
  2466. * @idle_check: Check if ring is idle
  2467. * @idx: Ring index
  2468. */
  2469. static inline void hal_srng_dst_hw_init(struct hal_soc *hal,
  2470. struct hal_srng *srng, bool idle_check,
  2471. uint16_t idx)
  2472. {
  2473. hal->ops->hal_srng_dst_hw_init(hal, srng, idle_check, idx);
  2474. }
  2475. /**
  2476. * hal_srng_src_hw_init() - Private function to initialize SRNG
  2477. * source ring HW
  2478. * @hal: HAL SOC handle
  2479. * @srng: SRNG ring pointer
  2480. * @idle_check: Check if ring is idle
  2481. * @idx: Ring index
  2482. */
  2483. static inline void hal_srng_src_hw_init(struct hal_soc *hal,
  2484. struct hal_srng *srng, bool idle_check,
  2485. uint16_t idx)
  2486. {
  2487. hal->ops->hal_srng_src_hw_init(hal, srng, idle_check, idx);
  2488. }
  2489. /**
  2490. * hal_srng_hw_disable() - Private function to disable SRNG
  2491. * source ring HW
  2492. * @hal_soc: HAL SOC handle
  2493. * @srng: SRNG ring pointer
  2494. */
  2495. static inline
  2496. void hal_srng_hw_disable(struct hal_soc *hal_soc, struct hal_srng *srng)
  2497. {
  2498. if (hal_soc->ops->hal_srng_hw_disable)
  2499. hal_soc->ops->hal_srng_hw_disable(hal_soc, srng);
  2500. }
  2501. /**
  2502. * hal_get_hw_hptp() - Get HW head and tail pointer value for any ring
  2503. * @hal_soc_hdl: Opaque HAL SOC handle
  2504. * @hal_ring_hdl: Source ring pointer
  2505. * @headp: Head Pointer
  2506. * @tailp: Tail Pointer
  2507. * @ring_type: Ring
  2508. *
  2509. * Return: Update tail pointer and head pointer in arguments.
  2510. */
  2511. static inline
  2512. void hal_get_hw_hptp(hal_soc_handle_t hal_soc_hdl,
  2513. hal_ring_handle_t hal_ring_hdl,
  2514. uint32_t *headp, uint32_t *tailp,
  2515. uint8_t ring_type)
  2516. {
  2517. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2518. hal_soc->ops->hal_get_hw_hptp(hal_soc, hal_ring_hdl,
  2519. headp, tailp, ring_type);
  2520. }
  2521. /**
  2522. * hal_reo_setup() - Initialize HW REO block
  2523. * @hal_soc_hdl: Opaque HAL SOC handle
  2524. * @reoparams: parameters needed by HAL for REO config
  2525. * @qref_reset: reset qref
  2526. */
  2527. static inline void hal_reo_setup(hal_soc_handle_t hal_soc_hdl,
  2528. void *reoparams, int qref_reset)
  2529. {
  2530. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2531. hal_soc->ops->hal_reo_setup(hal_soc, reoparams, qref_reset);
  2532. }
  2533. static inline
  2534. void hal_compute_reo_remap_ix2_ix3(hal_soc_handle_t hal_soc_hdl,
  2535. uint32_t *ring, uint32_t num_rings,
  2536. uint32_t *remap1, uint32_t *remap2)
  2537. {
  2538. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2539. return hal_soc->ops->hal_compute_reo_remap_ix2_ix3(ring,
  2540. num_rings, remap1, remap2);
  2541. }
  2542. static inline
  2543. void hal_compute_reo_remap_ix0(hal_soc_handle_t hal_soc_hdl, uint32_t *remap0)
  2544. {
  2545. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2546. if (hal_soc->ops->hal_compute_reo_remap_ix0)
  2547. hal_soc->ops->hal_compute_reo_remap_ix0(remap0);
  2548. }
  2549. /**
  2550. * hal_setup_link_idle_list() - Setup scattered idle list using the
  2551. * buffer list provided
  2552. * @hal_soc_hdl: Opaque HAL SOC handle
  2553. * @scatter_bufs_base_paddr: Array of physical base addresses
  2554. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  2555. * @num_scatter_bufs: Number of scatter buffers in the above lists
  2556. * @scatter_buf_size: Size of each scatter buffer
  2557. * @last_buf_end_offset: Offset to the last entry
  2558. * @num_entries: Total entries of all scatter bufs
  2559. *
  2560. */
  2561. static inline
  2562. void hal_setup_link_idle_list(hal_soc_handle_t hal_soc_hdl,
  2563. qdf_dma_addr_t scatter_bufs_base_paddr[],
  2564. void *scatter_bufs_base_vaddr[],
  2565. uint32_t num_scatter_bufs,
  2566. uint32_t scatter_buf_size,
  2567. uint32_t last_buf_end_offset,
  2568. uint32_t num_entries)
  2569. {
  2570. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2571. hal_soc->ops->hal_setup_link_idle_list(hal_soc, scatter_bufs_base_paddr,
  2572. scatter_bufs_base_vaddr, num_scatter_bufs,
  2573. scatter_buf_size, last_buf_end_offset,
  2574. num_entries);
  2575. }
  2576. #ifdef DUMP_REO_QUEUE_INFO_IN_DDR
  2577. /**
  2578. * hal_dump_rx_reo_queue_desc() - Dump reo queue descriptor fields
  2579. * @hw_qdesc_vaddr_aligned: Pointer to hw reo queue desc virtual addr
  2580. *
  2581. * Use the virtual addr pointer to reo h/w queue desc to read
  2582. * the values from ddr and log them.
  2583. *
  2584. * Return: none
  2585. */
  2586. static inline void hal_dump_rx_reo_queue_desc(
  2587. void *hw_qdesc_vaddr_aligned)
  2588. {
  2589. struct rx_reo_queue *hw_qdesc =
  2590. (struct rx_reo_queue *)hw_qdesc_vaddr_aligned;
  2591. if (!hw_qdesc)
  2592. return;
  2593. hal_info("receive_queue_number %u vld %u window_jump_2k %u"
  2594. " hole_count %u ba_window_size %u ignore_ampdu_flag %u"
  2595. " svld %u ssn %u current_index %u"
  2596. " disable_duplicate_detection %u soft_reorder_enable %u"
  2597. " chk_2k_mode %u oor_mode %u mpdu_frames_processed_count %u"
  2598. " msdu_frames_processed_count %u total_processed_byte_count %u"
  2599. " late_receive_mpdu_count %u seq_2k_error_detected_flag %u"
  2600. " pn_error_detected_flag %u current_mpdu_count %u"
  2601. " current_msdu_count %u timeout_count %u"
  2602. " forward_due_to_bar_count %u duplicate_count %u"
  2603. " frames_in_order_count %u bar_received_count %u"
  2604. " pn_check_needed %u pn_shall_be_even %u"
  2605. " pn_shall_be_uneven %u pn_size %u",
  2606. hw_qdesc->receive_queue_number,
  2607. hw_qdesc->vld,
  2608. hw_qdesc->window_jump_2k,
  2609. hw_qdesc->hole_count,
  2610. hw_qdesc->ba_window_size,
  2611. hw_qdesc->ignore_ampdu_flag,
  2612. hw_qdesc->svld,
  2613. hw_qdesc->ssn,
  2614. hw_qdesc->current_index,
  2615. hw_qdesc->disable_duplicate_detection,
  2616. hw_qdesc->soft_reorder_enable,
  2617. hw_qdesc->chk_2k_mode,
  2618. hw_qdesc->oor_mode,
  2619. hw_qdesc->mpdu_frames_processed_count,
  2620. hw_qdesc->msdu_frames_processed_count,
  2621. hw_qdesc->total_processed_byte_count,
  2622. hw_qdesc->late_receive_mpdu_count,
  2623. hw_qdesc->seq_2k_error_detected_flag,
  2624. hw_qdesc->pn_error_detected_flag,
  2625. hw_qdesc->current_mpdu_count,
  2626. hw_qdesc->current_msdu_count,
  2627. hw_qdesc->timeout_count,
  2628. hw_qdesc->forward_due_to_bar_count,
  2629. hw_qdesc->duplicate_count,
  2630. hw_qdesc->frames_in_order_count,
  2631. hw_qdesc->bar_received_count,
  2632. hw_qdesc->pn_check_needed,
  2633. hw_qdesc->pn_shall_be_even,
  2634. hw_qdesc->pn_shall_be_uneven,
  2635. hw_qdesc->pn_size);
  2636. }
  2637. #else /* DUMP_REO_QUEUE_INFO_IN_DDR */
  2638. static inline void hal_dump_rx_reo_queue_desc(
  2639. void *hw_qdesc_vaddr_aligned)
  2640. {
  2641. }
  2642. #endif /* DUMP_REO_QUEUE_INFO_IN_DDR */
  2643. /**
  2644. * hal_srng_dump_ring_desc() - Dump ring descriptor info
  2645. * @hal_soc_hdl: Opaque HAL SOC handle
  2646. * @hal_ring_hdl: Source ring pointer
  2647. * @ring_desc: Opaque ring descriptor handle
  2648. */
  2649. static inline void hal_srng_dump_ring_desc(hal_soc_handle_t hal_soc_hdl,
  2650. hal_ring_handle_t hal_ring_hdl,
  2651. hal_ring_desc_t ring_desc)
  2652. {
  2653. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2654. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2655. ring_desc, (srng->entry_size << 2));
  2656. }
  2657. /**
  2658. * hal_srng_dump_ring() - Dump last 128 descs of the ring
  2659. * @hal_soc_hdl: Opaque HAL SOC handle
  2660. * @hal_ring_hdl: Source ring pointer
  2661. */
  2662. static inline void hal_srng_dump_ring(hal_soc_handle_t hal_soc_hdl,
  2663. hal_ring_handle_t hal_ring_hdl)
  2664. {
  2665. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2666. uint32_t *desc;
  2667. uint32_t tp, i;
  2668. tp = srng->u.dst_ring.tp;
  2669. for (i = 0; i < 128; i++) {
  2670. if (!tp)
  2671. tp = srng->ring_size;
  2672. desc = &srng->ring_base_vaddr[tp - srng->entry_size];
  2673. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP,
  2674. QDF_TRACE_LEVEL_DEBUG,
  2675. desc, (srng->entry_size << 2));
  2676. tp -= srng->entry_size;
  2677. }
  2678. }
  2679. /**
  2680. * hal_rxdma_desc_to_hal_ring_desc() - API to convert rxdma ring desc
  2681. * to opaque dp_ring desc type
  2682. * @ring_desc: rxdma ring desc
  2683. *
  2684. * Return: hal_rxdma_desc_t type
  2685. */
  2686. static inline
  2687. hal_ring_desc_t hal_rxdma_desc_to_hal_ring_desc(hal_rxdma_desc_t ring_desc)
  2688. {
  2689. return (hal_ring_desc_t)ring_desc;
  2690. }
  2691. /**
  2692. * hal_srng_set_event() - Set hal_srng event
  2693. * @hal_ring_hdl: Source ring pointer
  2694. * @event: SRNG ring event
  2695. *
  2696. * Return: None
  2697. */
  2698. static inline void hal_srng_set_event(hal_ring_handle_t hal_ring_hdl, int event)
  2699. {
  2700. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2701. qdf_atomic_set_bit(event, &srng->srng_event);
  2702. }
  2703. /**
  2704. * hal_srng_clear_event() - Clear hal_srng event
  2705. * @hal_ring_hdl: Source ring pointer
  2706. * @event: SRNG ring event
  2707. *
  2708. * Return: None
  2709. */
  2710. static inline
  2711. void hal_srng_clear_event(hal_ring_handle_t hal_ring_hdl, int event)
  2712. {
  2713. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2714. qdf_atomic_clear_bit(event, &srng->srng_event);
  2715. }
  2716. /**
  2717. * hal_srng_get_clear_event() - Clear srng event and return old value
  2718. * @hal_ring_hdl: Source ring pointer
  2719. * @event: SRNG ring event
  2720. *
  2721. * Return: Return old event value
  2722. */
  2723. static inline
  2724. int hal_srng_get_clear_event(hal_ring_handle_t hal_ring_hdl, int event)
  2725. {
  2726. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2727. return qdf_atomic_test_and_clear_bit(event, &srng->srng_event);
  2728. }
  2729. /**
  2730. * hal_srng_set_flush_last_ts() - Record last flush time stamp
  2731. * @hal_ring_hdl: Source ring pointer
  2732. *
  2733. * Return: None
  2734. */
  2735. static inline void hal_srng_set_flush_last_ts(hal_ring_handle_t hal_ring_hdl)
  2736. {
  2737. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2738. srng->last_flush_ts = qdf_get_log_timestamp();
  2739. }
  2740. /**
  2741. * hal_srng_inc_flush_cnt() - Increment flush counter
  2742. * @hal_ring_hdl: Source ring pointer
  2743. *
  2744. * Return: None
  2745. */
  2746. static inline void hal_srng_inc_flush_cnt(hal_ring_handle_t hal_ring_hdl)
  2747. {
  2748. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2749. srng->flush_count++;
  2750. }
  2751. /**
  2752. * hal_rx_sw_mon_desc_info_get() - Get SW monitor desc info
  2753. * @hal: Core HAL soc handle
  2754. * @ring_desc: Mon dest ring descriptor
  2755. * @desc_info: Desc info to be populated
  2756. *
  2757. * Return void
  2758. */
  2759. static inline void
  2760. hal_rx_sw_mon_desc_info_get(struct hal_soc *hal,
  2761. hal_ring_desc_t ring_desc,
  2762. hal_rx_mon_desc_info_t desc_info)
  2763. {
  2764. return hal->ops->hal_rx_sw_mon_desc_info_get(ring_desc, desc_info);
  2765. }
  2766. /**
  2767. * hal_reo_set_err_dst_remap() - Set REO error destination ring remap
  2768. * register value.
  2769. *
  2770. * @hal_soc_hdl: Opaque HAL soc handle
  2771. *
  2772. * Return: None
  2773. */
  2774. static inline void hal_reo_set_err_dst_remap(hal_soc_handle_t hal_soc_hdl)
  2775. {
  2776. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2777. if (hal_soc->ops->hal_reo_set_err_dst_remap)
  2778. hal_soc->ops->hal_reo_set_err_dst_remap(hal_soc);
  2779. }
  2780. /**
  2781. * hal_reo_enable_pn_in_dest() - Subscribe for previous PN for 2k-jump or
  2782. * OOR error frames
  2783. * @hal_soc_hdl: Opaque HAL soc handle
  2784. *
  2785. * Return: true if feature is enabled,
  2786. * false, otherwise.
  2787. */
  2788. static inline uint8_t
  2789. hal_reo_enable_pn_in_dest(hal_soc_handle_t hal_soc_hdl)
  2790. {
  2791. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2792. if (hal_soc->ops->hal_reo_enable_pn_in_dest)
  2793. return hal_soc->ops->hal_reo_enable_pn_in_dest(hal_soc);
  2794. return 0;
  2795. }
  2796. #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
  2797. /**
  2798. * hal_set_one_target_reg_config() - Populate the target reg
  2799. * offset in hal_soc for one non srng related register at the
  2800. * given list index
  2801. * @hal: hal handle
  2802. * @target_reg_offset: target register offset
  2803. * @list_index: index in hal list for shadow regs
  2804. *
  2805. * Return: none
  2806. */
  2807. void hal_set_one_target_reg_config(struct hal_soc *hal,
  2808. uint32_t target_reg_offset,
  2809. int list_index);
  2810. /**
  2811. * hal_set_shadow_regs() - Populate register offset for
  2812. * registers that need to be populated in list_shadow_reg_config
  2813. * in order to be sent to FW. These reg offsets will be mapped
  2814. * to shadow registers.
  2815. * @hal_soc: hal handle
  2816. *
  2817. * Return: QDF_STATUS_OK on success
  2818. */
  2819. QDF_STATUS hal_set_shadow_regs(void *hal_soc);
  2820. /**
  2821. * hal_construct_shadow_regs() - initialize the shadow registers
  2822. * for non-srng related register configs
  2823. * @hal_soc: hal handle
  2824. *
  2825. * Return: QDF_STATUS_OK on success
  2826. */
  2827. QDF_STATUS hal_construct_shadow_regs(void *hal_soc);
  2828. #else /* GENERIC_SHADOW_REGISTER_ACCESS_ENABLE */
  2829. static inline void hal_set_one_target_reg_config(
  2830. struct hal_soc *hal,
  2831. uint32_t target_reg_offset,
  2832. int list_index)
  2833. {
  2834. }
  2835. static inline QDF_STATUS hal_set_shadow_regs(void *hal_soc)
  2836. {
  2837. return QDF_STATUS_SUCCESS;
  2838. }
  2839. static inline QDF_STATUS hal_construct_shadow_regs(void *hal_soc)
  2840. {
  2841. return QDF_STATUS_SUCCESS;
  2842. }
  2843. #endif /* GENERIC_SHADOW_REGISTER_ACCESS_ENABLE */
  2844. #ifdef FEATURE_HAL_DELAYED_REG_WRITE
  2845. /**
  2846. * hal_flush_reg_write_work() - flush all writes from register write queue
  2847. * @hal_handle: hal_soc pointer
  2848. *
  2849. * Return: None
  2850. */
  2851. void hal_flush_reg_write_work(hal_soc_handle_t hal_handle);
  2852. #else
  2853. static inline void hal_flush_reg_write_work(hal_soc_handle_t hal_handle) { }
  2854. #endif
  2855. /**
  2856. * hal_get_ring_usage() - Calculate the ring usage percentage
  2857. * @hal_ring_hdl: Ring pointer
  2858. * @ring_type: Ring type
  2859. * @headp: pointer to head value
  2860. * @tailp: pointer to tail value
  2861. *
  2862. * Calculate the ring usage percentage for src and dest rings
  2863. *
  2864. * Return: Ring usage percentage
  2865. */
  2866. static inline
  2867. uint32_t hal_get_ring_usage(
  2868. hal_ring_handle_t hal_ring_hdl,
  2869. enum hal_ring_type ring_type, uint32_t *headp, uint32_t *tailp)
  2870. {
  2871. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2872. uint32_t num_avail, num_valid = 0;
  2873. uint32_t ring_usage;
  2874. if (srng->ring_dir == HAL_SRNG_SRC_RING) {
  2875. if (*tailp > *headp)
  2876. num_avail = ((*tailp - *headp) / srng->entry_size) - 1;
  2877. else
  2878. num_avail = ((srng->ring_size - *headp + *tailp) /
  2879. srng->entry_size) - 1;
  2880. if (ring_type == WBM_IDLE_LINK)
  2881. num_valid = num_avail;
  2882. else
  2883. num_valid = srng->num_entries - num_avail;
  2884. } else {
  2885. if (*headp >= *tailp)
  2886. num_valid = ((*headp - *tailp) / srng->entry_size);
  2887. else
  2888. num_valid = ((srng->ring_size - *tailp + *headp) /
  2889. srng->entry_size);
  2890. }
  2891. ring_usage = (100 * num_valid) / srng->num_entries;
  2892. return ring_usage;
  2893. }
  2894. /**
  2895. * hal_cmem_write() - function for CMEM buffer writing
  2896. * @hal_soc_hdl: HAL SOC handle
  2897. * @offset: CMEM address
  2898. * @value: value to write
  2899. *
  2900. * Return: None.
  2901. */
  2902. static inline void
  2903. hal_cmem_write(hal_soc_handle_t hal_soc_hdl, uint32_t offset,
  2904. uint32_t value)
  2905. {
  2906. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2907. if (hal_soc->ops->hal_cmem_write)
  2908. hal_soc->ops->hal_cmem_write(hal_soc_hdl, offset, value);
  2909. return;
  2910. }
  2911. static inline bool
  2912. hal_dmac_cmn_src_rxbuf_ring_get(hal_soc_handle_t hal_soc_hdl)
  2913. {
  2914. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2915. return hal_soc->dmac_cmn_src_rxbuf_ring;
  2916. }
  2917. /**
  2918. * hal_srng_dst_prefetch() - function to prefetch 4 destination ring descs
  2919. * @hal_soc_hdl: HAL SOC handle
  2920. * @hal_ring_hdl: Destination ring pointer
  2921. * @num_valid: valid entries in the ring
  2922. *
  2923. * Return: last prefetched destination ring descriptor
  2924. */
  2925. static inline
  2926. void *hal_srng_dst_prefetch(hal_soc_handle_t hal_soc_hdl,
  2927. hal_ring_handle_t hal_ring_hdl,
  2928. uint16_t num_valid)
  2929. {
  2930. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2931. uint8_t *desc;
  2932. uint32_t cnt;
  2933. /*
  2934. * prefetching 4 HW descriptors will ensure atleast by the time
  2935. * 5th HW descriptor is being processed it is guaranteed that the
  2936. * 5th HW descriptor, its SW Desc, its nbuf and its nbuf's data
  2937. * are in cache line. basically ensuring all the 4 (HW, SW, nbuf
  2938. * & nbuf->data) are prefetched.
  2939. */
  2940. uint32_t max_prefetch = 4;
  2941. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  2942. return NULL;
  2943. desc = (uint8_t *)&srng->ring_base_vaddr[srng->u.dst_ring.tp];
  2944. if (num_valid < max_prefetch)
  2945. max_prefetch = num_valid;
  2946. for (cnt = 0; cnt < max_prefetch; cnt++) {
  2947. desc += srng->entry_size * sizeof(uint32_t);
  2948. if (desc == ((uint8_t *)srng->ring_vaddr_end))
  2949. desc = (uint8_t *)&srng->ring_base_vaddr[0];
  2950. qdf_prefetch(desc);
  2951. }
  2952. return (void *)desc;
  2953. }
  2954. /**
  2955. * hal_srng_dst_prefetch_next_cached_desc() - function to prefetch next desc
  2956. * @hal_soc_hdl: HAL SOC handle
  2957. * @hal_ring_hdl: Destination ring pointer
  2958. * @last_prefetched_hw_desc: last prefetched HW descriptor
  2959. *
  2960. * Return: next prefetched destination descriptor
  2961. */
  2962. static inline
  2963. void *hal_srng_dst_prefetch_next_cached_desc(hal_soc_handle_t hal_soc_hdl,
  2964. hal_ring_handle_t hal_ring_hdl,
  2965. uint8_t *last_prefetched_hw_desc)
  2966. {
  2967. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2968. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  2969. return NULL;
  2970. last_prefetched_hw_desc += srng->entry_size * sizeof(uint32_t);
  2971. if (last_prefetched_hw_desc == ((uint8_t *)srng->ring_vaddr_end))
  2972. last_prefetched_hw_desc = (uint8_t *)&srng->ring_base_vaddr[0];
  2973. qdf_prefetch(last_prefetched_hw_desc);
  2974. return (void *)last_prefetched_hw_desc;
  2975. }
  2976. /**
  2977. * hal_srng_dst_prefetch_32_byte_desc() - function to prefetch a desc at
  2978. * 64 byte offset
  2979. * @hal_soc_hdl: HAL SOC handle
  2980. * @hal_ring_hdl: Destination ring pointer
  2981. * @num_valid: valid entries in the ring
  2982. *
  2983. * Return: last prefetched destination ring descriptor
  2984. */
  2985. static inline
  2986. void *hal_srng_dst_prefetch_32_byte_desc(hal_soc_handle_t hal_soc_hdl,
  2987. hal_ring_handle_t hal_ring_hdl,
  2988. uint16_t num_valid)
  2989. {
  2990. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  2991. uint8_t *desc;
  2992. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  2993. return NULL;
  2994. desc = (uint8_t *)&srng->ring_base_vaddr[srng->u.dst_ring.tp];
  2995. if ((uintptr_t)desc & 0x3f)
  2996. desc += srng->entry_size * sizeof(uint32_t);
  2997. else
  2998. desc += (srng->entry_size * sizeof(uint32_t)) * 2;
  2999. if (desc == ((uint8_t *)srng->ring_vaddr_end))
  3000. desc = (uint8_t *)&srng->ring_base_vaddr[0];
  3001. qdf_prefetch(desc);
  3002. return (void *)(desc + srng->entry_size * sizeof(uint32_t));
  3003. }
  3004. /**
  3005. * hal_srng_dst_get_next_32_byte_desc() - function to prefetch next desc
  3006. * @hal_soc_hdl: HAL SOC handle
  3007. * @hal_ring_hdl: Destination ring pointer
  3008. * @last_prefetched_hw_desc: last prefetched HW descriptor
  3009. *
  3010. * Return: next prefetched destination descriptor
  3011. */
  3012. static inline
  3013. void *hal_srng_dst_get_next_32_byte_desc(hal_soc_handle_t hal_soc_hdl,
  3014. hal_ring_handle_t hal_ring_hdl,
  3015. uint8_t *last_prefetched_hw_desc)
  3016. {
  3017. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  3018. if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp)
  3019. return NULL;
  3020. last_prefetched_hw_desc += srng->entry_size * sizeof(uint32_t);
  3021. if (last_prefetched_hw_desc == ((uint8_t *)srng->ring_vaddr_end))
  3022. last_prefetched_hw_desc = (uint8_t *)&srng->ring_base_vaddr[0];
  3023. return (void *)last_prefetched_hw_desc;
  3024. }
  3025. /**
  3026. * hal_srng_src_set_hp() - set head idx.
  3027. * @hal_ring_hdl: srng handle
  3028. * @idx: head idx
  3029. *
  3030. * Return: none
  3031. */
  3032. static inline
  3033. void hal_srng_src_set_hp(hal_ring_handle_t hal_ring_hdl, uint16_t idx)
  3034. {
  3035. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  3036. srng->u.src_ring.hp = idx * srng->entry_size;
  3037. }
  3038. /**
  3039. * hal_srng_dst_set_tp() - set tail idx.
  3040. * @hal_ring_hdl: srng handle
  3041. * @idx: tail idx
  3042. *
  3043. * Return: none
  3044. */
  3045. static inline
  3046. void hal_srng_dst_set_tp(hal_ring_handle_t hal_ring_hdl, uint16_t idx)
  3047. {
  3048. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  3049. srng->u.dst_ring.tp = idx * srng->entry_size;
  3050. }
  3051. /**
  3052. * hal_srng_src_get_tpidx() - get tail idx
  3053. * @hal_ring_hdl: srng handle
  3054. *
  3055. * Return: tail idx
  3056. */
  3057. static inline
  3058. uint16_t hal_srng_src_get_tpidx(hal_ring_handle_t hal_ring_hdl)
  3059. {
  3060. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  3061. uint32_t tp = *(volatile uint32_t *)(srng->u.src_ring.tp_addr);
  3062. return tp / srng->entry_size;
  3063. }
  3064. /**
  3065. * hal_srng_dst_get_hpidx() - get head idx
  3066. * @hal_ring_hdl: srng handle
  3067. *
  3068. * Return: head idx
  3069. */
  3070. static inline
  3071. uint16_t hal_srng_dst_get_hpidx(hal_ring_handle_t hal_ring_hdl)
  3072. {
  3073. struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
  3074. uint32_t hp = *(volatile uint32_t *)(srng->u.dst_ring.hp_addr);
  3075. return hp / srng->entry_size;
  3076. }
  3077. #ifdef FEATURE_DIRECT_LINK
  3078. /**
  3079. * hal_srng_set_msi_irq_config() - Set the MSI irq configuration for srng
  3080. * @hal_soc_hdl: hal soc handle
  3081. * @hal_ring_hdl: srng handle
  3082. * @ring_params: ring parameters
  3083. *
  3084. * Return: QDF status
  3085. */
  3086. static inline QDF_STATUS
  3087. hal_srng_set_msi_irq_config(hal_soc_handle_t hal_soc_hdl,
  3088. hal_ring_handle_t hal_ring_hdl,
  3089. struct hal_srng_params *ring_params)
  3090. {
  3091. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  3092. return hal_soc->ops->hal_srng_set_msi_config(hal_ring_hdl, ring_params);
  3093. }
  3094. #else
  3095. static inline QDF_STATUS
  3096. hal_srng_set_msi_irq_config(hal_soc_handle_t hal_soc_hdl,
  3097. hal_ring_handle_t hal_ring_hdl,
  3098. struct hal_srng_params *ring_params)
  3099. {
  3100. return QDF_STATUS_E_NOSUPPORT;
  3101. }
  3102. #endif
  3103. #endif /* _HAL_APIH_ */