hal_be_api_mon.h 118 KB

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  1. /*
  2. * Copyright (c) 2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifndef _HAL_BE_API_MON_H_
  18. #define _HAL_BE_API_MON_H_
  19. #include "hal_be_hw_headers.h"
  20. #ifdef QCA_MONITOR_2_0_SUPPORT
  21. #include <mon_ingress_ring.h>
  22. #include <mon_destination_ring.h>
  23. #include <mon_drop.h>
  24. #endif
  25. #include <hal_be_hw_headers.h>
  26. #include "hal_api_mon.h"
  27. #include <hal_generic_api.h>
  28. #include <hal_generic_api.h>
  29. #include <hal_api_mon.h>
  30. #if defined(QCA_MONITOR_2_0_SUPPORT) || \
  31. defined(QCA_SINGLE_WIFI_3_0)
  32. #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000
  33. #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0
  34. #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff
  35. #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004
  36. #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0
  37. #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff
  38. #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008
  39. #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0
  40. #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31
  41. #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
  42. #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c
  43. #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0
  44. #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31
  45. #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
  46. #define HAL_MON_PADDR_LO_SET(buff_addr_info, paddr_lo) \
  47. ((*(((unsigned int *) buff_addr_info) + \
  48. (HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \
  49. ((paddr_lo) << HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \
  50. HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK)
  51. #define HAL_MON_PADDR_HI_SET(buff_addr_info, paddr_hi) \
  52. ((*(((unsigned int *) buff_addr_info) + \
  53. (HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \
  54. ((paddr_hi) << HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \
  55. HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK)
  56. #define HAL_MON_VADDR_LO_SET(buff_addr_info, vaddr_lo) \
  57. ((*(((unsigned int *) buff_addr_info) + \
  58. (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET >> 2))) = \
  59. ((vaddr_lo) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB) & \
  60. HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK)
  61. #define HAL_MON_VADDR_HI_SET(buff_addr_info, vaddr_hi) \
  62. ((*(((unsigned int *) buff_addr_info) + \
  63. (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET >> 2))) = \
  64. ((vaddr_hi) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB) & \
  65. HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK)
  66. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
  67. RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET
  68. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
  69. RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK
  70. #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
  71. RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB
  72. #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
  73. PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET
  74. #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
  75. PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
  76. #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
  77. PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET
  78. #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
  79. PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET
  80. #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
  81. PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET
  82. #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
  83. PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET
  84. #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
  85. PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET
  86. #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
  87. PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET
  88. #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
  89. PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET
  90. #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
  91. PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
  92. #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
  93. PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
  94. #endif
  95. #define RX_MON_MPDU_START_WMASK 0x07F0
  96. #define RX_MON_MSDU_END_WMASK 0x0AE1
  97. #define RX_MON_PPDU_END_USR_STATS_WMASK 0xB7E
  98. #ifdef CONFIG_MON_WORD_BASED_TLV
  99. #ifndef BIG_ENDIAN_HOST
  100. struct rx_mpdu_start_mon_data {
  101. uint32_t peer_meta_data : 32;
  102. uint32_t rxpcu_mpdu_filter_in_category : 2,
  103. sw_frame_group_id : 7,
  104. ndp_frame : 1,
  105. phy_err : 1,
  106. phy_err_during_mpdu_header : 1,
  107. protocol_version_err : 1,
  108. ast_based_lookup_valid : 1,
  109. reserved_0a : 2,
  110. phy_ppdu_id : 16;
  111. uint32_t ast_index : 16,
  112. sw_peer_id : 16;
  113. uint32_t mpdu_frame_control_valid : 1,
  114. mpdu_duration_valid : 1,
  115. mac_addr_ad1_valid : 1,
  116. mac_addr_ad2_valid : 1,
  117. mac_addr_ad3_valid : 1,
  118. mac_addr_ad4_valid : 1,
  119. mpdu_sequence_control_valid : 1,
  120. mpdu_qos_control_valid : 1,
  121. mpdu_ht_control_valid : 1,
  122. frame_encryption_info_valid : 1,
  123. mpdu_fragment_number : 4,
  124. more_fragment_flag : 1,
  125. reserved_11a : 1,
  126. fr_ds : 1,
  127. to_ds : 1,
  128. encrypted : 1,
  129. mpdu_retry : 1,
  130. mpdu_sequence_number : 12;
  131. uint32_t key_id_octet : 8,
  132. new_peer_entry : 1,
  133. decrypt_needed : 1,
  134. decap_type : 2,
  135. rx_insert_vlan_c_tag_padding : 1,
  136. rx_insert_vlan_s_tag_padding : 1,
  137. strip_vlan_c_tag_decap : 1,
  138. strip_vlan_s_tag_decap : 1,
  139. pre_delim_count : 12,
  140. ampdu_flag : 1,
  141. bar_frame : 1,
  142. raw_mpdu : 1,
  143. reserved_12 : 1;
  144. uint32_t mpdu_length : 14,
  145. first_mpdu : 1,
  146. mcast_bcast : 1,
  147. ast_index_not_found : 1,
  148. ast_index_timeout : 1,
  149. power_mgmt : 1,
  150. non_qos : 1,
  151. null_data : 1,
  152. mgmt_type : 1,
  153. ctrl_type : 1,
  154. more_data : 1,
  155. eosp : 1,
  156. fragment_flag : 1,
  157. order : 1,
  158. u_apsd_trigger : 1,
  159. encrypt_required : 1,
  160. directed : 1,
  161. amsdu_present : 1,
  162. reserved_13 : 1;
  163. uint32_t mpdu_frame_control_field : 16,
  164. mpdu_duration_field : 16;
  165. uint32_t mac_addr_ad1_31_0 : 32;
  166. uint32_t mac_addr_ad1_47_32 : 16,
  167. mac_addr_ad2_15_0 : 16;
  168. uint32_t mac_addr_ad2_47_16 : 32;
  169. uint32_t mac_addr_ad3_31_0 : 32;
  170. uint32_t mac_addr_ad3_47_32 : 16,
  171. mpdu_sequence_control_field : 16;
  172. uint32_t mac_addr_ad4_31_0 : 32;
  173. uint32_t mac_addr_ad4_47_32 : 16,
  174. mpdu_qos_control_field : 16;
  175. };
  176. struct rx_msdu_end_mon_data {
  177. uint32_t rxpcu_mpdu_filter_in_category : 2,
  178. sw_frame_group_id : 7,
  179. reserved_0 : 7,
  180. phy_ppdu_id : 16;
  181. uint32_t ip_hdr_chksum : 16,
  182. reported_mpdu_length : 14,
  183. reserved_1a : 2;
  184. uint32_t sa_sw_peer_id : 16,
  185. sa_idx_timeout : 1,
  186. da_idx_timeout : 1,
  187. to_ds : 1,
  188. tid : 4,
  189. sa_is_valid : 1,
  190. da_is_valid : 1,
  191. da_is_mcbc : 1,
  192. l3_header_padding : 2,
  193. first_msdu : 1,
  194. last_msdu : 1,
  195. fr_ds : 1,
  196. ip_chksum_fail_copy : 1;
  197. uint32_t sa_idx : 16,
  198. da_idx_or_sw_peer_id : 16;
  199. uint32_t msdu_drop : 1,
  200. reo_destination_indication : 5,
  201. flow_idx : 20,
  202. use_ppe : 1,
  203. mesh_sta : 2,
  204. vlan_ctag_stripped : 1,
  205. vlan_stag_stripped : 1,
  206. fragment_flag : 1;
  207. uint32_t fse_metadata : 32;
  208. uint32_t cce_metadata : 16,
  209. tcp_udp_chksum : 16;
  210. uint32_t aggregation_count : 8,
  211. flow_aggregation_continuation : 1,
  212. fisa_timeout : 1,
  213. tcp_udp_chksum_fail_copy : 1,
  214. msdu_limit_error : 1,
  215. flow_idx_timeout : 1,
  216. flow_idx_invalid : 1,
  217. cce_match : 1,
  218. amsdu_parser_error : 1,
  219. cumulative_ip_length : 16;
  220. uint32_t msdu_length : 14,
  221. stbc : 1,
  222. ipsec_esp : 1,
  223. l3_offset : 7,
  224. ipsec_ah : 1,
  225. l4_offset : 8;
  226. uint32_t msdu_number : 8,
  227. decap_format : 2,
  228. ipv4_proto : 1,
  229. ipv6_proto : 1,
  230. tcp_proto : 1,
  231. udp_proto : 1,
  232. ip_frag : 1,
  233. tcp_only_ack : 1,
  234. da_is_bcast_mcast : 1,
  235. toeplitz_hash_sel : 2,
  236. ip_fixed_header_valid : 1,
  237. ip_extn_header_valid : 1,
  238. tcp_udp_header_valid : 1,
  239. mesh_control_present : 1,
  240. ldpc : 1,
  241. ip4_protocol_ip6_next_header : 8;
  242. uint32_t user_rssi : 8,
  243. pkt_type : 4,
  244. sgi : 2,
  245. rate_mcs : 4,
  246. receive_bandwidth : 3,
  247. reception_type : 3,
  248. mimo_ss_bitmap : 7,
  249. msdu_done_copy : 1;
  250. uint32_t flow_id_toeplitz : 32;
  251. };
  252. struct rx_ppdu_end_user_mon_data {
  253. uint32_t sw_peer_id : 16,
  254. mpdu_cnt_fcs_err : 11,
  255. sw2rxdma0_buf_source_used : 1,
  256. fw2rxdma_pmac0_buf_source_used : 1,
  257. sw2rxdma1_buf_source_used : 1,
  258. sw2rxdma_exception_buf_source_used: 1,
  259. fw2rxdma_pmac1_buf_source_used : 1;
  260. uint32_t mpdu_cnt_fcs_ok : 11,
  261. frame_control_info_valid : 1,
  262. qos_control_info_valid : 1,
  263. ht_control_info_valid : 1,
  264. data_sequence_control_info_valid : 1,
  265. ht_control_info_null_valid : 1,
  266. rxdma2fw_pmac1_ring_used : 1,
  267. rxdma2reo_ring_used : 1,
  268. rxdma2fw_pmac0_ring_used : 1,
  269. rxdma2sw_ring_used : 1,
  270. rxdma_release_ring_used : 1,
  271. ht_control_field_pkt_type : 4,
  272. rxdma2reo_remote0_ring_used : 1,
  273. rxdma2reo_remote1_ring_used : 1,
  274. reserved_3b : 5;
  275. uint32_t ast_index : 16,
  276. frame_control_field : 16;
  277. uint32_t first_data_seq_ctrl : 16,
  278. qos_control_field : 16;
  279. uint32_t ht_control_field : 32;
  280. uint32_t fcs_ok_bitmap_31_0 : 32;
  281. uint32_t fcs_ok_bitmap_63_32 : 32;
  282. uint32_t udp_msdu_count : 16,
  283. tcp_msdu_count : 16;
  284. uint32_t other_msdu_count : 16,
  285. tcp_ack_msdu_count : 16;
  286. uint32_t sw_response_reference_ptr : 32;
  287. uint32_t received_qos_data_tid_bitmap : 16,
  288. received_qos_data_tid_eosp_bitmap : 16;
  289. uint32_t qosctrl_15_8_tid0 : 8,
  290. qosctrl_15_8_tid1 : 8,
  291. qosctrl_15_8_tid2 : 8,
  292. qosctrl_15_8_tid3 : 8;
  293. uint32_t qosctrl_15_8_tid12 : 8,
  294. qosctrl_15_8_tid13 : 8,
  295. qosctrl_15_8_tid14 : 8,
  296. qosctrl_15_8_tid15 : 8;
  297. uint32_t mpdu_ok_byte_count : 25,
  298. ampdu_delim_ok_count_6_0 : 7;
  299. uint32_t ampdu_delim_err_count : 25,
  300. ampdu_delim_ok_count_13_7 : 7;
  301. uint32_t mpdu_err_byte_count : 25,
  302. ampdu_delim_ok_count_20_14 : 7;
  303. uint32_t sw_response_reference_ptr_ext : 32;
  304. uint32_t corrupted_due_to_fifo_delay : 1,
  305. frame_control_info_null_valid : 1,
  306. frame_control_field_null : 16,
  307. retried_mpdu_count : 11,
  308. reserved_23a : 3;
  309. };
  310. #else
  311. struct rx_mpdu_start_mon_data {
  312. uint32_t peer_meta_data : 32;
  313. uint32_t phy_ppdu_id : 16,
  314. reserved_0a : 2,
  315. ast_based_lookup_valid : 1,
  316. protocol_version_err : 1,
  317. phy_err_during_mpdu_header : 1,
  318. phy_err : 1,
  319. ndp_frame : 1,
  320. sw_frame_group_id : 7,
  321. rxpcu_mpdu_filter_in_category : 2;
  322. uint32_t sw_peer_id : 16,
  323. ast_index : 16;
  324. uint32_t mpdu_sequence_number : 12,
  325. mpdu_retry : 1,
  326. encrypted : 1,
  327. to_ds : 1,
  328. fr_ds : 1,
  329. reserved_11a : 1,
  330. more_fragment_flag : 1,
  331. mpdu_fragment_number : 4,
  332. frame_encryption_info_valid : 1,
  333. mpdu_ht_control_valid : 1,
  334. mpdu_qos_control_valid : 1,
  335. mpdu_sequence_control_valid : 1,
  336. mac_addr_ad4_valid : 1,
  337. mac_addr_ad3_valid : 1,
  338. mac_addr_ad2_valid : 1,
  339. mac_addr_ad1_valid : 1,
  340. mpdu_duration_valid : 1,
  341. mpdu_frame_control_valid : 1;
  342. uint32_t reserved_12 : 1,
  343. raw_mpdu : 1,
  344. bar_frame : 1,
  345. ampdu_flag : 1,
  346. pre_delim_count : 12,
  347. strip_vlan_s_tag_decap : 1,
  348. strip_vlan_c_tag_decap : 1,
  349. rx_insert_vlan_s_tag_padding : 1,
  350. rx_insert_vlan_c_tag_padding : 1,
  351. decap_type : 2,
  352. decrypt_needed : 1,
  353. new_peer_entry : 1,
  354. key_id_octet : 8;
  355. uint32_t reserved_13 : 1;
  356. amsdu_present : 1,
  357. directed : 1,
  358. encrypt_required : 1,
  359. u_apsd_trigger : 1,
  360. order : 1,
  361. fragment_flag : 1,
  362. eosp : 1,
  363. more_data : 1,
  364. ctrl_type : 1,
  365. mgmt_type : 1,
  366. null_data : 1,
  367. non_qos : 1,
  368. power_mgmt : 1,
  369. ast_index_timeout : 1,
  370. ast_index_not_found : 1,
  371. mcast_bcast : 1,
  372. first_mpdu : 1,
  373. mpdu_length : 14,
  374. uint32_t mpdu_duration_field : 16,
  375. mpdu_frame_control_field : 16;
  376. uint32_t mac_addr_ad1_31_0 : 32;
  377. uint32_t mac_addr_ad2_15_0 : 16,
  378. mac_addr_ad1_47_32 : 16;
  379. uint32_t mac_addr_ad2_47_16 : 32;
  380. uint32_t mac_addr_ad3_31_0 : 32;
  381. uint32_t mpdu_sequence_control_field : 16,
  382. mac_addr_ad3_47_32 : 16;
  383. uint32_t mac_addr_ad4_31_0 : 32;
  384. uint32_t mpdu_qos_control_field : 16,
  385. mac_addr_ad4_47_32 : 16;
  386. };
  387. struct rx_msdu_end_mon_data {
  388. uint32_t phy_ppdu_id : 16,
  389. reserved_0 : 7,
  390. sw_frame_group_id : 7,
  391. rxpcu_mpdu_filter_in_category : 2;
  392. uint32_t reserved_1a : 2,
  393. reported_mpdu_length : 14,
  394. ip_hdr_chksum : 16;
  395. uint32_t ip_chksum_fail_copy : 1,
  396. fr_ds : 1,
  397. last_msdu : 1,
  398. first_msdu : 1,
  399. l3_header_padding : 2,
  400. da_is_mcbc : 1,
  401. da_is_valid : 1,
  402. sa_is_valid : 1,
  403. tid : 4,
  404. to_ds : 1,
  405. da_idx_timeout : 1,
  406. sa_idx_timeout : 1,
  407. sa_sw_peer_id : 16;
  408. uint32_t da_idx_or_sw_peer_id : 16,
  409. sa_idx : 16;
  410. uint32_t fragment_flag : 1,
  411. vlan_stag_stripped : 1,
  412. vlan_ctag_stripped : 1,
  413. mesh_sta : 2,
  414. use_ppe : 1,
  415. flow_idx : 20,
  416. reo_destination_indication : 5,
  417. msdu_drop : 1;
  418. uint32_t fse_metadata : 32;
  419. uint32_t cce_metadata : 16,
  420. tcp_udp_chksum : 16;
  421. uint32_t cumulative_ip_length : 16,
  422. amsdu_parser_error : 1,
  423. cce_match : 1,
  424. flow_idx_invalid : 1,
  425. flow_idx_timeout : 1,
  426. msdu_limit_error : 1,
  427. tcp_udp_chksum_fail_copy : 1,
  428. fisa_timeout : 1,
  429. flow_aggregation_continuation : 1,
  430. aggregation_count : 8;
  431. uint32_t l4_offset : 8,
  432. ipsec_ah : 1,
  433. l3_offset : 7,
  434. ipsec_esp : 1,
  435. stbc : 1,
  436. msdu_length : 14;
  437. uint32_t ip4_protocol_ip6_next_header : 8,
  438. ldpc : 1,
  439. mesh_control_present : 1,
  440. tcp_udp_header_valid : 1,
  441. ip_extn_header_valid : 1,
  442. ip_fixed_header_valid : 1,
  443. toeplitz_hash_sel : 2,
  444. da_is_bcast_mcast : 1,
  445. tcp_only_ack : 1,
  446. ip_frag : 1,
  447. udp_proto : 1,
  448. tcp_proto : 1,
  449. ipv6_proto : 1,
  450. ipv4_proto : 1,
  451. decap_format : 2,
  452. msdu_number : 8;
  453. uint32_t msdu_done_copy : 1,
  454. mimo_ss_bitmap : 7,
  455. reception_type : 3,
  456. receive_bandwidth : 3,
  457. rate_mcs : 4,
  458. sgi : 2,
  459. pkt_type : 4,
  460. user_rssi : 8;
  461. uint32_t flow_id_toeplitz : 32;
  462. };
  463. struct rx_ppdu_end_user_mon_data {
  464. uint32_t fw2rxdma_pmac1_buf_source_used : 1,
  465. sw2rxdma_exception_buf_source_used: 1,
  466. sw2rxdma1_buf_source_used : 1,
  467. fw2rxdma_pmac0_buf_source_used : 1,
  468. sw2rxdma0_buf_source_used : 1,
  469. mpdu_cnt_fcs_err : 11,
  470. sw_peer_id : 16;
  471. uint32_t reserved_3b : 5,
  472. rxdma2reo_remote1_ring_used : 1,
  473. rxdma2reo_remote0_ring_used : 1,
  474. ht_control_field_pkt_type : 4,
  475. rxdma_release_ring_used : 1,
  476. rxdma2sw_ring_used : 1,
  477. rxdma2fw_pmac0_ring_used : 1,
  478. rxdma2reo_ring_used : 1,
  479. rxdma2fw_pmac1_ring_used : 1,
  480. ht_control_info_null_valid : 1,
  481. data_sequence_control_info_valid : 1,
  482. ht_control_info_valid : 1,
  483. qos_control_info_valid : 1,
  484. frame_control_info_valid : 1,
  485. mpdu_cnt_fcs_ok : 11;
  486. uint32_t frame_control_field : 16,
  487. ast_index : 16;
  488. uint32_t qos_control_field : 16,
  489. first_data_seq_ctrl : 16;
  490. uint32_t ht_control_field : 32;
  491. uint32_t fcs_ok_bitmap_31_0 : 32;
  492. uint32_t fcs_ok_bitmap_63_32 : 32;
  493. uint32_t tcp_msdu_count : 16,
  494. udp_msdu_count : 16;
  495. uint32_t tcp_ack_msdu_count : 16,
  496. other_msdu_count : 16;
  497. uint32_t sw_response_reference_ptr : 32;
  498. uint32_t received_qos_data_tid_eosp_bitmap : 16,
  499. received_qos_data_tid_bitmap : 16;
  500. uint32_t qosctrl_15_8_tid3 : 8,
  501. qosctrl_15_8_tid2 : 8,
  502. qosctrl_15_8_tid1 : 8,
  503. qosctrl_15_8_tid0 : 8;
  504. uint32_t qosctrl_15_8_tid15 : 8,
  505. qosctrl_15_8_tid14 : 8,
  506. qosctrl_15_8_tid13 : 8,
  507. qosctrl_15_8_tid12 : 8;
  508. uint32_t ampdu_delim_ok_count_6_0 : 7,
  509. mpdu_ok_byte_count : 25;
  510. uint32_t ampdu_delim_ok_count_13_7 : 7,
  511. ampdu_delim_err_count : 25;
  512. uint32_t ampdu_delim_ok_count_20_14 : 7,
  513. mpdu_err_byte_count : 25;
  514. uint32_t sw_response_reference_ptr_ext : 32;
  515. uint32_t reserved_23a : 3,
  516. retried_mpdu_count : 11,
  517. frame_control_field_null : 16,
  518. frame_control_info_null_valid : 1,
  519. corrupted_due_to_fifo_delay : 1;
  520. };
  521. #endif
  522. struct rx_mpdu_start_mon_data_t {
  523. struct rx_mpdu_start_mon_data rx_mpdu_info_details;
  524. };
  525. struct rx_msdu_end_mon_data_t {
  526. struct rx_msdu_end_mon_data rx_mpdu_info_details;
  527. };
  528. /* TLV struct for word based Tlv */
  529. typedef struct rx_mpdu_start_mon_data_t hal_rx_mon_mpdu_start_t;
  530. typedef struct rx_msdu_end_mon_data hal_rx_mon_msdu_end_t;
  531. typedef struct rx_ppdu_end_user_mon_data hal_rx_mon_ppdu_end_user_t;
  532. #else
  533. typedef struct rx_mpdu_start hal_rx_mon_mpdu_start_t;
  534. typedef struct rx_msdu_end hal_rx_mon_msdu_end_t;
  535. typedef struct rx_ppdu_end_user_stats hal_rx_mon_ppdu_end_user_t;
  536. #endif
  537. /*
  538. * struct mon_destination_drop - monitor drop descriptor
  539. *
  540. * @ppdu_drop_cnt: PPDU drop count
  541. * @mpdu_drop_cnt: MPDU drop count
  542. * @tlv_drop_cnt: TLV drop count
  543. * @end_of_ppdu_seen: end of ppdu seen
  544. * @reserved_0a: rsvd
  545. * @reserved_1a: rsvd
  546. * @ppdu_id: PPDU ID
  547. * @reserved_3a: rsvd
  548. * @initiator: initiator ppdu
  549. * @empty_descriptor: empty descriptor
  550. * @ring_id: ring id
  551. * @looping_count: looping count
  552. */
  553. struct mon_destination_drop {
  554. uint32_t ppdu_drop_cnt : 10,
  555. mpdu_drop_cnt : 10,
  556. tlv_drop_cnt : 10,
  557. end_of_ppdu_seen : 1,
  558. reserved_0a : 1;
  559. uint32_t reserved_1a : 32;
  560. uint32_t ppdu_id : 32;
  561. uint32_t reserved_3a : 18,
  562. initiator : 1,
  563. empty_descriptor : 1,
  564. ring_id : 8,
  565. looping_count : 4;
  566. };
  567. #define HAL_MON_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  568. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  569. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \
  570. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \
  571. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB))
  572. #define HAL_MON_BUFFER_ADDR_39_32_GET(buff_addr_info) \
  573. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  574. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \
  575. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \
  576. HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB))
  577. /**
  578. * struct hal_rx_status_buffer_done - status buffer done tlv
  579. * placeholder structure
  580. *
  581. * @ppdu_start_offset: ppdu start
  582. * @first_ppdu_start_user_info_offset:
  583. * @mult_ppdu_start_user_info:
  584. * @end_offset:
  585. * @ppdu_end_detected:
  586. * @flush_detected:
  587. * @rsvd:
  588. */
  589. struct hal_rx_status_buffer_done {
  590. uint32_t ppdu_start_offset : 3,
  591. first_ppdu_start_user_info_offset : 6,
  592. mult_ppdu_start_user_info : 1,
  593. end_offset : 13,
  594. ppdu_end_detected : 1,
  595. flush_detected : 1,
  596. rsvd : 7;
  597. };
  598. /**
  599. * enum hal_mon_status_end_reason - ppdu status buffer end reason
  600. *
  601. * @HAL_MON_STATUS_BUFFER_FULL: status buffer full
  602. * @HAL_MON_FLUSH_DETECTED: flush detected
  603. * @HAL_MON_END_OF_PPDU: end of ppdu detected
  604. * @HAL_MON_PPDU_TRUNCATED: truncated ppdu status
  605. */
  606. enum hal_mon_status_end_reason {
  607. HAL_MON_STATUS_BUFFER_FULL,
  608. HAL_MON_FLUSH_DETECTED,
  609. HAL_MON_END_OF_PPDU,
  610. HAL_MON_PPDU_TRUNCATED,
  611. };
  612. /**
  613. * struct hal_mon_desc - HAL Monitor descriptor
  614. *
  615. * @buf_addr: virtual buffer address
  616. * @ppdu_id: ppdu id
  617. * - TxMon fills scheduler id
  618. * - RxMON fills phy_ppdu_id
  619. * @end_offset: offset (units in 4 bytes) where status buffer ended
  620. * i.e offset of TLV + last TLV size
  621. * @reserved_3a: reserved bits
  622. * @end_reason: ppdu end reason
  623. * 0 - status buffer is full
  624. * 1 - flush detected
  625. * 2 - TX_FES_STATUS_END or RX_PPDU_END
  626. * 3 - PPDU truncated due to system error
  627. * @initiator: 1 - descriptor belongs to TX FES
  628. * 0 - descriptor belongs to TX RESPONSE
  629. * @empty_descriptor: 0 - this descriptor is written on a flush
  630. * or end of ppdu or end of status buffer
  631. * 1 - descriptor provided to indicate drop
  632. * @ring_id: ring id for debugging
  633. * @looping_count: count to indicate number of times producer
  634. * of entries has looped around the ring
  635. * @flush_detected: if flush detected
  636. * @end_of_ppdu_dropped: if end_of_ppdu is dropped
  637. * @ppdu_drop_count: PPDU drop count
  638. * @mpdu_drop_count: MPDU drop count
  639. * @tlv_drop_count: TLV drop count
  640. */
  641. struct hal_mon_desc {
  642. uint64_t buf_addr;
  643. uint32_t ppdu_id;
  644. uint32_t end_offset:12,
  645. reserved_3a:4,
  646. end_reason:2,
  647. initiator:1,
  648. empty_descriptor:1,
  649. ring_id:8,
  650. looping_count:4;
  651. uint16_t flush_detected:1,
  652. end_of_ppdu_dropped:1;
  653. uint32_t ppdu_drop_count;
  654. uint32_t mpdu_drop_count;
  655. uint32_t tlv_drop_count;
  656. };
  657. typedef struct hal_mon_desc *hal_mon_desc_t;
  658. /**
  659. * struct hal_mon_buf_addr_status - HAL buffer address tlv get status
  660. *
  661. * @buffer_virt_addr_31_0: Lower 32 bits of virtual address of status buffer
  662. * @buffer_virt_addr_63_32: Upper 32 bits of virtual address of status buffer
  663. * @dma_length: DMA length
  664. * @reserved_2a: reserved bits
  665. * @msdu_continuation: is msdu size more than fragment size
  666. * @truncated: is msdu got truncated
  667. * @reserved_2b: reserved bits
  668. * @tlv64_padding: tlv paddding
  669. */
  670. struct hal_mon_buf_addr_status {
  671. uint32_t buffer_virt_addr_31_0;
  672. uint32_t buffer_virt_addr_63_32;
  673. uint32_t dma_length:12,
  674. reserved_2a:4,
  675. msdu_continuation:1,
  676. truncated:1,
  677. reserved_2b:14;
  678. uint32_t tlv64_padding;
  679. };
  680. #ifdef QCA_MONITOR_2_0_SUPPORT
  681. /**
  682. * hal_be_get_mon_dest_status() - Get monitor descriptor status
  683. * @hal_soc: HAL Soc handle
  684. * @hw_desc: HAL monitor descriptor
  685. * @status: pointer to write descriptor status
  686. *
  687. * Return: none
  688. */
  689. static inline void
  690. hal_be_get_mon_dest_status(hal_soc_handle_t hal_soc,
  691. void *hw_desc,
  692. struct hal_mon_desc *status)
  693. {
  694. struct mon_destination_ring *desc = hw_desc;
  695. status->empty_descriptor = desc->empty_descriptor;
  696. if (status->empty_descriptor) {
  697. struct mon_destination_drop *drop_desc = hw_desc;
  698. status->buf_addr = 0;
  699. status->ppdu_drop_count = drop_desc->ppdu_drop_cnt;
  700. status->mpdu_drop_count = drop_desc->mpdu_drop_cnt;
  701. status->tlv_drop_count = drop_desc->tlv_drop_cnt;
  702. status->end_of_ppdu_dropped = drop_desc->end_of_ppdu_seen;
  703. } else {
  704. status->buf_addr = HAL_RX_GET(desc, MON_DESTINATION_RING_STAT,BUF_VIRT_ADDR_31_0) |
  705. (((uint64_t)HAL_RX_GET(desc,
  706. MON_DESTINATION_RING_STAT,
  707. BUF_VIRT_ADDR_63_32)) << 32);
  708. status->end_reason = desc->end_reason;
  709. status->end_offset = desc->end_offset;
  710. }
  711. status->ppdu_id = desc->ppdu_id;
  712. status->initiator = desc->initiator;
  713. status->looping_count = desc->looping_count;
  714. }
  715. #endif
  716. #if defined(RX_PPDU_END_USER_STATS_OFDMA_INFO_VALID_OFFSET) && \
  717. defined(RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET)
  718. static inline void
  719. hal_rx_handle_mu_ul_info(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user,
  720. struct mon_rx_user_status *mon_rx_user_status)
  721. {
  722. mon_rx_user_status->mu_ul_user_v0_word0 =
  723. rx_ppdu_end_user->sw_response_reference_ptr;
  724. mon_rx_user_status->mu_ul_user_v0_word1 =
  725. rx_ppdu_end_user->sw_response_reference_ptr_ext;
  726. }
  727. #else
  728. static inline void
  729. hal_rx_handle_mu_ul_info(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user,
  730. struct mon_rx_user_status *mon_rx_user_status)
  731. {
  732. }
  733. #endif
  734. static inline void
  735. hal_rx_populate_byte_count(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user,
  736. void *ppduinfo,
  737. struct mon_rx_user_status *mon_rx_user_status)
  738. {
  739. mon_rx_user_status->mpdu_ok_byte_count =
  740. rx_ppdu_end_user->mpdu_ok_byte_count;
  741. mon_rx_user_status->mpdu_err_byte_count =
  742. rx_ppdu_end_user->mpdu_err_byte_count;
  743. }
  744. static inline void
  745. hal_rx_populate_mu_user_info(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user,
  746. void *ppduinfo, uint32_t user_id,
  747. struct mon_rx_user_status *mon_rx_user_status)
  748. {
  749. struct mon_rx_info *mon_rx_info;
  750. struct mon_rx_user_info *mon_rx_user_info;
  751. struct hal_rx_ppdu_info *ppdu_info =
  752. (struct hal_rx_ppdu_info *)ppduinfo;
  753. mon_rx_info = &ppdu_info->rx_info;
  754. mon_rx_user_info = &ppdu_info->rx_user_info[user_id];
  755. mon_rx_user_info->qos_control_info_valid =
  756. mon_rx_info->qos_control_info_valid;
  757. mon_rx_user_info->qos_control = mon_rx_info->qos_control;
  758. mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index;
  759. mon_rx_user_status->tid = ppdu_info->rx_status.tid;
  760. mon_rx_user_status->tcp_msdu_count =
  761. ppdu_info->rx_status.tcp_msdu_count;
  762. mon_rx_user_status->udp_msdu_count =
  763. ppdu_info->rx_status.udp_msdu_count;
  764. mon_rx_user_status->other_msdu_count =
  765. ppdu_info->rx_status.other_msdu_count;
  766. mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control;
  767. mon_rx_user_status->frame_control_info_valid =
  768. ppdu_info->rx_status.frame_control_info_valid;
  769. mon_rx_user_status->data_sequence_control_info_valid =
  770. ppdu_info->rx_status.data_sequence_control_info_valid;
  771. mon_rx_user_status->first_data_seq_ctrl =
  772. ppdu_info->rx_status.first_data_seq_ctrl;
  773. mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type;
  774. mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags;
  775. mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags;
  776. mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags;
  777. if (mon_rx_user_status->vht_flags) {
  778. mon_rx_user_status->vht_flag_values2 =
  779. ppdu_info->rx_status.vht_flag_values2;
  780. qdf_mem_copy(mon_rx_user_status->vht_flag_values3,
  781. ppdu_info->rx_status.vht_flag_values3,
  782. sizeof(mon_rx_user_status->vht_flag_values3));
  783. mon_rx_user_status->vht_flag_values4 =
  784. ppdu_info->rx_status.vht_flag_values4;
  785. mon_rx_user_status->vht_flag_values5 =
  786. ppdu_info->rx_status.vht_flag_values5;
  787. mon_rx_user_status->vht_flag_values6 =
  788. ppdu_info->rx_status.vht_flag_values6;
  789. }
  790. mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags;
  791. mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags;
  792. mon_rx_user_status->mpdu_cnt_fcs_ok =
  793. ppdu_info->com_info.mpdu_cnt_fcs_ok;
  794. mon_rx_user_status->mpdu_cnt_fcs_err =
  795. ppdu_info->com_info.mpdu_cnt_fcs_err;
  796. qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap,
  797. &ppdu_info->com_info.mpdu_fcs_ok_bitmap,
  798. HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
  799. sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0]));
  800. mon_rx_user_status->retry_mpdu =
  801. ppdu_info->rx_status.mpdu_retry_cnt;
  802. hal_rx_populate_byte_count(rx_ppdu_end_user, ppdu_info,
  803. mon_rx_user_status);
  804. }
  805. #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, \
  806. ppdu_info, rssi_info_tlv) \
  807. { \
  808. ppdu_info->rx_status.rssi_chain[chain][0] = \
  809. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  810. RSSI_PRI20_CHAIN##chain); \
  811. ppdu_info->rx_status.rssi_chain[chain][1] = \
  812. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  813. RSSI_EXT20_CHAIN##chain); \
  814. ppdu_info->rx_status.rssi_chain[chain][2] = \
  815. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  816. RSSI_EXT40_LOW20_CHAIN##chain); \
  817. ppdu_info->rx_status.rssi_chain[chain][3] = \
  818. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\
  819. RSSI_EXT40_HIGH20_CHAIN##chain); \
  820. } \
  821. #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \
  822. {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, ppdu_info, rssi_info_tlv) \
  823. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, ppdu_info, rssi_info_tlv) \
  824. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, ppdu_info, rssi_info_tlv) \
  825. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, ppdu_info, rssi_info_tlv) \
  826. } \
  827. static inline uint32_t
  828. hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info,
  829. uint8_t *rssi_info_tlv)
  830. {
  831. HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv)
  832. return 0;
  833. }
  834. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  835. static inline void
  836. hal_get_qos_control(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user,
  837. struct hal_rx_ppdu_info *ppdu_info)
  838. {
  839. ppdu_info->rx_info.qos_control_info_valid =
  840. rx_ppdu_end_user->qos_control_info_valid;
  841. if (ppdu_info->rx_info.qos_control_info_valid)
  842. ppdu_info->rx_info.qos_control =
  843. rx_ppdu_end_user->qos_control_field;
  844. }
  845. static inline void
  846. hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start,
  847. struct hal_rx_ppdu_info *ppdu_info)
  848. {
  849. if ((ppdu_info->sw_frame_group_id
  850. == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) ||
  851. (ppdu_info->sw_frame_group_id ==
  852. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) {
  853. ppdu_info->rx_info.mac_addr1_valid =
  854. rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_valid;
  855. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] =
  856. rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_31_0;
  857. if (ppdu_info->sw_frame_group_id ==
  858. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) {
  859. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] =
  860. rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_47_32;
  861. }
  862. }
  863. }
  864. #else
  865. static inline void
  866. hal_get_qos_control(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user,
  867. struct hal_rx_ppdu_info *ppdu_info)
  868. {
  869. }
  870. static inline void
  871. hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start,
  872. struct hal_rx_ppdu_info *ppdu_info)
  873. {
  874. }
  875. #endif
  876. #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS
  877. static inline void
  878. hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start,
  879. struct hal_rx_ppdu_info *ppdu_info)
  880. {
  881. uint16_t frame_ctrl;
  882. uint8_t fc_type;
  883. if (rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid) {
  884. frame_ctrl = rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field;
  885. fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl);
  886. if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT)
  887. ppdu_info->frm_type_info.rx_mgmt_cnt++;
  888. else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL)
  889. ppdu_info->frm_type_info.rx_ctrl_cnt++;
  890. else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA)
  891. ppdu_info->frm_type_info.rx_data_cnt++;
  892. }
  893. }
  894. #else
  895. static inline void
  896. hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start,
  897. struct hal_rx_ppdu_info *ppdu_info)
  898. {
  899. }
  900. #endif
  901. #ifdef QCA_MONITOR_2_0_SUPPORT
  902. /**
  903. * hal_mon_buff_addr_info_set() - set desc address in cookie
  904. * @hal_soc_hdl: HAL Soc handle
  905. * @mon_entry: monitor srng
  906. * @mon_desc_addr: HAL monitor descriptor virtual address
  907. * @phy_addr: HAL monitor descriptor physical address
  908. *
  909. * Return: none
  910. */
  911. static inline
  912. void hal_mon_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl,
  913. void *mon_entry,
  914. void *mon_desc_addr,
  915. qdf_dma_addr_t phy_addr)
  916. {
  917. uint32_t paddr_lo = ((uintptr_t)phy_addr & 0x00000000ffffffff);
  918. uint32_t paddr_hi = ((uintptr_t)phy_addr & 0xffffffff00000000) >> 32;
  919. uint32_t vaddr_lo = ((uintptr_t)mon_desc_addr & 0x00000000ffffffff);
  920. uint32_t vaddr_hi = ((uintptr_t)mon_desc_addr & 0xffffffff00000000) >> 32;
  921. HAL_MON_PADDR_LO_SET(mon_entry, paddr_lo);
  922. HAL_MON_PADDR_HI_SET(mon_entry, paddr_hi);
  923. HAL_MON_VADDR_LO_SET(mon_entry, vaddr_lo);
  924. HAL_MON_VADDR_HI_SET(mon_entry, vaddr_hi);
  925. }
  926. /* TX monitor */
  927. #define TX_MON_STATUS_BUF_SIZE 2048
  928. #define HAL_INVALID_PPDU_ID 0xFFFFFFFF
  929. #define HAL_MAX_DL_MU_USERS 37
  930. #define HAL_MAX_RU_INDEX 7
  931. enum hal_tx_tlv_status {
  932. HAL_MON_TX_FES_SETUP,
  933. HAL_MON_TX_FES_STATUS_END,
  934. HAL_MON_RX_RESPONSE_REQUIRED_INFO,
  935. HAL_MON_RESPONSE_END_STATUS_INFO,
  936. HAL_MON_TX_PCU_PPDU_SETUP_INIT,
  937. HAL_MON_TX_MPDU_START,
  938. HAL_MON_TX_MSDU_START,
  939. HAL_MON_TX_BUFFER_ADDR,
  940. HAL_MON_TX_DATA,
  941. HAL_MON_TX_FES_STATUS_START,
  942. HAL_MON_TX_FES_STATUS_PROT,
  943. HAL_MON_TX_FES_STATUS_START_PROT,
  944. HAL_MON_TX_FES_STATUS_START_PPDU,
  945. HAL_MON_TX_FES_STATUS_USER_PPDU,
  946. HAL_MON_TX_QUEUE_EXTENSION,
  947. HAL_MON_RX_FRAME_BITMAP_ACK,
  948. HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_256,
  949. HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K,
  950. HAL_MON_COEX_TX_STATUS,
  951. HAL_MON_MACTX_HE_SIG_A_SU,
  952. HAL_MON_MACTX_HE_SIG_A_MU_DL,
  953. HAL_MON_MACTX_HE_SIG_B1_MU,
  954. HAL_MON_MACTX_HE_SIG_B2_MU,
  955. HAL_MON_MACTX_HE_SIG_B2_OFDMA,
  956. HAL_MON_MACTX_L_SIG_A,
  957. HAL_MON_MACTX_L_SIG_B,
  958. HAL_MON_MACTX_HT_SIG,
  959. HAL_MON_MACTX_VHT_SIG_A,
  960. HAL_MON_MACTX_USER_DESC_PER_USER,
  961. HAL_MON_MACTX_USER_DESC_COMMON,
  962. HAL_MON_MACTX_PHY_DESC,
  963. HAL_MON_TX_FW2SW,
  964. HAL_MON_TX_STATUS_PPDU_NOT_DONE,
  965. };
  966. enum txmon_coex_tx_status_reason {
  967. COEX_FES_TX_START,
  968. COEX_FES_TX_END,
  969. COEX_FES_END,
  970. COEX_RESPONSE_TX_START,
  971. COEX_RESPONSE_TX_END,
  972. COEX_NO_TX_ONGOING,
  973. };
  974. enum txmon_transmission_type {
  975. TXMON_SU_TRANSMISSION = 0,
  976. TXMON_MU_TRANSMISSION,
  977. TXMON_MU_SU_TRANSMISSION,
  978. TXMON_MU_MIMO_TRANSMISSION = 1,
  979. TXMON_MU_OFDMA_TRANMISSION
  980. };
  981. enum txmon_he_ppdu_subtype {
  982. TXMON_HE_SUBTYPE_SU = 0,
  983. TXMON_HE_SUBTYPE_TRIG,
  984. TXMON_HE_SUBTYPE_MU,
  985. TXMON_HE_SUBTYPE_EXT_SU
  986. };
  987. enum txmon_pkt_type {
  988. TXMON_PKT_TYPE_11A = 0,
  989. TXMON_PKT_TYPE_11B,
  990. TXMON_PKT_TYPE_11N_MM,
  991. TXMON_PKT_TYPE_11AC,
  992. TXMON_PKT_TYPE_11AX,
  993. TXMON_PKT_TYPE_11BA,
  994. TXMON_PKT_TYPE_11BE,
  995. TXMON_PKT_TYPE_11AZ
  996. };
  997. enum txmon_generated_response {
  998. TXMON_GEN_RESP_SELFGEN_ACK = 0,
  999. TXMON_GEN_RESP_SELFGEN_CTS,
  1000. TXMON_GEN_RESP_SELFGEN_BA,
  1001. TXMON_GEN_RESP_SELFGEN_MBA,
  1002. TXMON_GEN_RESP_SELFGEN_CBF,
  1003. TXMON_GEN_RESP_SELFGEN_TRIG,
  1004. TXMON_GEN_RESP_SELFGEN_NDP_LMR
  1005. };
  1006. #ifdef MONITOR_TLV_RECORDING_ENABLE
  1007. /*
  1008. * Please make sure that the maximum total size of fields in each TLV
  1009. * is 22 bits.
  1010. * 10 bits are reserved for tlv_tag
  1011. */
  1012. struct hal_ppdu_start_tlv_record {
  1013. uint32_t ppdu_id:10;
  1014. };
  1015. struct hal_ppdu_start_user_info_tlv_record {
  1016. uint32_t user_id:6,
  1017. rate_mcs:4,
  1018. nss:3,
  1019. reception_type:3,
  1020. sgi:2;
  1021. };
  1022. struct hal_mpdu_start_tlv_record {
  1023. uint32_t user_id:6,
  1024. wrap_flag:1;
  1025. };
  1026. struct hal_mpdu_end_tlv_record {
  1027. uint32_t user_id:6,
  1028. fcs_err:1,
  1029. wrap_flag:1;
  1030. };
  1031. struct hal_header_tlv_record {
  1032. uint32_t wrap_flag:1;
  1033. };
  1034. struct hal_msdu_end_tlv_record {
  1035. uint32_t user_id:6,
  1036. msdu_num:8,
  1037. tid:4,
  1038. tcp_proto:1,
  1039. udp_proto:1,
  1040. wrap_flag:1;
  1041. };
  1042. struct hal_mon_buffer_addr_tlv_record {
  1043. uint32_t dma_length:12,
  1044. truncation:1,
  1045. continuation:1,
  1046. wrap_flag:1;
  1047. };
  1048. struct hal_phy_location_tlv_record {
  1049. uint32_t rtt_cfr_status:8,
  1050. rtt_num_streams:8,
  1051. rx_location_info_valid:1;
  1052. };
  1053. struct hal_ppdu_end_user_stats_tlv_record {
  1054. uint32_t ast_index:16,
  1055. pkt_type:4;
  1056. };
  1057. struct hal_pcu_ppdu_end_info_tlv_record {
  1058. uint32_t dialog_topken:8,
  1059. bb_captured_reason:3,
  1060. bb_captured_channel:1,
  1061. bb_captured_timeout:1,
  1062. mpdu_delimiter_error_seen:1;
  1063. };
  1064. struct hal_phy_rx_ht_sig_tlv_record {
  1065. uint32_t crc:8,
  1066. mcs:7,
  1067. stbc:2,
  1068. aggregation:1,
  1069. short_gi:1,
  1070. fes_coding:1,
  1071. cbw:1;
  1072. };
  1073. /*
  1074. * enum hal_ppdu_tlv_category - Categories of TLV
  1075. * @PPDU_START: PPDU start level TLV
  1076. * @MPDU: MPDU level TLV
  1077. * @PPDU_END: PPDU end level TLV
  1078. *
  1079. */
  1080. enum hal_ppdu_tlv_category {
  1081. CATEGORY_PPDU_START = 1,
  1082. CATEGORY_MPDU,
  1083. CATEGORY_PPDU_END
  1084. };
  1085. #endif
  1086. /**
  1087. * struct hal_txmon_user_desc_per_user - user desc per user information
  1088. * @psdu_length: PSDU length of the user in octet
  1089. * @ru_start_index: RU number to which user is assigned
  1090. * @ru_size: Size of the RU for that user
  1091. * @ofdma_mu_mimo_enabled: mu mimo transmission within the RU
  1092. * @nss: Number of spatial stream occupied by the user
  1093. * @stream_offset: Stream Offset from which the User occupies the Streams
  1094. * @mcs: Modulation Coding Scheme for the User
  1095. * @dcm: Indicates whether dual sub-carrier modulation is applied
  1096. * @fec_type: Indicates whether it is BCC or LDPC
  1097. * @user_bf_type: user beamforming type
  1098. * @drop_user_cbf: frame dropped because of CBF FCS failure
  1099. * @ldpc_extra_symbol: LDPC encoding process
  1100. * @force_extra_symbol: force an extra OFDM symbol
  1101. * @reserved: reserved
  1102. * @sw_peer_id: user sw peer id
  1103. * @per_user_subband_mask: Per user sub band mask
  1104. */
  1105. struct hal_txmon_user_desc_per_user {
  1106. uint32_t psdu_length;
  1107. uint32_t ru_start_index :8,
  1108. ru_size :4,
  1109. ofdma_mu_mimo_enabled :1,
  1110. nss :3,
  1111. stream_offset :3,
  1112. mcs :4,
  1113. dcm :1,
  1114. fec_type :1,
  1115. user_bf_type :2,
  1116. drop_user_cbf :1,
  1117. ldpc_extra_symbol :1,
  1118. force_extra_symbol :1,
  1119. reserved :2;
  1120. uint32_t sw_peer_id :16,
  1121. per_user_subband_mask :16;
  1122. };
  1123. /**
  1124. * struct hal_txmon_usr_desc_common - user desc common information
  1125. * @num_users: Number of users
  1126. * @ltf_size: LTF size
  1127. * @pkt_extn_pe: packet extension duration of the trigger-based PPDU
  1128. * @a_factor: packet extension duration of the trigger-based PPDU
  1129. * @center_ru_0: Center RU is occupied in the lower 80 MHz band
  1130. * @center_ru_1: Center RU is occupied in the upper 80 MHz band
  1131. * @num_ltf_symbols: number of LTF symbols
  1132. * @doppler_indication: doppler indication
  1133. * @reserved: reserved
  1134. * @spatial_reuse: spatial reuse
  1135. * @ru_channel_0: RU arrangement for band 0
  1136. * @ru_channel_1: RU arrangement for band 1
  1137. */
  1138. struct hal_txmon_usr_desc_common {
  1139. uint32_t num_users :6,
  1140. ltf_size :2,
  1141. pkt_extn_pe :1,
  1142. a_factor :2,
  1143. center_ru_0 :1,
  1144. center_ru_1 :1,
  1145. num_ltf_symbols :16,
  1146. doppler_indication :1,
  1147. reserved :2;
  1148. uint16_t spatial_reuse;
  1149. uint16_t ru_channel_0[8];
  1150. uint16_t ru_channel_1[8];
  1151. };
  1152. #define IS_MULTI_USERS(num_users) (!!(0xFFFE & num_users))
  1153. #define TXMON_HAL(hal_tx_ppdu_info, field) \
  1154. hal_tx_ppdu_info->field
  1155. #define TXMON_HAL_STATUS(hal_tx_ppdu_info, field) \
  1156. hal_tx_ppdu_info->rx_status.field
  1157. #define TXMON_HAL_USER(hal_tx_ppdu_info, user_id, field) \
  1158. hal_tx_ppdu_info->rx_user_status[user_id].field
  1159. #define TXMON_STATUS_INFO(hal_tx_status_info, field) \
  1160. hal_tx_status_info->field
  1161. /**
  1162. * struct hal_tx_status_info - status info that wasn't populated in rx_status
  1163. * @reception_type: su or uplink mu reception type
  1164. * @transmission_type: su or mu transmission type
  1165. * @medium_prot_type: medium protection type
  1166. * @generated_response: Generated frame in response window
  1167. * @band_center_freq1:
  1168. * @band_center_freq2:
  1169. * @freq:
  1170. * @phy_mode:
  1171. * @schedule_id:
  1172. * @no_bitmap_avail: Bitmap available flag
  1173. * @explicit_ack: Explicit Acknowledge flag
  1174. * @explicit_ack_type: Explicit Acknowledge type
  1175. * @r2r_end_status_follow: Response to Response status flag
  1176. * @response_type: Response type in response window
  1177. * @ndp_frame: NDP frame
  1178. * @num_users: number of users
  1179. * @reserved: reserved bits
  1180. * @mba_count: MBA count
  1181. * @mba_fake_bitmap_count: MBA fake bitmap count
  1182. * @sw_frame_group_id: software frame group ID
  1183. * @r2r_to_follow: Response to Response follow flag
  1184. * @phy_abort_reason: Reason for PHY abort
  1185. * @phy_abort_user_number: User number for PHY abort
  1186. * @buffer: Packet buffer pointer address
  1187. * @offset: Packet buffer offset
  1188. * @length: Packet buffer length
  1189. * @protection_addr: Protection Address flag
  1190. * @addr1: MAC address 1
  1191. * @addr2: MAC address 2
  1192. * @addr3: MAC address 3
  1193. * @addr4: MAC address 4
  1194. */
  1195. struct hal_tx_status_info {
  1196. uint8_t reception_type;
  1197. uint8_t transmission_type;
  1198. uint8_t medium_prot_type;
  1199. uint8_t generated_response;
  1200. uint16_t band_center_freq1;
  1201. uint16_t band_center_freq2;
  1202. uint16_t freq;
  1203. uint16_t phy_mode;
  1204. uint32_t schedule_id;
  1205. uint32_t no_bitmap_avail :1,
  1206. explicit_ack :1,
  1207. explicit_ack_type :4,
  1208. r2r_end_status_follow :1,
  1209. response_type :5,
  1210. ndp_frame :2,
  1211. num_users :8,
  1212. reserved :10;
  1213. uint8_t mba_count;
  1214. uint8_t mba_fake_bitmap_count;
  1215. uint8_t sw_frame_group_id;
  1216. uint32_t r2r_to_follow;
  1217. uint16_t phy_abort_reason;
  1218. uint8_t phy_abort_user_number;
  1219. void *buffer;
  1220. uint32_t offset;
  1221. uint32_t length;
  1222. uint8_t protection_addr;
  1223. uint8_t addr1[QDF_MAC_ADDR_SIZE];
  1224. uint8_t addr2[QDF_MAC_ADDR_SIZE];
  1225. uint8_t addr3[QDF_MAC_ADDR_SIZE];
  1226. uint8_t addr4[QDF_MAC_ADDR_SIZE];
  1227. };
  1228. /**
  1229. * struct hal_tx_ppdu_info - tx monitor ppdu information
  1230. * @ppdu_id: Id of the PLCP protocol data unit
  1231. * @num_users: number of users
  1232. * @is_used: boolean flag to identify valid ppdu info
  1233. * @is_data: boolean flag to identify data frame
  1234. * @cur_usr_idx: Current user index of the PPDU
  1235. * @reserved: for future purpose
  1236. * @prot_tlv_status: protection tlv status
  1237. * @packet_info: packet information
  1238. * @rx_status: monitor mode rx status information
  1239. * @rx_user_status: monitor mode rx user status information
  1240. */
  1241. struct hal_tx_ppdu_info {
  1242. uint32_t ppdu_id;
  1243. uint32_t num_users :8,
  1244. is_used :1,
  1245. is_data :1,
  1246. cur_usr_idx :8,
  1247. reserved :15;
  1248. uint32_t prot_tlv_status;
  1249. /* placeholder to hold packet buffer info */
  1250. struct hal_mon_packet_info packet_info;
  1251. struct mon_rx_status rx_status;
  1252. struct mon_rx_user_status rx_user_status[];
  1253. };
  1254. /**
  1255. * hal_tx_status_get_next_tlv() - get next tx status TLV
  1256. * @tx_tlv: pointer to TLV header
  1257. *
  1258. * Return: pointer to next tlv info
  1259. */
  1260. static inline uint8_t*
  1261. hal_tx_status_get_next_tlv(uint8_t *tx_tlv) {
  1262. uint32_t tlv_len, tlv_tag;
  1263. tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv);
  1264. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv);
  1265. return (uint8_t *)(((unsigned long)(tx_tlv + tlv_len +
  1266. HAL_RX_TLV32_HDR_SIZE + 7)) & (~7));
  1267. }
  1268. /**
  1269. * hal_txmon_status_parse_tlv() - process transmit info TLV
  1270. * @hal_soc_hdl: HAL soc handle
  1271. * @data_ppdu_info: pointer to hal data ppdu info
  1272. * @prot_ppdu_info: pointer to hal prot ppdu info
  1273. * @data_status_info: pointer to data status info
  1274. * @prot_status_info: pointer to prot status info
  1275. * @tx_tlv_hdr: pointer to TLV header
  1276. * @status_frag: pointer to status frag
  1277. *
  1278. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE
  1279. */
  1280. static inline uint32_t
  1281. hal_txmon_status_parse_tlv(hal_soc_handle_t hal_soc_hdl,
  1282. void *data_ppdu_info,
  1283. void *prot_ppdu_info,
  1284. void *data_status_info,
  1285. void *prot_status_info,
  1286. void *tx_tlv_hdr,
  1287. qdf_frag_t status_frag)
  1288. {
  1289. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1290. return hal_soc->ops->hal_txmon_status_parse_tlv(data_ppdu_info,
  1291. prot_ppdu_info,
  1292. data_status_info,
  1293. prot_status_info,
  1294. tx_tlv_hdr,
  1295. status_frag);
  1296. }
  1297. /**
  1298. * hal_txmon_status_get_num_users() - api to get num users from start of fes
  1299. * window
  1300. * @hal_soc_hdl: HAL soc handle
  1301. * @tx_tlv_hdr: pointer to TLV header
  1302. * @num_users: reference to number of user
  1303. *
  1304. * Return: status
  1305. */
  1306. static inline uint32_t
  1307. hal_txmon_status_get_num_users(hal_soc_handle_t hal_soc_hdl,
  1308. void *tx_tlv_hdr, uint8_t *num_users)
  1309. {
  1310. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1311. return hal_soc->ops->hal_txmon_status_get_num_users(tx_tlv_hdr,
  1312. num_users);
  1313. }
  1314. /**
  1315. * hal_tx_status_get_tlv_tag() - api to get tlv tag
  1316. * @tx_tlv_hdr: pointer to TLV header
  1317. *
  1318. * Return tlv_tag
  1319. */
  1320. static inline uint32_t
  1321. hal_tx_status_get_tlv_tag(void *tx_tlv_hdr)
  1322. {
  1323. uint32_t tlv_tag = 0;
  1324. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr);
  1325. return tlv_tag;
  1326. }
  1327. /**
  1328. * hal_txmon_get_word_mask() - api to get word mask for tx monitor
  1329. * @hal_soc_hdl: HAL soc handle
  1330. * @wmask: pointer to hal_txmon_word_mask_config_t
  1331. *
  1332. * Return: bool
  1333. */
  1334. static inline bool
  1335. hal_txmon_get_word_mask(hal_soc_handle_t hal_soc_hdl,
  1336. hal_txmon_word_mask_config_t *wmask)
  1337. {
  1338. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1339. if (hal_soc->ops->hal_txmon_get_word_mask) {
  1340. hal_soc->ops->hal_txmon_get_word_mask(wmask);
  1341. return true;
  1342. }
  1343. return false;
  1344. }
  1345. #endif
  1346. /**
  1347. * hal_txmon_is_mon_buf_addr_tlv() - api to find packet buffer addr tlv
  1348. * @hal_soc_hdl: HAL soc handle
  1349. * @tx_tlv_hdr: pointer to TLV header
  1350. *
  1351. * Return: bool
  1352. */
  1353. static inline bool
  1354. hal_txmon_is_mon_buf_addr_tlv(hal_soc_handle_t hal_soc_hdl, void *tx_tlv_hdr)
  1355. {
  1356. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1357. if (qdf_unlikely(!hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv))
  1358. return false;
  1359. return hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv(tx_tlv_hdr);
  1360. }
  1361. /**
  1362. * hal_txmon_populate_packet_info() - api to populate packet info
  1363. * @hal_soc_hdl: HAL soc handle
  1364. * @tx_tlv_hdr: pointer to TLV header
  1365. * @packet_info: pointer to placeholder for packet info
  1366. *
  1367. * Return void
  1368. */
  1369. static inline void
  1370. hal_txmon_populate_packet_info(hal_soc_handle_t hal_soc_hdl,
  1371. void *tx_tlv_hdr,
  1372. void *packet_info)
  1373. {
  1374. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1375. if (qdf_unlikely(!hal_soc->ops->hal_txmon_populate_packet_info))
  1376. return;
  1377. hal_soc->ops->hal_txmon_populate_packet_info(tx_tlv_hdr, packet_info);
  1378. }
  1379. static inline uint32_t
  1380. hal_rx_parse_u_sig_cmn(struct hal_soc *hal_soc, void *rx_tlv,
  1381. struct hal_rx_ppdu_info *ppdu_info)
  1382. {
  1383. struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv;
  1384. struct hal_mon_usig_cmn *usig_1 = &usig->usig_1;
  1385. uint8_t bad_usig_crc;
  1386. bad_usig_crc = HAL_RX_MON_USIG_GET_RX_INTEGRITY_CHECK_PASSED(rx_tlv) ?
  1387. 0 : 1;
  1388. ppdu_info->rx_status.usig_common |=
  1389. QDF_MON_STATUS_USIG_PHY_VERSION_KNOWN |
  1390. QDF_MON_STATUS_USIG_BW_KNOWN |
  1391. QDF_MON_STATUS_USIG_UL_DL_KNOWN |
  1392. QDF_MON_STATUS_USIG_BSS_COLOR_KNOWN |
  1393. QDF_MON_STATUS_USIG_TXOP_KNOWN;
  1394. ppdu_info->rx_status.usig_common |= (usig_1->phy_version <<
  1395. QDF_MON_STATUS_USIG_PHY_VERSION_SHIFT);
  1396. ppdu_info->rx_status.usig_common |= (usig_1->bw <<
  1397. QDF_MON_STATUS_USIG_BW_SHIFT);
  1398. ppdu_info->rx_status.usig_common |= (usig_1->ul_dl <<
  1399. QDF_MON_STATUS_USIG_UL_DL_SHIFT);
  1400. ppdu_info->rx_status.usig_common |= (usig_1->bss_color <<
  1401. QDF_MON_STATUS_USIG_BSS_COLOR_SHIFT);
  1402. ppdu_info->rx_status.usig_common |= (usig_1->txop <<
  1403. QDF_MON_STATUS_USIG_TXOP_SHIFT);
  1404. ppdu_info->rx_status.usig_common |= bad_usig_crc;
  1405. ppdu_info->u_sig_info.ul_dl = usig_1->ul_dl;
  1406. ppdu_info->u_sig_info.bw = usig_1->bw;
  1407. ppdu_info->rx_status.bw = usig_1->bw;
  1408. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1409. }
  1410. static inline uint32_t
  1411. hal_rx_parse_u_sig_tb(struct hal_soc *hal_soc, void *rx_tlv,
  1412. struct hal_rx_ppdu_info *ppdu_info)
  1413. {
  1414. struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv;
  1415. struct hal_mon_usig_tb *usig_tb = &usig->usig_2.tb;
  1416. ppdu_info->rx_status.usig_mask |=
  1417. QDF_MON_STATUS_USIG_DISREGARD_KNOWN |
  1418. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN |
  1419. QDF_MON_STATUS_USIG_VALIDATE_KNOWN |
  1420. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_KNOWN |
  1421. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_KNOWN |
  1422. QDF_MON_STATUS_USIG_TB_DISREGARD1_KNOWN |
  1423. QDF_MON_STATUS_USIG_CRC_KNOWN |
  1424. QDF_MON_STATUS_USIG_TAIL_KNOWN;
  1425. ppdu_info->rx_status.usig_value |= (0x3F <<
  1426. QDF_MON_STATUS_USIG_DISREGARD_SHIFT);
  1427. ppdu_info->rx_status.usig_value |= (usig_tb->ppdu_type_comp_mode <<
  1428. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT);
  1429. ppdu_info->rx_status.usig_value |= (0x1 <<
  1430. QDF_MON_STATUS_USIG_VALIDATE_SHIFT);
  1431. ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_1 <<
  1432. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_SHIFT);
  1433. ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_2 <<
  1434. QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_SHIFT);
  1435. ppdu_info->rx_status.usig_value |= (0x1F <<
  1436. QDF_MON_STATUS_USIG_TB_DISREGARD1_SHIFT);
  1437. ppdu_info->rx_status.usig_value |= (usig_tb->crc <<
  1438. QDF_MON_STATUS_USIG_CRC_SHIFT);
  1439. ppdu_info->rx_status.usig_value |= (usig_tb->tail <<
  1440. QDF_MON_STATUS_USIG_TAIL_SHIFT);
  1441. ppdu_info->u_sig_info.ppdu_type_comp_mode =
  1442. usig_tb->ppdu_type_comp_mode;
  1443. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1444. }
  1445. static inline uint32_t
  1446. hal_rx_parse_u_sig_mu(struct hal_soc *hal_soc, void *rx_tlv,
  1447. struct hal_rx_ppdu_info *ppdu_info)
  1448. {
  1449. struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv;
  1450. struct hal_mon_usig_mu *usig_mu = &usig->usig_2.mu;
  1451. ppdu_info->rx_status.usig_mask |=
  1452. QDF_MON_STATUS_USIG_DISREGARD_KNOWN |
  1453. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN |
  1454. QDF_MON_STATUS_USIG_VALIDATE_KNOWN |
  1455. QDF_MON_STATUS_USIG_MU_VALIDATE1_KNOWN |
  1456. QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_KNOWN |
  1457. QDF_MON_STATUS_USIG_MU_VALIDATE2_KNOWN |
  1458. QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_KNOWN |
  1459. QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_KNOWN |
  1460. QDF_MON_STATUS_USIG_CRC_KNOWN |
  1461. QDF_MON_STATUS_USIG_TAIL_KNOWN;
  1462. ppdu_info->rx_status.usig_value |= (0x1F <<
  1463. QDF_MON_STATUS_USIG_DISREGARD_SHIFT);
  1464. ppdu_info->rx_status.usig_value |= (0x1 <<
  1465. QDF_MON_STATUS_USIG_MU_VALIDATE1_SHIFT);
  1466. ppdu_info->rx_status.usig_value |= (usig_mu->ppdu_type_comp_mode <<
  1467. QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT);
  1468. ppdu_info->rx_status.usig_value |= (0x1 <<
  1469. QDF_MON_STATUS_USIG_VALIDATE_SHIFT);
  1470. ppdu_info->rx_status.usig_value |= (usig_mu->punc_ch_info <<
  1471. QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_SHIFT);
  1472. ppdu_info->rx_status.usig_value |= (0x1 <<
  1473. QDF_MON_STATUS_USIG_MU_VALIDATE2_SHIFT);
  1474. ppdu_info->rx_status.usig_value |= (usig_mu->eht_sig_mcs <<
  1475. QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_SHIFT);
  1476. ppdu_info->rx_status.usig_value |= (usig_mu->num_eht_sig_sym <<
  1477. QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_SHIFT);
  1478. ppdu_info->rx_status.usig_value |= (usig_mu->crc <<
  1479. QDF_MON_STATUS_USIG_CRC_SHIFT);
  1480. ppdu_info->rx_status.usig_value |= (usig_mu->tail <<
  1481. QDF_MON_STATUS_USIG_TAIL_SHIFT);
  1482. ppdu_info->u_sig_info.ppdu_type_comp_mode =
  1483. usig_mu->ppdu_type_comp_mode;
  1484. ppdu_info->u_sig_info.eht_sig_mcs = usig_mu->eht_sig_mcs;
  1485. ppdu_info->u_sig_info.num_eht_sig_sym = usig_mu->num_eht_sig_sym;
  1486. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1487. }
  1488. static inline uint32_t
  1489. hal_rx_parse_u_sig_hdr(struct hal_soc *hal_soc, void *rx_tlv,
  1490. struct hal_rx_ppdu_info *ppdu_info)
  1491. {
  1492. struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv;
  1493. struct hal_mon_usig_cmn *usig_1 = &usig->usig_1;
  1494. ppdu_info->rx_status.usig_flags = 1;
  1495. hal_rx_parse_u_sig_cmn(hal_soc, rx_tlv, ppdu_info);
  1496. if (HAL_RX_MON_USIG_GET_PPDU_TYPE_N_COMP_MODE(rx_tlv) == 0 &&
  1497. usig_1->ul_dl == 1)
  1498. return hal_rx_parse_u_sig_tb(hal_soc, rx_tlv, ppdu_info);
  1499. else
  1500. return hal_rx_parse_u_sig_mu(hal_soc, rx_tlv, ppdu_info);
  1501. }
  1502. static inline uint32_t
  1503. hal_rx_parse_usig_overflow(struct hal_soc *hal_soc, void *tlv,
  1504. struct hal_rx_ppdu_info *ppdu_info)
  1505. {
  1506. struct hal_eht_sig_cc_usig_overflow *usig_ovflow =
  1507. (struct hal_eht_sig_cc_usig_overflow *)tlv;
  1508. ppdu_info->rx_status.eht_known |=
  1509. QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN |
  1510. QDF_MON_STATUS_EHT_EHT_LTF_KNOWN |
  1511. QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_KNOWN |
  1512. QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_KNOWN |
  1513. QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_KNOWN |
  1514. QDF_MON_STATUS_EHT_DISREARD_KNOWN;
  1515. ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->spatial_reuse <<
  1516. QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT);
  1517. /*
  1518. * GI and LTF size are separately indicated in radiotap header
  1519. * and hence will be parsed from other TLV
  1520. **/
  1521. ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->num_ltf_sym <<
  1522. QDF_MON_STATUS_EHT_EHT_LTF_SHIFT);
  1523. ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->ldpc_extra_sym <<
  1524. QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_SHIFT);
  1525. ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pre_fec_pad_factor <<
  1526. QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_SHIFT);
  1527. ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pe_disambiguity <<
  1528. QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_SHIFT);
  1529. ppdu_info->rx_status.eht_data[0] |= (0xF <<
  1530. QDF_MON_STATUS_EHT_DISREGARD_SHIFT);
  1531. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1532. }
  1533. static inline uint32_t
  1534. hal_rx_parse_non_ofdma_users(struct hal_soc *hal_soc, void *tlv,
  1535. struct hal_rx_ppdu_info *ppdu_info)
  1536. {
  1537. struct hal_eht_sig_non_ofdma_cmn_eb *non_ofdma_cmn_eb =
  1538. (struct hal_eht_sig_non_ofdma_cmn_eb *)tlv;
  1539. ppdu_info->rx_status.eht_known |=
  1540. QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_KNOWN;
  1541. ppdu_info->rx_status.eht_data[4] |= (non_ofdma_cmn_eb->num_users <<
  1542. QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_SHIFT);
  1543. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1544. }
  1545. static inline uint32_t
  1546. hal_rx_parse_ru_allocation(struct hal_soc *hal_soc, void *tlv,
  1547. struct hal_rx_ppdu_info *ppdu_info)
  1548. {
  1549. uint64_t *ehtsig_tlv = (uint64_t *)tlv;
  1550. struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cmn_eb1;
  1551. struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cmn_eb2;
  1552. uint8_t num_ru_allocation_known = 0;
  1553. ofdma_cmn_eb1 = (struct hal_eht_sig_ofdma_cmn_eb1 *)ehtsig_tlv;
  1554. ofdma_cmn_eb2 = (struct hal_eht_sig_ofdma_cmn_eb2 *)(ehtsig_tlv + 1);
  1555. switch (ppdu_info->u_sig_info.bw) {
  1556. case HAL_EHT_BW_320_2:
  1557. case HAL_EHT_BW_320_1:
  1558. num_ru_allocation_known += 4;
  1559. ppdu_info->rx_status.eht_data[3] |=
  1560. (ofdma_cmn_eb2->ru_allocation2_6 <<
  1561. QDF_MON_STATUS_EHT_RU_ALLOCATION2_6_SHIFT);
  1562. ppdu_info->rx_status.eht_data[3] |=
  1563. (ofdma_cmn_eb2->ru_allocation2_5 <<
  1564. QDF_MON_STATUS_EHT_RU_ALLOCATION2_5_SHIFT);
  1565. ppdu_info->rx_status.eht_data[3] |=
  1566. (ofdma_cmn_eb2->ru_allocation2_4 <<
  1567. QDF_MON_STATUS_EHT_RU_ALLOCATION2_4_SHIFT);
  1568. ppdu_info->rx_status.eht_data[2] |=
  1569. (ofdma_cmn_eb2->ru_allocation2_3 <<
  1570. QDF_MON_STATUS_EHT_RU_ALLOCATION2_3_SHIFT);
  1571. fallthrough;
  1572. case HAL_EHT_BW_160:
  1573. num_ru_allocation_known += 2;
  1574. ppdu_info->rx_status.eht_data[2] |=
  1575. (ofdma_cmn_eb2->ru_allocation2_2 <<
  1576. QDF_MON_STATUS_EHT_RU_ALLOCATION2_2_SHIFT);
  1577. ppdu_info->rx_status.eht_data[2] |=
  1578. (ofdma_cmn_eb2->ru_allocation2_1 <<
  1579. QDF_MON_STATUS_EHT_RU_ALLOCATION2_1_SHIFT);
  1580. fallthrough;
  1581. case HAL_EHT_BW_80:
  1582. num_ru_allocation_known += 1;
  1583. ppdu_info->rx_status.eht_data[1] |=
  1584. (ofdma_cmn_eb1->ru_allocation1_2 <<
  1585. QDF_MON_STATUS_EHT_RU_ALLOCATION1_2_SHIFT);
  1586. fallthrough;
  1587. case HAL_EHT_BW_40:
  1588. case HAL_EHT_BW_20:
  1589. num_ru_allocation_known += 1;
  1590. ppdu_info->rx_status.eht_data[1] |=
  1591. (ofdma_cmn_eb1->ru_allocation1_1 <<
  1592. QDF_MON_STATUS_EHT_RU_ALLOCATION1_1_SHIFT);
  1593. break;
  1594. default:
  1595. break;
  1596. }
  1597. ppdu_info->rx_status.eht_known |= (num_ru_allocation_known <<
  1598. QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT);
  1599. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1600. }
  1601. static inline uint32_t
  1602. hal_rx_parse_eht_sig_mumimo_user_info(struct hal_soc *hal_soc, void *tlv,
  1603. struct hal_rx_ppdu_info *ppdu_info)
  1604. {
  1605. struct hal_eht_sig_mu_mimo_user_info *user_info;
  1606. uint32_t user_idx = ppdu_info->rx_status.num_eht_user_info_valid;
  1607. user_info = (struct hal_eht_sig_mu_mimo_user_info *)tlv;
  1608. ppdu_info->rx_status.eht_user_info[user_idx] |=
  1609. QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN |
  1610. QDF_MON_STATUS_EHT_USER_MCS_KNOWN |
  1611. QDF_MON_STATUS_EHT_USER_CODING_KNOWN |
  1612. QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_KNOWN;
  1613. ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->sta_id <<
  1614. QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT);
  1615. ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->mcs <<
  1616. QDF_MON_STATUS_EHT_USER_MCS_SHIFT);
  1617. ppdu_info->rx_status.mcs = user_info->mcs;
  1618. ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->coding <<
  1619. QDF_MON_STATUS_EHT_USER_CODING_SHIFT);
  1620. ppdu_info->rx_status.eht_user_info[user_idx] |=
  1621. (user_info->spatial_coding <<
  1622. QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_SHIFT);
  1623. /* CRC for matched user block */
  1624. ppdu_info->rx_status.eht_known |=
  1625. QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN |
  1626. QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN;
  1627. ppdu_info->rx_status.eht_data[4] |= (user_info->crc <<
  1628. QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT);
  1629. ppdu_info->rx_status.num_eht_user_info_valid++;
  1630. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1631. }
  1632. static inline uint32_t
  1633. hal_rx_parse_eht_sig_non_mumimo_user_info(struct hal_soc *hal_soc, void *tlv,
  1634. struct hal_rx_ppdu_info *ppdu_info)
  1635. {
  1636. struct hal_eht_sig_non_mu_mimo_user_info *user_info;
  1637. uint32_t user_idx = ppdu_info->rx_status.num_eht_user_info_valid;
  1638. user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tlv;
  1639. ppdu_info->rx_status.eht_user_info[user_idx] |=
  1640. QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN |
  1641. QDF_MON_STATUS_EHT_USER_MCS_KNOWN |
  1642. QDF_MON_STATUS_EHT_USER_CODING_KNOWN |
  1643. QDF_MON_STATUS_EHT_USER_NSS_KNOWN |
  1644. QDF_MON_STATUS_EHT_USER_BEAMFORMING_KNOWN;
  1645. ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->sta_id <<
  1646. QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT);
  1647. ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->mcs <<
  1648. QDF_MON_STATUS_EHT_USER_MCS_SHIFT);
  1649. ppdu_info->rx_status.mcs = user_info->mcs;
  1650. ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->nss <<
  1651. QDF_MON_STATUS_EHT_USER_NSS_SHIFT);
  1652. ppdu_info->rx_status.nss = user_info->nss + 1;
  1653. ppdu_info->rx_status.eht_user_info[user_idx] |=
  1654. (user_info->beamformed <<
  1655. QDF_MON_STATUS_EHT_USER_BEAMFORMING_SHIFT);
  1656. ppdu_info->rx_status.eht_user_info[user_idx] |= (user_info->coding <<
  1657. QDF_MON_STATUS_EHT_USER_CODING_SHIFT);
  1658. /* CRC for matched user block */
  1659. ppdu_info->rx_status.eht_known |=
  1660. QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN |
  1661. QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN;
  1662. ppdu_info->rx_status.eht_data[4] |= (user_info->crc <<
  1663. QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT);
  1664. ppdu_info->rx_status.num_eht_user_info_valid++;
  1665. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1666. }
  1667. static inline bool hal_rx_is_ofdma(struct hal_soc *hal_soc,
  1668. struct hal_rx_ppdu_info *ppdu_info)
  1669. {
  1670. if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 0 &&
  1671. ppdu_info->u_sig_info.ul_dl == 0)
  1672. return true;
  1673. return false;
  1674. }
  1675. static inline bool hal_rx_is_non_ofdma(struct hal_soc *hal_soc,
  1676. struct hal_rx_ppdu_info *ppdu_info)
  1677. {
  1678. uint32_t ppdu_type_comp_mode =
  1679. ppdu_info->u_sig_info.ppdu_type_comp_mode;
  1680. uint32_t ul_dl = ppdu_info->u_sig_info.ul_dl;
  1681. if ((ppdu_type_comp_mode == 1 && ul_dl == 0) ||
  1682. (ppdu_type_comp_mode == 2 && ul_dl == 0) ||
  1683. (ppdu_type_comp_mode == 1 && ul_dl == 1))
  1684. return true;
  1685. return false;
  1686. }
  1687. static inline bool hal_rx_is_mu_mimo_user(struct hal_soc *hal_soc,
  1688. struct hal_rx_ppdu_info *ppdu_info)
  1689. {
  1690. if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 2 &&
  1691. ppdu_info->u_sig_info.ul_dl == 0)
  1692. return true;
  1693. return false;
  1694. }
  1695. static inline bool
  1696. hal_rx_is_frame_type_ndp(struct hal_soc *hal_soc,
  1697. struct hal_rx_ppdu_info *ppdu_info)
  1698. {
  1699. if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 1 &&
  1700. ppdu_info->u_sig_info.eht_sig_mcs == 0 &&
  1701. ppdu_info->u_sig_info.num_eht_sig_sym == 0)
  1702. return true;
  1703. return false;
  1704. }
  1705. static inline uint32_t
  1706. hal_rx_parse_eht_sig_ndp(struct hal_soc *hal_soc, void *tlv,
  1707. struct hal_rx_ppdu_info *ppdu_info)
  1708. {
  1709. struct hal_eht_sig_ndp_cmn_eb *eht_sig_ndp =
  1710. (struct hal_eht_sig_ndp_cmn_eb *)tlv;
  1711. ppdu_info->rx_status.eht_known |=
  1712. QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN |
  1713. QDF_MON_STATUS_EHT_EHT_LTF_KNOWN |
  1714. QDF_MON_STATUS_EHT_NDP_NSS_KNOWN |
  1715. QDF_MON_STATUS_EHT_NDP_BEAMFORMED_KNOWN |
  1716. QDF_MON_STATUS_EHT_NDP_DISREGARD_KNOWN |
  1717. QDF_MON_STATUS_EHT_CRC1_KNOWN |
  1718. QDF_MON_STATUS_EHT_TAIL1_KNOWN;
  1719. ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->spatial_reuse <<
  1720. QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT);
  1721. /*
  1722. * GI and LTF size are separately indicated in radiotap header
  1723. * and hence will be parsed from other TLV
  1724. **/
  1725. ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->num_ltf_sym <<
  1726. QDF_MON_STATUS_EHT_EHT_LTF_SHIFT);
  1727. ppdu_info->rx_status.eht_data[0] |= (0xF <<
  1728. QDF_MON_STATUS_EHT_NDP_DISREGARD_SHIFT);
  1729. ppdu_info->rx_status.eht_data[4] |= (eht_sig_ndp->nss <<
  1730. QDF_MON_STATUS_EHT_NDP_NSS_SHIFT);
  1731. ppdu_info->rx_status.eht_data[4] |= (eht_sig_ndp->beamformed <<
  1732. QDF_MON_STATUS_EHT_NDP_BEAMFORMED_SHIFT);
  1733. ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->crc <<
  1734. QDF_MON_STATUS_EHT_CRC1_SHIFT);
  1735. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1736. }
  1737. static inline uint32_t
  1738. hal_rx_parse_eht_sig_non_ofdma(struct hal_soc *hal_soc, void *tlv,
  1739. struct hal_rx_ppdu_info *ppdu_info)
  1740. {
  1741. void *user_info = (void *)((uint8_t *)tlv + 4);
  1742. hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info);
  1743. hal_rx_parse_non_ofdma_users(hal_soc, tlv, ppdu_info);
  1744. if (hal_rx_is_mu_mimo_user(hal_soc, ppdu_info))
  1745. hal_rx_parse_eht_sig_mumimo_user_info(hal_soc, user_info,
  1746. ppdu_info);
  1747. else
  1748. hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, user_info,
  1749. ppdu_info);
  1750. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1751. }
  1752. static inline uint32_t
  1753. hal_rx_parse_eht_sig_ofdma(struct hal_soc *hal_soc, void *tlv,
  1754. struct hal_rx_ppdu_info *ppdu_info)
  1755. {
  1756. uint64_t *eht_sig_tlv = (uint64_t *)tlv;
  1757. void *user_info = (void *)(eht_sig_tlv + 2);
  1758. hal_rx_parse_usig_overflow(hal_soc, tlv, ppdu_info);
  1759. hal_rx_parse_ru_allocation(hal_soc, tlv, ppdu_info);
  1760. hal_rx_parse_eht_sig_non_mumimo_user_info(hal_soc, user_info,
  1761. ppdu_info);
  1762. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1763. }
  1764. static inline uint32_t
  1765. hal_rx_parse_eht_sig_hdr(struct hal_soc *hal_soc, uint8_t *tlv,
  1766. struct hal_rx_ppdu_info *ppdu_info)
  1767. {
  1768. ppdu_info->rx_status.eht_flags = 1;
  1769. if (hal_rx_is_frame_type_ndp(hal_soc, ppdu_info))
  1770. hal_rx_parse_eht_sig_ndp(hal_soc, tlv, ppdu_info);
  1771. else if (hal_rx_is_non_ofdma(hal_soc, ppdu_info))
  1772. hal_rx_parse_eht_sig_non_ofdma(hal_soc, tlv, ppdu_info);
  1773. else if (hal_rx_is_ofdma(hal_soc, ppdu_info))
  1774. hal_rx_parse_eht_sig_ofdma(hal_soc, tlv, ppdu_info);
  1775. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1776. }
  1777. #ifdef WLAN_FEATURE_11BE
  1778. static inline void
  1779. hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info,
  1780. struct hal_rx_ppdu_info *ppdu_info)
  1781. {
  1782. ppdu_info->rx_status.punctured_pattern = cmn_usr_info->puncture_bitmap;
  1783. }
  1784. #else
  1785. static inline void
  1786. hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info,
  1787. struct hal_rx_ppdu_info *ppdu_info)
  1788. {
  1789. }
  1790. #endif
  1791. static inline uint32_t
  1792. hal_rx_parse_cmn_usr_info(struct hal_soc *hal_soc, uint8_t *tlv,
  1793. struct hal_rx_ppdu_info *ppdu_info)
  1794. {
  1795. struct phyrx_common_user_info *cmn_usr_info =
  1796. (struct phyrx_common_user_info *)tlv;
  1797. ppdu_info->rx_status.eht_known |=
  1798. QDF_MON_STATUS_EHT_GUARD_INTERVAL_KNOWN |
  1799. QDF_MON_STATUS_EHT_LTF_KNOWN;
  1800. ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->cp_setting <<
  1801. QDF_MON_STATUS_EHT_GI_SHIFT);
  1802. if (!ppdu_info->rx_status.sgi)
  1803. ppdu_info->rx_status.sgi = cmn_usr_info->cp_setting;
  1804. ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->ltf_size <<
  1805. QDF_MON_STATUS_EHT_LTF_SHIFT);
  1806. if (!ppdu_info->rx_status.ltf_size)
  1807. ppdu_info->rx_status.ltf_size = cmn_usr_info->ltf_size;
  1808. hal_rx_parse_punctured_pattern(cmn_usr_info, ppdu_info);
  1809. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1810. }
  1811. #ifdef WLAN_FEATURE_11BE
  1812. static inline void
  1813. hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size,
  1814. uint32_t *ru_width)
  1815. {
  1816. uint32_t width;
  1817. width = 0;
  1818. switch (ru_size) {
  1819. case IEEE80211_EHT_RU_26:
  1820. width = RU_26;
  1821. break;
  1822. case IEEE80211_EHT_RU_52:
  1823. width = RU_52;
  1824. break;
  1825. case IEEE80211_EHT_RU_52_26:
  1826. width = RU_52_26;
  1827. break;
  1828. case IEEE80211_EHT_RU_106:
  1829. width = RU_106;
  1830. break;
  1831. case IEEE80211_EHT_RU_106_26:
  1832. width = RU_106_26;
  1833. break;
  1834. case IEEE80211_EHT_RU_242:
  1835. width = RU_242;
  1836. break;
  1837. case IEEE80211_EHT_RU_484:
  1838. width = RU_484;
  1839. break;
  1840. case IEEE80211_EHT_RU_484_242:
  1841. width = RU_484_242;
  1842. break;
  1843. case IEEE80211_EHT_RU_996:
  1844. width = RU_996;
  1845. break;
  1846. case IEEE80211_EHT_RU_996_484:
  1847. width = RU_996_484;
  1848. break;
  1849. case IEEE80211_EHT_RU_996_484_242:
  1850. width = RU_996_484_242;
  1851. break;
  1852. case IEEE80211_EHT_RU_996x2:
  1853. width = RU_2X996;
  1854. break;
  1855. case IEEE80211_EHT_RU_996x2_484:
  1856. width = RU_2X996_484;
  1857. break;
  1858. case IEEE80211_EHT_RU_996x3:
  1859. width = RU_3X996;
  1860. break;
  1861. case IEEE80211_EHT_RU_996x3_484:
  1862. width = RU_3X996_484;
  1863. break;
  1864. case IEEE80211_EHT_RU_996x4:
  1865. width = RU_4X996;
  1866. break;
  1867. default:
  1868. hal_err_rl("RU size(%d) to width convert err", ru_size);
  1869. break;
  1870. }
  1871. *ru_width = width;
  1872. }
  1873. #else
  1874. static inline void
  1875. hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size,
  1876. uint32_t *ru_width)
  1877. {
  1878. *ru_width = 0;
  1879. }
  1880. #endif
  1881. static inline enum ieee80211_eht_ru_size
  1882. hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(struct hal_soc *hal_soc,
  1883. uint32_t hal_ru_size)
  1884. {
  1885. switch (hal_ru_size) {
  1886. case HAL_EHT_RU_26:
  1887. return IEEE80211_EHT_RU_26;
  1888. case HAL_EHT_RU_52:
  1889. return IEEE80211_EHT_RU_52;
  1890. case HAL_EHT_RU_78:
  1891. return IEEE80211_EHT_RU_52_26;
  1892. case HAL_EHT_RU_106:
  1893. return IEEE80211_EHT_RU_106;
  1894. case HAL_EHT_RU_132:
  1895. return IEEE80211_EHT_RU_106_26;
  1896. case HAL_EHT_RU_242:
  1897. return IEEE80211_EHT_RU_242;
  1898. case HAL_EHT_RU_484:
  1899. return IEEE80211_EHT_RU_484;
  1900. case HAL_EHT_RU_726:
  1901. return IEEE80211_EHT_RU_484_242;
  1902. case HAL_EHT_RU_996:
  1903. return IEEE80211_EHT_RU_996;
  1904. case HAL_EHT_RU_996x2:
  1905. return IEEE80211_EHT_RU_996x2;
  1906. case HAL_EHT_RU_996x3:
  1907. return IEEE80211_EHT_RU_996x3;
  1908. case HAL_EHT_RU_996x4:
  1909. return IEEE80211_EHT_RU_996x4;
  1910. case HAL_EHT_RU_NONE:
  1911. return IEEE80211_EHT_RU_INVALID;
  1912. case HAL_EHT_RU_996_484:
  1913. return IEEE80211_EHT_RU_996_484;
  1914. case HAL_EHT_RU_996x2_484:
  1915. return IEEE80211_EHT_RU_996x2_484;
  1916. case HAL_EHT_RU_996x3_484:
  1917. return IEEE80211_EHT_RU_996x3_484;
  1918. case HAL_EHT_RU_996_484_242:
  1919. return IEEE80211_EHT_RU_996_484_242;
  1920. default:
  1921. return IEEE80211_EHT_RU_INVALID;
  1922. }
  1923. }
  1924. #define HAL_SET_RU_PER80(ru_320mhz, ru_per80, ru_idx_per80mhz, num_80mhz) \
  1925. ((ru_320mhz) |= ((uint64_t)(ru_per80) << \
  1926. (((num_80mhz) * NUM_RU_BITS_PER80) + \
  1927. ((ru_idx_per80mhz) * NUM_RU_BITS_PER20))))
  1928. static inline uint32_t
  1929. hal_rx_parse_receive_user_info(struct hal_soc *hal_soc, uint8_t *tlv,
  1930. struct hal_rx_ppdu_info *ppdu_info,
  1931. uint32_t user_id)
  1932. {
  1933. struct receive_user_info *rx_usr_info = (struct receive_user_info *)tlv;
  1934. struct mon_rx_user_status *mon_rx_user_status = NULL;
  1935. uint64_t ru_index_320mhz = 0;
  1936. uint16_t ru_index_per80mhz;
  1937. uint32_t ru_size = 0, num_80mhz_with_ru = 0;
  1938. uint32_t ru_index = HAL_EHT_RU_INVALID;
  1939. uint32_t rtap_ru_size = IEEE80211_EHT_RU_INVALID;
  1940. uint32_t ru_width;
  1941. ppdu_info->rx_status.eht_known |=
  1942. QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_KNOWN;
  1943. ppdu_info->rx_status.eht_data[0] |=
  1944. (rx_usr_info->dl_ofdma_content_channel <<
  1945. QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_SHIFT);
  1946. switch (rx_usr_info->reception_type) {
  1947. case HAL_RECEPTION_TYPE_SU:
  1948. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  1949. break;
  1950. case HAL_RECEPTION_TYPE_DL_MU_MIMO:
  1951. ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL;
  1952. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1953. break;
  1954. case HAL_RECEPTION_TYPE_UL_MU_MIMO:
  1955. ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL;
  1956. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1957. break;
  1958. case HAL_RECEPTION_TYPE_DL_MU_OFMA:
  1959. ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL;
  1960. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA;
  1961. break;
  1962. case HAL_RECEPTION_TYPE_UL_MU_OFDMA:
  1963. ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL;
  1964. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA;
  1965. break;
  1966. case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO:
  1967. ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL;
  1968. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA_MIMO;
  1969. break;
  1970. case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO:
  1971. ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL;
  1972. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA_MIMO;
  1973. break;
  1974. }
  1975. ppdu_info->start_user_info_cnt++;
  1976. ppdu_info->rx_status.is_stbc = rx_usr_info->stbc;
  1977. ppdu_info->rx_status.ldpc = rx_usr_info->ldpc;
  1978. ppdu_info->rx_status.dcm = rx_usr_info->sta_dcm;
  1979. ppdu_info->rx_status.mcs = rx_usr_info->rate_mcs;
  1980. ppdu_info->rx_status.nss = rx_usr_info->nss + 1;
  1981. if (user_id < HAL_MAX_UL_MU_USERS) {
  1982. mon_rx_user_status =
  1983. &ppdu_info->rx_user_status[user_id];
  1984. mon_rx_user_status->mcs = ppdu_info->rx_status.mcs;
  1985. mon_rx_user_status->nss = ppdu_info->rx_status.nss;
  1986. }
  1987. if (!(ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_MIMO ||
  1988. ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA ||
  1989. ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA_MIMO))
  1990. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1991. /* RU allocation present only for OFDMA reception */
  1992. if (rx_usr_info->ru_type_80_0 != HAL_EHT_RU_NONE) {
  1993. ru_size += rx_usr_info->ru_type_80_0;
  1994. ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_0;
  1995. HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_0,
  1996. ru_index_per80mhz, 0);
  1997. num_80mhz_with_ru++;
  1998. }
  1999. if (rx_usr_info->ru_type_80_1 != HAL_EHT_RU_NONE) {
  2000. ru_size += rx_usr_info->ru_type_80_1;
  2001. ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_1;
  2002. HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_1,
  2003. ru_index_per80mhz, 1);
  2004. num_80mhz_with_ru++;
  2005. }
  2006. if (rx_usr_info->ru_type_80_2 != HAL_EHT_RU_NONE) {
  2007. ru_size += rx_usr_info->ru_type_80_2;
  2008. ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_2;
  2009. HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_2,
  2010. ru_index_per80mhz, 2);
  2011. num_80mhz_with_ru++;
  2012. }
  2013. if (rx_usr_info->ru_type_80_3 != HAL_EHT_RU_NONE) {
  2014. ru_size += rx_usr_info->ru_type_80_3;
  2015. ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_3;
  2016. HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_3,
  2017. ru_index_per80mhz, 3);
  2018. num_80mhz_with_ru++;
  2019. }
  2020. if (num_80mhz_with_ru > 1) {
  2021. /* Calculate the MRU index */
  2022. switch (ru_index_320mhz) {
  2023. case HAL_EHT_RU_996_484_0:
  2024. case HAL_EHT_RU_996x2_484_0:
  2025. case HAL_EHT_RU_996x3_484_0:
  2026. ru_index = 0;
  2027. break;
  2028. case HAL_EHT_RU_996_484_1:
  2029. case HAL_EHT_RU_996x2_484_1:
  2030. case HAL_EHT_RU_996x3_484_1:
  2031. ru_index = 1;
  2032. break;
  2033. case HAL_EHT_RU_996_484_2:
  2034. case HAL_EHT_RU_996x2_484_2:
  2035. case HAL_EHT_RU_996x3_484_2:
  2036. ru_index = 2;
  2037. break;
  2038. case HAL_EHT_RU_996_484_3:
  2039. case HAL_EHT_RU_996x2_484_3:
  2040. case HAL_EHT_RU_996x3_484_3:
  2041. ru_index = 3;
  2042. break;
  2043. case HAL_EHT_RU_996_484_4:
  2044. case HAL_EHT_RU_996x2_484_4:
  2045. case HAL_EHT_RU_996x3_484_4:
  2046. ru_index = 4;
  2047. break;
  2048. case HAL_EHT_RU_996_484_5:
  2049. case HAL_EHT_RU_996x2_484_5:
  2050. case HAL_EHT_RU_996x3_484_5:
  2051. ru_index = 5;
  2052. break;
  2053. case HAL_EHT_RU_996_484_6:
  2054. case HAL_EHT_RU_996x2_484_6:
  2055. case HAL_EHT_RU_996x3_484_6:
  2056. ru_index = 6;
  2057. break;
  2058. case HAL_EHT_RU_996_484_7:
  2059. case HAL_EHT_RU_996x2_484_7:
  2060. case HAL_EHT_RU_996x3_484_7:
  2061. ru_index = 7;
  2062. break;
  2063. case HAL_EHT_RU_996x2_484_8:
  2064. ru_index = 8;
  2065. break;
  2066. case HAL_EHT_RU_996x2_484_9:
  2067. ru_index = 9;
  2068. break;
  2069. case HAL_EHT_RU_996x2_484_10:
  2070. ru_index = 10;
  2071. break;
  2072. case HAL_EHT_RU_996x2_484_11:
  2073. ru_index = 11;
  2074. break;
  2075. default:
  2076. ru_index = HAL_EHT_RU_INVALID;
  2077. dp_debug("Invalid RU index");
  2078. qdf_assert(0);
  2079. break;
  2080. }
  2081. ru_size += 4;
  2082. }
  2083. rtap_ru_size = hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(hal_soc,
  2084. ru_size);
  2085. if (rtap_ru_size != IEEE80211_EHT_RU_INVALID) {
  2086. ppdu_info->rx_status.eht_known |=
  2087. QDF_MON_STATUS_EHT_RU_MRU_SIZE_KNOWN;
  2088. ppdu_info->rx_status.eht_data[1] |= (rtap_ru_size <<
  2089. QDF_MON_STATUS_EHT_RU_MRU_SIZE_SHIFT);
  2090. }
  2091. if (ru_index != HAL_EHT_RU_INVALID) {
  2092. ppdu_info->rx_status.eht_known |=
  2093. QDF_MON_STATUS_EHT_RU_MRU_INDEX_KNOWN;
  2094. ppdu_info->rx_status.eht_data[1] |= (ru_index <<
  2095. QDF_MON_STATUS_EHT_RU_MRU_INDEX_SHIFT);
  2096. }
  2097. if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID &&
  2098. rtap_ru_size != IEEE80211_EHT_RU_INVALID) {
  2099. mon_rx_user_status->ofdma_ru_start_index = ru_index;
  2100. mon_rx_user_status->ofdma_ru_size = rtap_ru_size;
  2101. hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size, &ru_width);
  2102. mon_rx_user_status->ofdma_ru_width = ru_width;
  2103. mon_rx_user_status->mu_ul_info_valid = 1;
  2104. }
  2105. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  2106. }
  2107. #ifdef QCA_MONITOR_2_0_SUPPORT
  2108. static inline void
  2109. hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info,
  2110. hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user)
  2111. {
  2112. ppdu_info->rx_status.mpdu_retry_cnt =
  2113. rx_ppdu_end_user->retried_mpdu_count;
  2114. }
  2115. static inline void
  2116. hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv,
  2117. struct hal_rx_ppdu_info *ppdu_info)
  2118. {
  2119. struct mon_buffer_addr *addr = (struct mon_buffer_addr *)rx_tlv;
  2120. ppdu_info->packet_info.sw_cookie = (((uint64_t)qdf_le32_to_cpu(addr->buffer_virt_addr_63_32) << 32) |
  2121. qdf_le32_to_cpu(addr->buffer_virt_addr_31_0));
  2122. /* HW DMA length is '-1' of actual DMA length*/
  2123. ppdu_info->packet_info.dma_length = addr->dma_length + 1;
  2124. ppdu_info->packet_info.msdu_continuation = addr->msdu_continuation;
  2125. ppdu_info->packet_info.truncated = addr->truncated;
  2126. }
  2127. static inline void
  2128. hal_rx_update_ppdu_drop_cnt(uint8_t *rx_tlv,
  2129. struct hal_rx_ppdu_info *ppdu_info)
  2130. {
  2131. struct mon_drop *drop_cnt = (struct mon_drop *)rx_tlv;
  2132. ppdu_info->drop_cnt.ppdu_drop_cnt = drop_cnt->ppdu_drop_cnt;
  2133. ppdu_info->drop_cnt.mpdu_drop_cnt = drop_cnt->mpdu_drop_cnt;
  2134. ppdu_info->drop_cnt.end_of_ppdu_drop_cnt = drop_cnt->end_of_ppdu_seen;
  2135. ppdu_info->drop_cnt.tlv_drop_cnt = drop_cnt->tlv_drop_cnt;
  2136. }
  2137. #else
  2138. static inline void
  2139. hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info,
  2140. hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user)
  2141. {
  2142. ppdu_info->rx_status.mpdu_retry_cnt = 0;
  2143. }
  2144. static inline void
  2145. hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv,
  2146. struct hal_rx_ppdu_info *ppdu_info)
  2147. {
  2148. }
  2149. static inline void
  2150. hal_rx_update_ppdu_drop_cnt(uint8_t *rx_tlv,
  2151. struct hal_rx_ppdu_info *ppdu_info)
  2152. {
  2153. }
  2154. #endif
  2155. #ifdef WLAN_SUPPORT_CTRL_FRAME_STATS
  2156. static inline void
  2157. hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info,
  2158. uint32_t user_id)
  2159. {
  2160. uint16_t fc = ppdu_info->nac_info.frame_control;
  2161. if (HAL_RX_GET_FRAME_CTRL_TYPE(fc) == HAL_RX_FRAME_CTRL_TYPE_CTRL) {
  2162. if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) ==
  2163. QDF_IEEE80211_FC0_SUBTYPE_VHT_NDP_AN)
  2164. ppdu_info->ctrl_frm_info[user_id].ndpa = 1;
  2165. if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) ==
  2166. QDF_IEEE80211_FC0_SUBTYPE_BAR)
  2167. ppdu_info->ctrl_frm_info[user_id].bar = 1;
  2168. }
  2169. }
  2170. #else
  2171. static inline void
  2172. hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info,
  2173. uint32_t user_id)
  2174. {
  2175. }
  2176. #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */
  2177. #ifdef MONITOR_TLV_RECORDING_ENABLE
  2178. /**
  2179. * hal_rx_record_tlv_info() - Record received TLV info
  2180. * @ppdu_info: pointer to ppdu_info
  2181. * @tlv_tag: TLV tag of the TLV to record
  2182. *
  2183. * Return
  2184. */
  2185. static inline void
  2186. hal_rx_record_tlv_info(struct hal_rx_ppdu_info *ppdu_info, uint32_t tlv_tag) {
  2187. ppdu_info->rx_tlv_info.tlv_tag = tlv_tag;
  2188. switch (tlv_tag) {
  2189. case WIFIRX_PPDU_START_E:
  2190. case WIFIRX_PPDU_START_USER_INFO_E:
  2191. ppdu_info->rx_tlv_info.tlv_category = CATEGORY_PPDU_START;
  2192. break;
  2193. case WIFIRX_HEADER_E:
  2194. case WIFIRX_MPDU_START_E:
  2195. case WIFIMON_BUFFER_ADDR_E:
  2196. case WIFIRX_MSDU_END_E:
  2197. case WIFIRX_MPDU_END_E:
  2198. ppdu_info->rx_tlv_info.tlv_category = CATEGORY_MPDU;
  2199. break;
  2200. case WIFIRX_USER_PPDU_END_E:
  2201. case WIFIRX_PPDU_END_E:
  2202. case WIFIPHYRX_RSSI_LEGACY_E:
  2203. case WIFIPHYRX_L_SIG_B_E:
  2204. case WIFIPHYRX_COMMON_USER_INFO_E:
  2205. case WIFIPHYRX_DATA_DONE_E:
  2206. case WIFIPHYRX_PKT_END_PART1_E:
  2207. case WIFIPHYRX_PKT_END_E:
  2208. case WIFIRXPCU_PPDU_END_INFO_E:
  2209. case WIFIRX_PPDU_END_USER_STATS_E:
  2210. case WIFIRX_PPDU_END_STATUS_DONE_E:
  2211. ppdu_info->rx_tlv_info.tlv_category = CATEGORY_PPDU_END;
  2212. break;
  2213. }
  2214. }
  2215. #else
  2216. static inline void
  2217. hal_rx_record_tlv_info(struct hal_rx_ppdu_info *ppdu_info, uint32_t tlv_tag) {
  2218. }
  2219. #endif
  2220. /**
  2221. * hal_rx_status_get_tlv_info_generic_be() - process receive info TLV
  2222. * @rx_tlv_hdr: pointer to TLV header
  2223. * @ppduinfo: pointer to ppdu_info
  2224. * @hal_soc_hdl: HAL version of the SOC pointer
  2225. * @nbuf: Network buffer
  2226. *
  2227. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  2228. */
  2229. static inline uint32_t
  2230. hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo,
  2231. hal_soc_handle_t hal_soc_hdl,
  2232. qdf_nbuf_t nbuf)
  2233. {
  2234. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2235. uint32_t tlv_tag, user_id, tlv_len, value;
  2236. uint8_t group_id = 0;
  2237. uint8_t he_dcm = 0;
  2238. uint8_t he_stbc = 0;
  2239. uint16_t he_gi = 0;
  2240. uint16_t he_ltf = 0;
  2241. void *rx_tlv;
  2242. struct mon_rx_user_status *mon_rx_user_status;
  2243. struct hal_rx_ppdu_info *ppdu_info =
  2244. (struct hal_rx_ppdu_info *)ppduinfo;
  2245. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr);
  2246. user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr);
  2247. tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr);
  2248. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  2249. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2250. rx_tlv, tlv_len);
  2251. ppdu_info->user_id = user_id;
  2252. switch (tlv_tag) {
  2253. case WIFIRX_PPDU_START_E:
  2254. {
  2255. if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id ==
  2256. HAL_RX_GET_64(rx_tlv, RX_PPDU_START, PHY_PPDU_ID)))
  2257. hal_err("Matching ppdu_id(%u) detected",
  2258. ppdu_info->com_info.last_ppdu_id);
  2259. /* Reset ppdu_info before processing the ppdu */
  2260. qdf_mem_zero(ppdu_info,
  2261. sizeof(struct hal_rx_ppdu_info));
  2262. ppdu_info->com_info.last_ppdu_id =
  2263. ppdu_info->com_info.ppdu_id =
  2264. HAL_RX_GET_64(rx_tlv, RX_PPDU_START,
  2265. PHY_PPDU_ID);
  2266. /* channel number is set in PHY meta data */
  2267. ppdu_info->rx_status.chan_num =
  2268. (HAL_RX_GET_64(rx_tlv, RX_PPDU_START,
  2269. SW_PHY_META_DATA) & 0x0000FFFF);
  2270. ppdu_info->rx_status.chan_freq =
  2271. (HAL_RX_GET_64(rx_tlv, RX_PPDU_START,
  2272. SW_PHY_META_DATA) & 0xFFFF0000) >> 16;
  2273. if (ppdu_info->rx_status.chan_num &&
  2274. ppdu_info->rx_status.chan_freq) {
  2275. ppdu_info->rx_status.chan_freq =
  2276. hal_rx_radiotap_num_to_freq(
  2277. ppdu_info->rx_status.chan_num,
  2278. ppdu_info->rx_status.chan_freq);
  2279. }
  2280. ppdu_info->com_info.ppdu_timestamp =
  2281. HAL_RX_GET_64(rx_tlv, RX_PPDU_START,
  2282. PPDU_START_TIMESTAMP_31_0);
  2283. ppdu_info->rx_status.ppdu_timestamp =
  2284. ppdu_info->com_info.ppdu_timestamp;
  2285. ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
  2286. break;
  2287. }
  2288. case WIFIRX_PPDU_START_USER_INFO_E:
  2289. hal_rx_parse_receive_user_info(hal, rx_tlv, ppdu_info, user_id);
  2290. break;
  2291. case WIFIRX_PPDU_END_E:
  2292. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2293. "[%s][%d] ppdu_end_e len=%d",
  2294. __func__, __LINE__, tlv_len);
  2295. /* This is followed by sub-TLVs of PPDU_END */
  2296. ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
  2297. break;
  2298. case WIFIPHYRX_LOCATION_E:
  2299. hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info);
  2300. break;
  2301. case WIFIRXPCU_PPDU_END_INFO_E:
  2302. ppdu_info->rx_status.rx_antenna =
  2303. HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, RX_ANTENNA);
  2304. ppdu_info->rx_status.tsft =
  2305. HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO,
  2306. WB_TIMESTAMP_UPPER_32);
  2307. ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
  2308. HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO,
  2309. WB_TIMESTAMP_LOWER_32);
  2310. ppdu_info->rx_status.duration =
  2311. HAL_RX_GET_64(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8,
  2312. RX_PPDU_DURATION);
  2313. hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info);
  2314. break;
  2315. /*
  2316. * WIFIRX_PPDU_END_USER_STATS_E comes for each user received.
  2317. * for MU, based on num users we see this tlv that many times.
  2318. */
  2319. case WIFIRX_PPDU_END_USER_STATS_E:
  2320. {
  2321. hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user = rx_tlv;
  2322. unsigned long tid = 0;
  2323. uint16_t seq = 0;
  2324. ppdu_info->rx_status.ast_index =
  2325. rx_ppdu_end_user->ast_index;
  2326. tid = rx_ppdu_end_user->received_qos_data_tid_bitmap;
  2327. ppdu_info->rx_status.tid = qdf_find_first_bit(&tid,
  2328. sizeof(tid) * 8);
  2329. if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
  2330. ppdu_info->rx_status.tid = HAL_TID_INVALID;
  2331. ppdu_info->rx_status.tcp_msdu_count =
  2332. rx_ppdu_end_user->tcp_msdu_count +
  2333. rx_ppdu_end_user->tcp_ack_msdu_count;
  2334. ppdu_info->rx_status.udp_msdu_count =
  2335. rx_ppdu_end_user->udp_msdu_count;
  2336. ppdu_info->rx_status.other_msdu_count =
  2337. rx_ppdu_end_user->other_msdu_count;
  2338. hal_rx_status_get_mpdu_retry_cnt(ppdu_info, rx_ppdu_end_user);
  2339. if (ppdu_info->sw_frame_group_id
  2340. != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  2341. ppdu_info->rx_status.frame_control_info_valid =
  2342. rx_ppdu_end_user->frame_control_info_valid;
  2343. if (ppdu_info->rx_status.frame_control_info_valid)
  2344. ppdu_info->rx_status.frame_control =
  2345. rx_ppdu_end_user->frame_control_field;
  2346. hal_get_qos_control(rx_ppdu_end_user, ppdu_info);
  2347. }
  2348. ppdu_info->rx_status.data_sequence_control_info_valid =
  2349. rx_ppdu_end_user->data_sequence_control_info_valid;
  2350. seq = rx_ppdu_end_user->first_data_seq_ctrl;
  2351. if (ppdu_info->rx_status.data_sequence_control_info_valid)
  2352. ppdu_info->rx_status.first_data_seq_ctrl = seq;
  2353. ppdu_info->rx_status.preamble_type =
  2354. rx_ppdu_end_user->ht_control_field_pkt_type;
  2355. ppdu_info->end_user_stats_cnt++;
  2356. switch (ppdu_info->rx_status.preamble_type) {
  2357. case HAL_RX_PKT_TYPE_11N:
  2358. ppdu_info->rx_status.ht_flags = 1;
  2359. ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
  2360. break;
  2361. case HAL_RX_PKT_TYPE_11AC:
  2362. ppdu_info->rx_status.vht_flags = 1;
  2363. break;
  2364. case HAL_RX_PKT_TYPE_11AX:
  2365. ppdu_info->rx_status.he_flags = 1;
  2366. break;
  2367. default:
  2368. break;
  2369. }
  2370. ppdu_info->com_info.mpdu_cnt_fcs_ok =
  2371. rx_ppdu_end_user->mpdu_cnt_fcs_ok;
  2372. ppdu_info->com_info.mpdu_cnt_fcs_err =
  2373. rx_ppdu_end_user->mpdu_cnt_fcs_err;
  2374. if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
  2375. ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
  2376. ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
  2377. else
  2378. ppdu_info->rx_status.rs_flags &=
  2379. (~IEEE80211_AMPDU_FLAG);
  2380. ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] =
  2381. rx_ppdu_end_user->fcs_ok_bitmap_31_0;
  2382. ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] =
  2383. rx_ppdu_end_user->fcs_ok_bitmap_63_32;
  2384. if (user_id < HAL_MAX_UL_MU_USERS) {
  2385. mon_rx_user_status =
  2386. &ppdu_info->rx_user_status[user_id];
  2387. hal_rx_handle_mu_ul_info(rx_ppdu_end_user,
  2388. mon_rx_user_status);
  2389. ppdu_info->com_info.num_users++;
  2390. hal_rx_populate_mu_user_info(rx_ppdu_end_user, ppdu_info,
  2391. user_id,
  2392. mon_rx_user_status);
  2393. }
  2394. break;
  2395. }
  2396. case WIFIRX_PPDU_END_USER_STATS_EXT_E:
  2397. ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] =
  2398. HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  2399. FCS_OK_BITMAP_95_64);
  2400. ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] =
  2401. HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  2402. FCS_OK_BITMAP_127_96);
  2403. ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] =
  2404. HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  2405. FCS_OK_BITMAP_159_128);
  2406. ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] =
  2407. HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  2408. FCS_OK_BITMAP_191_160);
  2409. ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] =
  2410. HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  2411. FCS_OK_BITMAP_223_192);
  2412. ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] =
  2413. HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT,
  2414. FCS_OK_BITMAP_255_224);
  2415. break;
  2416. case WIFIRX_PPDU_END_STATUS_DONE_E:
  2417. hal_rx_record_tlv_info(ppdu_info, tlv_tag);
  2418. return HAL_TLV_STATUS_PPDU_DONE;
  2419. case WIFIPHYRX_PKT_END_E:
  2420. break;
  2421. case WIFIDUMMY_E:
  2422. hal_rx_record_tlv_info(ppdu_info, tlv_tag);
  2423. return HAL_TLV_STATUS_BUF_DONE;
  2424. case WIFIPHYRX_HT_SIG_E:
  2425. {
  2426. uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
  2427. HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0,
  2428. HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
  2429. value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO, FEC_CODING);
  2430. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  2431. 1 : 0;
  2432. ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
  2433. HT_SIG_INFO, MCS);
  2434. ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs;
  2435. ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
  2436. HT_SIG_INFO, CBW);
  2437. ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
  2438. HT_SIG_INFO, SHORT_GI);
  2439. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  2440. ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >>
  2441. HT_SIG_SU_NSS_SHIFT) + 1;
  2442. ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1);
  2443. break;
  2444. }
  2445. case WIFIPHYRX_L_SIG_B_E:
  2446. {
  2447. uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
  2448. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0,
  2449. L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
  2450. value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO, RATE);
  2451. ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info);
  2452. switch (value) {
  2453. case 1:
  2454. ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
  2455. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  2456. break;
  2457. case 2:
  2458. ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
  2459. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  2460. break;
  2461. case 3:
  2462. ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
  2463. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  2464. break;
  2465. case 4:
  2466. ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
  2467. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  2468. break;
  2469. case 5:
  2470. ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
  2471. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  2472. break;
  2473. case 6:
  2474. ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
  2475. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  2476. break;
  2477. case 7:
  2478. ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
  2479. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  2480. break;
  2481. default:
  2482. break;
  2483. }
  2484. ppdu_info->rx_status.cck_flag = 1;
  2485. break;
  2486. }
  2487. case WIFIPHYRX_L_SIG_A_E:
  2488. {
  2489. uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
  2490. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0,
  2491. L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
  2492. value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO, RATE);
  2493. ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info);
  2494. switch (value) {
  2495. case 8:
  2496. ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
  2497. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  2498. break;
  2499. case 9:
  2500. ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
  2501. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  2502. break;
  2503. case 10:
  2504. ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
  2505. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  2506. break;
  2507. case 11:
  2508. ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
  2509. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  2510. break;
  2511. case 12:
  2512. ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
  2513. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  2514. break;
  2515. case 13:
  2516. ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
  2517. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  2518. break;
  2519. case 14:
  2520. ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
  2521. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  2522. break;
  2523. case 15:
  2524. ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
  2525. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7;
  2526. break;
  2527. default:
  2528. break;
  2529. }
  2530. ppdu_info->rx_status.ofdm_flag = 1;
  2531. break;
  2532. }
  2533. case WIFIPHYRX_VHT_SIG_A_E:
  2534. {
  2535. uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
  2536. HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0,
  2537. VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
  2538. value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO,
  2539. SU_MU_CODING);
  2540. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  2541. 1 : 0;
  2542. group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, GROUP_ID);
  2543. ppdu_info->rx_status.vht_flag_values5 = group_id;
  2544. ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
  2545. VHT_SIG_A_INFO, MCS);
  2546. ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
  2547. VHT_SIG_A_INFO,
  2548. GI_SETTING);
  2549. switch (hal->target_type) {
  2550. case TARGET_TYPE_QCA8074:
  2551. case TARGET_TYPE_QCA8074V2:
  2552. case TARGET_TYPE_QCA6018:
  2553. case TARGET_TYPE_QCA5018:
  2554. case TARGET_TYPE_QCN9000:
  2555. case TARGET_TYPE_QCN6122:
  2556. case TARGET_TYPE_QCN6432:
  2557. #ifdef QCA_WIFI_QCA6390
  2558. case TARGET_TYPE_QCA6390:
  2559. #endif
  2560. ppdu_info->rx_status.is_stbc =
  2561. HAL_RX_GET(vht_sig_a_info,
  2562. VHT_SIG_A_INFO, STBC);
  2563. value = HAL_RX_GET(vht_sig_a_info,
  2564. VHT_SIG_A_INFO, N_STS);
  2565. value = value & VHT_SIG_SU_NSS_MASK;
  2566. if (ppdu_info->rx_status.is_stbc && (value > 0))
  2567. value = ((value + 1) >> 1) - 1;
  2568. ppdu_info->rx_status.nss =
  2569. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  2570. break;
  2571. case TARGET_TYPE_QCA6290:
  2572. #if !defined(QCA_WIFI_QCA6290_11AX)
  2573. ppdu_info->rx_status.is_stbc =
  2574. HAL_RX_GET(vht_sig_a_info,
  2575. VHT_SIG_A_INFO, STBC);
  2576. value = HAL_RX_GET(vht_sig_a_info,
  2577. VHT_SIG_A_INFO, N_STS);
  2578. value = value & VHT_SIG_SU_NSS_MASK;
  2579. if (ppdu_info->rx_status.is_stbc && (value > 0))
  2580. value = ((value + 1) >> 1) - 1;
  2581. ppdu_info->rx_status.nss =
  2582. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  2583. #else
  2584. ppdu_info->rx_status.nss = 0;
  2585. #endif
  2586. break;
  2587. case TARGET_TYPE_KIWI:
  2588. case TARGET_TYPE_MANGO:
  2589. case TARGET_TYPE_PEACH:
  2590. ppdu_info->rx_status.is_stbc =
  2591. HAL_RX_GET(vht_sig_a_info,
  2592. VHT_SIG_A_INFO, STBC);
  2593. value = HAL_RX_GET(vht_sig_a_info,
  2594. VHT_SIG_A_INFO, N_STS);
  2595. value = value & VHT_SIG_SU_NSS_MASK;
  2596. if (ppdu_info->rx_status.is_stbc && (value > 0))
  2597. value = ((value + 1) >> 1) - 1;
  2598. ppdu_info->rx_status.nss =
  2599. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  2600. break;
  2601. case TARGET_TYPE_QCA6490:
  2602. case TARGET_TYPE_QCA6750:
  2603. ppdu_info->rx_status.nss = 0;
  2604. break;
  2605. default:
  2606. break;
  2607. }
  2608. ppdu_info->rx_status.vht_flag_values3[0] =
  2609. (((ppdu_info->rx_status.mcs) << 4)
  2610. | ppdu_info->rx_status.nss);
  2611. ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
  2612. VHT_SIG_A_INFO, BANDWIDTH);
  2613. ppdu_info->rx_status.vht_flag_values2 =
  2614. ppdu_info->rx_status.bw;
  2615. ppdu_info->rx_status.vht_flag_values4 =
  2616. HAL_RX_GET(vht_sig_a_info,
  2617. VHT_SIG_A_INFO, SU_MU_CODING);
  2618. ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
  2619. VHT_SIG_A_INFO,
  2620. BEAMFORMED);
  2621. if (group_id == 0 || group_id == 63)
  2622. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  2623. else
  2624. ppdu_info->rx_status.reception_type =
  2625. HAL_RX_TYPE_MU_MIMO;
  2626. break;
  2627. }
  2628. case WIFIPHYRX_HE_SIG_A_SU_E:
  2629. {
  2630. uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
  2631. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0,
  2632. HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
  2633. ppdu_info->rx_status.he_flags = 1;
  2634. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  2635. FORMAT_INDICATION);
  2636. if (value == 0) {
  2637. ppdu_info->rx_status.he_data1 =
  2638. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  2639. } else {
  2640. ppdu_info->rx_status.he_data1 =
  2641. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  2642. }
  2643. /* data1 */
  2644. ppdu_info->rx_status.he_data1 |=
  2645. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  2646. QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
  2647. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  2648. QDF_MON_STATUS_HE_MCS_KNOWN |
  2649. QDF_MON_STATUS_HE_DCM_KNOWN |
  2650. QDF_MON_STATUS_HE_CODING_KNOWN |
  2651. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  2652. QDF_MON_STATUS_HE_STBC_KNOWN |
  2653. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  2654. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  2655. /* data2 */
  2656. ppdu_info->rx_status.he_data2 =
  2657. QDF_MON_STATUS_HE_GI_KNOWN;
  2658. ppdu_info->rx_status.he_data2 |=
  2659. QDF_MON_STATUS_TXBF_KNOWN |
  2660. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  2661. QDF_MON_STATUS_TXOP_KNOWN |
  2662. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  2663. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  2664. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  2665. /* data3 */
  2666. value = HAL_RX_GET(he_sig_a_su_info,
  2667. HE_SIG_A_SU_INFO, BSS_COLOR_ID);
  2668. ppdu_info->rx_status.he_data3 = value;
  2669. value = HAL_RX_GET(he_sig_a_su_info,
  2670. HE_SIG_A_SU_INFO, BEAM_CHANGE);
  2671. value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
  2672. ppdu_info->rx_status.he_data3 |= value;
  2673. value = HAL_RX_GET(he_sig_a_su_info,
  2674. HE_SIG_A_SU_INFO, DL_UL_FLAG);
  2675. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  2676. ppdu_info->rx_status.he_data3 |= value;
  2677. value = HAL_RX_GET(he_sig_a_su_info,
  2678. HE_SIG_A_SU_INFO, TRANSMIT_MCS);
  2679. ppdu_info->rx_status.mcs = value;
  2680. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  2681. ppdu_info->rx_status.he_data3 |= value;
  2682. value = HAL_RX_GET(he_sig_a_su_info,
  2683. HE_SIG_A_SU_INFO, DCM);
  2684. he_dcm = value;
  2685. value = value << QDF_MON_STATUS_DCM_SHIFT;
  2686. ppdu_info->rx_status.he_data3 |= value;
  2687. value = HAL_RX_GET(he_sig_a_su_info,
  2688. HE_SIG_A_SU_INFO, CODING);
  2689. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  2690. 1 : 0;
  2691. value = value << QDF_MON_STATUS_CODING_SHIFT;
  2692. ppdu_info->rx_status.he_data3 |= value;
  2693. value = HAL_RX_GET(he_sig_a_su_info,
  2694. HE_SIG_A_SU_INFO,
  2695. LDPC_EXTRA_SYMBOL);
  2696. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  2697. ppdu_info->rx_status.he_data3 |= value;
  2698. value = HAL_RX_GET(he_sig_a_su_info,
  2699. HE_SIG_A_SU_INFO, STBC);
  2700. he_stbc = value;
  2701. value = value << QDF_MON_STATUS_STBC_SHIFT;
  2702. ppdu_info->rx_status.he_data3 |= value;
  2703. /* data4 */
  2704. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  2705. SPATIAL_REUSE);
  2706. ppdu_info->rx_status.he_data4 = value;
  2707. /* data5 */
  2708. value = HAL_RX_GET(he_sig_a_su_info,
  2709. HE_SIG_A_SU_INFO, TRANSMIT_BW);
  2710. ppdu_info->rx_status.he_data5 = value;
  2711. ppdu_info->rx_status.bw = value;
  2712. value = HAL_RX_GET(he_sig_a_su_info,
  2713. HE_SIG_A_SU_INFO, CP_LTF_SIZE);
  2714. switch (value) {
  2715. case 0:
  2716. he_gi = HE_GI_0_8;
  2717. he_ltf = HE_LTF_1_X;
  2718. break;
  2719. case 1:
  2720. he_gi = HE_GI_0_8;
  2721. he_ltf = HE_LTF_2_X;
  2722. break;
  2723. case 2:
  2724. he_gi = HE_GI_1_6;
  2725. he_ltf = HE_LTF_2_X;
  2726. break;
  2727. case 3:
  2728. if (he_dcm && he_stbc) {
  2729. he_gi = HE_GI_0_8;
  2730. he_ltf = HE_LTF_4_X;
  2731. } else {
  2732. he_gi = HE_GI_3_2;
  2733. he_ltf = HE_LTF_4_X;
  2734. }
  2735. break;
  2736. }
  2737. ppdu_info->rx_status.sgi = he_gi;
  2738. ppdu_info->rx_status.ltf_size = he_ltf;
  2739. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  2740. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  2741. ppdu_info->rx_status.he_data5 |= value;
  2742. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  2743. ppdu_info->rx_status.he_data5 |= value;
  2744. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS);
  2745. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  2746. ppdu_info->rx_status.he_data5 |= value;
  2747. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  2748. PACKET_EXTENSION_A_FACTOR);
  2749. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  2750. ppdu_info->rx_status.he_data5 |= value;
  2751. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, TXBF);
  2752. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  2753. ppdu_info->rx_status.he_data5 |= value;
  2754. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  2755. PACKET_EXTENSION_PE_DISAMBIGUITY);
  2756. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  2757. ppdu_info->rx_status.he_data5 |= value;
  2758. /* data6 */
  2759. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS);
  2760. value++;
  2761. ppdu_info->rx_status.nss = value;
  2762. ppdu_info->rx_status.he_data6 = value;
  2763. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  2764. DOPPLER_INDICATION);
  2765. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  2766. ppdu_info->rx_status.he_data6 |= value;
  2767. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO,
  2768. TXOP_DURATION);
  2769. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  2770. ppdu_info->rx_status.he_data6 |= value;
  2771. ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
  2772. HE_SIG_A_SU_INFO,
  2773. TXBF);
  2774. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  2775. break;
  2776. }
  2777. case WIFIPHYRX_HE_SIG_A_MU_DL_E:
  2778. {
  2779. uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
  2780. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0,
  2781. HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
  2782. ppdu_info->rx_status.he_mu_flags = 1;
  2783. /* HE Flags */
  2784. /*data1*/
  2785. ppdu_info->rx_status.he_data1 =
  2786. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  2787. ppdu_info->rx_status.he_data1 |=
  2788. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  2789. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  2790. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  2791. QDF_MON_STATUS_HE_STBC_KNOWN |
  2792. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  2793. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  2794. /* data2 */
  2795. ppdu_info->rx_status.he_data2 =
  2796. QDF_MON_STATUS_HE_GI_KNOWN;
  2797. ppdu_info->rx_status.he_data2 |=
  2798. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  2799. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  2800. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  2801. QDF_MON_STATUS_TXOP_KNOWN |
  2802. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  2803. /*data3*/
  2804. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  2805. HE_SIG_A_MU_DL_INFO, BSS_COLOR_ID);
  2806. ppdu_info->rx_status.he_data3 = value;
  2807. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  2808. HE_SIG_A_MU_DL_INFO, DL_UL_FLAG);
  2809. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  2810. ppdu_info->rx_status.he_data3 |= value;
  2811. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  2812. HE_SIG_A_MU_DL_INFO,
  2813. LDPC_EXTRA_SYMBOL);
  2814. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  2815. ppdu_info->rx_status.he_data3 |= value;
  2816. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  2817. HE_SIG_A_MU_DL_INFO, STBC);
  2818. he_stbc = value;
  2819. value = value << QDF_MON_STATUS_STBC_SHIFT;
  2820. ppdu_info->rx_status.he_data3 |= value;
  2821. /*data4*/
  2822. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  2823. SPATIAL_REUSE);
  2824. ppdu_info->rx_status.he_data4 = value;
  2825. /*data5*/
  2826. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  2827. HE_SIG_A_MU_DL_INFO, TRANSMIT_BW);
  2828. ppdu_info->rx_status.he_data5 = value;
  2829. ppdu_info->rx_status.bw = value;
  2830. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  2831. HE_SIG_A_MU_DL_INFO, CP_LTF_SIZE);
  2832. switch (value) {
  2833. case 0:
  2834. he_gi = HE_GI_0_8;
  2835. he_ltf = HE_LTF_4_X;
  2836. break;
  2837. case 1:
  2838. he_gi = HE_GI_0_8;
  2839. he_ltf = HE_LTF_2_X;
  2840. break;
  2841. case 2:
  2842. he_gi = HE_GI_1_6;
  2843. he_ltf = HE_LTF_2_X;
  2844. break;
  2845. case 3:
  2846. he_gi = HE_GI_3_2;
  2847. he_ltf = HE_LTF_4_X;
  2848. break;
  2849. }
  2850. ppdu_info->rx_status.sgi = he_gi;
  2851. ppdu_info->rx_status.ltf_size = he_ltf;
  2852. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  2853. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  2854. ppdu_info->rx_status.he_data5 |= value;
  2855. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  2856. ppdu_info->rx_status.he_data5 |= value;
  2857. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  2858. HE_SIG_A_MU_DL_INFO, NUM_LTF_SYMBOLS);
  2859. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  2860. ppdu_info->rx_status.he_data5 |= value;
  2861. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  2862. PACKET_EXTENSION_A_FACTOR);
  2863. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  2864. ppdu_info->rx_status.he_data5 |= value;
  2865. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  2866. PACKET_EXTENSION_PE_DISAMBIGUITY);
  2867. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  2868. ppdu_info->rx_status.he_data5 |= value;
  2869. /*data6*/
  2870. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  2871. DOPPLER_INDICATION);
  2872. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  2873. ppdu_info->rx_status.he_data6 |= value;
  2874. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO,
  2875. TXOP_DURATION);
  2876. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  2877. ppdu_info->rx_status.he_data6 |= value;
  2878. /* HE-MU Flags */
  2879. /* HE-MU-flags1 */
  2880. ppdu_info->rx_status.he_flags1 =
  2881. QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  2882. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  2883. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  2884. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  2885. QDF_MON_STATUS_RU_0_KNOWN;
  2886. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  2887. HE_SIG_A_MU_DL_INFO, MCS_OF_SIG_B);
  2888. ppdu_info->rx_status.he_flags1 |= value;
  2889. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  2890. HE_SIG_A_MU_DL_INFO, DCM_OF_SIG_B);
  2891. value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
  2892. ppdu_info->rx_status.he_flags1 |= value;
  2893. /* HE-MU-flags2 */
  2894. ppdu_info->rx_status.he_flags2 =
  2895. QDF_MON_STATUS_BW_KNOWN;
  2896. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  2897. HE_SIG_A_MU_DL_INFO, TRANSMIT_BW);
  2898. ppdu_info->rx_status.he_flags2 |= value;
  2899. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  2900. HE_SIG_A_MU_DL_INFO, COMP_MODE_SIG_B);
  2901. value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  2902. ppdu_info->rx_status.he_flags2 |= value;
  2903. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  2904. HE_SIG_A_MU_DL_INFO, NUM_SIG_B_SYMBOLS);
  2905. value = value - 1;
  2906. value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  2907. ppdu_info->rx_status.he_flags2 |= value;
  2908. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  2909. break;
  2910. }
  2911. case WIFIPHYRX_HE_SIG_B1_MU_E:
  2912. {
  2913. uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
  2914. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0,
  2915. HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
  2916. ppdu_info->rx_status.he_sig_b_common_known |=
  2917. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  2918. /* TODO: Check on the availability of other fields in
  2919. * sig_b_common
  2920. */
  2921. value = HAL_RX_GET(he_sig_b1_mu_info,
  2922. HE_SIG_B1_MU_INFO, RU_ALLOCATION);
  2923. ppdu_info->rx_status.he_RU[0] = value;
  2924. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  2925. break;
  2926. }
  2927. case WIFIPHYRX_HE_SIG_B2_MU_E:
  2928. {
  2929. uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
  2930. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0,
  2931. HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
  2932. /*
  2933. * Not all "HE" fields can be updated from
  2934. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  2935. * to populate rest of the "HE" fields for MU scenarios.
  2936. */
  2937. /* HE-data1 */
  2938. ppdu_info->rx_status.he_data1 |=
  2939. QDF_MON_STATUS_HE_MCS_KNOWN |
  2940. QDF_MON_STATUS_HE_CODING_KNOWN;
  2941. /* HE-data2 */
  2942. /* HE-data3 */
  2943. value = HAL_RX_GET(he_sig_b2_mu_info,
  2944. HE_SIG_B2_MU_INFO, STA_MCS);
  2945. ppdu_info->rx_status.mcs = value;
  2946. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  2947. ppdu_info->rx_status.he_data3 |= value;
  2948. value = HAL_RX_GET(he_sig_b2_mu_info,
  2949. HE_SIG_B2_MU_INFO, STA_CODING);
  2950. value = value << QDF_MON_STATUS_CODING_SHIFT;
  2951. ppdu_info->rx_status.he_data3 |= value;
  2952. /* HE-data4 */
  2953. value = HAL_RX_GET(he_sig_b2_mu_info,
  2954. HE_SIG_B2_MU_INFO, STA_ID);
  2955. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  2956. ppdu_info->rx_status.he_data4 |= value;
  2957. /* HE-data5 */
  2958. /* HE-data6 */
  2959. value = HAL_RX_GET(he_sig_b2_mu_info,
  2960. HE_SIG_B2_MU_INFO, NSTS);
  2961. /* value n indicates n+1 spatial streams */
  2962. value++;
  2963. ppdu_info->rx_status.nss = value;
  2964. ppdu_info->rx_status.he_data6 |= value;
  2965. break;
  2966. }
  2967. case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
  2968. {
  2969. uint8_t *he_sig_b2_ofdma_info =
  2970. (uint8_t *)rx_tlv +
  2971. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0,
  2972. HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
  2973. /*
  2974. * Not all "HE" fields can be updated from
  2975. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  2976. * to populate rest of "HE" fields for MU OFDMA scenarios.
  2977. */
  2978. /* HE-data1 */
  2979. ppdu_info->rx_status.he_data1 |=
  2980. QDF_MON_STATUS_HE_MCS_KNOWN |
  2981. QDF_MON_STATUS_HE_DCM_KNOWN |
  2982. QDF_MON_STATUS_HE_CODING_KNOWN;
  2983. /* HE-data2 */
  2984. ppdu_info->rx_status.he_data2 |=
  2985. QDF_MON_STATUS_TXBF_KNOWN;
  2986. /* HE-data3 */
  2987. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  2988. HE_SIG_B2_OFDMA_INFO, STA_MCS);
  2989. ppdu_info->rx_status.mcs = value;
  2990. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  2991. ppdu_info->rx_status.he_data3 |= value;
  2992. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  2993. HE_SIG_B2_OFDMA_INFO, STA_DCM);
  2994. he_dcm = value;
  2995. value = value << QDF_MON_STATUS_DCM_SHIFT;
  2996. ppdu_info->rx_status.he_data3 |= value;
  2997. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  2998. HE_SIG_B2_OFDMA_INFO, STA_CODING);
  2999. value = value << QDF_MON_STATUS_CODING_SHIFT;
  3000. ppdu_info->rx_status.he_data3 |= value;
  3001. /* HE-data4 */
  3002. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  3003. HE_SIG_B2_OFDMA_INFO, STA_ID);
  3004. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  3005. ppdu_info->rx_status.he_data4 |= value;
  3006. /* HE-data5 */
  3007. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  3008. HE_SIG_B2_OFDMA_INFO, TXBF);
  3009. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  3010. ppdu_info->rx_status.he_data5 |= value;
  3011. /* HE-data6 */
  3012. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  3013. HE_SIG_B2_OFDMA_INFO, NSTS);
  3014. /* value n indicates n+1 spatial streams */
  3015. value++;
  3016. ppdu_info->rx_status.nss = value;
  3017. ppdu_info->rx_status.he_data6 |= value;
  3018. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA;
  3019. break;
  3020. }
  3021. case WIFIPHYRX_RSSI_LEGACY_E:
  3022. {
  3023. uint8_t reception_type;
  3024. int8_t rssi_value;
  3025. uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
  3026. HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19,
  3027. RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS);
  3028. ppdu_info->rx_status.rssi_comb =
  3029. HAL_RX_GET_64(rx_tlv,
  3030. PHYRX_RSSI_LEGACY, RSSI_COMB);
  3031. ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
  3032. ppdu_info->rx_status.he_re = 0;
  3033. reception_type = HAL_RX_GET_64(rx_tlv,
  3034. PHYRX_RSSI_LEGACY,
  3035. RECEPTION_TYPE);
  3036. switch (reception_type) {
  3037. case QDF_RECEPTION_TYPE_ULOFMDA:
  3038. ppdu_info->rx_status.ulofdma_flag = 1;
  3039. ppdu_info->rx_status.he_data1 =
  3040. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  3041. break;
  3042. case QDF_RECEPTION_TYPE_ULMIMO:
  3043. ppdu_info->rx_status.he_data1 =
  3044. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  3045. break;
  3046. default:
  3047. break;
  3048. }
  3049. hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv);
  3050. rssi_value = HAL_RX_GET_64(rssi_info_tlv,
  3051. RECEIVE_RSSI_INFO,
  3052. RSSI_PRI20_CHAIN0);
  3053. ppdu_info->rx_status.rssi[0] = rssi_value;
  3054. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3055. "RSSI_PRI20_CHAIN0: %d\n", rssi_value);
  3056. rssi_value = HAL_RX_GET_64(rssi_info_tlv,
  3057. RECEIVE_RSSI_INFO,
  3058. RSSI_PRI20_CHAIN1);
  3059. ppdu_info->rx_status.rssi[1] = rssi_value;
  3060. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3061. "RSSI_PRI20_CHAIN1: %d\n", rssi_value);
  3062. rssi_value = HAL_RX_GET_64(rssi_info_tlv,
  3063. RECEIVE_RSSI_INFO,
  3064. RSSI_PRI20_CHAIN2);
  3065. ppdu_info->rx_status.rssi[2] = rssi_value;
  3066. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3067. "RSSI_PRI20_CHAIN2: %d\n", rssi_value);
  3068. rssi_value = HAL_RX_GET_64(rssi_info_tlv,
  3069. RECEIVE_RSSI_INFO,
  3070. RSSI_PRI20_CHAIN3);
  3071. ppdu_info->rx_status.rssi[3] = rssi_value;
  3072. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3073. "RSSI_PRI20_CHAIN3: %d\n", rssi_value);
  3074. #ifdef DP_BE_NOTYET_WAR
  3075. // TODO - this is not preset for kiwi
  3076. rssi_value = HAL_RX_GET_64(rssi_info_tlv,
  3077. RECEIVE_RSSI_INFO,
  3078. RSSI_PRI20_CHAIN4);
  3079. ppdu_info->rx_status.rssi[4] = rssi_value;
  3080. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3081. "RSSI_PRI20_CHAIN4: %d\n", rssi_value);
  3082. rssi_value = HAL_RX_GET_64(rssi_info_tlv,
  3083. RECEIVE_RSSI_INFO,
  3084. RSSI_PRI20_CHAIN5);
  3085. ppdu_info->rx_status.rssi[5] = rssi_value;
  3086. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3087. "RSSI_PRI20_CHAIN5: %d\n", rssi_value);
  3088. rssi_value = HAL_RX_GET_64(rssi_info_tlv,
  3089. RECEIVE_RSSI_INFO,
  3090. RSSI_PRI20_CHAIN6);
  3091. ppdu_info->rx_status.rssi[6] = rssi_value;
  3092. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3093. "RSSI_PRI20_CHAIN6: %d\n", rssi_value);
  3094. rssi_value = HAL_RX_GET_64(rssi_info_tlv,
  3095. RECEIVE_RSSI_INFO,
  3096. RSSI_PRI20_CHAIN7);
  3097. ppdu_info->rx_status.rssi[7] = rssi_value;
  3098. #endif
  3099. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3100. "RSSI_PRI20_CHAIN7: %d\n", rssi_value);
  3101. break;
  3102. }
  3103. case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
  3104. hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
  3105. ppdu_info);
  3106. break;
  3107. case WIFIPHYRX_GENERIC_U_SIG_E:
  3108. hal_rx_parse_u_sig_hdr(hal, rx_tlv, ppdu_info);
  3109. break;
  3110. case WIFIPHYRX_COMMON_USER_INFO_E:
  3111. hal_rx_parse_cmn_usr_info(hal, rx_tlv, ppdu_info);
  3112. break;
  3113. case WIFIRX_HEADER_E:
  3114. {
  3115. struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info;
  3116. if (ppdu_info->fcs_ok_cnt >=
  3117. HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) {
  3118. hal_err("Number of MPDUs(%d) per status buff exceeded",
  3119. ppdu_info->fcs_ok_cnt);
  3120. break;
  3121. }
  3122. /* Update first_msdu_payload for every mpdu and increment
  3123. * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV
  3124. */
  3125. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload =
  3126. rx_tlv;
  3127. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len;
  3128. ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
  3129. ppdu_info->msdu_info.payload_len = tlv_len;
  3130. ppdu_info->user_id = user_id;
  3131. ppdu_info->hdr_len = tlv_len;
  3132. ppdu_info->data = rx_tlv;
  3133. ppdu_info->data += 4;
  3134. /* for every RX_HEADER TLV increment mpdu_cnt */
  3135. com_info->mpdu_cnt++;
  3136. hal_rx_record_tlv_info(ppdu_info, tlv_tag);
  3137. return HAL_TLV_STATUS_HEADER;
  3138. }
  3139. case WIFIRX_MPDU_START_E:
  3140. {
  3141. hal_rx_mon_mpdu_start_t *rx_mpdu_start = rx_tlv;
  3142. uint32_t ppdu_id = rx_mpdu_start->rx_mpdu_info_details.phy_ppdu_id;
  3143. uint8_t filter_category = 0;
  3144. ppdu_info->nac_info.fc_valid =
  3145. rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid;
  3146. ppdu_info->nac_info.to_ds_flag =
  3147. rx_mpdu_start->rx_mpdu_info_details.to_ds;
  3148. ppdu_info->nac_info.frame_control =
  3149. rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field;
  3150. ppdu_info->sw_frame_group_id =
  3151. rx_mpdu_start->rx_mpdu_info_details.sw_frame_group_id;
  3152. ppdu_info->rx_user_status[user_id].sw_peer_id =
  3153. rx_mpdu_start->rx_mpdu_info_details.sw_peer_id;
  3154. hal_update_rx_ctrl_frame_stats(ppdu_info, user_id);
  3155. if (ppdu_info->sw_frame_group_id ==
  3156. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  3157. ppdu_info->rx_status.frame_control_info_valid =
  3158. ppdu_info->nac_info.fc_valid;
  3159. ppdu_info->rx_status.frame_control =
  3160. ppdu_info->nac_info.frame_control;
  3161. }
  3162. hal_get_mac_addr1(rx_mpdu_start,
  3163. ppdu_info);
  3164. ppdu_info->nac_info.mac_addr2_valid =
  3165. rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_valid;
  3166. *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] =
  3167. rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_15_0;
  3168. *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] =
  3169. rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_47_16;
  3170. if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
  3171. ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
  3172. ppdu_info->rx_status.ppdu_len =
  3173. rx_mpdu_start->rx_mpdu_info_details.mpdu_length;
  3174. } else {
  3175. ppdu_info->rx_status.ppdu_len +=
  3176. rx_mpdu_start->rx_mpdu_info_details.mpdu_length;
  3177. }
  3178. filter_category =
  3179. rx_mpdu_start->rx_mpdu_info_details.rxpcu_mpdu_filter_in_category;
  3180. if (filter_category == 0)
  3181. ppdu_info->rx_status.rxpcu_filter_pass = 1;
  3182. else if (filter_category == 1)
  3183. ppdu_info->rx_status.monitor_direct_used = 1;
  3184. ppdu_info->rx_user_status[user_id].filter_category = filter_category;
  3185. ppdu_info->nac_info.mcast_bcast =
  3186. rx_mpdu_start->rx_mpdu_info_details.mcast_bcast;
  3187. ppdu_info->mpdu_info[user_id].decap_type =
  3188. rx_mpdu_start->rx_mpdu_info_details.decap_type;
  3189. hal_rx_record_tlv_info(ppdu_info, tlv_tag);
  3190. return HAL_TLV_STATUS_MPDU_START;
  3191. }
  3192. case WIFIRX_MPDU_END_E:
  3193. ppdu_info->user_id = user_id;
  3194. ppdu_info->fcs_err =
  3195. HAL_RX_GET_64(rx_tlv, RX_MPDU_END,
  3196. FCS_ERR);
  3197. hal_rx_record_tlv_info(ppdu_info, tlv_tag);
  3198. return HAL_TLV_STATUS_MPDU_END;
  3199. case WIFIRX_MSDU_END_E: {
  3200. hal_rx_mon_msdu_end_t *rx_msdu_end = rx_tlv;
  3201. if (user_id < HAL_MAX_UL_MU_USERS) {
  3202. ppdu_info->rx_msdu_info[user_id].cce_metadata =
  3203. rx_msdu_end->cce_metadata;
  3204. ppdu_info->rx_msdu_info[user_id].fse_metadata =
  3205. rx_msdu_end->fse_metadata;
  3206. ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout =
  3207. rx_msdu_end->flow_idx_timeout;
  3208. ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid =
  3209. rx_msdu_end->flow_idx_invalid;
  3210. ppdu_info->rx_msdu_info[user_id].flow_idx =
  3211. rx_msdu_end->flow_idx;
  3212. ppdu_info->msdu[user_id].first_msdu =
  3213. rx_msdu_end->first_msdu;
  3214. ppdu_info->msdu[user_id].last_msdu =
  3215. rx_msdu_end->last_msdu;
  3216. ppdu_info->msdu[user_id].msdu_len =
  3217. rx_msdu_end->msdu_length;
  3218. ppdu_info->msdu[user_id].user_rssi =
  3219. rx_msdu_end->user_rssi;
  3220. ppdu_info->msdu[user_id].reception_type =
  3221. rx_msdu_end->reception_type;
  3222. }
  3223. hal_rx_record_tlv_info(ppdu_info, tlv_tag);
  3224. return HAL_TLV_STATUS_MSDU_END;
  3225. }
  3226. case WIFIMON_BUFFER_ADDR_E:
  3227. hal_rx_status_get_mon_buf_addr(rx_tlv, ppdu_info);
  3228. hal_rx_record_tlv_info(ppdu_info, tlv_tag);
  3229. return HAL_TLV_STATUS_MON_BUF_ADDR;
  3230. case WIFIMON_DROP_E:
  3231. hal_rx_update_ppdu_drop_cnt(rx_tlv, ppdu_info);
  3232. hal_rx_record_tlv_info(ppdu_info, tlv_tag);
  3233. return HAL_TLV_STATUS_MON_DROP;
  3234. case 0:
  3235. hal_rx_record_tlv_info(ppdu_info, tlv_tag);
  3236. return HAL_TLV_STATUS_PPDU_DONE;
  3237. case WIFIRX_STATUS_BUFFER_DONE_E:
  3238. case WIFIPHYRX_DATA_DONE_E:
  3239. case WIFIPHYRX_PKT_END_PART1_E:
  3240. hal_rx_record_tlv_info(ppdu_info, tlv_tag);
  3241. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  3242. default:
  3243. hal_debug("unhandled tlv tag %d", tlv_tag);
  3244. }
  3245. hal_rx_record_tlv_info(ppdu_info, tlv_tag);
  3246. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3247. rx_tlv, tlv_len);
  3248. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  3249. }
  3250. static uint32_t
  3251. hal_rx_status_process_aggr_tlv(struct hal_soc *hal_soc,
  3252. struct hal_rx_ppdu_info *ppdu_info)
  3253. {
  3254. uint32_t aggr_tlv_tag = ppdu_info->tlv_aggr.tlv_tag;
  3255. switch (aggr_tlv_tag) {
  3256. case WIFIPHYRX_GENERIC_EHT_SIG_E:
  3257. hal_rx_parse_eht_sig_hdr(hal_soc, ppdu_info->tlv_aggr.buf,
  3258. ppdu_info);
  3259. break;
  3260. default:
  3261. /* Aggregated TLV cannot be handled */
  3262. qdf_assert(0);
  3263. break;
  3264. }
  3265. ppdu_info->tlv_aggr.in_progress = 0;
  3266. ppdu_info->tlv_aggr.cur_len = 0;
  3267. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  3268. }
  3269. static inline bool
  3270. hal_rx_status_tlv_should_aggregate(struct hal_soc *hal_soc, uint32_t tlv_tag)
  3271. {
  3272. switch (tlv_tag) {
  3273. case WIFIPHYRX_GENERIC_EHT_SIG_E:
  3274. return true;
  3275. }
  3276. return false;
  3277. }
  3278. static inline uint32_t
  3279. hal_rx_status_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr,
  3280. struct hal_rx_ppdu_info *ppdu_info,
  3281. qdf_nbuf_t nbuf)
  3282. {
  3283. uint32_t tlv_tag, user_id, tlv_len;
  3284. void *rx_tlv;
  3285. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr);
  3286. user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr);
  3287. tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr);
  3288. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  3289. if (tlv_len <= HAL_RX_MON_MAX_AGGR_SIZE - ppdu_info->tlv_aggr.cur_len) {
  3290. qdf_mem_copy(ppdu_info->tlv_aggr.buf +
  3291. ppdu_info->tlv_aggr.cur_len,
  3292. rx_tlv, tlv_len);
  3293. ppdu_info->tlv_aggr.cur_len += tlv_len;
  3294. } else {
  3295. dp_err("Length of TLV exceeds max aggregation length");
  3296. qdf_assert(0);
  3297. }
  3298. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  3299. }
  3300. static inline uint32_t
  3301. hal_rx_status_start_new_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr,
  3302. struct hal_rx_ppdu_info *ppdu_info,
  3303. qdf_nbuf_t nbuf)
  3304. {
  3305. uint32_t tlv_tag, user_id, tlv_len;
  3306. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr);
  3307. user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr);
  3308. tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr);
  3309. ppdu_info->tlv_aggr.in_progress = 1;
  3310. ppdu_info->tlv_aggr.tlv_tag = tlv_tag;
  3311. ppdu_info->tlv_aggr.cur_len = 0;
  3312. return hal_rx_status_aggr_tlv(hal_soc, rx_tlv_hdr, ppdu_info, nbuf);
  3313. }
  3314. static inline uint32_t
  3315. hal_rx_status_get_tlv_info_wrapper_be(void *rx_tlv_hdr, void *ppduinfo,
  3316. hal_soc_handle_t hal_soc_hdl,
  3317. qdf_nbuf_t nbuf)
  3318. {
  3319. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  3320. uint32_t tlv_tag, user_id, tlv_len;
  3321. struct hal_rx_ppdu_info *ppdu_info =
  3322. (struct hal_rx_ppdu_info *)ppduinfo;
  3323. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr);
  3324. user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr);
  3325. tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr);
  3326. /*
  3327. * Handle the case where aggregation is in progress
  3328. * or the current TLV is one of the TLVs which should be
  3329. * aggregated
  3330. */
  3331. if (ppdu_info->tlv_aggr.in_progress) {
  3332. if (ppdu_info->tlv_aggr.tlv_tag == tlv_tag) {
  3333. return hal_rx_status_aggr_tlv(hal, rx_tlv_hdr,
  3334. ppdu_info, nbuf);
  3335. } else {
  3336. /* Finish aggregation of current TLV */
  3337. hal_rx_status_process_aggr_tlv(hal, ppdu_info);
  3338. }
  3339. }
  3340. if (hal_rx_status_tlv_should_aggregate(hal, tlv_tag)) {
  3341. return hal_rx_status_start_new_aggr_tlv(hal, rx_tlv_hdr,
  3342. ppduinfo, nbuf);
  3343. }
  3344. return hal_rx_status_get_tlv_info_generic_be(rx_tlv_hdr, ppduinfo,
  3345. hal_soc_hdl, nbuf);
  3346. }
  3347. #endif /* _HAL_BE_API_MON_H_ */