dp_li_tx.c 18 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "dp_types.h"
  21. #include "dp_tx.h"
  22. #include "dp_li_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include <dp_internal.h>
  25. #include <dp_htt.h>
  26. #include <hal_li_api.h>
  27. #include <hal_li_tx.h>
  28. #include "dp_peer.h"
  29. #ifdef FEATURE_WDS
  30. #include "dp_txrx_wds.h"
  31. #endif
  32. #include "dp_li.h"
  33. extern uint8_t sec_type_map[MAX_CDP_SEC_TYPE];
  34. void dp_tx_comp_get_params_from_hal_desc_li(struct dp_soc *soc,
  35. void *tx_comp_hal_desc,
  36. struct dp_tx_desc_s **r_tx_desc)
  37. {
  38. uint8_t pool_id;
  39. uint32_t tx_desc_id;
  40. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  41. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  42. DP_TX_DESC_ID_POOL_OS;
  43. /* Find Tx descriptor */
  44. *r_tx_desc = dp_tx_desc_find(soc, pool_id,
  45. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  46. DP_TX_DESC_ID_PAGE_OS,
  47. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  48. DP_TX_DESC_ID_OFFSET_OS);
  49. /* Pool id is not matching. Error */
  50. if ((*r_tx_desc)->pool_id != pool_id) {
  51. dp_tx_comp_alert("Tx Comp pool id %d not matched %d",
  52. pool_id, (*r_tx_desc)->pool_id);
  53. qdf_assert_always(0);
  54. }
  55. (*r_tx_desc)->peer_id = hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  56. }
  57. static inline
  58. void dp_tx_process_mec_notify_li(struct dp_soc *soc, uint8_t *status)
  59. {
  60. struct dp_vdev *vdev;
  61. uint8_t vdev_id;
  62. uint32_t *htt_desc = (uint32_t *)status;
  63. /*
  64. * Get vdev id from HTT status word in case of MEC
  65. * notification
  66. */
  67. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  68. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  69. return;
  70. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  71. DP_MOD_ID_HTT_COMP);
  72. if (!vdev)
  73. return;
  74. dp_tx_mec_handler(vdev, status);
  75. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  76. }
  77. void dp_tx_process_htt_completion_li(struct dp_soc *soc,
  78. struct dp_tx_desc_s *tx_desc,
  79. uint8_t *status,
  80. uint8_t ring_id)
  81. {
  82. uint8_t tx_status;
  83. struct dp_pdev *pdev;
  84. struct dp_vdev *vdev = NULL;
  85. struct hal_tx_completion_status ts = {0};
  86. uint32_t *htt_desc = (uint32_t *)status;
  87. struct dp_txrx_peer *txrx_peer;
  88. dp_txrx_ref_handle txrx_ref_handle = NULL;
  89. struct cdp_tid_tx_stats *tid_stats = NULL;
  90. struct htt_soc *htt_handle;
  91. uint8_t vdev_id;
  92. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  93. htt_handle = (struct htt_soc *)soc->htt_handle;
  94. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  95. /*
  96. * There can be scenario where WBM consuming descriptor enqueued
  97. * from TQM2WBM first and TQM completion can happen before MEC
  98. * notification comes from FW2WBM. Avoid access any field of tx
  99. * descriptor in case of MEC notify.
  100. */
  101. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY)
  102. return dp_tx_process_mec_notify_li(soc, status);
  103. /*
  104. * If the descriptor is already freed in vdev_detach,
  105. * continue to next descriptor
  106. */
  107. if (qdf_unlikely(!tx_desc->flags)) {
  108. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  109. tx_desc->id);
  110. return;
  111. }
  112. if (qdf_unlikely(tx_desc->vdev_id == DP_INVALID_VDEV_ID)) {
  113. dp_tx_comp_info_rl("Invalid vdev_id %d", tx_desc->id);
  114. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  115. goto release_tx_desc;
  116. }
  117. pdev = tx_desc->pdev;
  118. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  119. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  120. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  121. goto release_tx_desc;
  122. }
  123. qdf_assert(tx_desc->pdev);
  124. vdev_id = tx_desc->vdev_id;
  125. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  126. DP_MOD_ID_HTT_COMP);
  127. if (qdf_unlikely(!vdev)) {
  128. dp_tx_comp_info_rl("Unable to get vdev ref %d", tx_desc->id);
  129. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  130. goto release_tx_desc;
  131. }
  132. switch (tx_status) {
  133. case HTT_TX_FW2WBM_TX_STATUS_OK:
  134. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  135. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  136. {
  137. uint8_t tid;
  138. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  139. ts.peer_id =
  140. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  141. htt_desc[2]);
  142. ts.tid =
  143. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  144. htt_desc[2]);
  145. } else {
  146. ts.peer_id = HTT_INVALID_PEER;
  147. ts.tid = HTT_INVALID_TID;
  148. }
  149. ts.release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
  150. ts.ppdu_id =
  151. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  152. htt_desc[1]);
  153. ts.ack_frame_rssi =
  154. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  155. htt_desc[1]);
  156. ts.tsf = htt_desc[3];
  157. ts.first_msdu = 1;
  158. ts.last_msdu = 1;
  159. switch (tx_status) {
  160. case HTT_TX_FW2WBM_TX_STATUS_OK:
  161. ts.status = HAL_TX_TQM_RR_FRAME_ACKED;
  162. break;
  163. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  164. ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
  165. break;
  166. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  167. ts.status = HAL_TX_TQM_RR_REM_CMD_TX;
  168. break;
  169. }
  170. tid = ts.tid;
  171. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  172. tid = CDP_MAX_DATA_TIDS - 1;
  173. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  174. if (qdf_unlikely(pdev->delay_stats_flag) ||
  175. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(vdev)))
  176. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  177. if (tx_status < CDP_MAX_TX_HTT_STATUS)
  178. tid_stats->htt_status_cnt[tx_status]++;
  179. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, ts.peer_id,
  180. &txrx_ref_handle,
  181. DP_MOD_ID_HTT_COMP);
  182. if (qdf_likely(txrx_peer)) {
  183. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1,
  184. qdf_nbuf_len(tx_desc->nbuf));
  185. if (tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)
  186. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  187. }
  188. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, txrx_peer,
  189. ring_id);
  190. dp_tx_comp_process_desc(soc, tx_desc, &ts, txrx_peer);
  191. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  192. if (qdf_likely(txrx_peer))
  193. dp_txrx_peer_unref_delete(txrx_ref_handle,
  194. DP_MOD_ID_HTT_COMP);
  195. break;
  196. }
  197. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  198. {
  199. uint8_t reinject_reason;
  200. reinject_reason =
  201. HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_GET(
  202. htt_desc[0]);
  203. dp_tx_reinject_handler(soc, vdev, tx_desc,
  204. status, reinject_reason);
  205. break;
  206. }
  207. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  208. {
  209. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  210. break;
  211. }
  212. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  213. {
  214. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  215. goto release_tx_desc;
  216. }
  217. default:
  218. dp_tx_comp_err("Invalid HTT tx_status %d\n",
  219. tx_status);
  220. goto release_tx_desc;
  221. }
  222. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  223. return;
  224. release_tx_desc:
  225. dp_tx_comp_free_buf(soc, tx_desc, false);
  226. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  227. if (vdev)
  228. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  229. }
  230. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  231. /**
  232. * dp_tx_get_rbm_id_li() - Get the RBM ID for data transmission completion.
  233. * @soc: DP soc structure pointer
  234. * @ring_id: Transmit Queue/ring_id to be used when XPS is enabled
  235. *
  236. * Return: HAL ring handle
  237. */
  238. #ifdef IPA_OFFLOAD
  239. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  240. uint8_t ring_id)
  241. {
  242. return (ring_id + soc->wbm_sw0_bm_id);
  243. }
  244. #else
  245. #ifndef QCA_DP_ENABLE_TX_COMP_RING4
  246. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  247. uint8_t ring_id)
  248. {
  249. return (ring_id ? HAL_WBM_SW0_BM_ID + (ring_id - 1) :
  250. HAL_WBM_SW2_BM_ID);
  251. }
  252. #else
  253. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  254. uint8_t ring_id)
  255. {
  256. if (ring_id == soc->num_tcl_data_rings)
  257. return HAL_WBM_SW4_BM_ID(soc->wbm_sw0_bm_id);
  258. return (ring_id + HAL_WBM_SW0_BM_ID(soc->wbm_sw0_bm_id));
  259. }
  260. #endif
  261. #endif
  262. #else
  263. #ifdef TX_MULTI_TCL
  264. #ifdef IPA_OFFLOAD
  265. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  266. uint8_t ring_id)
  267. {
  268. if (soc->wlan_cfg_ctx->ipa_enabled)
  269. return (ring_id + soc->wbm_sw0_bm_id);
  270. return soc->wlan_cfg_ctx->tcl_wbm_map_array[ring_id].wbm_rbm_id;
  271. }
  272. #else
  273. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  274. uint8_t ring_id)
  275. {
  276. return soc->wlan_cfg_ctx->tcl_wbm_map_array[ring_id].wbm_rbm_id;
  277. }
  278. #endif
  279. #else
  280. static inline uint8_t dp_tx_get_rbm_id_li(struct dp_soc *soc,
  281. uint8_t ring_id)
  282. {
  283. return (ring_id + soc->wbm_sw0_bm_id);
  284. }
  285. #endif
  286. #endif
  287. #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
  288. /**
  289. * dp_tx_clear_consumed_hw_descs - Reset all the consumed Tx ring descs to 0
  290. *
  291. * @soc: DP soc handle
  292. * @hal_ring_hdl: Source ring pointer
  293. *
  294. * Return: void
  295. */
  296. static inline
  297. void dp_tx_clear_consumed_hw_descs(struct dp_soc *soc,
  298. hal_ring_handle_t hal_ring_hdl)
  299. {
  300. void *desc = hal_srng_src_get_next_consumed(soc->hal_soc, hal_ring_hdl);
  301. while (desc) {
  302. hal_tx_desc_clear(desc);
  303. desc = hal_srng_src_get_next_consumed(soc->hal_soc,
  304. hal_ring_hdl);
  305. }
  306. }
  307. #else
  308. static inline
  309. void dp_tx_clear_consumed_hw_descs(struct dp_soc *soc,
  310. hal_ring_handle_t hal_ring_hdl)
  311. {
  312. }
  313. #endif /* CLEAR_SW2TCL_CONSUMED_DESC */
  314. #ifdef WLAN_CONFIG_TX_DELAY
  315. static inline
  316. QDF_STATUS dp_tx_compute_hw_delay_li(struct dp_soc *soc,
  317. struct dp_vdev *vdev,
  318. struct hal_tx_completion_status *ts,
  319. uint32_t *delay_us)
  320. {
  321. return dp_tx_compute_hw_delay_us(ts, vdev->delta_tsf, delay_us);
  322. }
  323. #else
  324. static inline
  325. QDF_STATUS dp_tx_compute_hw_delay_li(struct dp_soc *soc,
  326. struct dp_vdev *vdev,
  327. struct hal_tx_completion_status *ts,
  328. uint32_t *delay_us)
  329. {
  330. return QDF_STATUS_SUCCESS;
  331. }
  332. #endif
  333. #ifdef CONFIG_SAWF
  334. /**
  335. * dp_sawf_config_li - Configure sawf specific fields in tcl
  336. *
  337. * @soc: DP soc handle
  338. * @hal_tx_desc_cached: tx descriptor
  339. * @fw_metadata: firmware metadata
  340. * @vdev_id: vdev id
  341. * @nbuf: skb buffer
  342. * @msdu_info: msdu info
  343. *
  344. * Return: void
  345. */
  346. static inline
  347. void dp_sawf_config_li(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  348. uint16_t *fw_metadata, uint16_t vdev_id,
  349. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  350. {
  351. uint8_t q_id = 0;
  352. uint32_t search_index;
  353. if (!wlan_cfg_get_sawf_config(soc->wlan_cfg_ctx))
  354. return;
  355. q_id = dp_sawf_queue_id_get(nbuf);
  356. if (q_id == DP_SAWF_DEFAULT_Q_INVALID)
  357. return;
  358. msdu_info->tid = (q_id & (CDP_DATA_TID_MAX - 1));
  359. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached,
  360. (q_id & (CDP_DATA_TID_MAX - 1)));
  361. if ((q_id >= DP_SAWF_DEFAULT_QUEUE_MIN) &&
  362. (q_id < DP_SAWF_DEFAULT_QUEUE_MAX))
  363. return;
  364. dp_sawf_tcl_cmd(fw_metadata, nbuf);
  365. search_index = dp_sawf_get_search_index(soc, nbuf, vdev_id,
  366. q_id);
  367. hal_tx_desc_set_search_type_li(soc->hal_soc, hal_tx_desc_cached,
  368. HAL_TX_ADDR_INDEX_SEARCH);
  369. hal_tx_desc_set_search_index_li(soc->hal_soc, hal_tx_desc_cached,
  370. search_index);
  371. }
  372. #else
  373. static inline
  374. void dp_sawf_config_li(struct dp_soc *soc, uint32_t *hal_tx_desc_cached,
  375. uint16_t *fw_metadata, uint16_t vdev_id,
  376. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  377. {
  378. }
  379. #define dp_sawf_tx_enqueue_peer_stats(soc, tx_desc)
  380. #define dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc)
  381. #endif
  382. QDF_STATUS
  383. dp_tx_hw_enqueue_li(struct dp_soc *soc, struct dp_vdev *vdev,
  384. struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata,
  385. struct cdp_tx_exception_metadata *tx_exc_metadata,
  386. struct dp_tx_msdu_info_s *msdu_info)
  387. {
  388. void *hal_tx_desc;
  389. uint32_t *hal_tx_desc_cached;
  390. int coalesce = 0;
  391. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  392. uint8_t ring_id = tx_q->ring_id & DP_TX_QUEUE_MASK;
  393. uint8_t tid;
  394. /*
  395. * Setting it initialization statically here to avoid
  396. * a memset call jump with qdf_mem_set call
  397. */
  398. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  399. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  400. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  401. tx_exc_metadata->sec_type : vdev->sec_type);
  402. /* Return Buffer Manager ID */
  403. uint8_t bm_id = dp_tx_get_rbm_id_li(soc, ring_id);
  404. hal_ring_handle_t hal_ring_hdl = NULL;
  405. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  406. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  407. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  408. return QDF_STATUS_E_RESOURCES;
  409. }
  410. hal_tx_desc_cached = (void *)cached_desc;
  411. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  412. tx_desc->dma_addr, bm_id, tx_desc->id,
  413. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG));
  414. hal_tx_desc_set_lmac_id_li(soc->hal_soc, hal_tx_desc_cached,
  415. vdev->lmac_id);
  416. hal_tx_desc_set_search_type_li(soc->hal_soc, hal_tx_desc_cached,
  417. vdev->search_type);
  418. hal_tx_desc_set_search_index_li(soc->hal_soc, hal_tx_desc_cached,
  419. vdev->bss_ast_idx);
  420. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  421. vdev->dscp_tid_map_id);
  422. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  423. sec_type_map[sec_type]);
  424. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  425. (vdev->bss_ast_hash & 0xF));
  426. if (dp_sawf_tag_valid_get(tx_desc->nbuf)) {
  427. dp_sawf_config_li(soc, hal_tx_desc_cached, &fw_metadata,
  428. vdev->vdev_id, tx_desc->nbuf, msdu_info);
  429. dp_sawf_tx_enqueue_peer_stats(soc, tx_desc);
  430. }
  431. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  432. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  433. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  434. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  435. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  436. vdev->hal_desc_addr_search_flags);
  437. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  438. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  439. /* verify checksum offload configuration*/
  440. if ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) ==
  441. QDF_NBUF_TX_CKSUM_TCP_UDP) ||
  442. qdf_nbuf_is_tso(tx_desc->nbuf)) {
  443. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  444. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  445. }
  446. tid = msdu_info->tid;
  447. if (tid != HTT_TX_EXT_TID_INVALID)
  448. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  449. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  450. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  451. if (!dp_tx_desc_set_ktimestamp(vdev, tx_desc))
  452. dp_tx_desc_set_timestamp(tx_desc);
  453. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  454. tx_desc->length,
  455. (tx_desc->flags & DP_TX_DESC_FLAG_FRAG),
  456. (uint64_t)tx_desc->dma_addr, tx_desc->pkt_offset,
  457. tx_desc->id);
  458. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  459. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  460. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  461. "%s %d : HAL RING Access Failed -- %pK",
  462. __func__, __LINE__, hal_ring_hdl);
  463. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  464. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  465. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  466. return status;
  467. }
  468. dp_tx_clear_consumed_hw_descs(soc, hal_ring_hdl);
  469. /* Sync cached descriptor with HW */
  470. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  471. if (qdf_unlikely(!hal_tx_desc)) {
  472. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  473. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  474. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  475. dp_sawf_tx_enqueue_fail_peer_stats(soc, tx_desc);
  476. goto ring_access_fail;
  477. }
  478. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  479. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  480. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  481. coalesce = dp_tx_attempt_coalescing(soc, vdev, tx_desc, tid,
  482. msdu_info, ring_id);
  483. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  484. DP_STATS_INC(soc, tx.tcl_enq[ring_id], 1);
  485. dp_tx_update_stats(soc, tx_desc, ring_id);
  486. status = QDF_STATUS_SUCCESS;
  487. dp_tx_hw_desc_update_evt((uint8_t *)hal_tx_desc_cached,
  488. hal_ring_hdl, soc, ring_id);
  489. ring_access_fail:
  490. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, coalesce);
  491. dp_pkt_add_timestamp(vdev, QDF_PKT_TX_DRIVER_EXIT,
  492. qdf_get_log_timestamp(), tx_desc->nbuf);
  493. return status;
  494. }
  495. QDF_STATUS dp_tx_desc_pool_init_li(struct dp_soc *soc,
  496. uint32_t num_elem,
  497. uint8_t pool_id)
  498. {
  499. uint32_t id, count, page_id, offset, pool_id_32;
  500. struct dp_tx_desc_s *tx_desc;
  501. struct dp_tx_desc_pool_s *tx_desc_pool;
  502. uint16_t num_desc_per_page;
  503. tx_desc_pool = &soc->tx_desc[pool_id];
  504. tx_desc = tx_desc_pool->freelist;
  505. count = 0;
  506. pool_id_32 = (uint32_t)pool_id;
  507. num_desc_per_page = tx_desc_pool->desc_pages.num_element_per_page;
  508. while (tx_desc) {
  509. page_id = count / num_desc_per_page;
  510. offset = count % num_desc_per_page;
  511. id = ((pool_id_32 << DP_TX_DESC_ID_POOL_OS) |
  512. (page_id << DP_TX_DESC_ID_PAGE_OS) | offset);
  513. tx_desc->id = id;
  514. tx_desc->pool_id = pool_id;
  515. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  516. dp_tx_desc_set_magic(tx_desc, DP_TX_MAGIC_PATTERN_FREE);
  517. tx_desc = tx_desc->next;
  518. count++;
  519. }
  520. return QDF_STATUS_SUCCESS;
  521. }
  522. void dp_tx_desc_pool_deinit_li(struct dp_soc *soc,
  523. struct dp_tx_desc_pool_s *tx_desc_pool,
  524. uint8_t pool_id)
  525. {
  526. }
  527. QDF_STATUS dp_tx_compute_tx_delay_li(struct dp_soc *soc,
  528. struct dp_vdev *vdev,
  529. struct hal_tx_completion_status *ts,
  530. uint32_t *delay_us)
  531. {
  532. return dp_tx_compute_hw_delay_li(soc, vdev, ts, delay_us);
  533. }
  534. QDF_STATUS dp_tx_desc_pool_alloc_li(struct dp_soc *soc, uint32_t num_elem,
  535. uint8_t pool_id)
  536. {
  537. return QDF_STATUS_SUCCESS;
  538. }
  539. void dp_tx_desc_pool_free_li(struct dp_soc *soc, uint8_t pool_id)
  540. {
  541. }