dp_rings_main.c 142 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_ipa_obj_mgmt_api.h>
  20. #include <qdf_types.h>
  21. #include <qdf_lock.h>
  22. #include <qdf_net_types.h>
  23. #include <qdf_lro.h>
  24. #include <qdf_module.h>
  25. #include <hal_hw_headers.h>
  26. #include <hal_api.h>
  27. #include <hif.h>
  28. #include <htt.h>
  29. #include <wdi_event.h>
  30. #include <queue.h>
  31. #include "dp_types.h"
  32. #include "dp_rings.h"
  33. #include "dp_internal.h"
  34. #include "dp_tx.h"
  35. #include "dp_tx_desc.h"
  36. #include "dp_rx.h"
  37. #ifdef DP_RATETABLE_SUPPORT
  38. #include "dp_ratetable.h"
  39. #endif
  40. #include <cdp_txrx_handle.h>
  41. #include <wlan_cfg.h>
  42. #include <wlan_utility.h>
  43. #include "cdp_txrx_cmn_struct.h"
  44. #include "cdp_txrx_stats_struct.h"
  45. #include "cdp_txrx_cmn_reg.h"
  46. #include <qdf_util.h>
  47. #include "dp_peer.h"
  48. #include "htt_stats.h"
  49. #include "dp_htt.h"
  50. #include "htt_ppdu_stats.h"
  51. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  52. #include "cfg_ucfg_api.h"
  53. #include <wlan_module_ids.h>
  54. #ifdef WIFI_MONITOR_SUPPORT
  55. #include <dp_mon.h>
  56. #endif
  57. #ifdef WLAN_FEATURE_STATS_EXT
  58. #define INIT_RX_HW_STATS_LOCK(_soc) \
  59. qdf_spinlock_create(&(_soc)->rx_hw_stats_lock)
  60. #define DEINIT_RX_HW_STATS_LOCK(_soc) \
  61. qdf_spinlock_destroy(&(_soc)->rx_hw_stats_lock)
  62. #else
  63. #define INIT_RX_HW_STATS_LOCK(_soc) /* no op */
  64. #define DEINIT_RX_HW_STATS_LOCK(_soc) /* no op */
  65. #endif
  66. #ifdef QCA_DP_ENABLE_TX_COMP_RING4
  67. #define TXCOMP_RING4_NUM 3
  68. #else
  69. #define TXCOMP_RING4_NUM WBM2SW_TXCOMP_RING4_NUM
  70. #endif
  71. static QDF_STATUS dp_init_tx_ring_pair_by_index(struct dp_soc *soc,
  72. uint8_t index);
  73. static void dp_deinit_tx_pair_by_index(struct dp_soc *soc, int index);
  74. static void dp_free_tx_ring_pair_by_index(struct dp_soc *soc, uint8_t index);
  75. static QDF_STATUS dp_alloc_tx_ring_pair_by_index(struct dp_soc *soc,
  76. uint8_t index);
  77. /* default_dscp_tid_map - Default DSCP-TID mapping
  78. *
  79. * DSCP TID
  80. * 000000 0
  81. * 001000 1
  82. * 010000 2
  83. * 011000 3
  84. * 100000 4
  85. * 101000 5
  86. * 110000 6
  87. * 111000 7
  88. */
  89. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 1, 1, 1, 1, 1, 1, 1, 1,
  92. 2, 2, 2, 2, 2, 2, 2, 2,
  93. 3, 3, 3, 3, 3, 3, 3, 3,
  94. 4, 4, 4, 4, 4, 4, 4, 4,
  95. 5, 5, 5, 5, 5, 5, 5, 5,
  96. 6, 6, 6, 6, 6, 6, 6, 6,
  97. 7, 7, 7, 7, 7, 7, 7, 7,
  98. };
  99. /* default_pcp_tid_map - Default PCP-TID mapping
  100. *
  101. * PCP TID
  102. * 000 0
  103. * 001 1
  104. * 010 2
  105. * 011 3
  106. * 100 4
  107. * 101 5
  108. * 110 6
  109. * 111 7
  110. */
  111. static uint8_t default_pcp_tid_map[PCP_TID_MAP_MAX] = {
  112. 0, 1, 2, 3, 4, 5, 6, 7,
  113. };
  114. uint8_t
  115. dp_cpu_ring_map[DP_NSS_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS_MAX] = {
  116. {0x0, 0x1, 0x2, 0x0, 0x0, 0x1, 0x2, 0x0, 0x0, 0x1, 0x2},
  117. {0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1, 0x2, 0x1},
  118. {0x0, 0x2, 0x0, 0x2, 0x0, 0x2, 0x0, 0x2, 0x0, 0x2, 0x0},
  119. {0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x2},
  120. {0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3},
  121. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  122. {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1}
  123. #endif
  124. };
  125. qdf_export_symbol(dp_cpu_ring_map);
  126. /**
  127. * dp_soc_ring_if_nss_offloaded() - find if ring is offloaded to NSS
  128. * @soc: DP soc handle
  129. * @ring_type: ring type
  130. * @ring_num: ring_num
  131. *
  132. * Return: 0 if the ring is not offloaded, non-0 if it is offloaded
  133. */
  134. static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc,
  135. enum hal_ring_type ring_type,
  136. int ring_num)
  137. {
  138. uint8_t nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  139. uint8_t status = 0;
  140. switch (ring_type) {
  141. case WBM2SW_RELEASE:
  142. case REO_DST:
  143. case RXDMA_BUF:
  144. case REO_EXCEPTION:
  145. status = ((nss_config) & (1 << ring_num));
  146. break;
  147. default:
  148. break;
  149. }
  150. return status;
  151. }
  152. /* MCL specific functions */
  153. #if defined(DP_CON_MON)
  154. #ifdef DP_CON_MON_MSI_ENABLED
  155. /**
  156. * dp_soc_get_mon_mask_for_interrupt_mode() - get mon mode mask for intr mode
  157. * @soc: pointer to dp_soc handle
  158. * @intr_ctx_num: interrupt context number for which mon mask is needed
  159. *
  160. * For MCL, monitor mode rings are being processed in timer contexts (polled).
  161. * This function is returning 0, since in interrupt mode(softirq based RX),
  162. * we donot want to process monitor mode rings in a softirq.
  163. *
  164. * So, in case packet log is enabled for SAP/STA/P2P modes,
  165. * regular interrupt processing will not process monitor mode rings. It would be
  166. * done in a separate timer context.
  167. *
  168. * Return: 0
  169. */
  170. static inline uint32_t
  171. dp_soc_get_mon_mask_for_interrupt_mode(struct dp_soc *soc, int intr_ctx_num)
  172. {
  173. return wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  174. }
  175. #else
  176. /**
  177. * dp_soc_get_mon_mask_for_interrupt_mode() - get mon mode mask for intr mode
  178. * @soc: pointer to dp_soc handle
  179. * @intr_ctx_num: interrupt context number for which mon mask is needed
  180. *
  181. * For MCL, monitor mode rings are being processed in timer contexts (polled).
  182. * This function is returning 0, since in interrupt mode(softirq based RX),
  183. * we donot want to process monitor mode rings in a softirq.
  184. *
  185. * So, in case packet log is enabled for SAP/STA/P2P modes,
  186. * regular interrupt processing will not process monitor mode rings. It would be
  187. * done in a separate timer context.
  188. *
  189. * Return: 0
  190. */
  191. static inline uint32_t
  192. dp_soc_get_mon_mask_for_interrupt_mode(struct dp_soc *soc, int intr_ctx_num)
  193. {
  194. return 0;
  195. }
  196. #endif
  197. #else
  198. /**
  199. * dp_soc_get_mon_mask_for_interrupt_mode() - get mon mode mask for intr mode
  200. * @soc: pointer to dp_soc handle
  201. * @intr_ctx_num: interrupt context number for which mon mask is needed
  202. *
  203. * Return: mon mask value
  204. */
  205. static inline
  206. uint32_t dp_soc_get_mon_mask_for_interrupt_mode(struct dp_soc *soc,
  207. int intr_ctx_num)
  208. {
  209. return wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  210. }
  211. void dp_soc_reset_mon_intr_mask(struct dp_soc *soc)
  212. {
  213. int i;
  214. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  215. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  216. soc->intr_ctx[i].host2rxdma_mon_ring_mask = 0;
  217. }
  218. }
  219. qdf_export_symbol(dp_soc_reset_mon_intr_mask);
  220. void dp_service_lmac_rings(void *arg)
  221. {
  222. struct dp_soc *soc = (struct dp_soc *)arg;
  223. int ring = 0, i;
  224. struct dp_pdev *pdev = NULL;
  225. union dp_rx_desc_list_elem_t *desc_list = NULL;
  226. union dp_rx_desc_list_elem_t *tail = NULL;
  227. /* Process LMAC interrupts */
  228. for (ring = 0 ; ring < MAX_NUM_LMAC_HW; ring++) {
  229. int mac_for_pdev = ring;
  230. struct dp_srng *rx_refill_buf_ring;
  231. pdev = dp_get_pdev_for_lmac_id(soc, mac_for_pdev);
  232. if (!pdev)
  233. continue;
  234. rx_refill_buf_ring = &soc->rx_refill_buf_ring[mac_for_pdev];
  235. dp_monitor_process(soc, NULL, mac_for_pdev,
  236. QCA_NAPI_BUDGET);
  237. for (i = 0;
  238. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  239. dp_rxdma_err_process(&soc->intr_ctx[i], soc,
  240. mac_for_pdev,
  241. QCA_NAPI_BUDGET);
  242. if (!dp_soc_ring_if_nss_offloaded(soc, RXDMA_BUF,
  243. mac_for_pdev))
  244. dp_rx_buffers_replenish(soc, mac_for_pdev,
  245. rx_refill_buf_ring,
  246. &soc->rx_desc_buf[mac_for_pdev],
  247. 0, &desc_list, &tail, false);
  248. }
  249. qdf_timer_mod(&soc->lmac_reap_timer, DP_INTR_POLL_TIMER_MS);
  250. }
  251. #endif
  252. /**
  253. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  254. * @ring_num: ring num of the ring being queried
  255. * @grp_mask: the grp_mask array for the ring type in question.
  256. *
  257. * The grp_mask array is indexed by group number and the bit fields correspond
  258. * to ring numbers. We are finding which interrupt group a ring belongs to.
  259. *
  260. * Return: the index in the grp_mask array with the ring number.
  261. * -QDF_STATUS_E_NOENT if no entry is found
  262. */
  263. static int dp_srng_find_ring_in_mask(int ring_num, uint8_t *grp_mask)
  264. {
  265. int ext_group_num;
  266. uint8_t mask = 1 << ring_num;
  267. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  268. ext_group_num++) {
  269. if (mask & grp_mask[ext_group_num])
  270. return ext_group_num;
  271. }
  272. return -QDF_STATUS_E_NOENT;
  273. }
  274. /**
  275. * dp_is_msi_group_number_invalid() - check msi_group_number valid or not
  276. * @soc: dp_soc
  277. * @msi_group_number: MSI group number.
  278. * @msi_data_count: MSI data count.
  279. *
  280. * Return: true if msi_group_number is invalid.
  281. */
  282. static bool dp_is_msi_group_number_invalid(struct dp_soc *soc,
  283. int msi_group_number,
  284. int msi_data_count)
  285. {
  286. if (soc && soc->osdev && soc->osdev->dev &&
  287. pld_is_one_msi(soc->osdev->dev))
  288. return false;
  289. return msi_group_number > msi_data_count;
  290. }
  291. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  292. /**
  293. * dp_is_reo_ring_num_in_nf_grp1() - Check if the current reo ring is part of
  294. * rx_near_full_grp1 mask
  295. * @soc: Datapath SoC Handle
  296. * @ring_num: REO ring number
  297. *
  298. * Return: 1 if the ring_num belongs to reo_nf_grp1,
  299. * 0, otherwise.
  300. */
  301. static inline int
  302. dp_is_reo_ring_num_in_nf_grp1(struct dp_soc *soc, int ring_num)
  303. {
  304. return (WLAN_CFG_RX_NEAR_FULL_IRQ_MASK_1 & (1 << ring_num));
  305. }
  306. /**
  307. * dp_is_reo_ring_num_in_nf_grp2() - Check if the current reo ring is part of
  308. * rx_near_full_grp2 mask
  309. * @soc: Datapath SoC Handle
  310. * @ring_num: REO ring number
  311. *
  312. * Return: 1 if the ring_num belongs to reo_nf_grp2,
  313. * 0, otherwise.
  314. */
  315. static inline int
  316. dp_is_reo_ring_num_in_nf_grp2(struct dp_soc *soc, int ring_num)
  317. {
  318. return (WLAN_CFG_RX_NEAR_FULL_IRQ_MASK_2 & (1 << ring_num));
  319. }
  320. /**
  321. * dp_srng_get_near_full_irq_mask() - Get near-full irq mask for a particular
  322. * ring type and number
  323. * @soc: Datapath SoC handle
  324. * @ring_type: SRNG type
  325. * @ring_num: ring num
  326. *
  327. * Return: near-full irq mask pointer
  328. */
  329. static inline
  330. uint8_t *dp_srng_get_near_full_irq_mask(struct dp_soc *soc,
  331. enum hal_ring_type ring_type,
  332. int ring_num)
  333. {
  334. struct wlan_cfg_dp_soc_ctxt *cfg_ctx = soc->wlan_cfg_ctx;
  335. uint8_t wbm2_sw_rx_rel_ring_id;
  336. uint8_t *nf_irq_mask = NULL;
  337. switch (ring_type) {
  338. case WBM2SW_RELEASE:
  339. wbm2_sw_rx_rel_ring_id =
  340. wlan_cfg_get_rx_rel_ring_id(cfg_ctx);
  341. if (ring_num != wbm2_sw_rx_rel_ring_id) {
  342. nf_irq_mask = &soc->wlan_cfg_ctx->
  343. int_tx_ring_near_full_irq_mask[0];
  344. }
  345. break;
  346. case REO_DST:
  347. if (dp_is_reo_ring_num_in_nf_grp1(soc, ring_num))
  348. nf_irq_mask =
  349. &soc->wlan_cfg_ctx->int_rx_ring_near_full_irq_1_mask[0];
  350. else if (dp_is_reo_ring_num_in_nf_grp2(soc, ring_num))
  351. nf_irq_mask =
  352. &soc->wlan_cfg_ctx->int_rx_ring_near_full_irq_2_mask[0];
  353. else
  354. qdf_assert(0);
  355. break;
  356. default:
  357. break;
  358. }
  359. return nf_irq_mask;
  360. }
  361. /**
  362. * dp_srng_set_msi2_ring_params() - Set the msi2 addr/data in the ring params
  363. * @soc: Datapath SoC handle
  364. * @ring_params: srng params handle
  365. * @msi2_addr: MSI2 addr to be set for the SRNG
  366. * @msi2_data: MSI2 data to be set for the SRNG
  367. *
  368. * Return: None
  369. */
  370. static inline
  371. void dp_srng_set_msi2_ring_params(struct dp_soc *soc,
  372. struct hal_srng_params *ring_params,
  373. qdf_dma_addr_t msi2_addr,
  374. uint32_t msi2_data)
  375. {
  376. ring_params->msi2_addr = msi2_addr;
  377. ring_params->msi2_data = msi2_data;
  378. }
  379. /**
  380. * dp_srng_msi2_setup() - Setup MSI2 details for near full IRQ of an SRNG
  381. * @soc: Datapath SoC handle
  382. * @ring_params: ring_params for SRNG
  383. * @ring_type: SENG type
  384. * @ring_num: ring number for the SRNG
  385. * @nf_msi_grp_num: near full msi group number
  386. *
  387. * Return: None
  388. */
  389. static inline void
  390. dp_srng_msi2_setup(struct dp_soc *soc,
  391. struct hal_srng_params *ring_params,
  392. int ring_type, int ring_num, int nf_msi_grp_num)
  393. {
  394. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  395. int msi_data_count, ret;
  396. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  397. &msi_data_count, &msi_data_start,
  398. &msi_irq_start);
  399. if (ret)
  400. return;
  401. if (nf_msi_grp_num < 0) {
  402. dp_init_info("%pK: ring near full IRQ not part of an ext_group; ring_type: %d,ring_num %d",
  403. soc, ring_type, ring_num);
  404. ring_params->msi2_addr = 0;
  405. ring_params->msi2_data = 0;
  406. return;
  407. }
  408. if (dp_is_msi_group_number_invalid(soc, nf_msi_grp_num,
  409. msi_data_count)) {
  410. dp_init_warn("%pK: 2 msi_groups will share an msi for near full IRQ; msi_group_num %d",
  411. soc, nf_msi_grp_num);
  412. QDF_ASSERT(0);
  413. }
  414. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  415. ring_params->nf_irq_support = 1;
  416. ring_params->msi2_addr = addr_low;
  417. ring_params->msi2_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  418. ring_params->msi2_data = (nf_msi_grp_num % msi_data_count)
  419. + msi_data_start;
  420. ring_params->flags |= HAL_SRNG_MSI_INTR;
  421. }
  422. /* Percentage of ring entries considered as nearly full */
  423. #define DP_NF_HIGH_THRESH_PERCENTAGE 75
  424. /* Percentage of ring entries considered as critically full */
  425. #define DP_NF_CRIT_THRESH_PERCENTAGE 90
  426. /* Percentage of ring entries considered as safe threshold */
  427. #define DP_NF_SAFE_THRESH_PERCENTAGE 50
  428. /**
  429. * dp_srng_configure_nf_interrupt_thresholds() - Configure the thresholds for
  430. * near full irq
  431. * @soc: Datapath SoC handle
  432. * @ring_params: ring params for SRNG
  433. * @ring_type: ring type
  434. */
  435. static inline void
  436. dp_srng_configure_nf_interrupt_thresholds(struct dp_soc *soc,
  437. struct hal_srng_params *ring_params,
  438. int ring_type)
  439. {
  440. if (ring_params->nf_irq_support) {
  441. ring_params->high_thresh = (ring_params->num_entries *
  442. DP_NF_HIGH_THRESH_PERCENTAGE) / 100;
  443. ring_params->crit_thresh = (ring_params->num_entries *
  444. DP_NF_CRIT_THRESH_PERCENTAGE) / 100;
  445. ring_params->safe_thresh = (ring_params->num_entries *
  446. DP_NF_SAFE_THRESH_PERCENTAGE) /100;
  447. }
  448. }
  449. /**
  450. * dp_srng_set_nf_thresholds() - Set the near full thresholds to srng data
  451. * structure from the ring params
  452. * @soc: Datapath SoC handle
  453. * @srng: SRNG handle
  454. * @ring_params: ring params for a SRNG
  455. *
  456. * Return: None
  457. */
  458. static inline void
  459. dp_srng_set_nf_thresholds(struct dp_soc *soc, struct dp_srng *srng,
  460. struct hal_srng_params *ring_params)
  461. {
  462. srng->crit_thresh = ring_params->crit_thresh;
  463. srng->safe_thresh = ring_params->safe_thresh;
  464. }
  465. #else
  466. static inline
  467. uint8_t *dp_srng_get_near_full_irq_mask(struct dp_soc *soc,
  468. enum hal_ring_type ring_type,
  469. int ring_num)
  470. {
  471. return NULL;
  472. }
  473. static inline
  474. void dp_srng_set_msi2_ring_params(struct dp_soc *soc,
  475. struct hal_srng_params *ring_params,
  476. qdf_dma_addr_t msi2_addr,
  477. uint32_t msi2_data)
  478. {
  479. }
  480. static inline void
  481. dp_srng_msi2_setup(struct dp_soc *soc,
  482. struct hal_srng_params *ring_params,
  483. int ring_type, int ring_num, int nf_msi_grp_num)
  484. {
  485. }
  486. static inline void
  487. dp_srng_configure_nf_interrupt_thresholds(struct dp_soc *soc,
  488. struct hal_srng_params *ring_params,
  489. int ring_type)
  490. {
  491. }
  492. static inline void
  493. dp_srng_set_nf_thresholds(struct dp_soc *soc, struct dp_srng *srng,
  494. struct hal_srng_params *ring_params)
  495. {
  496. }
  497. #endif
  498. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  499. enum hal_ring_type ring_type,
  500. int ring_num,
  501. int *reg_msi_grp_num,
  502. bool nf_irq_support,
  503. int *nf_msi_grp_num)
  504. {
  505. struct wlan_cfg_dp_soc_ctxt *cfg_ctx = soc->wlan_cfg_ctx;
  506. uint8_t *grp_mask, *nf_irq_mask = NULL;
  507. bool nf_irq_enabled = false;
  508. uint8_t wbm2_sw_rx_rel_ring_id;
  509. switch (ring_type) {
  510. case WBM2SW_RELEASE:
  511. wbm2_sw_rx_rel_ring_id =
  512. wlan_cfg_get_rx_rel_ring_id(cfg_ctx);
  513. if (ring_num == wbm2_sw_rx_rel_ring_id) {
  514. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  515. grp_mask = &cfg_ctx->int_rx_wbm_rel_ring_mask[0];
  516. ring_num = 0;
  517. } else if (ring_num == WBM2_SW_PPE_REL_RING_ID) {
  518. grp_mask = &cfg_ctx->int_ppeds_wbm_release_ring_mask[0];
  519. ring_num = 0;
  520. } else { /* dp_tx_comp_handler - soc->tx_comp_ring */
  521. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  522. nf_irq_mask = dp_srng_get_near_full_irq_mask(soc,
  523. ring_type,
  524. ring_num);
  525. if (nf_irq_mask)
  526. nf_irq_enabled = true;
  527. /*
  528. * Using ring 4 as 4th tx completion ring since ring 3
  529. * is Rx error ring
  530. */
  531. if (ring_num == WBM2SW_TXCOMP_RING4_NUM)
  532. ring_num = TXCOMP_RING4_NUM;
  533. }
  534. break;
  535. case REO_EXCEPTION:
  536. /* dp_rx_err_process - &soc->reo_exception_ring */
  537. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  538. break;
  539. case REO_DST:
  540. /* dp_rx_process - soc->reo_dest_ring */
  541. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  542. nf_irq_mask = dp_srng_get_near_full_irq_mask(soc, ring_type,
  543. ring_num);
  544. if (nf_irq_mask)
  545. nf_irq_enabled = true;
  546. break;
  547. case REO_STATUS:
  548. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  549. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  550. break;
  551. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  552. case RXDMA_MONITOR_STATUS:
  553. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  554. case RXDMA_MONITOR_DST:
  555. /* dp_mon_process */
  556. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  557. break;
  558. case TX_MONITOR_DST:
  559. /* dp_tx_mon_process */
  560. grp_mask = &soc->wlan_cfg_ctx->int_tx_mon_ring_mask[0];
  561. break;
  562. case RXDMA_DST:
  563. /* dp_rxdma_err_process */
  564. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  565. break;
  566. case RXDMA_BUF:
  567. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  568. break;
  569. case RXDMA_MONITOR_BUF:
  570. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_mon_ring_mask[0];
  571. break;
  572. case TX_MONITOR_BUF:
  573. grp_mask = &soc->wlan_cfg_ctx->int_host2txmon_ring_mask[0];
  574. break;
  575. case REO2PPE:
  576. grp_mask = &soc->wlan_cfg_ctx->int_reo2ppe_ring_mask[0];
  577. break;
  578. case PPE2TCL:
  579. grp_mask = &soc->wlan_cfg_ctx->int_ppe2tcl_ring_mask[0];
  580. break;
  581. case TCL_DATA:
  582. /* CMD_CREDIT_RING is used as command in 8074 and credit in 9000 */
  583. case TCL_CMD_CREDIT:
  584. case REO_CMD:
  585. case SW2WBM_RELEASE:
  586. case WBM_IDLE_LINK:
  587. /* normally empty SW_TO_HW rings */
  588. return -QDF_STATUS_E_NOENT;
  589. break;
  590. case TCL_STATUS:
  591. case REO_REINJECT:
  592. /* misc unused rings */
  593. return -QDF_STATUS_E_NOENT;
  594. break;
  595. case CE_SRC:
  596. case CE_DST:
  597. case CE_DST_STATUS:
  598. /* CE_rings - currently handled by hif */
  599. default:
  600. return -QDF_STATUS_E_NOENT;
  601. break;
  602. }
  603. *reg_msi_grp_num = dp_srng_find_ring_in_mask(ring_num, grp_mask);
  604. if (nf_irq_support && nf_irq_enabled) {
  605. *nf_msi_grp_num = dp_srng_find_ring_in_mask(ring_num,
  606. nf_irq_mask);
  607. }
  608. return QDF_STATUS_SUCCESS;
  609. }
  610. /**
  611. * dp_get_num_msi_available()- API to get number of MSIs available
  612. * @soc: DP soc Handle
  613. * @interrupt_mode: Mode of interrupts
  614. *
  615. * Return: Number of MSIs available or 0 in case of integrated
  616. */
  617. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  618. static int dp_get_num_msi_available(struct dp_soc *soc, int interrupt_mode)
  619. {
  620. return 0;
  621. }
  622. #else
  623. static int dp_get_num_msi_available(struct dp_soc *soc, int interrupt_mode)
  624. {
  625. int msi_data_count;
  626. int msi_data_start;
  627. int msi_irq_start;
  628. int ret;
  629. if (interrupt_mode == DP_INTR_INTEGRATED) {
  630. return 0;
  631. } else if (interrupt_mode == DP_INTR_MSI || interrupt_mode ==
  632. DP_INTR_POLL) {
  633. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  634. &msi_data_count,
  635. &msi_data_start,
  636. &msi_irq_start);
  637. if (ret) {
  638. qdf_err("Unable to get DP MSI assignment %d",
  639. interrupt_mode);
  640. return -EINVAL;
  641. }
  642. return msi_data_count;
  643. }
  644. qdf_err("Interrupt mode invalid %d", interrupt_mode);
  645. return -EINVAL;
  646. }
  647. #endif
  648. #if defined(IPA_OFFLOAD) && defined(IPA_WDI3_VLAN_SUPPORT)
  649. static void
  650. dp_ipa_vlan_srng_msi_setup(struct hal_srng_params *ring_params, int ring_type,
  651. int ring_num)
  652. {
  653. if (wlan_ipa_is_vlan_enabled()) {
  654. if ((ring_type == REO_DST) &&
  655. (ring_num == IPA_ALT_REO_DEST_RING_IDX)) {
  656. ring_params->msi_addr = 0;
  657. ring_params->msi_data = 0;
  658. ring_params->flags &= ~HAL_SRNG_MSI_INTR;
  659. }
  660. }
  661. }
  662. #else
  663. static inline void
  664. dp_ipa_vlan_srng_msi_setup(struct hal_srng_params *ring_params, int ring_type,
  665. int ring_num)
  666. {
  667. }
  668. #endif
  669. static void dp_srng_msi_setup(struct dp_soc *soc, struct dp_srng *srng,
  670. struct hal_srng_params *ring_params,
  671. int ring_type, int ring_num)
  672. {
  673. int reg_msi_grp_num;
  674. /*
  675. * nf_msi_grp_num needs to be initialized with negative value,
  676. * to avoid configuring near-full msi for WBM2SW3 ring
  677. */
  678. int nf_msi_grp_num = -1;
  679. int msi_data_count;
  680. int ret;
  681. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  682. bool nf_irq_support;
  683. int vector;
  684. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  685. &msi_data_count, &msi_data_start,
  686. &msi_irq_start);
  687. if (ret)
  688. return;
  689. nf_irq_support = hal_srng_is_near_full_irq_supported(soc->hal_soc,
  690. ring_type,
  691. ring_num);
  692. ret = dp_srng_calculate_msi_group(soc, ring_type, ring_num,
  693. &reg_msi_grp_num,
  694. nf_irq_support,
  695. &nf_msi_grp_num);
  696. if (ret < 0) {
  697. dp_init_info("%pK: ring not part of an ext_group; ring_type: %d,ring_num %d",
  698. soc, ring_type, ring_num);
  699. ring_params->msi_addr = 0;
  700. ring_params->msi_data = 0;
  701. dp_srng_set_msi2_ring_params(soc, ring_params, 0, 0);
  702. return;
  703. }
  704. if (reg_msi_grp_num < 0) {
  705. dp_init_info("%pK: ring not part of an ext_group; ring_type: %d,ring_num %d",
  706. soc, ring_type, ring_num);
  707. ring_params->msi_addr = 0;
  708. ring_params->msi_data = 0;
  709. goto configure_msi2;
  710. }
  711. if (dp_is_msi_group_number_invalid(soc, reg_msi_grp_num,
  712. msi_data_count)) {
  713. dp_init_warn("%pK: 2 msi_groups will share an msi; msi_group_num %d",
  714. soc, reg_msi_grp_num);
  715. QDF_ASSERT(0);
  716. }
  717. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  718. ring_params->msi_addr = addr_low;
  719. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  720. ring_params->msi_data = (reg_msi_grp_num % msi_data_count)
  721. + msi_data_start;
  722. ring_params->flags |= HAL_SRNG_MSI_INTR;
  723. dp_ipa_vlan_srng_msi_setup(ring_params, ring_type, ring_num);
  724. dp_debug("ring type %u ring_num %u msi->data %u msi_addr %llx",
  725. ring_type, ring_num, ring_params->msi_data,
  726. (uint64_t)ring_params->msi_addr);
  727. vector = msi_irq_start + (reg_msi_grp_num % msi_data_count);
  728. /*
  729. * During umac reset ppeds interrupts free is not called.
  730. * Avoid registering interrupts again.
  731. *
  732. */
  733. if (dp_check_umac_reset_in_progress(soc))
  734. goto configure_msi2;
  735. if (soc->arch_ops.dp_register_ppeds_interrupts)
  736. if (soc->arch_ops.dp_register_ppeds_interrupts(soc, srng,
  737. vector,
  738. ring_type,
  739. ring_num))
  740. return;
  741. configure_msi2:
  742. if (!nf_irq_support) {
  743. dp_srng_set_msi2_ring_params(soc, ring_params, 0, 0);
  744. return;
  745. }
  746. dp_srng_msi2_setup(soc, ring_params, ring_type, ring_num,
  747. nf_msi_grp_num);
  748. }
  749. /**
  750. * dp_srng_configure_pointer_update_thresholds() - Retrieve pointer
  751. * update threshold value from wlan_cfg_ctx
  752. * @soc: device handle
  753. * @ring_params: per ring specific parameters
  754. * @ring_type: Ring type
  755. * @ring_num: Ring number for a given ring type
  756. * @num_entries: number of entries to fill
  757. *
  758. * Fill the ring params with the pointer update threshold
  759. * configuration parameters available in wlan_cfg_ctx
  760. *
  761. * Return: None
  762. */
  763. static void
  764. dp_srng_configure_pointer_update_thresholds(
  765. struct dp_soc *soc,
  766. struct hal_srng_params *ring_params,
  767. int ring_type, int ring_num,
  768. int num_entries)
  769. {
  770. if (ring_type == REO_DST) {
  771. ring_params->pointer_timer_threshold =
  772. wlan_cfg_get_pointer_timer_threshold_rx(
  773. soc->wlan_cfg_ctx);
  774. ring_params->pointer_num_threshold =
  775. wlan_cfg_get_pointer_num_threshold_rx(
  776. soc->wlan_cfg_ctx);
  777. }
  778. }
  779. #ifdef WLAN_DP_PER_RING_TYPE_CONFIG
  780. /**
  781. * dp_srng_configure_interrupt_thresholds() - Retrieve interrupt
  782. * threshold values from the wlan_srng_cfg table for each ring type
  783. * @soc: device handle
  784. * @ring_params: per ring specific parameters
  785. * @ring_type: Ring type
  786. * @ring_num: Ring number for a given ring type
  787. * @num_entries: number of entries to fill
  788. *
  789. * Fill the ring params with the interrupt threshold
  790. * configuration parameters available in the per ring type wlan_srng_cfg
  791. * table.
  792. *
  793. * Return: None
  794. */
  795. static void
  796. dp_srng_configure_interrupt_thresholds(struct dp_soc *soc,
  797. struct hal_srng_params *ring_params,
  798. int ring_type, int ring_num,
  799. int num_entries)
  800. {
  801. uint8_t wbm2_sw_rx_rel_ring_id;
  802. wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc->wlan_cfg_ctx);
  803. if (ring_type == REO_DST) {
  804. ring_params->intr_timer_thres_us =
  805. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  806. ring_params->intr_batch_cntr_thres_entries =
  807. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  808. } else if (ring_type == WBM2SW_RELEASE &&
  809. (ring_num == wbm2_sw_rx_rel_ring_id)) {
  810. ring_params->intr_timer_thres_us =
  811. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  812. ring_params->intr_batch_cntr_thres_entries =
  813. wlan_cfg_get_int_batch_threshold_other(soc->wlan_cfg_ctx);
  814. } else {
  815. ring_params->intr_timer_thres_us =
  816. soc->wlan_srng_cfg[ring_type].timer_threshold;
  817. ring_params->intr_batch_cntr_thres_entries =
  818. soc->wlan_srng_cfg[ring_type].batch_count_threshold;
  819. }
  820. ring_params->low_threshold =
  821. soc->wlan_srng_cfg[ring_type].low_threshold;
  822. if (ring_params->low_threshold)
  823. ring_params->flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  824. dp_srng_configure_nf_interrupt_thresholds(soc, ring_params, ring_type);
  825. }
  826. #else
  827. static void
  828. dp_srng_configure_interrupt_thresholds(struct dp_soc *soc,
  829. struct hal_srng_params *ring_params,
  830. int ring_type, int ring_num,
  831. int num_entries)
  832. {
  833. uint8_t wbm2_sw_rx_rel_ring_id;
  834. bool rx_refill_lt_disable;
  835. wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc->wlan_cfg_ctx);
  836. if (ring_type == REO_DST || ring_type == REO2PPE) {
  837. ring_params->intr_timer_thres_us =
  838. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  839. ring_params->intr_batch_cntr_thres_entries =
  840. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  841. } else if (ring_type == WBM2SW_RELEASE &&
  842. (ring_num < wbm2_sw_rx_rel_ring_id ||
  843. ring_num == WBM2SW_TXCOMP_RING4_NUM ||
  844. ring_num == WBM2_SW_PPE_REL_RING_ID)) {
  845. ring_params->intr_timer_thres_us =
  846. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  847. ring_params->intr_batch_cntr_thres_entries =
  848. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  849. } else if (ring_type == RXDMA_BUF) {
  850. rx_refill_lt_disable =
  851. wlan_cfg_get_dp_soc_rxdma_refill_lt_disable
  852. (soc->wlan_cfg_ctx);
  853. ring_params->intr_timer_thres_us =
  854. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  855. if (!rx_refill_lt_disable) {
  856. ring_params->low_threshold = num_entries >> 3;
  857. ring_params->flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  858. ring_params->intr_batch_cntr_thres_entries = 0;
  859. }
  860. } else {
  861. ring_params->intr_timer_thres_us =
  862. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  863. ring_params->intr_batch_cntr_thres_entries =
  864. wlan_cfg_get_int_batch_threshold_other(soc->wlan_cfg_ctx);
  865. }
  866. /* These rings donot require interrupt to host. Make them zero */
  867. switch (ring_type) {
  868. case REO_REINJECT:
  869. case REO_CMD:
  870. case TCL_DATA:
  871. case TCL_CMD_CREDIT:
  872. case TCL_STATUS:
  873. case WBM_IDLE_LINK:
  874. case SW2WBM_RELEASE:
  875. case SW2RXDMA_NEW:
  876. ring_params->intr_timer_thres_us = 0;
  877. ring_params->intr_batch_cntr_thres_entries = 0;
  878. break;
  879. case PPE2TCL:
  880. ring_params->intr_timer_thres_us =
  881. wlan_cfg_get_int_timer_threshold_ppe2tcl(soc->wlan_cfg_ctx);
  882. ring_params->intr_batch_cntr_thres_entries =
  883. wlan_cfg_get_int_batch_threshold_ppe2tcl(soc->wlan_cfg_ctx);
  884. break;
  885. }
  886. /* Enable low threshold interrupts for rx buffer rings (regular and
  887. * monitor buffer rings.
  888. * TODO: See if this is required for any other ring
  889. */
  890. if ((ring_type == RXDMA_MONITOR_BUF) ||
  891. (ring_type == RXDMA_MONITOR_STATUS ||
  892. (ring_type == TX_MONITOR_BUF))) {
  893. /* TODO: Setting low threshold to 1/8th of ring size
  894. * see if this needs to be configurable
  895. */
  896. ring_params->low_threshold = num_entries >> 3;
  897. ring_params->intr_timer_thres_us =
  898. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  899. ring_params->flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  900. ring_params->intr_batch_cntr_thres_entries = 0;
  901. }
  902. /* During initialisation monitor rings are only filled with
  903. * MON_BUF_MIN_ENTRIES entries. So low threshold needs to be set to
  904. * a value less than that. Low threshold value is reconfigured again
  905. * to 1/8th of the ring size when monitor vap is created.
  906. */
  907. if (ring_type == RXDMA_MONITOR_BUF)
  908. ring_params->low_threshold = MON_BUF_MIN_ENTRIES >> 1;
  909. /* In case of PCI chipsets, we dont have PPDU end interrupts,
  910. * so MONITOR STATUS ring is reaped by receiving MSI from srng.
  911. * Keep batch threshold as 8 so that interrupt is received for
  912. * every 4 packets in MONITOR_STATUS ring
  913. */
  914. if ((ring_type == RXDMA_MONITOR_STATUS) &&
  915. (soc->intr_mode == DP_INTR_MSI))
  916. ring_params->intr_batch_cntr_thres_entries = 4;
  917. }
  918. #endif
  919. #ifdef DISABLE_MON_RING_MSI_CFG
  920. /**
  921. * dp_skip_msi_cfg() - Check if msi cfg has to be skipped for ring_type
  922. * @soc: DP SoC context
  923. * @ring_type: sring type
  924. *
  925. * Return: True if msi cfg should be skipped for srng type else false
  926. */
  927. static inline bool dp_skip_msi_cfg(struct dp_soc *soc, int ring_type)
  928. {
  929. if (ring_type == RXDMA_MONITOR_STATUS)
  930. return true;
  931. return false;
  932. }
  933. #else
  934. #ifdef DP_CON_MON_MSI_ENABLED
  935. static inline bool dp_skip_msi_cfg(struct dp_soc *soc, int ring_type)
  936. {
  937. if (soc->cdp_soc.ol_ops->get_con_mode &&
  938. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE) {
  939. if (ring_type == REO_DST || ring_type == RXDMA_DST)
  940. return true;
  941. } else if (ring_type == RXDMA_MONITOR_STATUS) {
  942. return true;
  943. }
  944. return false;
  945. }
  946. #else
  947. static inline bool dp_skip_msi_cfg(struct dp_soc *soc, int ring_type)
  948. {
  949. return false;
  950. }
  951. #endif /* DP_CON_MON_MSI_ENABLED */
  952. #endif /* DISABLE_MON_RING_MSI_CFG */
  953. QDF_STATUS dp_srng_init_idx(struct dp_soc *soc, struct dp_srng *srng,
  954. int ring_type, int ring_num, int mac_id,
  955. uint32_t idx)
  956. {
  957. bool idle_check;
  958. hal_soc_handle_t hal_soc = soc->hal_soc;
  959. struct hal_srng_params ring_params;
  960. if (srng->hal_srng) {
  961. dp_init_err("%pK: Ring type: %d, num:%d is already initialized",
  962. soc, ring_type, ring_num);
  963. return QDF_STATUS_SUCCESS;
  964. }
  965. /* memset the srng ring to zero */
  966. qdf_mem_zero(srng->base_vaddr_unaligned, srng->alloc_size);
  967. qdf_mem_zero(&ring_params, sizeof(struct hal_srng_params));
  968. ring_params.ring_base_paddr = srng->base_paddr_aligned;
  969. ring_params.ring_base_vaddr = srng->base_vaddr_aligned;
  970. ring_params.num_entries = srng->num_entries;
  971. dp_info("Ring type: %d, num:%d vaddr %pK paddr %pK entries %u",
  972. ring_type, ring_num,
  973. (void *)ring_params.ring_base_vaddr,
  974. (void *)ring_params.ring_base_paddr,
  975. ring_params.num_entries);
  976. if (soc->intr_mode == DP_INTR_MSI && !dp_skip_msi_cfg(soc, ring_type)) {
  977. dp_srng_msi_setup(soc, srng, &ring_params, ring_type, ring_num);
  978. dp_verbose_debug("Using MSI for ring_type: %d, ring_num %d",
  979. ring_type, ring_num);
  980. } else {
  981. ring_params.msi_data = 0;
  982. ring_params.msi_addr = 0;
  983. dp_srng_set_msi2_ring_params(soc, &ring_params, 0, 0);
  984. dp_verbose_debug("Skipping MSI for ring_type: %d, ring_num %d",
  985. ring_type, ring_num);
  986. }
  987. dp_srng_configure_interrupt_thresholds(soc, &ring_params,
  988. ring_type, ring_num,
  989. srng->num_entries);
  990. dp_srng_set_nf_thresholds(soc, srng, &ring_params);
  991. dp_srng_configure_pointer_update_thresholds(soc, &ring_params,
  992. ring_type, ring_num,
  993. srng->num_entries);
  994. if (srng->cached)
  995. ring_params.flags |= HAL_SRNG_CACHED_DESC;
  996. idle_check = dp_check_umac_reset_in_progress(soc);
  997. srng->hal_srng = hal_srng_setup_idx(hal_soc, ring_type, ring_num,
  998. mac_id, &ring_params, idle_check,
  999. idx);
  1000. if (!srng->hal_srng) {
  1001. dp_srng_free(soc, srng);
  1002. return QDF_STATUS_E_FAILURE;
  1003. }
  1004. return QDF_STATUS_SUCCESS;
  1005. }
  1006. qdf_export_symbol(dp_srng_init_idx);
  1007. static int dp_process_rxdma_dst_ring(struct dp_soc *soc,
  1008. struct dp_intr *int_ctx,
  1009. int mac_for_pdev,
  1010. int total_budget)
  1011. {
  1012. uint32_t target_type;
  1013. target_type = hal_get_target_type(soc->hal_soc);
  1014. if (target_type == TARGET_TYPE_QCN9160)
  1015. return dp_monitor_process(soc, int_ctx,
  1016. mac_for_pdev, total_budget);
  1017. else
  1018. return dp_rxdma_err_process(int_ctx, soc, mac_for_pdev,
  1019. total_budget);
  1020. }
  1021. /**
  1022. * dp_process_lmac_rings() - Process LMAC rings
  1023. * @int_ctx: interrupt context
  1024. * @total_budget: budget of work which can be done
  1025. *
  1026. * Return: work done
  1027. */
  1028. static int dp_process_lmac_rings(struct dp_intr *int_ctx, int total_budget)
  1029. {
  1030. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1031. struct dp_soc *soc = int_ctx->soc;
  1032. uint32_t remaining_quota = total_budget;
  1033. struct dp_pdev *pdev = NULL;
  1034. uint32_t work_done = 0;
  1035. int budget = total_budget;
  1036. int ring = 0;
  1037. bool rx_refill_lt_disable;
  1038. rx_refill_lt_disable =
  1039. wlan_cfg_get_dp_soc_rxdma_refill_lt_disable(soc->wlan_cfg_ctx);
  1040. /* Process LMAC interrupts */
  1041. for (ring = 0 ; ring < MAX_NUM_LMAC_HW; ring++) {
  1042. int mac_for_pdev = ring;
  1043. pdev = dp_get_pdev_for_lmac_id(soc, mac_for_pdev);
  1044. if (!pdev)
  1045. continue;
  1046. if (int_ctx->rx_mon_ring_mask & (1 << mac_for_pdev)) {
  1047. work_done = dp_monitor_process(soc, int_ctx,
  1048. mac_for_pdev,
  1049. remaining_quota);
  1050. if (work_done)
  1051. intr_stats->num_rx_mon_ring_masks++;
  1052. budget -= work_done;
  1053. if (budget <= 0)
  1054. goto budget_done;
  1055. remaining_quota = budget;
  1056. }
  1057. if (int_ctx->tx_mon_ring_mask & (1 << mac_for_pdev)) {
  1058. work_done = dp_tx_mon_process(soc, int_ctx,
  1059. mac_for_pdev,
  1060. remaining_quota);
  1061. if (work_done)
  1062. intr_stats->num_tx_mon_ring_masks++;
  1063. budget -= work_done;
  1064. if (budget <= 0)
  1065. goto budget_done;
  1066. remaining_quota = budget;
  1067. }
  1068. if (int_ctx->rxdma2host_ring_mask &
  1069. (1 << mac_for_pdev)) {
  1070. work_done = dp_process_rxdma_dst_ring(soc, int_ctx,
  1071. mac_for_pdev,
  1072. remaining_quota);
  1073. if (work_done)
  1074. intr_stats->num_rxdma2host_ring_masks++;
  1075. budget -= work_done;
  1076. if (budget <= 0)
  1077. goto budget_done;
  1078. remaining_quota = budget;
  1079. }
  1080. if (int_ctx->host2rxdma_ring_mask & (1 << mac_for_pdev)) {
  1081. union dp_rx_desc_list_elem_t *desc_list = NULL;
  1082. union dp_rx_desc_list_elem_t *tail = NULL;
  1083. struct dp_srng *rx_refill_buf_ring;
  1084. struct rx_desc_pool *rx_desc_pool;
  1085. rx_desc_pool = &soc->rx_desc_buf[mac_for_pdev];
  1086. if (wlan_cfg_per_pdev_lmac_ring(soc->wlan_cfg_ctx))
  1087. rx_refill_buf_ring =
  1088. &soc->rx_refill_buf_ring[mac_for_pdev];
  1089. else
  1090. rx_refill_buf_ring =
  1091. &soc->rx_refill_buf_ring[pdev->lmac_id];
  1092. intr_stats->num_host2rxdma_ring_masks++;
  1093. if (!rx_refill_lt_disable)
  1094. dp_rx_buffers_lt_replenish_simple(soc,
  1095. mac_for_pdev,
  1096. rx_refill_buf_ring,
  1097. rx_desc_pool,
  1098. 0,
  1099. &desc_list,
  1100. &tail);
  1101. }
  1102. }
  1103. if (int_ctx->host2rxdma_mon_ring_mask)
  1104. dp_rx_mon_buf_refill(int_ctx);
  1105. if (int_ctx->host2txmon_ring_mask)
  1106. dp_tx_mon_buf_refill(int_ctx);
  1107. budget_done:
  1108. return total_budget - budget;
  1109. }
  1110. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1111. /**
  1112. * dp_service_near_full_srngs() - Bottom half handler to process the near
  1113. * full IRQ on a SRNG
  1114. * @dp_ctx: Datapath SoC handle
  1115. * @dp_budget: Number of SRNGs which can be processed in a single attempt
  1116. * without rescheduling
  1117. * @cpu: cpu id
  1118. *
  1119. * Return: remaining budget/quota for the soc device
  1120. */
  1121. static
  1122. uint32_t dp_service_near_full_srngs(void *dp_ctx, uint32_t dp_budget, int cpu)
  1123. {
  1124. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  1125. struct dp_soc *soc = int_ctx->soc;
  1126. /*
  1127. * dp_service_near_full_srngs arch ops should be initialized always
  1128. * if the NEAR FULL IRQ feature is enabled.
  1129. */
  1130. return soc->arch_ops.dp_service_near_full_srngs(soc, int_ctx,
  1131. dp_budget);
  1132. }
  1133. #endif
  1134. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1135. uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget, int cpu)
  1136. {
  1137. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  1138. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1139. struct dp_soc *soc = int_ctx->soc;
  1140. int ring = 0;
  1141. int index;
  1142. uint32_t work_done = 0;
  1143. int budget = dp_budget;
  1144. uint8_t tx_mask = int_ctx->tx_ring_mask;
  1145. uint8_t rx_mask = int_ctx->rx_ring_mask;
  1146. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  1147. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  1148. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  1149. uint32_t remaining_quota = dp_budget;
  1150. qdf_atomic_set_bit(cpu, &soc->service_rings_running);
  1151. dp_verbose_debug("tx %x rx %x rx_err %x rx_wbm_rel %x reo_status %x rx_mon_ring %x host2rxdma %x rxdma2host %x\n",
  1152. tx_mask, rx_mask, rx_err_mask, rx_wbm_rel_mask,
  1153. reo_status_mask,
  1154. int_ctx->rx_mon_ring_mask,
  1155. int_ctx->host2rxdma_ring_mask,
  1156. int_ctx->rxdma2host_ring_mask);
  1157. /* Process Tx completion interrupts first to return back buffers */
  1158. for (index = 0; index < soc->num_tx_comp_rings; index++) {
  1159. if (!(1 << wlan_cfg_get_wbm_ring_num_for_index(soc->wlan_cfg_ctx, index) & tx_mask))
  1160. continue;
  1161. work_done = dp_tx_comp_handler(int_ctx,
  1162. soc,
  1163. soc->tx_comp_ring[index].hal_srng,
  1164. index, remaining_quota);
  1165. if (work_done) {
  1166. intr_stats->num_tx_ring_masks[index]++;
  1167. dp_verbose_debug("tx mask 0x%x index %d, budget %d, work_done %d",
  1168. tx_mask, index, budget,
  1169. work_done);
  1170. }
  1171. budget -= work_done;
  1172. if (budget <= 0)
  1173. goto budget_done;
  1174. remaining_quota = budget;
  1175. }
  1176. /* Process REO Exception ring interrupt */
  1177. if (rx_err_mask) {
  1178. work_done = dp_rx_err_process(int_ctx, soc,
  1179. soc->reo_exception_ring.hal_srng,
  1180. remaining_quota);
  1181. if (work_done) {
  1182. intr_stats->num_rx_err_ring_masks++;
  1183. dp_verbose_debug("REO Exception Ring: work_done %d budget %d",
  1184. work_done, budget);
  1185. }
  1186. budget -= work_done;
  1187. if (budget <= 0) {
  1188. goto budget_done;
  1189. }
  1190. remaining_quota = budget;
  1191. }
  1192. /* Process Rx WBM release ring interrupt */
  1193. if (rx_wbm_rel_mask) {
  1194. work_done = dp_rx_wbm_err_process(int_ctx, soc,
  1195. soc->rx_rel_ring.hal_srng,
  1196. remaining_quota);
  1197. if (work_done) {
  1198. intr_stats->num_rx_wbm_rel_ring_masks++;
  1199. dp_verbose_debug("WBM Release Ring: work_done %d budget %d",
  1200. work_done, budget);
  1201. }
  1202. budget -= work_done;
  1203. if (budget <= 0) {
  1204. goto budget_done;
  1205. }
  1206. remaining_quota = budget;
  1207. }
  1208. /* Process Rx interrupts */
  1209. if (rx_mask) {
  1210. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  1211. if (!(rx_mask & (1 << ring)))
  1212. continue;
  1213. work_done = soc->arch_ops.dp_rx_process(int_ctx,
  1214. soc->reo_dest_ring[ring].hal_srng,
  1215. ring,
  1216. remaining_quota);
  1217. if (work_done) {
  1218. intr_stats->num_rx_ring_masks[ring]++;
  1219. dp_verbose_debug("rx mask 0x%x ring %d, work_done %d budget %d",
  1220. rx_mask, ring,
  1221. work_done, budget);
  1222. budget -= work_done;
  1223. if (budget <= 0)
  1224. goto budget_done;
  1225. remaining_quota = budget;
  1226. }
  1227. }
  1228. }
  1229. if (reo_status_mask) {
  1230. if (dp_reo_status_ring_handler(int_ctx, soc))
  1231. int_ctx->intr_stats.num_reo_status_ring_masks++;
  1232. }
  1233. if (qdf_unlikely(!dp_monitor_is_vdev_timer_running(soc))) {
  1234. work_done = dp_process_lmac_rings(int_ctx, remaining_quota);
  1235. if (work_done) {
  1236. budget -= work_done;
  1237. if (budget <= 0)
  1238. goto budget_done;
  1239. remaining_quota = budget;
  1240. }
  1241. }
  1242. qdf_lro_flush(int_ctx->lro_ctx);
  1243. intr_stats->num_masks++;
  1244. budget_done:
  1245. qdf_atomic_clear_bit(cpu, &soc->service_rings_running);
  1246. if (soc->notify_fw_callback)
  1247. soc->notify_fw_callback(soc);
  1248. return dp_budget - budget;
  1249. }
  1250. #else /* QCA_HOST_MODE_WIFI_DISABLED */
  1251. uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget, int cpu)
  1252. {
  1253. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  1254. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1255. struct dp_soc *soc = int_ctx->soc;
  1256. uint32_t remaining_quota = dp_budget;
  1257. uint32_t work_done = 0;
  1258. int budget = dp_budget;
  1259. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  1260. if (reo_status_mask) {
  1261. if (dp_reo_status_ring_handler(int_ctx, soc))
  1262. int_ctx->intr_stats.num_reo_status_ring_masks++;
  1263. }
  1264. if (qdf_unlikely(!dp_monitor_is_vdev_timer_running(soc))) {
  1265. work_done = dp_process_lmac_rings(int_ctx, remaining_quota);
  1266. if (work_done) {
  1267. budget -= work_done;
  1268. if (budget <= 0)
  1269. goto budget_done;
  1270. remaining_quota = budget;
  1271. }
  1272. }
  1273. qdf_lro_flush(int_ctx->lro_ctx);
  1274. intr_stats->num_masks++;
  1275. budget_done:
  1276. return dp_budget - budget;
  1277. }
  1278. #endif /* QCA_HOST_MODE_WIFI_DISABLED */
  1279. #ifdef WLAN_FEATURE_DP_EVENT_HISTORY
  1280. static inline bool dp_is_mon_mask_valid(struct dp_soc *soc,
  1281. struct dp_intr *intr_ctx)
  1282. {
  1283. if (intr_ctx->rx_mon_ring_mask)
  1284. return true;
  1285. return false;
  1286. }
  1287. #else
  1288. static inline bool dp_is_mon_mask_valid(struct dp_soc *soc,
  1289. struct dp_intr *intr_ctx)
  1290. {
  1291. return false;
  1292. }
  1293. #endif
  1294. QDF_STATUS dp_soc_attach_poll(struct cdp_soc_t *txrx_soc)
  1295. {
  1296. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1297. int i;
  1298. int lmac_id = 0;
  1299. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  1300. sizeof(soc->mon_intr_id_lmac_map), DP_MON_INVALID_LMAC_ID);
  1301. soc->intr_mode = DP_INTR_POLL;
  1302. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1303. soc->intr_ctx[i].dp_intr_id = i;
  1304. soc->intr_ctx[i].tx_ring_mask =
  1305. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1306. soc->intr_ctx[i].rx_ring_mask =
  1307. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1308. soc->intr_ctx[i].rx_mon_ring_mask =
  1309. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1310. soc->intr_ctx[i].rx_err_ring_mask =
  1311. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1312. soc->intr_ctx[i].rx_wbm_rel_ring_mask =
  1313. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1314. soc->intr_ctx[i].reo_status_ring_mask =
  1315. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1316. soc->intr_ctx[i].rxdma2host_ring_mask =
  1317. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1318. soc->intr_ctx[i].soc = soc;
  1319. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1320. if (dp_is_mon_mask_valid(soc, &soc->intr_ctx[i])) {
  1321. hif_event_history_init(soc->hif_handle, i);
  1322. soc->mon_intr_id_lmac_map[lmac_id] = i;
  1323. lmac_id++;
  1324. }
  1325. }
  1326. qdf_timer_init(soc->osdev, &soc->int_timer,
  1327. dp_interrupt_timer, (void *)soc,
  1328. QDF_TIMER_TYPE_WAKE_APPS);
  1329. return QDF_STATUS_SUCCESS;
  1330. }
  1331. void dp_soc_set_interrupt_mode(struct dp_soc *soc)
  1332. {
  1333. uint32_t msi_base_data, msi_vector_start;
  1334. int msi_vector_count, ret;
  1335. soc->intr_mode = DP_INTR_INTEGRATED;
  1336. if (!(soc->wlan_cfg_ctx->napi_enabled) ||
  1337. (dp_is_monitor_mode_using_poll(soc) &&
  1338. soc->cdp_soc.ol_ops->get_con_mode &&
  1339. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)) {
  1340. soc->intr_mode = DP_INTR_POLL;
  1341. } else {
  1342. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  1343. &msi_vector_count,
  1344. &msi_base_data,
  1345. &msi_vector_start);
  1346. if (ret)
  1347. return;
  1348. soc->intr_mode = DP_INTR_MSI;
  1349. }
  1350. }
  1351. #ifdef QCA_SUPPORT_LEGACY_INTERRUPTS
  1352. /**
  1353. * dp_soc_interrupt_map_calculate_wifi3_pci_legacy() -
  1354. * Calculate interrupt map for legacy interrupts
  1355. * @soc: DP soc handle
  1356. * @intr_ctx_num: Interrupt context number
  1357. * @irq_id_map: IRQ map
  1358. * @num_irq_r: Number of interrupts assigned for this context
  1359. *
  1360. * Return: void
  1361. */
  1362. static void dp_soc_interrupt_map_calculate_wifi3_pci_legacy(struct dp_soc *soc,
  1363. int intr_ctx_num,
  1364. int *irq_id_map,
  1365. int *num_irq_r)
  1366. {
  1367. int j;
  1368. int num_irq = 0;
  1369. int tx_mask = wlan_cfg_get_tx_ring_mask(
  1370. soc->wlan_cfg_ctx, intr_ctx_num);
  1371. int rx_mask = wlan_cfg_get_rx_ring_mask(
  1372. soc->wlan_cfg_ctx, intr_ctx_num);
  1373. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  1374. soc->wlan_cfg_ctx, intr_ctx_num);
  1375. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1376. soc->wlan_cfg_ctx, intr_ctx_num);
  1377. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1378. soc->wlan_cfg_ctx, intr_ctx_num);
  1379. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1380. soc->wlan_cfg_ctx, intr_ctx_num);
  1381. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1382. soc->wlan_cfg_ctx, intr_ctx_num);
  1383. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  1384. soc->wlan_cfg_ctx, intr_ctx_num);
  1385. int host2rxdma_mon_ring_mask = wlan_cfg_get_host2rxdma_mon_ring_mask(
  1386. soc->wlan_cfg_ctx, intr_ctx_num);
  1387. int host2txmon_ring_mask = wlan_cfg_get_host2txmon_ring_mask(
  1388. soc->wlan_cfg_ctx, intr_ctx_num);
  1389. int txmon2host_mon_ring_mask = wlan_cfg_get_tx_mon_ring_mask(
  1390. soc->wlan_cfg_ctx, intr_ctx_num);
  1391. soc->intr_mode = DP_INTR_LEGACY_VIRTUAL_IRQ;
  1392. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  1393. if (tx_mask & (1 << j))
  1394. irq_id_map[num_irq++] = (wbm2sw0_release - j);
  1395. if (rx_mask & (1 << j))
  1396. irq_id_map[num_irq++] = (reo2sw1_intr - j);
  1397. if (rx_mon_mask & (1 << j))
  1398. irq_id_map[num_irq++] = (rxmon2sw_p0_dest0 - j);
  1399. if (rx_err_ring_mask & (1 << j))
  1400. irq_id_map[num_irq++] = (reo2sw0_intr - j);
  1401. if (rx_wbm_rel_ring_mask & (1 << j))
  1402. irq_id_map[num_irq++] = (wbm2sw5_release - j);
  1403. if (reo_status_ring_mask & (1 << j))
  1404. irq_id_map[num_irq++] = (reo_status - j);
  1405. if (rxdma2host_ring_mask & (1 << j))
  1406. irq_id_map[num_irq++] = (rxdma2sw_dst_ring0 - j);
  1407. if (host2rxdma_ring_mask & (1 << j))
  1408. irq_id_map[num_irq++] = (sw2rxdma_0 - j);
  1409. if (host2rxdma_mon_ring_mask & (1 << j))
  1410. irq_id_map[num_irq++] = (sw2rxmon_src_ring - j);
  1411. if (host2txmon_ring_mask & (1 << j))
  1412. irq_id_map[num_irq++] = sw2txmon_src_ring;
  1413. if (txmon2host_mon_ring_mask & (1 << j))
  1414. irq_id_map[num_irq++] = (txmon2sw_p0_dest0 - j);
  1415. }
  1416. *num_irq_r = num_irq;
  1417. }
  1418. #else
  1419. static void dp_soc_interrupt_map_calculate_wifi3_pci_legacy(struct dp_soc *soc,
  1420. int intr_ctx_num,
  1421. int *irq_id_map,
  1422. int *num_irq_r)
  1423. {
  1424. }
  1425. #endif
  1426. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  1427. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  1428. {
  1429. int j;
  1430. int num_irq = 0;
  1431. int tx_mask =
  1432. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  1433. int rx_mask =
  1434. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  1435. int rx_mon_mask =
  1436. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  1437. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1438. soc->wlan_cfg_ctx, intr_ctx_num);
  1439. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1440. soc->wlan_cfg_ctx, intr_ctx_num);
  1441. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1442. soc->wlan_cfg_ctx, intr_ctx_num);
  1443. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1444. soc->wlan_cfg_ctx, intr_ctx_num);
  1445. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  1446. soc->wlan_cfg_ctx, intr_ctx_num);
  1447. int host2rxdma_mon_ring_mask = wlan_cfg_get_host2rxdma_mon_ring_mask(
  1448. soc->wlan_cfg_ctx, intr_ctx_num);
  1449. int host2txmon_ring_mask = wlan_cfg_get_host2txmon_ring_mask(
  1450. soc->wlan_cfg_ctx, intr_ctx_num);
  1451. int txmon2host_mon_ring_mask = wlan_cfg_get_tx_mon_ring_mask(
  1452. soc->wlan_cfg_ctx, intr_ctx_num);
  1453. soc->intr_mode = DP_INTR_INTEGRATED;
  1454. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  1455. if (tx_mask & (1 << j)) {
  1456. irq_id_map[num_irq++] =
  1457. (wbm2host_tx_completions_ring1 - j);
  1458. }
  1459. if (rx_mask & (1 << j)) {
  1460. irq_id_map[num_irq++] =
  1461. (reo2host_destination_ring1 - j);
  1462. }
  1463. if (rxdma2host_ring_mask & (1 << j)) {
  1464. irq_id_map[num_irq++] =
  1465. rxdma2host_destination_ring_mac1 - j;
  1466. }
  1467. if (host2rxdma_ring_mask & (1 << j)) {
  1468. irq_id_map[num_irq++] =
  1469. host2rxdma_host_buf_ring_mac1 - j;
  1470. }
  1471. if (host2rxdma_mon_ring_mask & (1 << j)) {
  1472. irq_id_map[num_irq++] =
  1473. host2rxdma_monitor_ring1 - j;
  1474. }
  1475. if (rx_mon_mask & (1 << j)) {
  1476. irq_id_map[num_irq++] =
  1477. ppdu_end_interrupts_mac1 - j;
  1478. irq_id_map[num_irq++] =
  1479. rxdma2host_monitor_status_ring_mac1 - j;
  1480. irq_id_map[num_irq++] =
  1481. rxdma2host_monitor_destination_mac1 - j;
  1482. }
  1483. if (rx_wbm_rel_ring_mask & (1 << j))
  1484. irq_id_map[num_irq++] = wbm2host_rx_release;
  1485. if (rx_err_ring_mask & (1 << j))
  1486. irq_id_map[num_irq++] = reo2host_exception;
  1487. if (reo_status_ring_mask & (1 << j))
  1488. irq_id_map[num_irq++] = reo2host_status;
  1489. if (host2txmon_ring_mask & (1 << j))
  1490. irq_id_map[num_irq++] = host2tx_monitor_ring1;
  1491. if (txmon2host_mon_ring_mask & (1 << j)) {
  1492. irq_id_map[num_irq++] =
  1493. (txmon2host_monitor_destination_mac1 - j);
  1494. }
  1495. }
  1496. *num_irq_r = num_irq;
  1497. }
  1498. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  1499. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  1500. int msi_vector_count, int msi_vector_start)
  1501. {
  1502. int tx_mask = wlan_cfg_get_tx_ring_mask(
  1503. soc->wlan_cfg_ctx, intr_ctx_num);
  1504. int rx_mask = wlan_cfg_get_rx_ring_mask(
  1505. soc->wlan_cfg_ctx, intr_ctx_num);
  1506. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  1507. soc->wlan_cfg_ctx, intr_ctx_num);
  1508. int tx_mon_mask = wlan_cfg_get_tx_mon_ring_mask(
  1509. soc->wlan_cfg_ctx, intr_ctx_num);
  1510. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  1511. soc->wlan_cfg_ctx, intr_ctx_num);
  1512. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  1513. soc->wlan_cfg_ctx, intr_ctx_num);
  1514. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  1515. soc->wlan_cfg_ctx, intr_ctx_num);
  1516. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  1517. soc->wlan_cfg_ctx, intr_ctx_num);
  1518. int host2rxdma_ring_mask = wlan_cfg_get_host2rxdma_ring_mask(
  1519. soc->wlan_cfg_ctx, intr_ctx_num);
  1520. int host2rxdma_mon_ring_mask = wlan_cfg_get_host2rxdma_mon_ring_mask(
  1521. soc->wlan_cfg_ctx, intr_ctx_num);
  1522. int rx_near_full_grp_1_mask =
  1523. wlan_cfg_get_rx_near_full_grp_1_mask(soc->wlan_cfg_ctx,
  1524. intr_ctx_num);
  1525. int rx_near_full_grp_2_mask =
  1526. wlan_cfg_get_rx_near_full_grp_2_mask(soc->wlan_cfg_ctx,
  1527. intr_ctx_num);
  1528. int tx_ring_near_full_mask =
  1529. wlan_cfg_get_tx_ring_near_full_mask(soc->wlan_cfg_ctx,
  1530. intr_ctx_num);
  1531. int host2txmon_ring_mask =
  1532. wlan_cfg_get_host2txmon_ring_mask(soc->wlan_cfg_ctx,
  1533. intr_ctx_num);
  1534. unsigned int vector =
  1535. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  1536. int num_irq = 0;
  1537. soc->intr_mode = DP_INTR_MSI;
  1538. if (tx_mask | rx_mask | rx_mon_mask | tx_mon_mask | rx_err_ring_mask |
  1539. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask |
  1540. host2rxdma_ring_mask | host2rxdma_mon_ring_mask |
  1541. rx_near_full_grp_1_mask | rx_near_full_grp_2_mask |
  1542. tx_ring_near_full_mask | host2txmon_ring_mask)
  1543. irq_id_map[num_irq++] =
  1544. pld_get_msi_irq(soc->osdev->dev, vector);
  1545. *num_irq_r = num_irq;
  1546. }
  1547. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  1548. int *irq_id_map, int *num_irq)
  1549. {
  1550. int msi_vector_count, ret;
  1551. uint32_t msi_base_data, msi_vector_start;
  1552. if (pld_get_enable_intx(soc->osdev->dev)) {
  1553. return dp_soc_interrupt_map_calculate_wifi3_pci_legacy(soc,
  1554. intr_ctx_num, irq_id_map, num_irq);
  1555. }
  1556. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  1557. &msi_vector_count,
  1558. &msi_base_data,
  1559. &msi_vector_start);
  1560. if (ret)
  1561. return dp_soc_interrupt_map_calculate_integrated(soc,
  1562. intr_ctx_num, irq_id_map, num_irq);
  1563. else
  1564. dp_soc_interrupt_map_calculate_msi(soc,
  1565. intr_ctx_num, irq_id_map, num_irq,
  1566. msi_vector_count, msi_vector_start);
  1567. }
  1568. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1569. /**
  1570. * dp_soc_near_full_interrupt_attach() - Register handler for DP near fill irq
  1571. * @soc: DP soc handle
  1572. * @num_irq: IRQ number
  1573. * @irq_id_map: IRQ map
  1574. * @intr_id: interrupt context ID
  1575. *
  1576. * Return: 0 for success. nonzero for failure.
  1577. */
  1578. static inline int
  1579. dp_soc_near_full_interrupt_attach(struct dp_soc *soc, int num_irq,
  1580. int irq_id_map[], int intr_id)
  1581. {
  1582. return hif_register_ext_group(soc->hif_handle,
  1583. num_irq, irq_id_map,
  1584. dp_service_near_full_srngs,
  1585. &soc->intr_ctx[intr_id], "dp_nf_intr",
  1586. HIF_EXEC_NAPI_TYPE,
  1587. QCA_NAPI_DEF_SCALE_BIN_SHIFT);
  1588. }
  1589. #else
  1590. static inline int
  1591. dp_soc_near_full_interrupt_attach(struct dp_soc *soc, int num_irq,
  1592. int *irq_id_map, int intr_id)
  1593. {
  1594. return 0;
  1595. }
  1596. #endif
  1597. #ifdef DP_CON_MON_MSI_SKIP_SET
  1598. static inline bool dp_skip_rx_mon_ring_mask_set(struct dp_soc *soc)
  1599. {
  1600. return !!(soc->cdp_soc.ol_ops->get_con_mode() !=
  1601. QDF_GLOBAL_MONITOR_MODE);
  1602. }
  1603. #else
  1604. static inline bool dp_skip_rx_mon_ring_mask_set(struct dp_soc *soc)
  1605. {
  1606. return false;
  1607. }
  1608. #endif
  1609. void dp_soc_interrupt_detach(struct cdp_soc_t *txrx_soc)
  1610. {
  1611. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1612. int i;
  1613. if (soc->intr_mode == DP_INTR_POLL) {
  1614. qdf_timer_free(&soc->int_timer);
  1615. } else {
  1616. hif_deconfigure_ext_group_interrupts(soc->hif_handle);
  1617. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1618. hif_deregister_exec_group(soc->hif_handle, "dp_nf_intr");
  1619. }
  1620. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1621. soc->intr_ctx[i].tx_ring_mask = 0;
  1622. soc->intr_ctx[i].rx_ring_mask = 0;
  1623. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1624. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1625. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1626. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1627. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  1628. soc->intr_ctx[i].host2rxdma_ring_mask = 0;
  1629. soc->intr_ctx[i].host2rxdma_mon_ring_mask = 0;
  1630. soc->intr_ctx[i].rx_near_full_grp_1_mask = 0;
  1631. soc->intr_ctx[i].rx_near_full_grp_2_mask = 0;
  1632. soc->intr_ctx[i].tx_ring_near_full_mask = 0;
  1633. soc->intr_ctx[i].tx_mon_ring_mask = 0;
  1634. soc->intr_ctx[i].host2txmon_ring_mask = 0;
  1635. soc->intr_ctx[i].umac_reset_intr_mask = 0;
  1636. hif_event_history_deinit(soc->hif_handle, i);
  1637. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1638. }
  1639. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  1640. sizeof(soc->mon_intr_id_lmac_map),
  1641. DP_MON_INVALID_LMAC_ID);
  1642. }
  1643. QDF_STATUS dp_soc_interrupt_attach(struct cdp_soc_t *txrx_soc)
  1644. {
  1645. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1646. int i = 0;
  1647. int num_irq = 0;
  1648. int rx_err_ring_intr_ctxt_id = HIF_MAX_GROUP;
  1649. int lmac_id = 0;
  1650. int napi_scale;
  1651. qdf_mem_set(&soc->mon_intr_id_lmac_map,
  1652. sizeof(soc->mon_intr_id_lmac_map), DP_MON_INVALID_LMAC_ID);
  1653. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1654. int ret = 0;
  1655. /* Map of IRQ ids registered with one interrupt context */
  1656. int irq_id_map[HIF_MAX_GRP_IRQ];
  1657. int tx_mask =
  1658. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1659. int rx_mask =
  1660. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1661. int rx_mon_mask =
  1662. dp_soc_get_mon_mask_for_interrupt_mode(soc, i);
  1663. int tx_mon_ring_mask =
  1664. wlan_cfg_get_tx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1665. int rx_err_ring_mask =
  1666. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1667. int rx_wbm_rel_ring_mask =
  1668. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1669. int reo_status_ring_mask =
  1670. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1671. int rxdma2host_ring_mask =
  1672. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1673. int host2rxdma_ring_mask =
  1674. wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx, i);
  1675. int host2rxdma_mon_ring_mask =
  1676. wlan_cfg_get_host2rxdma_mon_ring_mask(
  1677. soc->wlan_cfg_ctx, i);
  1678. int rx_near_full_grp_1_mask =
  1679. wlan_cfg_get_rx_near_full_grp_1_mask(soc->wlan_cfg_ctx,
  1680. i);
  1681. int rx_near_full_grp_2_mask =
  1682. wlan_cfg_get_rx_near_full_grp_2_mask(soc->wlan_cfg_ctx,
  1683. i);
  1684. int tx_ring_near_full_mask =
  1685. wlan_cfg_get_tx_ring_near_full_mask(soc->wlan_cfg_ctx,
  1686. i);
  1687. int host2txmon_ring_mask =
  1688. wlan_cfg_get_host2txmon_ring_mask(soc->wlan_cfg_ctx, i);
  1689. int umac_reset_intr_mask =
  1690. wlan_cfg_get_umac_reset_intr_mask(soc->wlan_cfg_ctx, i);
  1691. if (dp_skip_rx_mon_ring_mask_set(soc))
  1692. rx_mon_mask = 0;
  1693. soc->intr_ctx[i].dp_intr_id = i;
  1694. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1695. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1696. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1697. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1698. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1699. soc->intr_ctx[i].host2rxdma_ring_mask = host2rxdma_ring_mask;
  1700. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1701. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1702. soc->intr_ctx[i].host2rxdma_mon_ring_mask =
  1703. host2rxdma_mon_ring_mask;
  1704. soc->intr_ctx[i].rx_near_full_grp_1_mask =
  1705. rx_near_full_grp_1_mask;
  1706. soc->intr_ctx[i].rx_near_full_grp_2_mask =
  1707. rx_near_full_grp_2_mask;
  1708. soc->intr_ctx[i].tx_ring_near_full_mask =
  1709. tx_ring_near_full_mask;
  1710. soc->intr_ctx[i].tx_mon_ring_mask = tx_mon_ring_mask;
  1711. soc->intr_ctx[i].host2txmon_ring_mask = host2txmon_ring_mask;
  1712. soc->intr_ctx[i].umac_reset_intr_mask = umac_reset_intr_mask;
  1713. soc->intr_ctx[i].soc = soc;
  1714. num_irq = 0;
  1715. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1716. &num_irq);
  1717. if (rx_near_full_grp_1_mask | rx_near_full_grp_2_mask |
  1718. tx_ring_near_full_mask) {
  1719. dp_soc_near_full_interrupt_attach(soc, num_irq,
  1720. irq_id_map, i);
  1721. } else {
  1722. napi_scale = wlan_cfg_get_napi_scale_factor(
  1723. soc->wlan_cfg_ctx);
  1724. if (!napi_scale)
  1725. napi_scale = QCA_NAPI_DEF_SCALE_BIN_SHIFT;
  1726. ret = hif_register_ext_group(soc->hif_handle,
  1727. num_irq, irq_id_map, dp_service_srngs,
  1728. &soc->intr_ctx[i], "dp_intr",
  1729. HIF_EXEC_NAPI_TYPE, napi_scale);
  1730. }
  1731. dp_debug(" int ctx %u num_irq %u irq_id_map %u %u",
  1732. i, num_irq, irq_id_map[0], irq_id_map[1]);
  1733. if (ret) {
  1734. dp_init_err("%pK: failed, ret = %d", soc, ret);
  1735. dp_soc_interrupt_detach(txrx_soc);
  1736. return QDF_STATUS_E_FAILURE;
  1737. }
  1738. hif_event_history_init(soc->hif_handle, i);
  1739. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1740. if (rx_err_ring_mask)
  1741. rx_err_ring_intr_ctxt_id = i;
  1742. if (dp_is_mon_mask_valid(soc, &soc->intr_ctx[i])) {
  1743. soc->mon_intr_id_lmac_map[lmac_id] = i;
  1744. lmac_id++;
  1745. }
  1746. }
  1747. hif_configure_ext_group_interrupts(soc->hif_handle);
  1748. if (rx_err_ring_intr_ctxt_id != HIF_MAX_GROUP)
  1749. hif_config_irq_clear_cpu_affinity(soc->hif_handle,
  1750. rx_err_ring_intr_ctxt_id, 0);
  1751. return QDF_STATUS_SUCCESS;
  1752. }
  1753. #define AVG_MAX_MPDUS_PER_TID 128
  1754. #define AVG_TIDS_PER_CLIENT 2
  1755. #define AVG_FLOWS_PER_TID 2
  1756. #define AVG_MSDUS_PER_FLOW 128
  1757. #define AVG_MSDUS_PER_MPDU 4
  1758. void dp_hw_link_desc_pool_banks_free(struct dp_soc *soc, uint32_t mac_id)
  1759. {
  1760. struct qdf_mem_multi_page_t *pages;
  1761. if (mac_id != WLAN_INVALID_PDEV_ID) {
  1762. pages = dp_monitor_get_link_desc_pages(soc, mac_id);
  1763. } else {
  1764. pages = &soc->link_desc_pages;
  1765. }
  1766. if (!pages) {
  1767. dp_err("can not get link desc pages");
  1768. QDF_ASSERT(0);
  1769. return;
  1770. }
  1771. if (pages->dma_pages) {
  1772. wlan_minidump_remove((void *)
  1773. pages->dma_pages->page_v_addr_start,
  1774. pages->num_pages * pages->page_size,
  1775. soc->ctrl_psoc,
  1776. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1777. "hw_link_desc_bank");
  1778. dp_desc_multi_pages_mem_free(soc, DP_HW_LINK_DESC_TYPE,
  1779. pages, 0, false);
  1780. }
  1781. }
  1782. qdf_export_symbol(dp_hw_link_desc_pool_banks_free);
  1783. QDF_STATUS dp_hw_link_desc_pool_banks_alloc(struct dp_soc *soc, uint32_t mac_id)
  1784. {
  1785. hal_soc_handle_t hal_soc = soc->hal_soc;
  1786. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1787. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1788. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1789. uint32_t num_mpdus_per_link_desc = hal_num_mpdus_per_link_desc(hal_soc);
  1790. uint32_t num_msdus_per_link_desc = hal_num_msdus_per_link_desc(hal_soc);
  1791. uint32_t num_mpdu_links_per_queue_desc =
  1792. hal_num_mpdu_links_per_queue_desc(hal_soc);
  1793. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1794. uint32_t *total_link_descs, total_mem_size;
  1795. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1796. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1797. uint32_t num_entries;
  1798. struct qdf_mem_multi_page_t *pages;
  1799. struct dp_srng *dp_srng;
  1800. uint8_t minidump_str[MINIDUMP_STR_SIZE];
  1801. /* Only Tx queue descriptors are allocated from common link descriptor
  1802. * pool Rx queue descriptors are not included in this because (REO queue
  1803. * extension descriptors) they are expected to be allocated contiguously
  1804. * with REO queue descriptors
  1805. */
  1806. if (mac_id != WLAN_INVALID_PDEV_ID) {
  1807. pages = dp_monitor_get_link_desc_pages(soc, mac_id);
  1808. /* dp_monitor_get_link_desc_pages returns NULL only
  1809. * if monitor SOC is NULL
  1810. */
  1811. if (!pages) {
  1812. dp_err("can not get link desc pages");
  1813. QDF_ASSERT(0);
  1814. return QDF_STATUS_E_FAULT;
  1815. }
  1816. dp_srng = &soc->rxdma_mon_desc_ring[mac_id];
  1817. num_entries = dp_srng->alloc_size /
  1818. hal_srng_get_entrysize(soc->hal_soc,
  1819. RXDMA_MONITOR_DESC);
  1820. total_link_descs = dp_monitor_get_total_link_descs(soc, mac_id);
  1821. qdf_str_lcopy(minidump_str, "mon_link_desc_bank",
  1822. MINIDUMP_STR_SIZE);
  1823. } else {
  1824. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1825. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1826. num_mpdu_queue_descs = num_mpdu_link_descs /
  1827. num_mpdu_links_per_queue_desc;
  1828. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1829. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1830. num_msdus_per_link_desc;
  1831. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1832. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1833. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1834. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1835. pages = &soc->link_desc_pages;
  1836. total_link_descs = &soc->total_link_descs;
  1837. qdf_str_lcopy(minidump_str, "link_desc_bank",
  1838. MINIDUMP_STR_SIZE);
  1839. }
  1840. /* If link descriptor banks are allocated, return from here */
  1841. if (pages->num_pages)
  1842. return QDF_STATUS_SUCCESS;
  1843. /* Round up to power of 2 */
  1844. *total_link_descs = 1;
  1845. while (*total_link_descs < num_entries)
  1846. *total_link_descs <<= 1;
  1847. dp_init_info("%pK: total_link_descs: %u, link_desc_size: %d",
  1848. soc, *total_link_descs, link_desc_size);
  1849. total_mem_size = *total_link_descs * link_desc_size;
  1850. total_mem_size += link_desc_align;
  1851. dp_init_info("%pK: total_mem_size: %d",
  1852. soc, total_mem_size);
  1853. dp_set_max_page_size(pages, max_alloc_size);
  1854. dp_desc_multi_pages_mem_alloc(soc, DP_HW_LINK_DESC_TYPE,
  1855. pages,
  1856. link_desc_size,
  1857. *total_link_descs,
  1858. 0, false);
  1859. if (!pages->num_pages) {
  1860. dp_err("Multi page alloc fail for hw link desc pool");
  1861. return QDF_STATUS_E_FAULT;
  1862. }
  1863. wlan_minidump_log(pages->dma_pages->page_v_addr_start,
  1864. pages->num_pages * pages->page_size,
  1865. soc->ctrl_psoc,
  1866. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1867. "hw_link_desc_bank");
  1868. return QDF_STATUS_SUCCESS;
  1869. }
  1870. void dp_hw_link_desc_ring_free(struct dp_soc *soc)
  1871. {
  1872. uint32_t i;
  1873. uint32_t size = soc->wbm_idle_scatter_buf_size;
  1874. void *vaddr = soc->wbm_idle_link_ring.base_vaddr_unaligned;
  1875. qdf_dma_addr_t paddr;
  1876. if (soc->wbm_idle_scatter_buf_base_vaddr[0]) {
  1877. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1878. vaddr = soc->wbm_idle_scatter_buf_base_vaddr[i];
  1879. paddr = soc->wbm_idle_scatter_buf_base_paddr[i];
  1880. if (vaddr) {
  1881. qdf_mem_free_consistent(soc->osdev,
  1882. soc->osdev->dev,
  1883. size,
  1884. vaddr,
  1885. paddr,
  1886. 0);
  1887. vaddr = NULL;
  1888. }
  1889. }
  1890. } else {
  1891. wlan_minidump_remove(soc->wbm_idle_link_ring.base_vaddr_unaligned,
  1892. soc->wbm_idle_link_ring.alloc_size,
  1893. soc->ctrl_psoc,
  1894. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1895. "wbm_idle_link_ring");
  1896. dp_srng_free(soc, &soc->wbm_idle_link_ring);
  1897. }
  1898. }
  1899. QDF_STATUS dp_hw_link_desc_ring_alloc(struct dp_soc *soc)
  1900. {
  1901. uint32_t entry_size, i;
  1902. uint32_t total_mem_size;
  1903. qdf_dma_addr_t *baseaddr = NULL;
  1904. struct dp_srng *dp_srng;
  1905. uint32_t ring_type;
  1906. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1907. uint32_t tlds;
  1908. ring_type = WBM_IDLE_LINK;
  1909. dp_srng = &soc->wbm_idle_link_ring;
  1910. tlds = soc->total_link_descs;
  1911. entry_size = hal_srng_get_entrysize(soc->hal_soc, ring_type);
  1912. total_mem_size = entry_size * tlds;
  1913. if (total_mem_size <= max_alloc_size) {
  1914. if (dp_srng_alloc(soc, dp_srng, ring_type, tlds, 0)) {
  1915. dp_init_err("%pK: Link desc idle ring setup failed",
  1916. soc);
  1917. goto fail;
  1918. }
  1919. wlan_minidump_log(soc->wbm_idle_link_ring.base_vaddr_unaligned,
  1920. soc->wbm_idle_link_ring.alloc_size,
  1921. soc->ctrl_psoc,
  1922. WLAN_MD_DP_SRNG_WBM_IDLE_LINK,
  1923. "wbm_idle_link_ring");
  1924. } else {
  1925. uint32_t num_scatter_bufs;
  1926. uint32_t buf_size = 0;
  1927. soc->wbm_idle_scatter_buf_size =
  1928. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1929. hal_idle_scatter_buf_num_entries(
  1930. soc->hal_soc,
  1931. soc->wbm_idle_scatter_buf_size);
  1932. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1933. soc->hal_soc, total_mem_size,
  1934. soc->wbm_idle_scatter_buf_size);
  1935. if (num_scatter_bufs > MAX_IDLE_SCATTER_BUFS) {
  1936. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1937. FL("scatter bufs size out of bounds"));
  1938. goto fail;
  1939. }
  1940. for (i = 0; i < num_scatter_bufs; i++) {
  1941. baseaddr = &soc->wbm_idle_scatter_buf_base_paddr[i];
  1942. buf_size = soc->wbm_idle_scatter_buf_size;
  1943. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1944. qdf_mem_alloc_consistent(soc->osdev,
  1945. soc->osdev->dev,
  1946. buf_size,
  1947. baseaddr);
  1948. if (!soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1949. QDF_TRACE(QDF_MODULE_ID_DP,
  1950. QDF_TRACE_LEVEL_ERROR,
  1951. FL("Scatter lst memory alloc fail"));
  1952. goto fail;
  1953. }
  1954. }
  1955. soc->num_scatter_bufs = num_scatter_bufs;
  1956. }
  1957. return QDF_STATUS_SUCCESS;
  1958. fail:
  1959. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1960. void *vaddr = soc->wbm_idle_scatter_buf_base_vaddr[i];
  1961. qdf_dma_addr_t paddr = soc->wbm_idle_scatter_buf_base_paddr[i];
  1962. if (vaddr) {
  1963. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1964. soc->wbm_idle_scatter_buf_size,
  1965. vaddr,
  1966. paddr, 0);
  1967. vaddr = NULL;
  1968. }
  1969. }
  1970. return QDF_STATUS_E_NOMEM;
  1971. }
  1972. qdf_export_symbol(dp_hw_link_desc_pool_banks_alloc);
  1973. QDF_STATUS dp_hw_link_desc_ring_init(struct dp_soc *soc)
  1974. {
  1975. struct dp_srng *dp_srng = &soc->wbm_idle_link_ring;
  1976. if (dp_srng->base_vaddr_unaligned) {
  1977. if (dp_srng_init(soc, dp_srng, WBM_IDLE_LINK, 0, 0))
  1978. return QDF_STATUS_E_FAILURE;
  1979. }
  1980. return QDF_STATUS_SUCCESS;
  1981. }
  1982. void dp_hw_link_desc_ring_deinit(struct dp_soc *soc)
  1983. {
  1984. dp_srng_deinit(soc, &soc->wbm_idle_link_ring, WBM_IDLE_LINK, 0);
  1985. }
  1986. void dp_link_desc_ring_replenish(struct dp_soc *soc, uint32_t mac_id)
  1987. {
  1988. uint32_t cookie = 0;
  1989. uint32_t page_idx = 0;
  1990. struct qdf_mem_multi_page_t *pages;
  1991. struct qdf_mem_dma_page_t *dma_pages;
  1992. uint32_t offset = 0;
  1993. uint32_t count = 0;
  1994. uint32_t desc_id = 0;
  1995. void *desc_srng;
  1996. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1997. uint32_t *total_link_descs_addr;
  1998. uint32_t total_link_descs;
  1999. uint32_t scatter_buf_num;
  2000. uint32_t num_entries_per_buf = 0;
  2001. uint32_t rem_entries;
  2002. uint32_t num_descs_per_page;
  2003. uint32_t num_scatter_bufs = 0;
  2004. uint8_t *scatter_buf_ptr;
  2005. void *desc;
  2006. num_scatter_bufs = soc->num_scatter_bufs;
  2007. if (mac_id == WLAN_INVALID_PDEV_ID) {
  2008. pages = &soc->link_desc_pages;
  2009. total_link_descs = soc->total_link_descs;
  2010. desc_srng = soc->wbm_idle_link_ring.hal_srng;
  2011. } else {
  2012. pages = dp_monitor_get_link_desc_pages(soc, mac_id);
  2013. /* dp_monitor_get_link_desc_pages returns NULL only
  2014. * if monitor SOC is NULL
  2015. */
  2016. if (!pages) {
  2017. dp_err("can not get link desc pages");
  2018. QDF_ASSERT(0);
  2019. return;
  2020. }
  2021. total_link_descs_addr =
  2022. dp_monitor_get_total_link_descs(soc, mac_id);
  2023. total_link_descs = *total_link_descs_addr;
  2024. desc_srng = soc->rxdma_mon_desc_ring[mac_id].hal_srng;
  2025. }
  2026. dma_pages = pages->dma_pages;
  2027. do {
  2028. qdf_mem_zero(dma_pages[page_idx].page_v_addr_start,
  2029. pages->page_size);
  2030. page_idx++;
  2031. } while (page_idx < pages->num_pages);
  2032. if (desc_srng) {
  2033. hal_srng_access_start_unlocked(soc->hal_soc, desc_srng);
  2034. page_idx = 0;
  2035. count = 0;
  2036. offset = 0;
  2037. pages = &soc->link_desc_pages;
  2038. while ((desc = hal_srng_src_get_next(soc->hal_soc,
  2039. desc_srng)) &&
  2040. (count < total_link_descs)) {
  2041. page_idx = count / pages->num_element_per_page;
  2042. if (desc_id == pages->num_element_per_page)
  2043. desc_id = 0;
  2044. offset = count % pages->num_element_per_page;
  2045. cookie = LINK_DESC_COOKIE(desc_id, page_idx,
  2046. soc->link_desc_id_start);
  2047. hal_set_link_desc_addr(soc->hal_soc, desc, cookie,
  2048. dma_pages[page_idx].page_p_addr
  2049. + (offset * link_desc_size),
  2050. soc->idle_link_bm_id);
  2051. count++;
  2052. desc_id++;
  2053. }
  2054. hal_srng_access_end_unlocked(soc->hal_soc, desc_srng);
  2055. } else {
  2056. /* Populate idle list scatter buffers with link descriptor
  2057. * pointers
  2058. */
  2059. scatter_buf_num = 0;
  2060. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  2061. soc->hal_soc,
  2062. soc->wbm_idle_scatter_buf_size);
  2063. scatter_buf_ptr = (uint8_t *)(
  2064. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  2065. rem_entries = num_entries_per_buf;
  2066. pages = &soc->link_desc_pages;
  2067. page_idx = 0; count = 0;
  2068. offset = 0;
  2069. num_descs_per_page = pages->num_element_per_page;
  2070. while (count < total_link_descs) {
  2071. page_idx = count / num_descs_per_page;
  2072. offset = count % num_descs_per_page;
  2073. if (desc_id == pages->num_element_per_page)
  2074. desc_id = 0;
  2075. cookie = LINK_DESC_COOKIE(desc_id, page_idx,
  2076. soc->link_desc_id_start);
  2077. hal_set_link_desc_addr(soc->hal_soc,
  2078. (void *)scatter_buf_ptr,
  2079. cookie,
  2080. dma_pages[page_idx].page_p_addr +
  2081. (offset * link_desc_size),
  2082. soc->idle_link_bm_id);
  2083. rem_entries--;
  2084. if (rem_entries) {
  2085. scatter_buf_ptr += link_desc_size;
  2086. } else {
  2087. rem_entries = num_entries_per_buf;
  2088. scatter_buf_num++;
  2089. if (scatter_buf_num >= num_scatter_bufs)
  2090. break;
  2091. scatter_buf_ptr = (uint8_t *)
  2092. (soc->wbm_idle_scatter_buf_base_vaddr[
  2093. scatter_buf_num]);
  2094. }
  2095. count++;
  2096. desc_id++;
  2097. }
  2098. /* Setup link descriptor idle list in HW */
  2099. hal_setup_link_idle_list(soc->hal_soc,
  2100. soc->wbm_idle_scatter_buf_base_paddr,
  2101. soc->wbm_idle_scatter_buf_base_vaddr,
  2102. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  2103. (uint32_t)(scatter_buf_ptr -
  2104. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  2105. scatter_buf_num-1])), total_link_descs);
  2106. }
  2107. }
  2108. qdf_export_symbol(dp_link_desc_ring_replenish);
  2109. #ifdef IPA_OFFLOAD
  2110. #define USE_1_IPA_RX_REO_RING 1
  2111. #define USE_2_IPA_RX_REO_RINGS 2
  2112. #define REO_DST_RING_SIZE_QCA6290 1023
  2113. #ifndef CONFIG_WIFI_EMULATION_WIFI_3_0
  2114. #define REO_DST_RING_SIZE_QCA8074 1023
  2115. #define REO_DST_RING_SIZE_QCN9000 2048
  2116. #else
  2117. #define REO_DST_RING_SIZE_QCA8074 8
  2118. #define REO_DST_RING_SIZE_QCN9000 8
  2119. #endif /* CONFIG_WIFI_EMULATION_WIFI_3_0 */
  2120. #ifdef IPA_WDI3_TX_TWO_PIPES
  2121. #ifdef DP_MEMORY_OPT
  2122. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2123. {
  2124. return dp_init_tx_ring_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2125. }
  2126. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2127. {
  2128. dp_deinit_tx_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2129. }
  2130. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2131. {
  2132. return dp_alloc_tx_ring_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2133. }
  2134. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2135. {
  2136. dp_free_tx_ring_pair_by_index(soc, IPA_TX_ALT_RING_IDX);
  2137. }
  2138. #else /* !DP_MEMORY_OPT */
  2139. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2140. {
  2141. return 0;
  2142. }
  2143. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2144. {
  2145. }
  2146. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2147. {
  2148. return 0
  2149. }
  2150. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2151. {
  2152. }
  2153. #endif /* DP_MEMORY_OPT */
  2154. void dp_ipa_hal_tx_init_alt_data_ring(struct dp_soc *soc)
  2155. {
  2156. hal_tx_init_data_ring(soc->hal_soc,
  2157. soc->tcl_data_ring[IPA_TX_ALT_RING_IDX].hal_srng);
  2158. }
  2159. #else /* !IPA_WDI3_TX_TWO_PIPES */
  2160. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2161. {
  2162. return 0;
  2163. }
  2164. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2165. {
  2166. }
  2167. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2168. {
  2169. return 0;
  2170. }
  2171. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2172. {
  2173. }
  2174. void dp_ipa_hal_tx_init_alt_data_ring(struct dp_soc *soc)
  2175. {
  2176. }
  2177. #endif /* IPA_WDI3_TX_TWO_PIPES */
  2178. #else
  2179. #define REO_DST_RING_SIZE_QCA6290 1024
  2180. static int dp_ipa_init_alt_tx_ring(struct dp_soc *soc)
  2181. {
  2182. return 0;
  2183. }
  2184. static void dp_ipa_deinit_alt_tx_ring(struct dp_soc *soc)
  2185. {
  2186. }
  2187. static int dp_ipa_alloc_alt_tx_ring(struct dp_soc *soc)
  2188. {
  2189. return 0;
  2190. }
  2191. static void dp_ipa_free_alt_tx_ring(struct dp_soc *soc)
  2192. {
  2193. }
  2194. void dp_ipa_hal_tx_init_alt_data_ring(struct dp_soc *soc)
  2195. {
  2196. }
  2197. #endif /* IPA_OFFLOAD */
  2198. /**
  2199. * dp_soc_reset_cpu_ring_map() - Reset cpu ring map
  2200. * @soc: Datapath soc handler
  2201. *
  2202. * This api resets the default cpu ring map
  2203. */
  2204. void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  2205. {
  2206. uint8_t i;
  2207. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  2208. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  2209. switch (nss_config) {
  2210. case dp_nss_cfg_first_radio:
  2211. /*
  2212. * Setting Tx ring map for one nss offloaded radio
  2213. */
  2214. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  2215. break;
  2216. case dp_nss_cfg_second_radio:
  2217. /*
  2218. * Setting Tx ring for two nss offloaded radios
  2219. */
  2220. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  2221. break;
  2222. case dp_nss_cfg_dbdc:
  2223. /*
  2224. * Setting Tx ring map for 2 nss offloaded radios
  2225. */
  2226. soc->tx_ring_map[i] =
  2227. dp_cpu_ring_map[DP_NSS_DBDC_OFFLOADED_MAP][i];
  2228. break;
  2229. case dp_nss_cfg_dbtc:
  2230. /*
  2231. * Setting Tx ring map for 3 nss offloaded radios
  2232. */
  2233. soc->tx_ring_map[i] =
  2234. dp_cpu_ring_map[DP_NSS_DBTC_OFFLOADED_MAP][i];
  2235. break;
  2236. default:
  2237. dp_err("tx_ring_map failed due to invalid nss cfg");
  2238. break;
  2239. }
  2240. }
  2241. }
  2242. /**
  2243. * dp_soc_disable_unused_mac_intr_mask() - reset interrupt mask for
  2244. * unused WMAC hw rings
  2245. * @soc: DP Soc handle
  2246. * @mac_num: wmac num
  2247. *
  2248. * Return: Return void
  2249. */
  2250. static void dp_soc_disable_unused_mac_intr_mask(struct dp_soc *soc,
  2251. int mac_num)
  2252. {
  2253. uint8_t *grp_mask = NULL;
  2254. int group_number;
  2255. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  2256. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2257. wlan_cfg_set_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  2258. group_number, 0x0);
  2259. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  2260. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2261. wlan_cfg_set_rx_mon_ring_mask(soc->wlan_cfg_ctx,
  2262. group_number, 0x0);
  2263. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  2264. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2265. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx,
  2266. group_number, 0x0);
  2267. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_mon_ring_mask[0];
  2268. group_number = dp_srng_find_ring_in_mask(mac_num, grp_mask);
  2269. wlan_cfg_set_host2rxdma_mon_ring_mask(soc->wlan_cfg_ctx,
  2270. group_number, 0x0);
  2271. }
  2272. #ifdef IPA_OFFLOAD
  2273. #ifdef IPA_WDI3_VLAN_SUPPORT
  2274. /**
  2275. * dp_soc_reset_ipa_vlan_intr_mask() - reset interrupt mask for IPA offloaded
  2276. * ring for vlan tagged traffic
  2277. * @soc: DP Soc handle
  2278. *
  2279. * Return: Return void
  2280. */
  2281. void dp_soc_reset_ipa_vlan_intr_mask(struct dp_soc *soc)
  2282. {
  2283. uint8_t *grp_mask = NULL;
  2284. int group_number, mask;
  2285. if (!wlan_ipa_is_vlan_enabled())
  2286. return;
  2287. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  2288. group_number = dp_srng_find_ring_in_mask(IPA_ALT_REO_DEST_RING_IDX, grp_mask);
  2289. if (group_number < 0) {
  2290. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2291. soc, REO_DST, IPA_ALT_REO_DEST_RING_IDX);
  2292. return;
  2293. }
  2294. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  2295. /* reset the interrupt mask for offloaded ring */
  2296. mask &= (~(1 << IPA_ALT_REO_DEST_RING_IDX));
  2297. /*
  2298. * set the interrupt mask to zero for rx offloaded radio.
  2299. */
  2300. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  2301. }
  2302. #else
  2303. inline
  2304. void dp_soc_reset_ipa_vlan_intr_mask(struct dp_soc *soc)
  2305. { }
  2306. #endif /* IPA_WDI3_VLAN_SUPPORT */
  2307. #else
  2308. inline
  2309. void dp_soc_reset_ipa_vlan_intr_mask(struct dp_soc *soc)
  2310. { }
  2311. #endif /* IPA_OFFLOAD */
  2312. /**
  2313. * dp_soc_reset_intr_mask() - reset interrupt mask
  2314. * @soc: DP Soc handle
  2315. *
  2316. * Return: Return void
  2317. */
  2318. void dp_soc_reset_intr_mask(struct dp_soc *soc)
  2319. {
  2320. uint8_t j;
  2321. uint8_t *grp_mask = NULL;
  2322. int group_number, mask, num_ring;
  2323. /* number of tx ring */
  2324. num_ring = soc->num_tcl_data_rings;
  2325. /*
  2326. * group mask for tx completion ring.
  2327. */
  2328. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  2329. /* loop and reset the mask for only offloaded ring */
  2330. for (j = 0; j < WLAN_CFG_NUM_TCL_DATA_RINGS; j++) {
  2331. /*
  2332. * Group number corresponding to tx offloaded ring.
  2333. */
  2334. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  2335. if (group_number < 0) {
  2336. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2337. soc, WBM2SW_RELEASE, j);
  2338. continue;
  2339. }
  2340. mask = wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, group_number);
  2341. if (!dp_soc_ring_if_nss_offloaded(soc, WBM2SW_RELEASE, j) &&
  2342. (!mask)) {
  2343. continue;
  2344. }
  2345. /* reset the tx mask for offloaded ring */
  2346. mask &= (~(1 << j));
  2347. /*
  2348. * reset the interrupt mask for offloaded ring.
  2349. */
  2350. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  2351. }
  2352. /* number of rx rings */
  2353. num_ring = soc->num_reo_dest_rings;
  2354. /*
  2355. * group mask for reo destination ring.
  2356. */
  2357. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  2358. /* loop and reset the mask for only offloaded ring */
  2359. for (j = 0; j < WLAN_CFG_NUM_REO_DEST_RING; j++) {
  2360. /*
  2361. * Group number corresponding to rx offloaded ring.
  2362. */
  2363. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  2364. if (group_number < 0) {
  2365. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2366. soc, REO_DST, j);
  2367. continue;
  2368. }
  2369. mask = wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, group_number);
  2370. if (!dp_soc_ring_if_nss_offloaded(soc, REO_DST, j) &&
  2371. (!mask)) {
  2372. continue;
  2373. }
  2374. /* reset the interrupt mask for offloaded ring */
  2375. mask &= (~(1 << j));
  2376. /*
  2377. * set the interrupt mask to zero for rx offloaded radio.
  2378. */
  2379. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, group_number, mask);
  2380. }
  2381. /*
  2382. * group mask for Rx buffer refill ring
  2383. */
  2384. grp_mask = &soc->wlan_cfg_ctx->int_host2rxdma_ring_mask[0];
  2385. /* loop and reset the mask for only offloaded ring */
  2386. for (j = 0; j < MAX_PDEV_CNT; j++) {
  2387. int lmac_id = wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  2388. if (!dp_soc_ring_if_nss_offloaded(soc, RXDMA_BUF, j)) {
  2389. continue;
  2390. }
  2391. /*
  2392. * Group number corresponding to rx offloaded ring.
  2393. */
  2394. group_number = dp_srng_find_ring_in_mask(lmac_id, grp_mask);
  2395. if (group_number < 0) {
  2396. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2397. soc, REO_DST, lmac_id);
  2398. continue;
  2399. }
  2400. /* set the interrupt mask for offloaded ring */
  2401. mask = wlan_cfg_get_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  2402. group_number);
  2403. mask &= (~(1 << lmac_id));
  2404. /*
  2405. * set the interrupt mask to zero for rx offloaded radio.
  2406. */
  2407. wlan_cfg_set_host2rxdma_ring_mask(soc->wlan_cfg_ctx,
  2408. group_number, mask);
  2409. }
  2410. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  2411. for (j = 0; j < num_ring; j++) {
  2412. if (!dp_soc_ring_if_nss_offloaded(soc, REO_EXCEPTION, j)) {
  2413. continue;
  2414. }
  2415. /*
  2416. * Group number corresponding to rx err ring.
  2417. */
  2418. group_number = dp_srng_find_ring_in_mask(j, grp_mask);
  2419. if (group_number < 0) {
  2420. dp_init_debug("%pK: ring not part of any group; ring_type: %d,ring_num %d",
  2421. soc, REO_EXCEPTION, j);
  2422. continue;
  2423. }
  2424. wlan_cfg_set_rx_err_ring_mask(soc->wlan_cfg_ctx,
  2425. group_number, 0);
  2426. }
  2427. }
  2428. #ifdef IPA_OFFLOAD
  2429. bool dp_reo_remap_config(struct dp_soc *soc, uint32_t *remap0,
  2430. uint32_t *remap1, uint32_t *remap2)
  2431. {
  2432. uint32_t ring[WLAN_CFG_NUM_REO_DEST_RING_MAX] = {
  2433. REO_REMAP_SW1, REO_REMAP_SW2, REO_REMAP_SW3,
  2434. REO_REMAP_SW5, REO_REMAP_SW6, REO_REMAP_SW7};
  2435. switch (soc->arch_id) {
  2436. case CDP_ARCH_TYPE_BE:
  2437. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2438. soc->num_reo_dest_rings -
  2439. USE_2_IPA_RX_REO_RINGS, remap1,
  2440. remap2);
  2441. break;
  2442. case CDP_ARCH_TYPE_LI:
  2443. if (wlan_ipa_is_vlan_enabled()) {
  2444. hal_compute_reo_remap_ix2_ix3(
  2445. soc->hal_soc, ring,
  2446. soc->num_reo_dest_rings -
  2447. USE_2_IPA_RX_REO_RINGS, remap1,
  2448. remap2);
  2449. } else {
  2450. hal_compute_reo_remap_ix2_ix3(
  2451. soc->hal_soc, ring,
  2452. soc->num_reo_dest_rings -
  2453. USE_1_IPA_RX_REO_RING, remap1,
  2454. remap2);
  2455. }
  2456. hal_compute_reo_remap_ix0(soc->hal_soc, remap0);
  2457. break;
  2458. default:
  2459. dp_err("unknown arch_id 0x%x", soc->arch_id);
  2460. QDF_BUG(0);
  2461. }
  2462. dp_debug("remap1 %x remap2 %x", *remap1, *remap2);
  2463. return true;
  2464. }
  2465. #ifdef IPA_WDI3_TX_TWO_PIPES
  2466. static bool dp_ipa_is_alt_tx_ring(int index)
  2467. {
  2468. return index == IPA_TX_ALT_RING_IDX;
  2469. }
  2470. static bool dp_ipa_is_alt_tx_comp_ring(int index)
  2471. {
  2472. return index == IPA_TX_ALT_COMP_RING_IDX;
  2473. }
  2474. #else /* !IPA_WDI3_TX_TWO_PIPES */
  2475. static bool dp_ipa_is_alt_tx_ring(int index)
  2476. {
  2477. return false;
  2478. }
  2479. static bool dp_ipa_is_alt_tx_comp_ring(int index)
  2480. {
  2481. return false;
  2482. }
  2483. #endif /* IPA_WDI3_TX_TWO_PIPES */
  2484. /**
  2485. * dp_ipa_get_tx_ring_size() - Get Tx ring size for IPA
  2486. *
  2487. * @tx_ring_num: Tx ring number
  2488. * @tx_ipa_ring_sz: Return param only updated for IPA.
  2489. * @soc_cfg_ctx: dp soc cfg context
  2490. *
  2491. * Return: None
  2492. */
  2493. static void dp_ipa_get_tx_ring_size(int tx_ring_num, int *tx_ipa_ring_sz,
  2494. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2495. {
  2496. if (!soc_cfg_ctx->ipa_enabled)
  2497. return;
  2498. if (tx_ring_num == IPA_TCL_DATA_RING_IDX)
  2499. *tx_ipa_ring_sz = wlan_cfg_ipa_tx_ring_size(soc_cfg_ctx);
  2500. else if (dp_ipa_is_alt_tx_ring(tx_ring_num))
  2501. *tx_ipa_ring_sz = wlan_cfg_ipa_tx_alt_ring_size(soc_cfg_ctx);
  2502. }
  2503. /**
  2504. * dp_ipa_get_tx_comp_ring_size() - Get Tx comp ring size for IPA
  2505. *
  2506. * @tx_comp_ring_num: Tx comp ring number
  2507. * @tx_comp_ipa_ring_sz: Return param only updated for IPA.
  2508. * @soc_cfg_ctx: dp soc cfg context
  2509. *
  2510. * Return: None
  2511. */
  2512. static void dp_ipa_get_tx_comp_ring_size(int tx_comp_ring_num,
  2513. int *tx_comp_ipa_ring_sz,
  2514. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2515. {
  2516. if (!soc_cfg_ctx->ipa_enabled)
  2517. return;
  2518. if (tx_comp_ring_num == IPA_TCL_DATA_RING_IDX)
  2519. *tx_comp_ipa_ring_sz =
  2520. wlan_cfg_ipa_tx_comp_ring_size(soc_cfg_ctx);
  2521. else if (dp_ipa_is_alt_tx_comp_ring(tx_comp_ring_num))
  2522. *tx_comp_ipa_ring_sz =
  2523. wlan_cfg_ipa_tx_alt_comp_ring_size(soc_cfg_ctx);
  2524. }
  2525. #else
  2526. static uint8_t dp_reo_ring_selection(uint32_t value, uint32_t *ring)
  2527. {
  2528. uint8_t num = 0;
  2529. switch (value) {
  2530. /* should we have all the different possible ring configs */
  2531. case 0xFF:
  2532. num = 8;
  2533. ring[0] = REO_REMAP_SW1;
  2534. ring[1] = REO_REMAP_SW2;
  2535. ring[2] = REO_REMAP_SW3;
  2536. ring[3] = REO_REMAP_SW4;
  2537. ring[4] = REO_REMAP_SW5;
  2538. ring[5] = REO_REMAP_SW6;
  2539. ring[6] = REO_REMAP_SW7;
  2540. ring[7] = REO_REMAP_SW8;
  2541. break;
  2542. case 0x3F:
  2543. num = 6;
  2544. ring[0] = REO_REMAP_SW1;
  2545. ring[1] = REO_REMAP_SW2;
  2546. ring[2] = REO_REMAP_SW3;
  2547. ring[3] = REO_REMAP_SW4;
  2548. ring[4] = REO_REMAP_SW5;
  2549. ring[5] = REO_REMAP_SW6;
  2550. break;
  2551. case 0xF:
  2552. num = 4;
  2553. ring[0] = REO_REMAP_SW1;
  2554. ring[1] = REO_REMAP_SW2;
  2555. ring[2] = REO_REMAP_SW3;
  2556. ring[3] = REO_REMAP_SW4;
  2557. break;
  2558. case 0xE:
  2559. num = 3;
  2560. ring[0] = REO_REMAP_SW2;
  2561. ring[1] = REO_REMAP_SW3;
  2562. ring[2] = REO_REMAP_SW4;
  2563. break;
  2564. case 0xD:
  2565. num = 3;
  2566. ring[0] = REO_REMAP_SW1;
  2567. ring[1] = REO_REMAP_SW3;
  2568. ring[2] = REO_REMAP_SW4;
  2569. break;
  2570. case 0xC:
  2571. num = 2;
  2572. ring[0] = REO_REMAP_SW3;
  2573. ring[1] = REO_REMAP_SW4;
  2574. break;
  2575. case 0xB:
  2576. num = 3;
  2577. ring[0] = REO_REMAP_SW1;
  2578. ring[1] = REO_REMAP_SW2;
  2579. ring[2] = REO_REMAP_SW4;
  2580. break;
  2581. case 0xA:
  2582. num = 2;
  2583. ring[0] = REO_REMAP_SW2;
  2584. ring[1] = REO_REMAP_SW4;
  2585. break;
  2586. case 0x9:
  2587. num = 2;
  2588. ring[0] = REO_REMAP_SW1;
  2589. ring[1] = REO_REMAP_SW4;
  2590. break;
  2591. case 0x8:
  2592. num = 1;
  2593. ring[0] = REO_REMAP_SW4;
  2594. break;
  2595. case 0x7:
  2596. num = 3;
  2597. ring[0] = REO_REMAP_SW1;
  2598. ring[1] = REO_REMAP_SW2;
  2599. ring[2] = REO_REMAP_SW3;
  2600. break;
  2601. case 0x6:
  2602. num = 2;
  2603. ring[0] = REO_REMAP_SW2;
  2604. ring[1] = REO_REMAP_SW3;
  2605. break;
  2606. case 0x5:
  2607. num = 2;
  2608. ring[0] = REO_REMAP_SW1;
  2609. ring[1] = REO_REMAP_SW3;
  2610. break;
  2611. case 0x4:
  2612. num = 1;
  2613. ring[0] = REO_REMAP_SW3;
  2614. break;
  2615. case 0x3:
  2616. num = 2;
  2617. ring[0] = REO_REMAP_SW1;
  2618. ring[1] = REO_REMAP_SW2;
  2619. break;
  2620. case 0x2:
  2621. num = 1;
  2622. ring[0] = REO_REMAP_SW2;
  2623. break;
  2624. case 0x1:
  2625. num = 1;
  2626. ring[0] = REO_REMAP_SW1;
  2627. break;
  2628. default:
  2629. dp_err("unknown reo ring map 0x%x", value);
  2630. QDF_BUG(0);
  2631. }
  2632. return num;
  2633. }
  2634. bool dp_reo_remap_config(struct dp_soc *soc,
  2635. uint32_t *remap0,
  2636. uint32_t *remap1,
  2637. uint32_t *remap2)
  2638. {
  2639. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  2640. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  2641. uint8_t num;
  2642. uint32_t ring[WLAN_CFG_NUM_REO_DEST_RING_MAX];
  2643. uint32_t value;
  2644. switch (offload_radio) {
  2645. case dp_nss_cfg_default:
  2646. value = reo_config & WLAN_CFG_NUM_REO_RINGS_MAP_MAX;
  2647. num = dp_reo_ring_selection(value, ring);
  2648. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2649. num, remap1, remap2);
  2650. hal_compute_reo_remap_ix0(soc->hal_soc, remap0);
  2651. break;
  2652. case dp_nss_cfg_first_radio:
  2653. value = reo_config & 0xE;
  2654. num = dp_reo_ring_selection(value, ring);
  2655. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2656. num, remap1, remap2);
  2657. break;
  2658. case dp_nss_cfg_second_radio:
  2659. value = reo_config & 0xD;
  2660. num = dp_reo_ring_selection(value, ring);
  2661. hal_compute_reo_remap_ix2_ix3(soc->hal_soc, ring,
  2662. num, remap1, remap2);
  2663. break;
  2664. case dp_nss_cfg_dbdc:
  2665. case dp_nss_cfg_dbtc:
  2666. /* return false if both or all are offloaded to NSS */
  2667. return false;
  2668. }
  2669. dp_debug("remap1 %x remap2 %x offload_radio %u",
  2670. *remap1, *remap2, offload_radio);
  2671. return true;
  2672. }
  2673. static void dp_ipa_get_tx_ring_size(int ring_num, int *tx_ipa_ring_sz,
  2674. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2675. {
  2676. }
  2677. static void dp_ipa_get_tx_comp_ring_size(int tx_comp_ring_num,
  2678. int *tx_comp_ipa_ring_sz,
  2679. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx)
  2680. {
  2681. }
  2682. #endif /* IPA_OFFLOAD */
  2683. /**
  2684. * dp_reo_frag_dst_set() - configure reo register to set the
  2685. * fragment destination ring
  2686. * @soc: Datapath soc
  2687. * @frag_dst_ring: output parameter to set fragment destination ring
  2688. *
  2689. * Based on offload_radio below fragment destination rings is selected
  2690. * 0 - TCL
  2691. * 1 - SW1
  2692. * 2 - SW2
  2693. * 3 - SW3
  2694. * 4 - SW4
  2695. * 5 - Release
  2696. * 6 - FW
  2697. * 7 - alternate select
  2698. *
  2699. * Return: void
  2700. */
  2701. void dp_reo_frag_dst_set(struct dp_soc *soc, uint8_t *frag_dst_ring)
  2702. {
  2703. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  2704. switch (offload_radio) {
  2705. case dp_nss_cfg_default:
  2706. *frag_dst_ring = REO_REMAP_TCL;
  2707. break;
  2708. case dp_nss_cfg_first_radio:
  2709. /*
  2710. * This configuration is valid for single band radio which
  2711. * is also NSS offload.
  2712. */
  2713. case dp_nss_cfg_dbdc:
  2714. case dp_nss_cfg_dbtc:
  2715. *frag_dst_ring = HAL_SRNG_REO_ALTERNATE_SELECT;
  2716. break;
  2717. default:
  2718. dp_init_err("%pK: dp_reo_frag_dst_set invalid offload radio config", soc);
  2719. break;
  2720. }
  2721. }
  2722. #ifdef WLAN_FEATURE_STATS_EXT
  2723. static inline void dp_create_ext_stats_event(struct dp_soc *soc)
  2724. {
  2725. qdf_event_create(&soc->rx_hw_stats_event);
  2726. }
  2727. #else
  2728. static inline void dp_create_ext_stats_event(struct dp_soc *soc)
  2729. {
  2730. }
  2731. #endif
  2732. static void dp_deinit_tx_pair_by_index(struct dp_soc *soc, int index)
  2733. {
  2734. int tcl_ring_num, wbm_ring_num;
  2735. wlan_cfg_get_tcl_wbm_ring_num_for_index(soc->wlan_cfg_ctx,
  2736. index,
  2737. &tcl_ring_num,
  2738. &wbm_ring_num);
  2739. if (tcl_ring_num == -1) {
  2740. dp_err("incorrect tcl ring num for index %u", index);
  2741. return;
  2742. }
  2743. wlan_minidump_remove(soc->tcl_data_ring[index].base_vaddr_unaligned,
  2744. soc->tcl_data_ring[index].alloc_size,
  2745. soc->ctrl_psoc,
  2746. WLAN_MD_DP_SRNG_TCL_DATA,
  2747. "tcl_data_ring");
  2748. dp_info("index %u tcl %u wbm %u", index, tcl_ring_num, wbm_ring_num);
  2749. dp_srng_deinit(soc, &soc->tcl_data_ring[index], TCL_DATA,
  2750. tcl_ring_num);
  2751. if (wbm_ring_num == INVALID_WBM_RING_NUM)
  2752. return;
  2753. wlan_minidump_remove(soc->tx_comp_ring[index].base_vaddr_unaligned,
  2754. soc->tx_comp_ring[index].alloc_size,
  2755. soc->ctrl_psoc,
  2756. WLAN_MD_DP_SRNG_TX_COMP,
  2757. "tcl_comp_ring");
  2758. dp_srng_deinit(soc, &soc->tx_comp_ring[index], WBM2SW_RELEASE,
  2759. wbm_ring_num);
  2760. }
  2761. /**
  2762. * dp_init_tx_ring_pair_by_index() - The function inits tcl data/wbm completion
  2763. * ring pair
  2764. * @soc: DP soc pointer
  2765. * @index: index of soc->tcl_data or soc->tx_comp to initialize
  2766. *
  2767. * Return: QDF_STATUS_SUCCESS on success, error code otherwise.
  2768. */
  2769. static QDF_STATUS dp_init_tx_ring_pair_by_index(struct dp_soc *soc,
  2770. uint8_t index)
  2771. {
  2772. int tcl_ring_num, wbm_ring_num;
  2773. uint8_t bm_id;
  2774. if (index >= MAX_TCL_DATA_RINGS) {
  2775. dp_err("unexpected index!");
  2776. QDF_BUG(0);
  2777. goto fail1;
  2778. }
  2779. wlan_cfg_get_tcl_wbm_ring_num_for_index(soc->wlan_cfg_ctx,
  2780. index,
  2781. &tcl_ring_num,
  2782. &wbm_ring_num);
  2783. if (tcl_ring_num == -1) {
  2784. dp_err("incorrect tcl ring num for index %u", index);
  2785. goto fail1;
  2786. }
  2787. dp_info("index %u tcl %u wbm %u", index, tcl_ring_num, wbm_ring_num);
  2788. if (dp_srng_init(soc, &soc->tcl_data_ring[index], TCL_DATA,
  2789. tcl_ring_num, 0)) {
  2790. dp_err("dp_srng_init failed for tcl_data_ring");
  2791. goto fail1;
  2792. }
  2793. wlan_minidump_log(soc->tcl_data_ring[index].base_vaddr_unaligned,
  2794. soc->tcl_data_ring[index].alloc_size,
  2795. soc->ctrl_psoc,
  2796. WLAN_MD_DP_SRNG_TCL_DATA,
  2797. "tcl_data_ring");
  2798. if (wbm_ring_num == INVALID_WBM_RING_NUM)
  2799. goto set_rbm;
  2800. if (dp_srng_init(soc, &soc->tx_comp_ring[index], WBM2SW_RELEASE,
  2801. wbm_ring_num, 0)) {
  2802. dp_err("dp_srng_init failed for tx_comp_ring");
  2803. goto fail1;
  2804. }
  2805. wlan_minidump_log(soc->tx_comp_ring[index].base_vaddr_unaligned,
  2806. soc->tx_comp_ring[index].alloc_size,
  2807. soc->ctrl_psoc,
  2808. WLAN_MD_DP_SRNG_TX_COMP,
  2809. "tcl_comp_ring");
  2810. set_rbm:
  2811. bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx, tcl_ring_num);
  2812. soc->arch_ops.tx_implicit_rbm_set(soc, tcl_ring_num, bm_id);
  2813. return QDF_STATUS_SUCCESS;
  2814. fail1:
  2815. return QDF_STATUS_E_FAILURE;
  2816. }
  2817. static void dp_free_tx_ring_pair_by_index(struct dp_soc *soc, uint8_t index)
  2818. {
  2819. dp_debug("index %u", index);
  2820. dp_srng_free(soc, &soc->tcl_data_ring[index]);
  2821. dp_srng_free(soc, &soc->tx_comp_ring[index]);
  2822. }
  2823. /**
  2824. * dp_alloc_tx_ring_pair_by_index() - The function allocs tcl data/wbm2sw
  2825. * ring pair for the given "index"
  2826. * @soc: DP soc pointer
  2827. * @index: index of soc->tcl_data or soc->tx_comp to initialize
  2828. *
  2829. * Return: QDF_STATUS_SUCCESS on success, error code otherwise.
  2830. */
  2831. static QDF_STATUS dp_alloc_tx_ring_pair_by_index(struct dp_soc *soc,
  2832. uint8_t index)
  2833. {
  2834. int tx_ring_size;
  2835. int tx_comp_ring_size;
  2836. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  2837. int cached = 0;
  2838. if (index >= MAX_TCL_DATA_RINGS) {
  2839. dp_err("unexpected index!");
  2840. QDF_BUG(0);
  2841. goto fail1;
  2842. }
  2843. dp_debug("index %u", index);
  2844. tx_ring_size = wlan_cfg_tx_ring_size(soc_cfg_ctx);
  2845. dp_ipa_get_tx_ring_size(index, &tx_ring_size, soc_cfg_ctx);
  2846. if (dp_srng_alloc(soc, &soc->tcl_data_ring[index], TCL_DATA,
  2847. tx_ring_size, cached)) {
  2848. dp_err("dp_srng_alloc failed for tcl_data_ring");
  2849. goto fail1;
  2850. }
  2851. tx_comp_ring_size = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx);
  2852. dp_ipa_get_tx_comp_ring_size(index, &tx_comp_ring_size, soc_cfg_ctx);
  2853. /* Enable cached TCL desc if NSS offload is disabled */
  2854. if (!wlan_cfg_get_dp_soc_nss_cfg(soc_cfg_ctx))
  2855. cached = WLAN_CFG_DST_RING_CACHED_DESC;
  2856. if (wlan_cfg_get_wbm_ring_num_for_index(soc->wlan_cfg_ctx, index) ==
  2857. INVALID_WBM_RING_NUM)
  2858. return QDF_STATUS_SUCCESS;
  2859. if (dp_srng_alloc(soc, &soc->tx_comp_ring[index], WBM2SW_RELEASE,
  2860. tx_comp_ring_size, cached)) {
  2861. dp_err("dp_srng_alloc failed for tx_comp_ring");
  2862. goto fail1;
  2863. }
  2864. return QDF_STATUS_SUCCESS;
  2865. fail1:
  2866. return QDF_STATUS_E_FAILURE;
  2867. }
  2868. /**
  2869. * dp_dscp_tid_map_setup() - Initialize the dscp-tid maps
  2870. * @pdev: DP_PDEV handle
  2871. *
  2872. * Return: void
  2873. */
  2874. void
  2875. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  2876. {
  2877. uint8_t map_id;
  2878. struct dp_soc *soc = pdev->soc;
  2879. if (!soc)
  2880. return;
  2881. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  2882. qdf_mem_copy(pdev->dscp_tid_map[map_id],
  2883. default_dscp_tid_map,
  2884. sizeof(default_dscp_tid_map));
  2885. }
  2886. for (map_id = 0; map_id < soc->num_hw_dscp_tid_map; map_id++) {
  2887. hal_tx_set_dscp_tid_map(soc->hal_soc,
  2888. default_dscp_tid_map,
  2889. map_id);
  2890. }
  2891. }
  2892. /**
  2893. * dp_pcp_tid_map_setup() - Initialize the pcp-tid maps
  2894. * @pdev: DP_PDEV handle
  2895. *
  2896. * Return: void
  2897. */
  2898. void
  2899. dp_pcp_tid_map_setup(struct dp_pdev *pdev)
  2900. {
  2901. struct dp_soc *soc = pdev->soc;
  2902. if (!soc)
  2903. return;
  2904. qdf_mem_copy(soc->pcp_tid_map, default_pcp_tid_map,
  2905. sizeof(default_pcp_tid_map));
  2906. hal_tx_set_pcp_tid_map_default(soc->hal_soc, default_pcp_tid_map);
  2907. }
  2908. #ifndef DP_UMAC_HW_RESET_SUPPORT
  2909. static inline
  2910. #endif
  2911. void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2912. {
  2913. struct reo_desc_list_node *desc;
  2914. struct dp_rx_tid *rx_tid;
  2915. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2916. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2917. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2918. rx_tid = &desc->rx_tid;
  2919. qdf_mem_unmap_nbytes_single(soc->osdev,
  2920. rx_tid->hw_qdesc_paddr,
  2921. QDF_DMA_BIDIRECTIONAL,
  2922. rx_tid->hw_qdesc_alloc_size);
  2923. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2924. qdf_mem_free(desc);
  2925. }
  2926. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2927. qdf_list_destroy(&soc->reo_desc_freelist);
  2928. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2929. }
  2930. #ifdef WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY
  2931. /**
  2932. * dp_reo_desc_deferred_freelist_create() - Initialize the resources used
  2933. * for deferred reo desc list
  2934. * @soc: Datapath soc handle
  2935. *
  2936. * Return: void
  2937. */
  2938. static void dp_reo_desc_deferred_freelist_create(struct dp_soc *soc)
  2939. {
  2940. qdf_spinlock_create(&soc->reo_desc_deferred_freelist_lock);
  2941. qdf_list_create(&soc->reo_desc_deferred_freelist,
  2942. REO_DESC_DEFERRED_FREELIST_SIZE);
  2943. soc->reo_desc_deferred_freelist_init = true;
  2944. }
  2945. /**
  2946. * dp_reo_desc_deferred_freelist_destroy() - loop the deferred free list &
  2947. * free the leftover REO QDESCs
  2948. * @soc: Datapath soc handle
  2949. *
  2950. * Return: void
  2951. */
  2952. static void dp_reo_desc_deferred_freelist_destroy(struct dp_soc *soc)
  2953. {
  2954. struct reo_desc_deferred_freelist_node *desc;
  2955. qdf_spin_lock_bh(&soc->reo_desc_deferred_freelist_lock);
  2956. soc->reo_desc_deferred_freelist_init = false;
  2957. while (qdf_list_remove_front(&soc->reo_desc_deferred_freelist,
  2958. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2959. qdf_mem_unmap_nbytes_single(soc->osdev,
  2960. desc->hw_qdesc_paddr,
  2961. QDF_DMA_BIDIRECTIONAL,
  2962. desc->hw_qdesc_alloc_size);
  2963. qdf_mem_free(desc->hw_qdesc_vaddr_unaligned);
  2964. qdf_mem_free(desc);
  2965. }
  2966. qdf_spin_unlock_bh(&soc->reo_desc_deferred_freelist_lock);
  2967. qdf_list_destroy(&soc->reo_desc_deferred_freelist);
  2968. qdf_spinlock_destroy(&soc->reo_desc_deferred_freelist_lock);
  2969. }
  2970. #else
  2971. static inline void dp_reo_desc_deferred_freelist_create(struct dp_soc *soc)
  2972. {
  2973. }
  2974. static inline void dp_reo_desc_deferred_freelist_destroy(struct dp_soc *soc)
  2975. {
  2976. }
  2977. #endif /* !WLAN_DP_FEATURE_DEFERRED_REO_QDESC_DESTROY */
  2978. /**
  2979. * dp_soc_reset_txrx_ring_map() - reset tx ring map
  2980. * @soc: DP SOC handle
  2981. *
  2982. */
  2983. static void dp_soc_reset_txrx_ring_map(struct dp_soc *soc)
  2984. {
  2985. uint32_t i;
  2986. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++)
  2987. soc->tx_ring_map[i] = 0;
  2988. }
  2989. /**
  2990. * dp_soc_deinit() - Deinitialize txrx SOC
  2991. * @txrx_soc: Opaque DP SOC handle
  2992. *
  2993. * Return: None
  2994. */
  2995. void dp_soc_deinit(void *txrx_soc)
  2996. {
  2997. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2998. struct htt_soc *htt_soc = soc->htt_handle;
  2999. dp_monitor_soc_deinit(soc);
  3000. /* free peer tables & AST tables allocated during peer_map_attach */
  3001. if (soc->peer_map_attach_success) {
  3002. dp_peer_find_detach(soc);
  3003. soc->arch_ops.txrx_peer_map_detach(soc);
  3004. soc->peer_map_attach_success = FALSE;
  3005. }
  3006. qdf_flush_work(&soc->htt_stats.work);
  3007. qdf_disable_work(&soc->htt_stats.work);
  3008. qdf_spinlock_destroy(&soc->htt_stats.lock);
  3009. dp_soc_reset_txrx_ring_map(soc);
  3010. dp_reo_desc_freelist_destroy(soc);
  3011. dp_reo_desc_deferred_freelist_destroy(soc);
  3012. DEINIT_RX_HW_STATS_LOCK(soc);
  3013. qdf_spinlock_destroy(&soc->ast_lock);
  3014. dp_peer_mec_spinlock_destroy(soc);
  3015. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  3016. qdf_nbuf_queue_free(&soc->invalid_buf_queue);
  3017. qdf_spinlock_destroy(&soc->rx.defrag.defrag_lock);
  3018. qdf_spinlock_destroy(&soc->vdev_map_lock);
  3019. dp_reo_cmdlist_destroy(soc);
  3020. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  3021. dp_soc_tx_desc_sw_pools_deinit(soc);
  3022. dp_soc_srng_deinit(soc);
  3023. dp_hw_link_desc_ring_deinit(soc);
  3024. dp_soc_print_inactive_objects(soc);
  3025. qdf_spinlock_destroy(&soc->inactive_peer_list_lock);
  3026. qdf_spinlock_destroy(&soc->inactive_vdev_list_lock);
  3027. htt_soc_htc_dealloc(soc->htt_handle);
  3028. htt_soc_detach(htt_soc);
  3029. /* Free wbm sg list and reset flags in down path */
  3030. dp_rx_wbm_sg_list_deinit(soc);
  3031. wlan_minidump_remove(soc, sizeof(*soc), soc->ctrl_psoc,
  3032. WLAN_MD_DP_SOC, "dp_soc");
  3033. }
  3034. #ifdef QCA_HOST2FW_RXBUF_RING
  3035. void
  3036. dp_htt_setup_rxdma_err_dst_ring(struct dp_soc *soc, int mac_id,
  3037. int lmac_id)
  3038. {
  3039. if (soc->rxdma_err_dst_ring[lmac_id].hal_srng)
  3040. htt_srng_setup(soc->htt_handle, mac_id,
  3041. soc->rxdma_err_dst_ring[lmac_id].hal_srng,
  3042. RXDMA_DST);
  3043. }
  3044. #endif
  3045. void dp_vdev_get_default_reo_hash(struct dp_vdev *vdev,
  3046. enum cdp_host_reo_dest_ring *reo_dest,
  3047. bool *hash_based)
  3048. {
  3049. struct dp_soc *soc;
  3050. struct dp_pdev *pdev;
  3051. pdev = vdev->pdev;
  3052. soc = pdev->soc;
  3053. /*
  3054. * hash based steering is disabled for Radios which are offloaded
  3055. * to NSS
  3056. */
  3057. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  3058. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  3059. /*
  3060. * Below line of code will ensure the proper reo_dest ring is chosen
  3061. * for cases where toeplitz hash cannot be generated (ex: non TCP/UDP)
  3062. */
  3063. *reo_dest = pdev->reo_dest;
  3064. }
  3065. #ifdef IPA_OFFLOAD
  3066. /**
  3067. * dp_is_vdev_subtype_p2p() - Check if the subtype for vdev is P2P
  3068. * @vdev: Virtual device
  3069. *
  3070. * Return: true if the vdev is of subtype P2P
  3071. * false if the vdev is of any other subtype
  3072. */
  3073. static inline bool dp_is_vdev_subtype_p2p(struct dp_vdev *vdev)
  3074. {
  3075. if (vdev->subtype == wlan_op_subtype_p2p_device ||
  3076. vdev->subtype == wlan_op_subtype_p2p_cli ||
  3077. vdev->subtype == wlan_op_subtype_p2p_go)
  3078. return true;
  3079. return false;
  3080. }
  3081. /**
  3082. * dp_peer_setup_get_reo_hash() - get reo dest ring and hash values for a peer
  3083. * @vdev: Datapath VDEV handle
  3084. * @setup_info:
  3085. * @reo_dest: pointer to default reo_dest ring for vdev to be populated
  3086. * @hash_based: pointer to hash value (enabled/disabled) to be populated
  3087. * @lmac_peer_id_msb:
  3088. *
  3089. * If IPA is enabled in ini, for SAP mode, disable hash based
  3090. * steering, use default reo_dst ring for RX. Use config values for other modes.
  3091. *
  3092. * Return: None
  3093. */
  3094. static void dp_peer_setup_get_reo_hash(struct dp_vdev *vdev,
  3095. struct cdp_peer_setup_info *setup_info,
  3096. enum cdp_host_reo_dest_ring *reo_dest,
  3097. bool *hash_based,
  3098. uint8_t *lmac_peer_id_msb)
  3099. {
  3100. struct dp_soc *soc;
  3101. struct dp_pdev *pdev;
  3102. pdev = vdev->pdev;
  3103. soc = pdev->soc;
  3104. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  3105. /* For P2P-GO interfaces we do not need to change the REO
  3106. * configuration even if IPA config is enabled
  3107. */
  3108. if (dp_is_vdev_subtype_p2p(vdev))
  3109. return;
  3110. /*
  3111. * If IPA is enabled, disable hash-based flow steering and set
  3112. * reo_dest_ring_4 as the REO ring to receive packets on.
  3113. * IPA is configured to reap reo_dest_ring_4.
  3114. *
  3115. * Note - REO DST indexes are from 0 - 3, while cdp_host_reo_dest_ring
  3116. * value enum value is from 1 - 4.
  3117. * Hence, *reo_dest = IPA_REO_DEST_RING_IDX + 1
  3118. */
  3119. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  3120. if (dp_ipa_is_mdm_platform()) {
  3121. *reo_dest = IPA_REO_DEST_RING_IDX + 1;
  3122. if (vdev->opmode == wlan_op_mode_ap)
  3123. *hash_based = 0;
  3124. } else {
  3125. dp_debug("opt_dp: default HOST reo ring is set");
  3126. }
  3127. }
  3128. }
  3129. #else
  3130. /**
  3131. * dp_peer_setup_get_reo_hash() - get reo dest ring and hash values for a peer
  3132. * @vdev: Datapath VDEV handle
  3133. * @setup_info:
  3134. * @reo_dest: pointer to default reo_dest ring for vdev to be populated
  3135. * @hash_based: pointer to hash value (enabled/disabled) to be populated
  3136. * @lmac_peer_id_msb:
  3137. *
  3138. * Use system config values for hash based steering.
  3139. * Return: None
  3140. */
  3141. static void dp_peer_setup_get_reo_hash(struct dp_vdev *vdev,
  3142. struct cdp_peer_setup_info *setup_info,
  3143. enum cdp_host_reo_dest_ring *reo_dest,
  3144. bool *hash_based,
  3145. uint8_t *lmac_peer_id_msb)
  3146. {
  3147. struct dp_soc *soc = vdev->pdev->soc;
  3148. soc->arch_ops.peer_get_reo_hash(vdev, setup_info, reo_dest, hash_based,
  3149. lmac_peer_id_msb);
  3150. }
  3151. #endif /* IPA_OFFLOAD */
  3152. /**
  3153. * dp_peer_setup_wifi3() - initialize the peer
  3154. * @soc_hdl: soc handle object
  3155. * @vdev_id: vdev_id of vdev object
  3156. * @peer_mac: Peer's mac address
  3157. * @setup_info: peer setup info for MLO
  3158. *
  3159. * Return: QDF_STATUS
  3160. */
  3161. QDF_STATUS
  3162. dp_peer_setup_wifi3(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3163. uint8_t *peer_mac,
  3164. struct cdp_peer_setup_info *setup_info)
  3165. {
  3166. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3167. struct dp_pdev *pdev;
  3168. bool hash_based = 0;
  3169. enum cdp_host_reo_dest_ring reo_dest;
  3170. QDF_STATUS status = QDF_STATUS_SUCCESS;
  3171. struct dp_vdev *vdev = NULL;
  3172. struct dp_peer *peer =
  3173. dp_peer_find_hash_find(soc, peer_mac, 0, vdev_id,
  3174. DP_MOD_ID_CDP);
  3175. struct dp_peer *mld_peer = NULL;
  3176. enum wlan_op_mode vdev_opmode;
  3177. uint8_t lmac_peer_id_msb = 0;
  3178. if (!peer)
  3179. return QDF_STATUS_E_FAILURE;
  3180. vdev = peer->vdev;
  3181. if (!vdev) {
  3182. status = QDF_STATUS_E_FAILURE;
  3183. goto fail;
  3184. }
  3185. /* save vdev related member in case vdev freed */
  3186. vdev_opmode = vdev->opmode;
  3187. pdev = vdev->pdev;
  3188. dp_peer_setup_get_reo_hash(vdev, setup_info,
  3189. &reo_dest, &hash_based,
  3190. &lmac_peer_id_msb);
  3191. dp_cfg_event_record_peer_setup_evt(soc, DP_CFG_EVENT_PEER_SETUP,
  3192. peer, vdev, vdev->vdev_id,
  3193. setup_info);
  3194. dp_info("pdev: %d vdev :%d opmode:%u peer %pK (" QDF_MAC_ADDR_FMT ") "
  3195. "hash-based-steering:%d default-reo_dest:%u",
  3196. pdev->pdev_id, vdev->vdev_id,
  3197. vdev->opmode, peer,
  3198. QDF_MAC_ADDR_REF(peer->mac_addr.raw), hash_based, reo_dest);
  3199. /*
  3200. * There are corner cases where the AD1 = AD2 = "VAPs address"
  3201. * i.e both the devices have same MAC address. In these
  3202. * cases we want such pkts to be processed in NULL Q handler
  3203. * which is REO2TCL ring. for this reason we should
  3204. * not setup reo_queues and default route for bss_peer.
  3205. */
  3206. if (!IS_MLO_DP_MLD_PEER(peer))
  3207. dp_monitor_peer_tx_init(pdev, peer);
  3208. if (!setup_info)
  3209. if (dp_peer_legacy_setup(soc, peer) !=
  3210. QDF_STATUS_SUCCESS) {
  3211. status = QDF_STATUS_E_RESOURCES;
  3212. goto fail;
  3213. }
  3214. if (peer->bss_peer && vdev->opmode == wlan_op_mode_ap) {
  3215. status = QDF_STATUS_E_FAILURE;
  3216. goto fail;
  3217. }
  3218. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  3219. /* TODO: Check the destination ring number to be passed to FW */
  3220. soc->cdp_soc.ol_ops->peer_set_default_routing(
  3221. soc->ctrl_psoc,
  3222. peer->vdev->pdev->pdev_id,
  3223. peer->mac_addr.raw,
  3224. peer->vdev->vdev_id, hash_based, reo_dest,
  3225. lmac_peer_id_msb);
  3226. }
  3227. qdf_atomic_set(&peer->is_default_route_set, 1);
  3228. status = dp_peer_mlo_setup(soc, peer, vdev->vdev_id, setup_info);
  3229. if (QDF_IS_STATUS_ERROR(status)) {
  3230. dp_peer_err("peer mlo setup failed");
  3231. qdf_assert_always(0);
  3232. }
  3233. if (vdev_opmode != wlan_op_mode_monitor) {
  3234. /* In case of MLD peer, switch peer to mld peer and
  3235. * do peer_rx_init.
  3236. */
  3237. if (hal_reo_shared_qaddr_is_enable(soc->hal_soc) &&
  3238. IS_MLO_DP_LINK_PEER(peer)) {
  3239. if (setup_info && setup_info->is_first_link) {
  3240. mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer);
  3241. if (mld_peer)
  3242. dp_peer_rx_init(pdev, mld_peer);
  3243. else
  3244. dp_peer_err("MLD peer null. Primary link peer:%pK", peer);
  3245. }
  3246. } else {
  3247. dp_peer_rx_init(pdev, peer);
  3248. }
  3249. }
  3250. if (!IS_MLO_DP_MLD_PEER(peer))
  3251. dp_peer_ppdu_delayed_ba_init(peer);
  3252. fail:
  3253. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  3254. return status;
  3255. }
  3256. /**
  3257. * dp_set_ba_aging_timeout() - set ba aging timeout per AC
  3258. * @txrx_soc: cdp soc handle
  3259. * @ac: Access category
  3260. * @value: timeout value in millisec
  3261. *
  3262. * Return: void
  3263. */
  3264. void dp_set_ba_aging_timeout(struct cdp_soc_t *txrx_soc,
  3265. uint8_t ac, uint32_t value)
  3266. {
  3267. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3268. hal_set_ba_aging_timeout(soc->hal_soc, ac, value);
  3269. }
  3270. /**
  3271. * dp_get_ba_aging_timeout() - get ba aging timeout per AC
  3272. * @txrx_soc: cdp soc handle
  3273. * @ac: access category
  3274. * @value: timeout value in millisec
  3275. *
  3276. * Return: void
  3277. */
  3278. void dp_get_ba_aging_timeout(struct cdp_soc_t *txrx_soc,
  3279. uint8_t ac, uint32_t *value)
  3280. {
  3281. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  3282. hal_get_ba_aging_timeout(soc->hal_soc, ac, value);
  3283. }
  3284. /**
  3285. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  3286. * @txrx_soc: cdp soc handle
  3287. * @pdev_id: id of physical device object
  3288. * @val: reo destination ring index (1 - 4)
  3289. *
  3290. * Return: QDF_STATUS
  3291. */
  3292. QDF_STATUS
  3293. dp_set_pdev_reo_dest(struct cdp_soc_t *txrx_soc, uint8_t pdev_id,
  3294. enum cdp_host_reo_dest_ring val)
  3295. {
  3296. struct dp_pdev *pdev =
  3297. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)txrx_soc,
  3298. pdev_id);
  3299. if (pdev) {
  3300. pdev->reo_dest = val;
  3301. return QDF_STATUS_SUCCESS;
  3302. }
  3303. return QDF_STATUS_E_FAILURE;
  3304. }
  3305. /**
  3306. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  3307. * @txrx_soc: cdp soc handle
  3308. * @pdev_id: id of physical device object
  3309. *
  3310. * Return: reo destination ring index
  3311. */
  3312. enum cdp_host_reo_dest_ring
  3313. dp_get_pdev_reo_dest(struct cdp_soc_t *txrx_soc, uint8_t pdev_id)
  3314. {
  3315. struct dp_pdev *pdev =
  3316. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)txrx_soc,
  3317. pdev_id);
  3318. if (pdev)
  3319. return pdev->reo_dest;
  3320. else
  3321. return cdp_host_reo_dest_ring_unknown;
  3322. }
  3323. void dp_rx_bar_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3324. union hal_reo_status *reo_status)
  3325. {
  3326. struct dp_pdev *pdev = (struct dp_pdev *)cb_ctxt;
  3327. struct hal_reo_queue_status *queue_status = &(reo_status->queue_status);
  3328. if (!dp_check_pdev_exists(soc, pdev)) {
  3329. dp_err_rl("pdev doesn't exist");
  3330. return;
  3331. }
  3332. if (!qdf_atomic_read(&soc->cmn_init_done))
  3333. return;
  3334. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3335. DP_PRINT_STATS("REO stats failure %d",
  3336. queue_status->header.status);
  3337. qdf_atomic_set(&(pdev->stats_cmd_complete), 1);
  3338. return;
  3339. }
  3340. pdev->stats.rx.bar_recv_cnt += queue_status->bar_rcvd_cnt;
  3341. qdf_atomic_set(&(pdev->stats_cmd_complete), 1);
  3342. }
  3343. /**
  3344. * dp_dump_wbm_idle_hptp() - dump wbm idle ring, hw hp tp info.
  3345. * @soc: dp soc.
  3346. * @pdev: dp pdev.
  3347. *
  3348. * Return: None.
  3349. */
  3350. void
  3351. dp_dump_wbm_idle_hptp(struct dp_soc *soc, struct dp_pdev *pdev)
  3352. {
  3353. uint32_t hw_head;
  3354. uint32_t hw_tail;
  3355. struct dp_srng *srng;
  3356. if (!soc) {
  3357. dp_err("soc is NULL");
  3358. return;
  3359. }
  3360. if (!pdev) {
  3361. dp_err("pdev is NULL");
  3362. return;
  3363. }
  3364. srng = &pdev->soc->wbm_idle_link_ring;
  3365. if (!srng) {
  3366. dp_err("wbm_idle_link_ring srng is NULL");
  3367. return;
  3368. }
  3369. hal_get_hw_hptp(soc->hal_soc, srng->hal_srng, &hw_head,
  3370. &hw_tail, WBM_IDLE_LINK);
  3371. dp_debug("WBM_IDLE_LINK: HW hp: %d, HW tp: %d",
  3372. hw_head, hw_tail);
  3373. }
  3374. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3375. static void dp_update_soft_irq_limits(struct dp_soc *soc, uint32_t tx_limit,
  3376. uint32_t rx_limit)
  3377. {
  3378. soc->wlan_cfg_ctx->tx_comp_loop_pkt_limit = tx_limit;
  3379. soc->wlan_cfg_ctx->rx_reap_loop_pkt_limit = rx_limit;
  3380. }
  3381. #else
  3382. static inline
  3383. void dp_update_soft_irq_limits(struct dp_soc *soc, uint32_t tx_limit,
  3384. uint32_t rx_limit)
  3385. {
  3386. }
  3387. #endif /* WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT */
  3388. /**
  3389. * dp_display_srng_info() - Dump the srng HP TP info
  3390. * @soc_hdl: CDP Soc handle
  3391. *
  3392. * This function dumps the SW hp/tp values for the important rings.
  3393. * HW hp/tp values are not being dumped, since it can lead to
  3394. * READ NOC error when UMAC is in low power state. MCC does not have
  3395. * device force wake working yet.
  3396. *
  3397. * Return: none
  3398. */
  3399. void dp_display_srng_info(struct cdp_soc_t *soc_hdl)
  3400. {
  3401. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3402. hal_soc_handle_t hal_soc = soc->hal_soc;
  3403. uint32_t hp, tp, i;
  3404. dp_info("SRNG HP-TP data:");
  3405. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3406. hal_get_sw_hptp(hal_soc, soc->tcl_data_ring[i].hal_srng,
  3407. &tp, &hp);
  3408. dp_info("TCL DATA ring[%d]: hp=0x%x, tp=0x%x", i, hp, tp);
  3409. if (wlan_cfg_get_wbm_ring_num_for_index(soc->wlan_cfg_ctx, i) ==
  3410. INVALID_WBM_RING_NUM)
  3411. continue;
  3412. hal_get_sw_hptp(hal_soc, soc->tx_comp_ring[i].hal_srng,
  3413. &tp, &hp);
  3414. dp_info("TX comp ring[%d]: hp=0x%x, tp=0x%x", i, hp, tp);
  3415. }
  3416. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  3417. hal_get_sw_hptp(hal_soc, soc->reo_dest_ring[i].hal_srng,
  3418. &tp, &hp);
  3419. dp_info("REO DST ring[%d]: hp=0x%x, tp=0x%x", i, hp, tp);
  3420. }
  3421. hal_get_sw_hptp(hal_soc, soc->reo_exception_ring.hal_srng, &tp, &hp);
  3422. dp_info("REO exception ring: hp=0x%x, tp=0x%x", hp, tp);
  3423. hal_get_sw_hptp(hal_soc, soc->rx_rel_ring.hal_srng, &tp, &hp);
  3424. dp_info("WBM RX release ring: hp=0x%x, tp=0x%x", hp, tp);
  3425. hal_get_sw_hptp(hal_soc, soc->wbm_desc_rel_ring.hal_srng, &tp, &hp);
  3426. dp_info("WBM desc release ring: hp=0x%x, tp=0x%x", hp, tp);
  3427. }
  3428. /**
  3429. * dp_set_pdev_pcp_tid_map_wifi3() - update pcp tid map in pdev
  3430. * @psoc: dp soc handle
  3431. * @pdev_id: id of DP_PDEV handle
  3432. * @pcp: pcp value
  3433. * @tid: tid value passed by the user
  3434. *
  3435. * Return: QDF_STATUS_SUCCESS on success
  3436. */
  3437. QDF_STATUS dp_set_pdev_pcp_tid_map_wifi3(ol_txrx_soc_handle psoc,
  3438. uint8_t pdev_id,
  3439. uint8_t pcp, uint8_t tid)
  3440. {
  3441. struct dp_soc *soc = (struct dp_soc *)psoc;
  3442. soc->pcp_tid_map[pcp] = tid;
  3443. hal_tx_update_pcp_tid_map(soc->hal_soc, pcp, tid);
  3444. return QDF_STATUS_SUCCESS;
  3445. }
  3446. /**
  3447. * dp_set_vdev_pcp_tid_map_wifi3() - update pcp tid map in vdev
  3448. * @soc_hdl: DP soc handle
  3449. * @vdev_id: id of DP_VDEV handle
  3450. * @pcp: pcp value
  3451. * @tid: tid value passed by the user
  3452. *
  3453. * Return: QDF_STATUS_SUCCESS on success
  3454. */
  3455. QDF_STATUS dp_set_vdev_pcp_tid_map_wifi3(struct cdp_soc_t *soc_hdl,
  3456. uint8_t vdev_id,
  3457. uint8_t pcp, uint8_t tid)
  3458. {
  3459. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3460. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3461. DP_MOD_ID_CDP);
  3462. if (!vdev)
  3463. return QDF_STATUS_E_FAILURE;
  3464. vdev->pcp_tid_map[pcp] = tid;
  3465. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3466. return QDF_STATUS_SUCCESS;
  3467. }
  3468. #if defined(FEATURE_RUNTIME_PM) || defined(DP_POWER_SAVE)
  3469. void dp_drain_txrx(struct cdp_soc_t *soc_handle)
  3470. {
  3471. struct dp_soc *soc = (struct dp_soc *)soc_handle;
  3472. uint32_t cur_tx_limit, cur_rx_limit;
  3473. uint32_t budget = 0xffff;
  3474. uint32_t val;
  3475. int i;
  3476. int cpu = dp_srng_get_cpu();
  3477. cur_tx_limit = soc->wlan_cfg_ctx->tx_comp_loop_pkt_limit;
  3478. cur_rx_limit = soc->wlan_cfg_ctx->rx_reap_loop_pkt_limit;
  3479. /* Temporarily increase soft irq limits when going to drain
  3480. * the UMAC/LMAC SRNGs and restore them after polling.
  3481. * Though the budget is on higher side, the TX/RX reaping loops
  3482. * will not execute longer as both TX and RX would be suspended
  3483. * by the time this API is called.
  3484. */
  3485. dp_update_soft_irq_limits(soc, budget, budget);
  3486. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  3487. dp_service_srngs(&soc->intr_ctx[i], budget, cpu);
  3488. dp_update_soft_irq_limits(soc, cur_tx_limit, cur_rx_limit);
  3489. /* Do a dummy read at offset 0; this will ensure all
  3490. * pendings writes(HP/TP) are flushed before read returns.
  3491. */
  3492. val = HAL_REG_READ((struct hal_soc *)soc->hal_soc, 0);
  3493. dp_debug("Register value at offset 0: %u\n", val);
  3494. }
  3495. #endif
  3496. #if defined(DP_POWER_SAVE) || defined(FEATURE_RUNTIME_PM)
  3497. /**
  3498. * dp_flush_ring_hptp() - Update ring shadow
  3499. * register HP/TP address when runtime
  3500. * resume
  3501. * @soc: DP soc context
  3502. * @hal_srng: srng
  3503. *
  3504. * Return: None
  3505. */
  3506. static void dp_flush_ring_hptp(struct dp_soc *soc, hal_ring_handle_t hal_srng)
  3507. {
  3508. if (hal_srng && hal_srng_get_clear_event(hal_srng,
  3509. HAL_SRNG_FLUSH_EVENT)) {
  3510. /* Acquire the lock */
  3511. hal_srng_access_start(soc->hal_soc, hal_srng);
  3512. hal_srng_access_end(soc->hal_soc, hal_srng);
  3513. hal_srng_set_flush_last_ts(hal_srng);
  3514. dp_debug("flushed");
  3515. }
  3516. }
  3517. void dp_update_ring_hptp(struct dp_soc *soc, bool force_flush_tx)
  3518. {
  3519. uint8_t i;
  3520. if (force_flush_tx) {
  3521. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3522. hal_srng_set_event(soc->tcl_data_ring[i].hal_srng,
  3523. HAL_SRNG_FLUSH_EVENT);
  3524. dp_flush_ring_hptp(soc, soc->tcl_data_ring[i].hal_srng);
  3525. }
  3526. return;
  3527. }
  3528. for (i = 0; i < soc->num_tcl_data_rings; i++)
  3529. dp_flush_ring_hptp(soc, soc->tcl_data_ring[i].hal_srng);
  3530. dp_flush_ring_hptp(soc, soc->reo_cmd_ring.hal_srng);
  3531. }
  3532. #endif
  3533. #ifdef WLAN_FEATURE_STATS_EXT
  3534. /* rx hw stats event wait timeout in ms */
  3535. #define DP_REO_STATUS_STATS_TIMEOUT 100
  3536. /**
  3537. * dp_rx_hw_stats_cb() - request rx hw stats response callback
  3538. * @soc: soc handle
  3539. * @cb_ctxt: callback context
  3540. * @reo_status: reo command response status
  3541. *
  3542. * Return: None
  3543. */
  3544. static void dp_rx_hw_stats_cb(struct dp_soc *soc, void *cb_ctxt,
  3545. union hal_reo_status *reo_status)
  3546. {
  3547. struct dp_req_rx_hw_stats_t *rx_hw_stats = cb_ctxt;
  3548. struct hal_reo_queue_status *queue_status = &reo_status->queue_status;
  3549. bool is_query_timeout;
  3550. qdf_spin_lock_bh(&soc->rx_hw_stats_lock);
  3551. is_query_timeout = rx_hw_stats->is_query_timeout;
  3552. /* free the cb_ctxt if all pending tid stats query is received */
  3553. if (qdf_atomic_dec_and_test(&rx_hw_stats->pending_tid_stats_cnt)) {
  3554. if (!is_query_timeout) {
  3555. qdf_event_set(&soc->rx_hw_stats_event);
  3556. soc->is_last_stats_ctx_init = false;
  3557. }
  3558. qdf_mem_free(rx_hw_stats);
  3559. }
  3560. if (queue_status->header.status != HAL_REO_CMD_SUCCESS) {
  3561. dp_info("REO stats failure %d",
  3562. queue_status->header.status);
  3563. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3564. return;
  3565. }
  3566. if (!is_query_timeout) {
  3567. soc->ext_stats.rx_mpdu_received +=
  3568. queue_status->mpdu_frms_cnt;
  3569. soc->ext_stats.rx_mpdu_missed +=
  3570. queue_status->hole_cnt;
  3571. }
  3572. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3573. }
  3574. /**
  3575. * dp_request_rx_hw_stats() - request rx hardware stats
  3576. * @soc_hdl: soc handle
  3577. * @vdev_id: vdev id
  3578. *
  3579. * Return: None
  3580. */
  3581. QDF_STATUS
  3582. dp_request_rx_hw_stats(struct cdp_soc_t *soc_hdl, uint8_t vdev_id)
  3583. {
  3584. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3585. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3586. DP_MOD_ID_CDP);
  3587. struct dp_peer *peer = NULL;
  3588. QDF_STATUS status;
  3589. struct dp_req_rx_hw_stats_t *rx_hw_stats;
  3590. int rx_stats_sent_cnt = 0;
  3591. uint32_t last_rx_mpdu_received;
  3592. uint32_t last_rx_mpdu_missed;
  3593. if (!vdev) {
  3594. dp_err("vdev is null for vdev_id: %u", vdev_id);
  3595. status = QDF_STATUS_E_INVAL;
  3596. goto out;
  3597. }
  3598. peer = dp_vdev_bss_peer_ref_n_get(soc, vdev, DP_MOD_ID_CDP);
  3599. if (!peer) {
  3600. dp_err("Peer is NULL");
  3601. status = QDF_STATUS_E_INVAL;
  3602. goto out;
  3603. }
  3604. rx_hw_stats = qdf_mem_malloc(sizeof(*rx_hw_stats));
  3605. if (!rx_hw_stats) {
  3606. dp_err("malloc failed for hw stats structure");
  3607. status = QDF_STATUS_E_INVAL;
  3608. goto out;
  3609. }
  3610. qdf_event_reset(&soc->rx_hw_stats_event);
  3611. qdf_spin_lock_bh(&soc->rx_hw_stats_lock);
  3612. /* save the last soc cumulative stats and reset it to 0 */
  3613. last_rx_mpdu_received = soc->ext_stats.rx_mpdu_received;
  3614. last_rx_mpdu_missed = soc->ext_stats.rx_mpdu_missed;
  3615. soc->ext_stats.rx_mpdu_received = 0;
  3616. soc->ext_stats.rx_mpdu_missed = 0;
  3617. dp_debug("HW stats query start");
  3618. rx_stats_sent_cnt =
  3619. dp_peer_rxtid_stats(peer, dp_rx_hw_stats_cb, rx_hw_stats);
  3620. if (!rx_stats_sent_cnt) {
  3621. dp_err("no tid stats sent successfully");
  3622. qdf_mem_free(rx_hw_stats);
  3623. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3624. status = QDF_STATUS_E_INVAL;
  3625. goto out;
  3626. }
  3627. qdf_atomic_set(&rx_hw_stats->pending_tid_stats_cnt,
  3628. rx_stats_sent_cnt);
  3629. rx_hw_stats->is_query_timeout = false;
  3630. soc->is_last_stats_ctx_init = true;
  3631. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3632. status = qdf_wait_single_event(&soc->rx_hw_stats_event,
  3633. DP_REO_STATUS_STATS_TIMEOUT);
  3634. dp_debug("HW stats query end with %d", rx_stats_sent_cnt);
  3635. qdf_spin_lock_bh(&soc->rx_hw_stats_lock);
  3636. if (status != QDF_STATUS_SUCCESS) {
  3637. dp_info("partial rx hw stats event collected with %d",
  3638. qdf_atomic_read(
  3639. &rx_hw_stats->pending_tid_stats_cnt));
  3640. if (soc->is_last_stats_ctx_init)
  3641. rx_hw_stats->is_query_timeout = true;
  3642. /*
  3643. * If query timeout happened, use the last saved stats
  3644. * for this time query.
  3645. */
  3646. soc->ext_stats.rx_mpdu_received = last_rx_mpdu_received;
  3647. soc->ext_stats.rx_mpdu_missed = last_rx_mpdu_missed;
  3648. DP_STATS_INC(soc, rx.rx_hw_stats_timeout, 1);
  3649. }
  3650. qdf_spin_unlock_bh(&soc->rx_hw_stats_lock);
  3651. out:
  3652. if (peer)
  3653. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  3654. if (vdev)
  3655. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3656. DP_STATS_INC(soc, rx.rx_hw_stats_requested, 1);
  3657. return status;
  3658. }
  3659. /**
  3660. * dp_reset_rx_hw_ext_stats() - Reset rx hardware ext stats
  3661. * @soc_hdl: soc handle
  3662. *
  3663. * Return: None
  3664. */
  3665. void dp_reset_rx_hw_ext_stats(struct cdp_soc_t *soc_hdl)
  3666. {
  3667. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3668. soc->ext_stats.rx_mpdu_received = 0;
  3669. soc->ext_stats.rx_mpdu_missed = 0;
  3670. }
  3671. #endif /* WLAN_FEATURE_STATS_EXT */
  3672. uint32_t dp_get_tx_rings_grp_bitmap(struct cdp_soc_t *soc_hdl)
  3673. {
  3674. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  3675. return soc->wlan_cfg_ctx->tx_rings_grp_bitmap;
  3676. }
  3677. void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  3678. {
  3679. uint32_t i;
  3680. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  3681. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_DEFAULT_MAP][i];
  3682. }
  3683. }
  3684. qdf_export_symbol(dp_soc_set_txrx_ring_map);
  3685. static void dp_soc_cfg_dump(struct dp_soc *soc, uint32_t target_type)
  3686. {
  3687. dp_init_info("DP soc Dump for Target = %d", target_type);
  3688. dp_init_info("ast_override_support = %d, da_war_enabled = %d,",
  3689. soc->ast_override_support, soc->da_war_enabled);
  3690. wlan_cfg_dp_soc_ctx_dump(soc->wlan_cfg_ctx);
  3691. }
  3692. /**
  3693. * dp_soc_cfg_init() - initialize target specific configuration
  3694. * during dp_soc_init
  3695. * @soc: dp soc handle
  3696. */
  3697. static void dp_soc_cfg_init(struct dp_soc *soc)
  3698. {
  3699. uint32_t target_type;
  3700. target_type = hal_get_target_type(soc->hal_soc);
  3701. switch (target_type) {
  3702. case TARGET_TYPE_QCA6290:
  3703. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  3704. REO_DST_RING_SIZE_QCA6290);
  3705. soc->ast_override_support = 1;
  3706. soc->da_war_enabled = false;
  3707. break;
  3708. case TARGET_TYPE_QCA6390:
  3709. case TARGET_TYPE_QCA6490:
  3710. case TARGET_TYPE_QCA6750:
  3711. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  3712. REO_DST_RING_SIZE_QCA6290);
  3713. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, true);
  3714. soc->ast_override_support = 1;
  3715. if (soc->cdp_soc.ol_ops->get_con_mode &&
  3716. soc->cdp_soc.ol_ops->get_con_mode() ==
  3717. QDF_GLOBAL_MONITOR_MODE) {
  3718. int int_ctx;
  3719. for (int_ctx = 0; int_ctx < WLAN_CFG_INT_NUM_CONTEXTS; int_ctx++) {
  3720. soc->wlan_cfg_ctx->int_rx_ring_mask[int_ctx] = 0;
  3721. soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[int_ctx] = 0;
  3722. }
  3723. }
  3724. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  3725. break;
  3726. case TARGET_TYPE_KIWI:
  3727. case TARGET_TYPE_MANGO:
  3728. case TARGET_TYPE_PEACH:
  3729. soc->ast_override_support = 1;
  3730. soc->per_tid_basize_max_tid = 8;
  3731. if (soc->cdp_soc.ol_ops->get_con_mode &&
  3732. soc->cdp_soc.ol_ops->get_con_mode() ==
  3733. QDF_GLOBAL_MONITOR_MODE) {
  3734. int int_ctx;
  3735. for (int_ctx = 0; int_ctx < WLAN_CFG_INT_NUM_CONTEXTS;
  3736. int_ctx++) {
  3737. soc->wlan_cfg_ctx->int_rx_ring_mask[int_ctx] = 0;
  3738. if (dp_is_monitor_mode_using_poll(soc))
  3739. soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[int_ctx] = 0;
  3740. }
  3741. }
  3742. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  3743. soc->wlan_cfg_ctx->num_rxdma_dst_rings_per_pdev = 1;
  3744. break;
  3745. case TARGET_TYPE_QCA8074:
  3746. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, true);
  3747. soc->da_war_enabled = true;
  3748. soc->is_rx_fse_full_cache_invalidate_war_enabled = true;
  3749. break;
  3750. case TARGET_TYPE_QCA8074V2:
  3751. case TARGET_TYPE_QCA6018:
  3752. case TARGET_TYPE_QCA9574:
  3753. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3754. soc->ast_override_support = 1;
  3755. soc->per_tid_basize_max_tid = 8;
  3756. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS;
  3757. soc->da_war_enabled = false;
  3758. soc->is_rx_fse_full_cache_invalidate_war_enabled = true;
  3759. break;
  3760. case TARGET_TYPE_QCN9000:
  3761. soc->ast_override_support = 1;
  3762. soc->da_war_enabled = false;
  3763. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3764. soc->per_tid_basize_max_tid = 8;
  3765. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS;
  3766. soc->lmac_polled_mode = 0;
  3767. soc->wbm_release_desc_rx_sg_support = 1;
  3768. soc->is_rx_fse_full_cache_invalidate_war_enabled = true;
  3769. break;
  3770. case TARGET_TYPE_QCA5018:
  3771. case TARGET_TYPE_QCN6122:
  3772. case TARGET_TYPE_QCN9160:
  3773. soc->ast_override_support = 1;
  3774. soc->da_war_enabled = false;
  3775. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3776. soc->per_tid_basize_max_tid = 8;
  3777. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_MAPS_11AX;
  3778. soc->disable_mac1_intr = 1;
  3779. soc->disable_mac2_intr = 1;
  3780. soc->wbm_release_desc_rx_sg_support = 1;
  3781. break;
  3782. case TARGET_TYPE_QCN9224:
  3783. soc->ast_override_support = 1;
  3784. soc->da_war_enabled = false;
  3785. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3786. soc->per_tid_basize_max_tid = 8;
  3787. soc->wbm_release_desc_rx_sg_support = 1;
  3788. soc->rxdma2sw_rings_not_supported = 1;
  3789. soc->wbm_sg_last_msdu_war = 1;
  3790. soc->ast_offload_support = AST_OFFLOAD_ENABLE_STATUS;
  3791. soc->mec_fw_offload = FW_MEC_FW_OFFLOAD_ENABLED;
  3792. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS;
  3793. wlan_cfg_set_txmon_hw_support(soc->wlan_cfg_ctx, true);
  3794. soc->host_ast_db_enable = cfg_get(soc->ctrl_psoc,
  3795. CFG_DP_HOST_AST_DB_ENABLE);
  3796. soc->features.wds_ext_ast_override_enable = true;
  3797. break;
  3798. case TARGET_TYPE_QCA5332:
  3799. soc->ast_override_support = 1;
  3800. soc->da_war_enabled = false;
  3801. wlan_cfg_set_raw_mode_war(soc->wlan_cfg_ctx, false);
  3802. soc->per_tid_basize_max_tid = 8;
  3803. soc->wbm_release_desc_rx_sg_support = 1;
  3804. soc->rxdma2sw_rings_not_supported = 1;
  3805. soc->wbm_sg_last_msdu_war = 1;
  3806. soc->ast_offload_support = AST_OFFLOAD_ENABLE_STATUS;
  3807. soc->mec_fw_offload = FW_MEC_FW_OFFLOAD_ENABLED;
  3808. soc->num_hw_dscp_tid_map = HAL_MAX_HW_DSCP_TID_V2_MAPS_5332;
  3809. wlan_cfg_set_txmon_hw_support(soc->wlan_cfg_ctx, true);
  3810. soc->host_ast_db_enable = cfg_get(soc->ctrl_psoc,
  3811. CFG_DP_HOST_AST_DB_ENABLE);
  3812. soc->features.wds_ext_ast_override_enable = true;
  3813. break;
  3814. default:
  3815. qdf_print("%s: Unknown tgt type %d\n", __func__, target_type);
  3816. qdf_assert_always(0);
  3817. break;
  3818. }
  3819. dp_soc_cfg_dump(soc, target_type);
  3820. }
  3821. /**
  3822. * dp_soc_init() - Initialize txrx SOC
  3823. * @soc: Opaque DP SOC handle
  3824. * @htc_handle: Opaque HTC handle
  3825. * @hif_handle: Opaque HIF handle
  3826. *
  3827. * Return: DP SOC handle on success, NULL on failure
  3828. */
  3829. void *dp_soc_init(struct dp_soc *soc, HTC_HANDLE htc_handle,
  3830. struct hif_opaque_softc *hif_handle)
  3831. {
  3832. struct htt_soc *htt_soc = (struct htt_soc *)soc->htt_handle;
  3833. bool is_monitor_mode = false;
  3834. uint8_t i;
  3835. int num_dp_msi;
  3836. bool ppeds_attached = false;
  3837. htt_soc = htt_soc_attach(soc, htc_handle);
  3838. if (!htt_soc)
  3839. goto fail1;
  3840. soc->htt_handle = htt_soc;
  3841. if (htt_soc_htc_prealloc(htt_soc) != QDF_STATUS_SUCCESS)
  3842. goto fail2;
  3843. htt_set_htc_handle(htt_soc, htc_handle);
  3844. dp_soc_cfg_init(soc);
  3845. dp_monitor_soc_cfg_init(soc);
  3846. /* Reset/Initialize wbm sg list and flags */
  3847. dp_rx_wbm_sg_list_reset(soc);
  3848. /* Note: Any SRNG ring initialization should happen only after
  3849. * Interrupt mode is set and followed by filling up the
  3850. * interrupt mask. IT SHOULD ALWAYS BE IN THIS ORDER.
  3851. */
  3852. dp_soc_set_interrupt_mode(soc);
  3853. if (soc->cdp_soc.ol_ops->get_con_mode &&
  3854. soc->cdp_soc.ol_ops->get_con_mode() ==
  3855. QDF_GLOBAL_MONITOR_MODE) {
  3856. is_monitor_mode = true;
  3857. soc->curr_rx_pkt_tlv_size = soc->rx_mon_pkt_tlv_size;
  3858. } else {
  3859. soc->curr_rx_pkt_tlv_size = soc->rx_pkt_tlv_size;
  3860. }
  3861. num_dp_msi = dp_get_num_msi_available(soc, soc->intr_mode);
  3862. if (num_dp_msi < 0) {
  3863. dp_init_err("%pK: dp_interrupt assignment failed", soc);
  3864. goto fail3;
  3865. }
  3866. if (soc->arch_ops.ppeds_handle_attached)
  3867. ppeds_attached = soc->arch_ops.ppeds_handle_attached(soc);
  3868. wlan_cfg_fill_interrupt_mask(soc->wlan_cfg_ctx, num_dp_msi,
  3869. soc->intr_mode, is_monitor_mode,
  3870. ppeds_attached);
  3871. /* initialize WBM_IDLE_LINK ring */
  3872. if (dp_hw_link_desc_ring_init(soc)) {
  3873. dp_init_err("%pK: dp_hw_link_desc_ring_init failed", soc);
  3874. goto fail3;
  3875. }
  3876. dp_link_desc_ring_replenish(soc, WLAN_INVALID_PDEV_ID);
  3877. if (dp_soc_srng_init(soc)) {
  3878. dp_init_err("%pK: dp_soc_srng_init failed", soc);
  3879. goto fail4;
  3880. }
  3881. if (htt_soc_initialize(soc->htt_handle, soc->ctrl_psoc,
  3882. htt_get_htc_handle(htt_soc),
  3883. soc->hal_soc, soc->osdev) == NULL)
  3884. goto fail5;
  3885. /* Initialize descriptors in TCL Rings */
  3886. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  3887. hal_tx_init_data_ring(soc->hal_soc,
  3888. soc->tcl_data_ring[i].hal_srng);
  3889. }
  3890. if (dp_soc_tx_desc_sw_pools_init(soc)) {
  3891. dp_init_err("%pK: dp_tx_soc_attach failed", soc);
  3892. goto fail6;
  3893. }
  3894. if (soc->arch_ops.txrx_soc_ppeds_start) {
  3895. if (soc->arch_ops.txrx_soc_ppeds_start(soc)) {
  3896. dp_init_err("%pK: ppeds start failed", soc);
  3897. goto fail7;
  3898. }
  3899. }
  3900. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx,
  3901. cfg_get(soc->ctrl_psoc, CFG_DP_RX_HASH));
  3902. soc->cce_disable = false;
  3903. soc->max_ast_ageout_count = MAX_AST_AGEOUT_COUNT;
  3904. soc->sta_mode_search_policy = DP_TX_ADDR_SEARCH_ADDR_POLICY;
  3905. qdf_mem_zero(&soc->vdev_id_map, sizeof(soc->vdev_id_map));
  3906. qdf_spinlock_create(&soc->vdev_map_lock);
  3907. qdf_atomic_init(&soc->num_tx_outstanding);
  3908. qdf_atomic_init(&soc->num_tx_exception);
  3909. soc->num_tx_allowed =
  3910. wlan_cfg_get_dp_soc_tx_device_limit(soc->wlan_cfg_ctx);
  3911. soc->num_tx_spl_allowed =
  3912. wlan_cfg_get_dp_soc_tx_spl_device_limit(soc->wlan_cfg_ctx);
  3913. soc->num_reg_tx_allowed = soc->num_tx_allowed - soc->num_tx_spl_allowed;
  3914. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  3915. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  3916. CDP_CFG_MAX_PEER_ID);
  3917. if (ret != -EINVAL)
  3918. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  3919. ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc->ctrl_psoc,
  3920. CDP_CFG_CCE_DISABLE);
  3921. if (ret == 1)
  3922. soc->cce_disable = true;
  3923. }
  3924. /*
  3925. * Skip registering hw ring interrupts for WMAC2 on IPQ6018
  3926. * and IPQ5018 WMAC2 is not there in these platforms.
  3927. */
  3928. if (hal_get_target_type(soc->hal_soc) == TARGET_TYPE_QCA6018 ||
  3929. soc->disable_mac2_intr)
  3930. dp_soc_disable_unused_mac_intr_mask(soc, 0x2);
  3931. /*
  3932. * Skip registering hw ring interrupts for WMAC1 on IPQ5018
  3933. * WMAC1 is not there in this platform.
  3934. */
  3935. if (soc->disable_mac1_intr)
  3936. dp_soc_disable_unused_mac_intr_mask(soc, 0x1);
  3937. /* setup the global rx defrag waitlist */
  3938. TAILQ_INIT(&soc->rx.defrag.waitlist);
  3939. soc->rx.defrag.timeout_ms =
  3940. wlan_cfg_get_rx_defrag_min_timeout(soc->wlan_cfg_ctx);
  3941. soc->rx.defrag.next_flush_ms = 0;
  3942. soc->rx.flags.defrag_timeout_check =
  3943. wlan_cfg_get_defrag_timeout_check(soc->wlan_cfg_ctx);
  3944. qdf_spinlock_create(&soc->rx.defrag.defrag_lock);
  3945. dp_monitor_soc_init(soc);
  3946. qdf_atomic_set(&soc->cmn_init_done, 1);
  3947. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  3948. qdf_spinlock_create(&soc->ast_lock);
  3949. dp_peer_mec_spinlock_create(soc);
  3950. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  3951. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  3952. INIT_RX_HW_STATS_LOCK(soc);
  3953. qdf_nbuf_queue_init(&soc->invalid_buf_queue);
  3954. /* fill the tx/rx cpu ring map*/
  3955. dp_soc_set_txrx_ring_map(soc);
  3956. TAILQ_INIT(&soc->inactive_peer_list);
  3957. qdf_spinlock_create(&soc->inactive_peer_list_lock);
  3958. TAILQ_INIT(&soc->inactive_vdev_list);
  3959. qdf_spinlock_create(&soc->inactive_vdev_list_lock);
  3960. qdf_spinlock_create(&soc->htt_stats.lock);
  3961. /* initialize work queue for stats processing */
  3962. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  3963. dp_reo_desc_deferred_freelist_create(soc);
  3964. dp_info("Mem stats: DMA = %u HEAP = %u SKB = %u",
  3965. qdf_dma_mem_stats_read(),
  3966. qdf_heap_mem_stats_read(),
  3967. qdf_skb_total_mem_stats_read());
  3968. soc->vdev_stats_id_map = 0;
  3969. return soc;
  3970. fail7:
  3971. dp_soc_tx_desc_sw_pools_deinit(soc);
  3972. fail6:
  3973. htt_soc_htc_dealloc(soc->htt_handle);
  3974. fail5:
  3975. dp_soc_srng_deinit(soc);
  3976. fail4:
  3977. dp_hw_link_desc_ring_deinit(soc);
  3978. fail3:
  3979. htt_htc_pkt_pool_free(htt_soc);
  3980. fail2:
  3981. htt_soc_detach(htt_soc);
  3982. fail1:
  3983. return NULL;
  3984. }
  3985. #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG
  3986. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_init(struct dp_soc *soc)
  3987. {
  3988. QDF_STATUS status;
  3989. if (soc->init_tcl_cmd_cred_ring) {
  3990. status = dp_srng_init(soc, &soc->tcl_cmd_credit_ring,
  3991. TCL_CMD_CREDIT, 0, 0);
  3992. if (QDF_IS_STATUS_ERROR(status))
  3993. return status;
  3994. wlan_minidump_log(soc->tcl_cmd_credit_ring.base_vaddr_unaligned,
  3995. soc->tcl_cmd_credit_ring.alloc_size,
  3996. soc->ctrl_psoc,
  3997. WLAN_MD_DP_SRNG_TCL_CMD,
  3998. "wbm_desc_rel_ring");
  3999. }
  4000. return QDF_STATUS_SUCCESS;
  4001. }
  4002. static inline void dp_soc_tcl_cmd_cred_srng_deinit(struct dp_soc *soc)
  4003. {
  4004. if (soc->init_tcl_cmd_cred_ring) {
  4005. wlan_minidump_remove(soc->tcl_cmd_credit_ring.base_vaddr_unaligned,
  4006. soc->tcl_cmd_credit_ring.alloc_size,
  4007. soc->ctrl_psoc, WLAN_MD_DP_SRNG_TCL_CMD,
  4008. "wbm_desc_rel_ring");
  4009. dp_srng_deinit(soc, &soc->tcl_cmd_credit_ring,
  4010. TCL_CMD_CREDIT, 0);
  4011. }
  4012. }
  4013. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_alloc(struct dp_soc *soc)
  4014. {
  4015. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  4016. uint32_t entries;
  4017. QDF_STATUS status;
  4018. entries = wlan_cfg_get_dp_soc_tcl_cmd_credit_ring_size(soc_cfg_ctx);
  4019. if (soc->init_tcl_cmd_cred_ring) {
  4020. status = dp_srng_alloc(soc, &soc->tcl_cmd_credit_ring,
  4021. TCL_CMD_CREDIT, entries, 0);
  4022. if (QDF_IS_STATUS_ERROR(status))
  4023. return status;
  4024. }
  4025. return QDF_STATUS_SUCCESS;
  4026. }
  4027. static inline void dp_soc_tcl_cmd_cred_srng_free(struct dp_soc *soc)
  4028. {
  4029. if (soc->init_tcl_cmd_cred_ring)
  4030. dp_srng_free(soc, &soc->tcl_cmd_credit_ring);
  4031. }
  4032. inline void dp_tx_init_cmd_credit_ring(struct dp_soc *soc)
  4033. {
  4034. if (soc->init_tcl_cmd_cred_ring)
  4035. hal_tx_init_cmd_credit_ring(soc->hal_soc,
  4036. soc->tcl_cmd_credit_ring.hal_srng);
  4037. }
  4038. #else
  4039. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_init(struct dp_soc *soc)
  4040. {
  4041. return QDF_STATUS_SUCCESS;
  4042. }
  4043. static inline void dp_soc_tcl_cmd_cred_srng_deinit(struct dp_soc *soc)
  4044. {
  4045. }
  4046. static inline QDF_STATUS dp_soc_tcl_cmd_cred_srng_alloc(struct dp_soc *soc)
  4047. {
  4048. return QDF_STATUS_SUCCESS;
  4049. }
  4050. static inline void dp_soc_tcl_cmd_cred_srng_free(struct dp_soc *soc)
  4051. {
  4052. }
  4053. inline void dp_tx_init_cmd_credit_ring(struct dp_soc *soc)
  4054. {
  4055. }
  4056. #endif
  4057. #ifndef WLAN_DP_DISABLE_TCL_STATUS_SRNG
  4058. static inline QDF_STATUS dp_soc_tcl_status_srng_init(struct dp_soc *soc)
  4059. {
  4060. QDF_STATUS status;
  4061. status = dp_srng_init(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0);
  4062. if (QDF_IS_STATUS_ERROR(status))
  4063. return status;
  4064. wlan_minidump_log(soc->tcl_status_ring.base_vaddr_unaligned,
  4065. soc->tcl_status_ring.alloc_size,
  4066. soc->ctrl_psoc,
  4067. WLAN_MD_DP_SRNG_TCL_STATUS,
  4068. "wbm_desc_rel_ring");
  4069. return QDF_STATUS_SUCCESS;
  4070. }
  4071. static inline void dp_soc_tcl_status_srng_deinit(struct dp_soc *soc)
  4072. {
  4073. wlan_minidump_remove(soc->tcl_status_ring.base_vaddr_unaligned,
  4074. soc->tcl_status_ring.alloc_size,
  4075. soc->ctrl_psoc, WLAN_MD_DP_SRNG_TCL_STATUS,
  4076. "wbm_desc_rel_ring");
  4077. dp_srng_deinit(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  4078. }
  4079. static inline QDF_STATUS dp_soc_tcl_status_srng_alloc(struct dp_soc *soc)
  4080. {
  4081. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  4082. uint32_t entries;
  4083. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4084. entries = wlan_cfg_get_dp_soc_tcl_status_ring_size(soc_cfg_ctx);
  4085. status = dp_srng_alloc(soc, &soc->tcl_status_ring,
  4086. TCL_STATUS, entries, 0);
  4087. return status;
  4088. }
  4089. static inline void dp_soc_tcl_status_srng_free(struct dp_soc *soc)
  4090. {
  4091. dp_srng_free(soc, &soc->tcl_status_ring);
  4092. }
  4093. #else
  4094. static inline QDF_STATUS dp_soc_tcl_status_srng_init(struct dp_soc *soc)
  4095. {
  4096. return QDF_STATUS_SUCCESS;
  4097. }
  4098. static inline void dp_soc_tcl_status_srng_deinit(struct dp_soc *soc)
  4099. {
  4100. }
  4101. static inline QDF_STATUS dp_soc_tcl_status_srng_alloc(struct dp_soc *soc)
  4102. {
  4103. return QDF_STATUS_SUCCESS;
  4104. }
  4105. static inline void dp_soc_tcl_status_srng_free(struct dp_soc *soc)
  4106. {
  4107. }
  4108. #endif
  4109. /**
  4110. * dp_soc_srng_deinit() - de-initialize soc srng rings
  4111. * @soc: Datapath soc handle
  4112. *
  4113. */
  4114. void dp_soc_srng_deinit(struct dp_soc *soc)
  4115. {
  4116. uint32_t i;
  4117. if (soc->arch_ops.txrx_soc_srng_deinit)
  4118. soc->arch_ops.txrx_soc_srng_deinit(soc);
  4119. /* Free the ring memories */
  4120. /* Common rings */
  4121. wlan_minidump_remove(soc->wbm_desc_rel_ring.base_vaddr_unaligned,
  4122. soc->wbm_desc_rel_ring.alloc_size,
  4123. soc->ctrl_psoc, WLAN_MD_DP_SRNG_WBM_DESC_REL,
  4124. "wbm_desc_rel_ring");
  4125. dp_srng_deinit(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  4126. /* Tx data rings */
  4127. for (i = 0; i < soc->num_tcl_data_rings; i++)
  4128. dp_deinit_tx_pair_by_index(soc, i);
  4129. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4130. dp_deinit_tx_pair_by_index(soc, IPA_TCL_DATA_RING_IDX);
  4131. dp_ipa_deinit_alt_tx_ring(soc);
  4132. }
  4133. /* TCL command and status rings */
  4134. dp_soc_tcl_cmd_cred_srng_deinit(soc);
  4135. dp_soc_tcl_status_srng_deinit(soc);
  4136. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  4137. /* TODO: Get number of rings and ring sizes
  4138. * from wlan_cfg
  4139. */
  4140. wlan_minidump_remove(soc->reo_dest_ring[i].base_vaddr_unaligned,
  4141. soc->reo_dest_ring[i].alloc_size,
  4142. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_DEST,
  4143. "reo_dest_ring");
  4144. dp_srng_deinit(soc, &soc->reo_dest_ring[i], REO_DST, i);
  4145. }
  4146. /* REO reinjection ring */
  4147. wlan_minidump_remove(soc->reo_reinject_ring.base_vaddr_unaligned,
  4148. soc->reo_reinject_ring.alloc_size,
  4149. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_REINJECT,
  4150. "reo_reinject_ring");
  4151. dp_srng_deinit(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  4152. /* Rx release ring */
  4153. wlan_minidump_remove(soc->rx_rel_ring.base_vaddr_unaligned,
  4154. soc->rx_rel_ring.alloc_size,
  4155. soc->ctrl_psoc, WLAN_MD_DP_SRNG_RX_REL,
  4156. "reo_release_ring");
  4157. dp_srng_deinit(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  4158. /* Rx exception ring */
  4159. /* TODO: Better to store ring_type and ring_num in
  4160. * dp_srng during setup
  4161. */
  4162. wlan_minidump_remove(soc->reo_exception_ring.base_vaddr_unaligned,
  4163. soc->reo_exception_ring.alloc_size,
  4164. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_EXCEPTION,
  4165. "reo_exception_ring");
  4166. dp_srng_deinit(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  4167. /* REO command and status rings */
  4168. wlan_minidump_remove(soc->reo_cmd_ring.base_vaddr_unaligned,
  4169. soc->reo_cmd_ring.alloc_size,
  4170. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_CMD,
  4171. "reo_cmd_ring");
  4172. dp_srng_deinit(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  4173. wlan_minidump_remove(soc->reo_status_ring.base_vaddr_unaligned,
  4174. soc->reo_status_ring.alloc_size,
  4175. soc->ctrl_psoc, WLAN_MD_DP_SRNG_REO_STATUS,
  4176. "reo_status_ring");
  4177. dp_srng_deinit(soc, &soc->reo_status_ring, REO_STATUS, 0);
  4178. }
  4179. /**
  4180. * dp_soc_srng_init() - Initialize soc level srng rings
  4181. * @soc: Datapath soc handle
  4182. *
  4183. * Return: QDF_STATUS_SUCCESS on success
  4184. * QDF_STATUS_E_FAILURE on failure
  4185. */
  4186. QDF_STATUS dp_soc_srng_init(struct dp_soc *soc)
  4187. {
  4188. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  4189. uint8_t i;
  4190. uint8_t wbm2_sw_rx_rel_ring_id;
  4191. soc_cfg_ctx = soc->wlan_cfg_ctx;
  4192. dp_enable_verbose_debug(soc);
  4193. /* WBM descriptor release ring */
  4194. if (dp_srng_init(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0)) {
  4195. dp_init_err("%pK: dp_srng_init failed for wbm_desc_rel_ring", soc);
  4196. goto fail1;
  4197. }
  4198. wlan_minidump_log(soc->wbm_desc_rel_ring.base_vaddr_unaligned,
  4199. soc->wbm_desc_rel_ring.alloc_size,
  4200. soc->ctrl_psoc,
  4201. WLAN_MD_DP_SRNG_WBM_DESC_REL,
  4202. "wbm_desc_rel_ring");
  4203. /* TCL command and status rings */
  4204. if (dp_soc_tcl_cmd_cred_srng_init(soc)) {
  4205. dp_init_err("%pK: dp_srng_init failed for tcl_cmd_ring", soc);
  4206. goto fail1;
  4207. }
  4208. if (dp_soc_tcl_status_srng_init(soc)) {
  4209. dp_init_err("%pK: dp_srng_init failed for tcl_status_ring", soc);
  4210. goto fail1;
  4211. }
  4212. /* REO reinjection ring */
  4213. if (dp_srng_init(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0)) {
  4214. dp_init_err("%pK: dp_srng_init failed for reo_reinject_ring", soc);
  4215. goto fail1;
  4216. }
  4217. wlan_minidump_log(soc->reo_reinject_ring.base_vaddr_unaligned,
  4218. soc->reo_reinject_ring.alloc_size,
  4219. soc->ctrl_psoc,
  4220. WLAN_MD_DP_SRNG_REO_REINJECT,
  4221. "reo_reinject_ring");
  4222. wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc_cfg_ctx);
  4223. /* Rx release ring */
  4224. if (dp_srng_init(soc, &soc->rx_rel_ring, WBM2SW_RELEASE,
  4225. wbm2_sw_rx_rel_ring_id, 0)) {
  4226. dp_init_err("%pK: dp_srng_init failed for rx_rel_ring", soc);
  4227. goto fail1;
  4228. }
  4229. wlan_minidump_log(soc->rx_rel_ring.base_vaddr_unaligned,
  4230. soc->rx_rel_ring.alloc_size,
  4231. soc->ctrl_psoc,
  4232. WLAN_MD_DP_SRNG_RX_REL,
  4233. "reo_release_ring");
  4234. /* Rx exception ring */
  4235. if (dp_srng_init(soc, &soc->reo_exception_ring,
  4236. REO_EXCEPTION, 0, MAX_REO_DEST_RINGS)) {
  4237. dp_init_err("%pK: dp_srng_init failed - reo_exception", soc);
  4238. goto fail1;
  4239. }
  4240. wlan_minidump_log(soc->reo_exception_ring.base_vaddr_unaligned,
  4241. soc->reo_exception_ring.alloc_size,
  4242. soc->ctrl_psoc,
  4243. WLAN_MD_DP_SRNG_REO_EXCEPTION,
  4244. "reo_exception_ring");
  4245. /* REO command and status rings */
  4246. if (dp_srng_init(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0)) {
  4247. dp_init_err("%pK: dp_srng_init failed for reo_cmd_ring", soc);
  4248. goto fail1;
  4249. }
  4250. wlan_minidump_log(soc->reo_cmd_ring.base_vaddr_unaligned,
  4251. soc->reo_cmd_ring.alloc_size,
  4252. soc->ctrl_psoc,
  4253. WLAN_MD_DP_SRNG_REO_CMD,
  4254. "reo_cmd_ring");
  4255. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  4256. TAILQ_INIT(&soc->rx.reo_cmd_list);
  4257. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  4258. if (dp_srng_init(soc, &soc->reo_status_ring, REO_STATUS, 0, 0)) {
  4259. dp_init_err("%pK: dp_srng_init failed for reo_status_ring", soc);
  4260. goto fail1;
  4261. }
  4262. wlan_minidump_log(soc->reo_status_ring.base_vaddr_unaligned,
  4263. soc->reo_status_ring.alloc_size,
  4264. soc->ctrl_psoc,
  4265. WLAN_MD_DP_SRNG_REO_STATUS,
  4266. "reo_status_ring");
  4267. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  4268. if (dp_init_tx_ring_pair_by_index(soc, i))
  4269. goto fail1;
  4270. }
  4271. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4272. if (dp_init_tx_ring_pair_by_index(soc, IPA_TCL_DATA_RING_IDX))
  4273. goto fail1;
  4274. if (dp_ipa_init_alt_tx_ring(soc))
  4275. goto fail1;
  4276. }
  4277. dp_create_ext_stats_event(soc);
  4278. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  4279. /* Initialize REO destination ring */
  4280. if (dp_srng_init(soc, &soc->reo_dest_ring[i], REO_DST, i, 0)) {
  4281. dp_init_err("%pK: dp_srng_init failed for reo_dest_ringn", soc);
  4282. goto fail1;
  4283. }
  4284. wlan_minidump_log(soc->reo_dest_ring[i].base_vaddr_unaligned,
  4285. soc->reo_dest_ring[i].alloc_size,
  4286. soc->ctrl_psoc,
  4287. WLAN_MD_DP_SRNG_REO_DEST,
  4288. "reo_dest_ring");
  4289. }
  4290. if (soc->arch_ops.txrx_soc_srng_init) {
  4291. if (soc->arch_ops.txrx_soc_srng_init(soc)) {
  4292. dp_init_err("%pK: dp_srng_init failed for arch rings",
  4293. soc);
  4294. goto fail1;
  4295. }
  4296. }
  4297. return QDF_STATUS_SUCCESS;
  4298. fail1:
  4299. /*
  4300. * Cleanup will be done as part of soc_detach, which will
  4301. * be called on pdev attach failure
  4302. */
  4303. dp_soc_srng_deinit(soc);
  4304. return QDF_STATUS_E_FAILURE;
  4305. }
  4306. /**
  4307. * dp_soc_srng_free() - free soc level srng rings
  4308. * @soc: Datapath soc handle
  4309. *
  4310. */
  4311. void dp_soc_srng_free(struct dp_soc *soc)
  4312. {
  4313. uint32_t i;
  4314. if (soc->arch_ops.txrx_soc_srng_free)
  4315. soc->arch_ops.txrx_soc_srng_free(soc);
  4316. dp_srng_free(soc, &soc->wbm_desc_rel_ring);
  4317. for (i = 0; i < soc->num_tcl_data_rings; i++)
  4318. dp_free_tx_ring_pair_by_index(soc, i);
  4319. /* Free IPA rings for TCL_TX and TCL_COMPL ring */
  4320. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4321. dp_free_tx_ring_pair_by_index(soc, IPA_TCL_DATA_RING_IDX);
  4322. dp_ipa_free_alt_tx_ring(soc);
  4323. }
  4324. dp_soc_tcl_cmd_cred_srng_free(soc);
  4325. dp_soc_tcl_status_srng_free(soc);
  4326. for (i = 0; i < soc->num_reo_dest_rings; i++)
  4327. dp_srng_free(soc, &soc->reo_dest_ring[i]);
  4328. dp_srng_free(soc, &soc->reo_reinject_ring);
  4329. dp_srng_free(soc, &soc->rx_rel_ring);
  4330. dp_srng_free(soc, &soc->reo_exception_ring);
  4331. dp_srng_free(soc, &soc->reo_cmd_ring);
  4332. dp_srng_free(soc, &soc->reo_status_ring);
  4333. }
  4334. /**
  4335. * dp_soc_srng_alloc() - Allocate memory for soc level srng rings
  4336. * @soc: Datapath soc handle
  4337. *
  4338. * Return: QDF_STATUS_SUCCESS on success
  4339. * QDF_STATUS_E_NOMEM on failure
  4340. */
  4341. QDF_STATUS dp_soc_srng_alloc(struct dp_soc *soc)
  4342. {
  4343. uint32_t entries;
  4344. uint32_t i;
  4345. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  4346. uint32_t cached = WLAN_CFG_DST_RING_CACHED_DESC;
  4347. uint32_t reo_dst_ring_size;
  4348. soc_cfg_ctx = soc->wlan_cfg_ctx;
  4349. /* sw2wbm link descriptor release ring */
  4350. entries = wlan_cfg_get_dp_soc_wbm_release_ring_size(soc_cfg_ctx);
  4351. if (dp_srng_alloc(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE,
  4352. entries, 0)) {
  4353. dp_init_err("%pK: dp_srng_alloc failed for wbm_desc_rel_ring", soc);
  4354. goto fail1;
  4355. }
  4356. /* TCL command and status rings */
  4357. if (dp_soc_tcl_cmd_cred_srng_alloc(soc)) {
  4358. dp_init_err("%pK: dp_srng_alloc failed for tcl_cmd_ring", soc);
  4359. goto fail1;
  4360. }
  4361. if (dp_soc_tcl_status_srng_alloc(soc)) {
  4362. dp_init_err("%pK: dp_srng_alloc failed for tcl_status_ring", soc);
  4363. goto fail1;
  4364. }
  4365. /* REO reinjection ring */
  4366. entries = wlan_cfg_get_dp_soc_reo_reinject_ring_size(soc_cfg_ctx);
  4367. if (dp_srng_alloc(soc, &soc->reo_reinject_ring, REO_REINJECT,
  4368. entries, 0)) {
  4369. dp_init_err("%pK: dp_srng_alloc failed for reo_reinject_ring", soc);
  4370. goto fail1;
  4371. }
  4372. /* Rx release ring */
  4373. entries = wlan_cfg_get_dp_soc_rx_release_ring_size(soc_cfg_ctx);
  4374. if (dp_srng_alloc(soc, &soc->rx_rel_ring, WBM2SW_RELEASE,
  4375. entries, 0)) {
  4376. dp_init_err("%pK: dp_srng_alloc failed for rx_rel_ring", soc);
  4377. goto fail1;
  4378. }
  4379. /* Rx exception ring */
  4380. entries = wlan_cfg_get_dp_soc_reo_exception_ring_size(soc_cfg_ctx);
  4381. if (dp_srng_alloc(soc, &soc->reo_exception_ring, REO_EXCEPTION,
  4382. entries, 0)) {
  4383. dp_init_err("%pK: dp_srng_alloc failed - reo_exception", soc);
  4384. goto fail1;
  4385. }
  4386. /* REO command and status rings */
  4387. entries = wlan_cfg_get_dp_soc_reo_cmd_ring_size(soc_cfg_ctx);
  4388. if (dp_srng_alloc(soc, &soc->reo_cmd_ring, REO_CMD, entries, 0)) {
  4389. dp_init_err("%pK: dp_srng_alloc failed for reo_cmd_ring", soc);
  4390. goto fail1;
  4391. }
  4392. entries = wlan_cfg_get_dp_soc_reo_status_ring_size(soc_cfg_ctx);
  4393. if (dp_srng_alloc(soc, &soc->reo_status_ring, REO_STATUS,
  4394. entries, 0)) {
  4395. dp_init_err("%pK: dp_srng_alloc failed for reo_status_ring", soc);
  4396. goto fail1;
  4397. }
  4398. reo_dst_ring_size = wlan_cfg_get_reo_dst_ring_size(soc_cfg_ctx);
  4399. /* Disable cached desc if NSS offload is enabled */
  4400. if (wlan_cfg_get_dp_soc_nss_cfg(soc_cfg_ctx))
  4401. cached = 0;
  4402. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  4403. if (dp_alloc_tx_ring_pair_by_index(soc, i))
  4404. goto fail1;
  4405. }
  4406. /* IPA rings for TCL_TX and TX_COMP will be allocated here */
  4407. if (wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx)) {
  4408. if (dp_alloc_tx_ring_pair_by_index(soc, IPA_TCL_DATA_RING_IDX))
  4409. goto fail1;
  4410. if (dp_ipa_alloc_alt_tx_ring(soc))
  4411. goto fail1;
  4412. }
  4413. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  4414. /* Setup REO destination ring */
  4415. if (dp_srng_alloc(soc, &soc->reo_dest_ring[i], REO_DST,
  4416. reo_dst_ring_size, cached)) {
  4417. dp_init_err("%pK: dp_srng_alloc failed for reo_dest_ring", soc);
  4418. goto fail1;
  4419. }
  4420. }
  4421. if (soc->arch_ops.txrx_soc_srng_alloc) {
  4422. if (soc->arch_ops.txrx_soc_srng_alloc(soc)) {
  4423. dp_init_err("%pK: dp_srng_alloc failed for arch rings",
  4424. soc);
  4425. goto fail1;
  4426. }
  4427. }
  4428. return QDF_STATUS_SUCCESS;
  4429. fail1:
  4430. dp_soc_srng_free(soc);
  4431. return QDF_STATUS_E_NOMEM;
  4432. }
  4433. /**
  4434. * dp_soc_cfg_attach() - set target specific configuration in
  4435. * dp soc cfg.
  4436. * @soc: dp soc handle
  4437. */
  4438. void dp_soc_cfg_attach(struct dp_soc *soc)
  4439. {
  4440. int target_type;
  4441. int nss_cfg = 0;
  4442. target_type = hal_get_target_type(soc->hal_soc);
  4443. switch (target_type) {
  4444. case TARGET_TYPE_QCA6290:
  4445. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  4446. REO_DST_RING_SIZE_QCA6290);
  4447. break;
  4448. case TARGET_TYPE_QCA6390:
  4449. case TARGET_TYPE_QCA6490:
  4450. case TARGET_TYPE_QCA6750:
  4451. wlan_cfg_set_reo_dst_ring_size(soc->wlan_cfg_ctx,
  4452. REO_DST_RING_SIZE_QCA6290);
  4453. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  4454. break;
  4455. case TARGET_TYPE_KIWI:
  4456. case TARGET_TYPE_MANGO:
  4457. case TARGET_TYPE_PEACH:
  4458. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  4459. break;
  4460. case TARGET_TYPE_QCA8074:
  4461. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4462. break;
  4463. case TARGET_TYPE_QCA8074V2:
  4464. case TARGET_TYPE_QCA6018:
  4465. case TARGET_TYPE_QCA9574:
  4466. case TARGET_TYPE_QCN6122:
  4467. case TARGET_TYPE_QCA5018:
  4468. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4469. wlan_cfg_set_rxdma1_enable(soc->wlan_cfg_ctx);
  4470. break;
  4471. case TARGET_TYPE_QCN9160:
  4472. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4473. soc->wlan_cfg_ctx->rxdma1_enable = 0;
  4474. break;
  4475. case TARGET_TYPE_QCN9000:
  4476. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4477. wlan_cfg_set_rxdma1_enable(soc->wlan_cfg_ctx);
  4478. break;
  4479. case TARGET_TYPE_QCN9224:
  4480. case TARGET_TYPE_QCA5332:
  4481. wlan_cfg_set_tso_desc_attach_defer(soc->wlan_cfg_ctx, 1);
  4482. wlan_cfg_set_rxdma1_enable(soc->wlan_cfg_ctx);
  4483. break;
  4484. default:
  4485. qdf_print("%s: Unknown tgt type %d\n", __func__, target_type);
  4486. qdf_assert_always(0);
  4487. break;
  4488. }
  4489. if (soc->cdp_soc.ol_ops->get_soc_nss_cfg)
  4490. nss_cfg = soc->cdp_soc.ol_ops->get_soc_nss_cfg(soc->ctrl_psoc);
  4491. wlan_cfg_set_dp_soc_nss_cfg(soc->wlan_cfg_ctx, nss_cfg);
  4492. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  4493. wlan_cfg_set_num_tx_desc_pool(soc->wlan_cfg_ctx, 0);
  4494. wlan_cfg_set_num_tx_ext_desc_pool(soc->wlan_cfg_ctx, 0);
  4495. wlan_cfg_set_num_tx_desc(soc->wlan_cfg_ctx, 0);
  4496. wlan_cfg_set_num_tx_ext_desc(soc->wlan_cfg_ctx, 0);
  4497. soc->init_tcl_cmd_cred_ring = false;
  4498. soc->num_tcl_data_rings =
  4499. wlan_cfg_num_nss_tcl_data_rings(soc->wlan_cfg_ctx);
  4500. soc->num_reo_dest_rings =
  4501. wlan_cfg_num_nss_reo_dest_rings(soc->wlan_cfg_ctx);
  4502. } else {
  4503. soc->init_tcl_cmd_cred_ring = true;
  4504. soc->num_tx_comp_rings =
  4505. wlan_cfg_num_tx_comp_rings(soc->wlan_cfg_ctx);
  4506. soc->num_tcl_data_rings =
  4507. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  4508. soc->num_reo_dest_rings =
  4509. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  4510. }
  4511. }
  4512. void dp_pdev_set_default_reo(struct dp_pdev *pdev)
  4513. {
  4514. struct dp_soc *soc = pdev->soc;
  4515. switch (pdev->pdev_id) {
  4516. case 0:
  4517. pdev->reo_dest =
  4518. wlan_cfg_radio0_default_reo_get(soc->wlan_cfg_ctx);
  4519. break;
  4520. case 1:
  4521. pdev->reo_dest =
  4522. wlan_cfg_radio1_default_reo_get(soc->wlan_cfg_ctx);
  4523. break;
  4524. case 2:
  4525. pdev->reo_dest =
  4526. wlan_cfg_radio2_default_reo_get(soc->wlan_cfg_ctx);
  4527. break;
  4528. default:
  4529. dp_init_err("%pK: Invalid pdev_id %d for reo selection",
  4530. soc, pdev->pdev_id);
  4531. break;
  4532. }
  4533. }