dp_ipa.c 121 KB

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  1. /*
  2. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <wlan_ipa_ucfg_api.h>
  18. #include <wlan_ipa_core.h>
  19. #include <qdf_ipa_wdi3.h>
  20. #include <qdf_types.h>
  21. #include <qdf_lock.h>
  22. #include <hal_hw_headers.h>
  23. #include <hal_api.h>
  24. #include <hal_reo.h>
  25. #include <hif.h>
  26. #include <htt.h>
  27. #include <wdi_event.h>
  28. #include <queue.h>
  29. #include "dp_types.h"
  30. #include "dp_htt.h"
  31. #include "dp_tx.h"
  32. #include "dp_rx.h"
  33. #include "dp_ipa.h"
  34. #include "dp_internal.h"
  35. #ifdef WIFI_MONITOR_SUPPORT
  36. #include "dp_mon.h"
  37. #endif
  38. #ifdef FEATURE_WDS
  39. #include "dp_txrx_wds.h"
  40. #endif
  41. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  42. #include <pld_common.h>
  43. #endif
  44. #ifdef IPA_OFFLOAD
  45. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  46. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  47. /* WAR for IPA_OFFLOAD case. In some cases, its observed that WBM tries to
  48. * release a buffer into WBM2SW RELEASE ring for IPA, and the ring is full.
  49. * This causes back pressure, resulting in a FW crash.
  50. * By leaving some entries with no buffer attached, WBM will be able to write
  51. * to the ring, and from dumps we can figure out the buffer which is causing
  52. * this issue.
  53. */
  54. #define DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES 16
  55. /**
  56. * struct dp_ipa_reo_remap_record - history for dp ipa reo remaps
  57. * @timestamp: Timestamp when remap occurs
  58. * @ix0_reg: reo destination ring IX0 value
  59. * @ix2_reg: reo destination ring IX2 value
  60. * @ix3_reg: reo destination ring IX3 value
  61. */
  62. struct dp_ipa_reo_remap_record {
  63. uint64_t timestamp;
  64. uint32_t ix0_reg;
  65. uint32_t ix2_reg;
  66. uint32_t ix3_reg;
  67. };
  68. #ifdef IPA_WDS_EASYMESH_FEATURE
  69. #define WLAN_IPA_META_DATA_MASK htonl(0x000000FF)
  70. #else
  71. #define WLAN_IPA_META_DATA_MASK htonl(0x00FF0000)
  72. #endif
  73. #define REO_REMAP_HISTORY_SIZE 32
  74. struct dp_ipa_reo_remap_record dp_ipa_reo_remap_history[REO_REMAP_HISTORY_SIZE];
  75. static qdf_atomic_t dp_ipa_reo_remap_history_index;
  76. static int dp_ipa_reo_remap_record_index_next(qdf_atomic_t *index)
  77. {
  78. int next = qdf_atomic_inc_return(index);
  79. if (next == REO_REMAP_HISTORY_SIZE)
  80. qdf_atomic_sub(REO_REMAP_HISTORY_SIZE, index);
  81. return next % REO_REMAP_HISTORY_SIZE;
  82. }
  83. /**
  84. * dp_ipa_reo_remap_history_add() - Record dp ipa reo remap values
  85. * @ix0_val: reo destination ring IX0 value
  86. * @ix2_val: reo destination ring IX2 value
  87. * @ix3_val: reo destination ring IX3 value
  88. *
  89. * Return: None
  90. */
  91. static void dp_ipa_reo_remap_history_add(uint32_t ix0_val, uint32_t ix2_val,
  92. uint32_t ix3_val)
  93. {
  94. int idx = dp_ipa_reo_remap_record_index_next(
  95. &dp_ipa_reo_remap_history_index);
  96. struct dp_ipa_reo_remap_record *record = &dp_ipa_reo_remap_history[idx];
  97. record->timestamp = qdf_get_log_timestamp();
  98. record->ix0_reg = ix0_val;
  99. record->ix2_reg = ix2_val;
  100. record->ix3_reg = ix3_val;
  101. }
  102. static QDF_STATUS __dp_ipa_handle_buf_smmu_mapping(struct dp_soc *soc,
  103. qdf_nbuf_t nbuf,
  104. uint32_t size,
  105. bool create,
  106. const char *func,
  107. uint32_t line)
  108. {
  109. qdf_mem_info_t mem_map_table = {0};
  110. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  111. qdf_ipa_wdi_hdl_t hdl;
  112. /* Need to handle the case when one soc will
  113. * have multiple pdev(radio's), Currently passing
  114. * pdev_id as 0 assuming 1 soc has only 1 radio.
  115. */
  116. hdl = wlan_ipa_get_hdl(soc->ctrl_psoc, 0);
  117. if (hdl == DP_IPA_HDL_INVALID) {
  118. dp_err("IPA handle is invalid");
  119. return QDF_STATUS_E_INVAL;
  120. }
  121. qdf_update_mem_map_table(soc->osdev, &mem_map_table,
  122. qdf_nbuf_get_frag_paddr(nbuf, 0),
  123. size);
  124. if (create) {
  125. /* Assert if PA is zero */
  126. qdf_assert_always(mem_map_table.pa);
  127. ret = qdf_nbuf_smmu_map_debug(nbuf, hdl, 1, &mem_map_table,
  128. func, line);
  129. } else {
  130. ret = qdf_nbuf_smmu_unmap_debug(nbuf, hdl, 1, &mem_map_table,
  131. func, line);
  132. }
  133. qdf_assert_always(!ret);
  134. /* Return status of mapping/unmapping is stored in
  135. * mem_map_table.result field, assert if the result
  136. * is failure
  137. */
  138. if (create)
  139. qdf_assert_always(!mem_map_table.result);
  140. else
  141. qdf_assert_always(mem_map_table.result >= mem_map_table.size);
  142. return ret;
  143. }
  144. QDF_STATUS dp_ipa_handle_rx_buf_smmu_mapping(struct dp_soc *soc,
  145. qdf_nbuf_t nbuf,
  146. uint32_t size,
  147. bool create, const char *func,
  148. uint32_t line)
  149. {
  150. struct dp_pdev *pdev;
  151. int i;
  152. for (i = 0; i < soc->pdev_count; i++) {
  153. pdev = soc->pdev_list[i];
  154. if (pdev && dp_monitor_is_configured(pdev))
  155. return QDF_STATUS_SUCCESS;
  156. }
  157. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx) ||
  158. !qdf_mem_smmu_s1_enabled(soc->osdev))
  159. return QDF_STATUS_SUCCESS;
  160. /*
  161. * Even if ipa pipes is disabled, but if it's unmap
  162. * operation and nbuf has done ipa smmu map before,
  163. * do ipa smmu unmap as well.
  164. */
  165. if (!qdf_atomic_read(&soc->ipa_pipes_enabled)) {
  166. if (!create && qdf_nbuf_is_rx_ipa_smmu_map(nbuf)) {
  167. DP_STATS_INC(soc, rx.err.ipa_unmap_no_pipe, 1);
  168. } else {
  169. return QDF_STATUS_SUCCESS;
  170. }
  171. }
  172. if (qdf_unlikely(create == qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  173. if (create) {
  174. DP_STATS_INC(soc, rx.err.ipa_smmu_map_dup, 1);
  175. } else {
  176. DP_STATS_INC(soc, rx.err.ipa_smmu_unmap_dup, 1);
  177. }
  178. return QDF_STATUS_E_INVAL;
  179. }
  180. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  181. return __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, size, create,
  182. func, line);
  183. }
  184. static QDF_STATUS __dp_ipa_tx_buf_smmu_mapping(
  185. struct dp_soc *soc,
  186. struct dp_pdev *pdev,
  187. bool create,
  188. const char *func,
  189. uint32_t line)
  190. {
  191. uint32_t index;
  192. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  193. uint32_t tx_buffer_cnt = soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  194. qdf_nbuf_t nbuf;
  195. uint32_t buf_len;
  196. if (!ipa_is_ready()) {
  197. dp_info("IPA is not READY");
  198. return 0;
  199. }
  200. for (index = 0; index < tx_buffer_cnt; index++) {
  201. nbuf = (qdf_nbuf_t)
  202. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[index];
  203. if (!nbuf)
  204. continue;
  205. buf_len = qdf_nbuf_get_data_len(nbuf);
  206. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  207. create, func, line);
  208. }
  209. return ret;
  210. }
  211. #ifndef QCA_OL_DP_SRNG_LOCK_LESS_ACCESS
  212. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  213. bool lock_required)
  214. {
  215. hal_ring_handle_t hal_ring_hdl;
  216. int ring;
  217. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  218. hal_ring_hdl = soc->reo_dest_ring[ring].hal_srng;
  219. hal_srng_lock(hal_ring_hdl);
  220. soc->ipa_reo_ctx_lock_required[ring] = lock_required;
  221. hal_srng_unlock(hal_ring_hdl);
  222. }
  223. }
  224. #else
  225. static void dp_ipa_set_reo_ctx_mapping_lock_required(struct dp_soc *soc,
  226. bool lock_required)
  227. {
  228. }
  229. #endif
  230. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  231. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(struct dp_soc *soc,
  232. struct dp_pdev *pdev,
  233. bool create,
  234. const char *func,
  235. uint32_t line)
  236. {
  237. struct rx_desc_pool *rx_pool;
  238. uint8_t pdev_id;
  239. uint32_t num_desc, page_id, offset, i;
  240. uint16_t num_desc_per_page;
  241. union dp_rx_desc_list_elem_t *rx_desc_elem;
  242. struct dp_rx_desc *rx_desc;
  243. qdf_nbuf_t nbuf;
  244. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  245. if (!qdf_ipa_is_ready())
  246. return ret;
  247. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  248. return ret;
  249. pdev_id = pdev->pdev_id;
  250. rx_pool = &soc->rx_desc_buf[pdev_id];
  251. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  252. qdf_spin_lock_bh(&rx_pool->lock);
  253. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  254. num_desc = rx_pool->pool_size;
  255. num_desc_per_page = rx_pool->desc_pages.num_element_per_page;
  256. for (i = 0; i < num_desc; i++) {
  257. page_id = i / num_desc_per_page;
  258. offset = i % num_desc_per_page;
  259. if (qdf_unlikely(!(rx_pool->desc_pages.cacheable_pages)))
  260. break;
  261. rx_desc_elem = dp_rx_desc_find(page_id, offset, rx_pool);
  262. rx_desc = &rx_desc_elem->rx_desc;
  263. if ((!(rx_desc->in_use)) || rx_desc->unmapped)
  264. continue;
  265. nbuf = rx_desc->nbuf;
  266. if (qdf_unlikely(create ==
  267. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  268. if (create) {
  269. DP_STATS_INC(soc,
  270. rx.err.ipa_smmu_map_dup, 1);
  271. } else {
  272. DP_STATS_INC(soc,
  273. rx.err.ipa_smmu_unmap_dup, 1);
  274. }
  275. continue;
  276. }
  277. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  278. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf,
  279. rx_pool->buf_size,
  280. create, func, line);
  281. }
  282. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  283. qdf_spin_unlock_bh(&rx_pool->lock);
  284. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  285. return ret;
  286. }
  287. #else
  288. static QDF_STATUS dp_ipa_handle_rx_buf_pool_smmu_mapping(
  289. struct dp_soc *soc,
  290. struct dp_pdev *pdev,
  291. bool create,
  292. const char *func,
  293. uint32_t line)
  294. {
  295. struct rx_desc_pool *rx_pool;
  296. uint8_t pdev_id;
  297. qdf_nbuf_t nbuf;
  298. int i;
  299. if (!qdf_ipa_is_ready())
  300. return QDF_STATUS_SUCCESS;
  301. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  302. return QDF_STATUS_SUCCESS;
  303. pdev_id = pdev->pdev_id;
  304. rx_pool = &soc->rx_desc_buf[pdev_id];
  305. dp_ipa_set_reo_ctx_mapping_lock_required(soc, true);
  306. qdf_spin_lock_bh(&rx_pool->lock);
  307. dp_ipa_rx_buf_smmu_mapping_lock(soc);
  308. for (i = 0; i < rx_pool->pool_size; i++) {
  309. if ((!(rx_pool->array[i].rx_desc.in_use)) ||
  310. rx_pool->array[i].rx_desc.unmapped)
  311. continue;
  312. nbuf = rx_pool->array[i].rx_desc.nbuf;
  313. if (qdf_unlikely(create ==
  314. qdf_nbuf_is_rx_ipa_smmu_map(nbuf))) {
  315. if (create) {
  316. DP_STATS_INC(soc,
  317. rx.err.ipa_smmu_map_dup, 1);
  318. } else {
  319. DP_STATS_INC(soc,
  320. rx.err.ipa_smmu_unmap_dup, 1);
  321. }
  322. continue;
  323. }
  324. qdf_nbuf_set_rx_ipa_smmu_map(nbuf, create);
  325. __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, rx_pool->buf_size,
  326. create, func, line);
  327. }
  328. dp_ipa_rx_buf_smmu_mapping_unlock(soc);
  329. qdf_spin_unlock_bh(&rx_pool->lock);
  330. dp_ipa_set_reo_ctx_mapping_lock_required(soc, false);
  331. return QDF_STATUS_SUCCESS;
  332. }
  333. #endif /* RX_DESC_MULTI_PAGE_ALLOC */
  334. static QDF_STATUS dp_ipa_get_shared_mem_info(qdf_device_t osdev,
  335. qdf_shared_mem_t *shared_mem,
  336. void *cpu_addr,
  337. qdf_dma_addr_t dma_addr,
  338. uint32_t size)
  339. {
  340. qdf_dma_addr_t paddr;
  341. int ret;
  342. shared_mem->vaddr = cpu_addr;
  343. qdf_mem_set_dma_size(osdev, &shared_mem->mem_info, size);
  344. *qdf_mem_get_dma_addr_ptr(osdev, &shared_mem->mem_info) = dma_addr;
  345. paddr = qdf_mem_paddr_from_dmaaddr(osdev, dma_addr);
  346. qdf_mem_set_dma_pa(osdev, &shared_mem->mem_info, paddr);
  347. ret = qdf_mem_dma_get_sgtable(osdev->dev, &shared_mem->sgtable,
  348. shared_mem->vaddr, dma_addr, size);
  349. if (ret) {
  350. dp_err("Unable to get DMA sgtable");
  351. return QDF_STATUS_E_NOMEM;
  352. }
  353. qdf_dma_get_sgtable_dma_addr(&shared_mem->sgtable);
  354. return QDF_STATUS_SUCCESS;
  355. }
  356. /**
  357. * dp_ipa_get_tx_bank_id() - API to get TCL bank id
  358. * @soc: dp_soc handle
  359. * @bank_id: out parameter for bank id
  360. *
  361. * Return: QDF_STATUS
  362. */
  363. static QDF_STATUS dp_ipa_get_tx_bank_id(struct dp_soc *soc, uint8_t *bank_id)
  364. {
  365. if (soc->arch_ops.ipa_get_bank_id) {
  366. *bank_id = soc->arch_ops.ipa_get_bank_id(soc);
  367. if (*bank_id < 0) {
  368. return QDF_STATUS_E_INVAL;
  369. } else {
  370. dp_info("bank_id %u", *bank_id);
  371. return QDF_STATUS_SUCCESS;
  372. }
  373. } else {
  374. return QDF_STATUS_E_NOSUPPORT;
  375. }
  376. }
  377. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  378. defined(CONFIG_IPA_WDI_UNIFIED_API)
  379. static void dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  380. qdf_ipa_wdi_pipe_setup_info_t *tx)
  381. {
  382. uint8_t bank_id;
  383. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  384. QDF_IPA_WDI_SETUP_INFO_RX_BANK_ID(tx, bank_id);
  385. }
  386. static void
  387. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  388. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  389. {
  390. uint8_t bank_id;
  391. if (QDF_IS_STATUS_SUCCESS(dp_ipa_get_tx_bank_id(soc, &bank_id)))
  392. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_BANK_ID(tx_smmu, bank_id);
  393. }
  394. #else
  395. static inline void
  396. dp_ipa_setup_tx_params_bank_id(struct dp_soc *soc,
  397. qdf_ipa_wdi_pipe_setup_info_t *tx)
  398. {
  399. }
  400. static inline void
  401. dp_ipa_setup_tx_smmu_params_bank_id(struct dp_soc *soc,
  402. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  403. {
  404. }
  405. #endif
  406. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  407. static void
  408. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  409. qdf_ipa_wdi_pipe_setup_info_t *tx)
  410. {
  411. uint8_t pmac_id = 0;
  412. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  413. if (soc->pdev_count > 1)
  414. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  415. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  416. }
  417. static void
  418. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  419. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  420. {
  421. uint8_t pmac_id = 0;
  422. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  423. if (soc->pdev_count > 1)
  424. pmac_id = soc->pdev_list[soc->pdev_count - 1]->lmac_id;
  425. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  426. }
  427. static void
  428. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  429. qdf_ipa_wdi_pipe_setup_info_t *tx)
  430. {
  431. uint8_t pmac_id;
  432. pmac_id = soc->pdev_list[0]->lmac_id;
  433. QDF_IPA_WDI_SETUP_INFO_RX_PMAC_ID(tx, pmac_id);
  434. }
  435. static void
  436. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  437. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  438. {
  439. uint8_t pmac_id;
  440. pmac_id = soc->pdev_list[0]->lmac_id;
  441. QDF_IPA_WDI_SETUP_INFO_SMMU_RX_PMAC_ID(tx_smmu, pmac_id);
  442. }
  443. #else
  444. static inline void
  445. dp_ipa_setup_tx_alt_params_pmac_id(struct dp_soc *soc,
  446. qdf_ipa_wdi_pipe_setup_info_t *tx)
  447. {
  448. }
  449. static inline void
  450. dp_ipa_setup_tx_alt_smmu_params_pmac_id(struct dp_soc *soc,
  451. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  452. {
  453. }
  454. static inline void
  455. dp_ipa_setup_tx_params_pmac_id(struct dp_soc *soc,
  456. qdf_ipa_wdi_pipe_setup_info_t *tx)
  457. {
  458. }
  459. static inline void
  460. dp_ipa_setup_tx_smmu_params_pmac_id(struct dp_soc *soc,
  461. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  462. {
  463. }
  464. #endif
  465. #ifdef IPA_WDI3_TX_TWO_PIPES
  466. static void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  467. {
  468. struct dp_ipa_resources *ipa_res;
  469. qdf_nbuf_t nbuf;
  470. int idx;
  471. for (idx = 0; idx < soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt; idx++) {
  472. nbuf = (qdf_nbuf_t)
  473. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx];
  474. if (!nbuf)
  475. continue;
  476. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  477. qdf_mem_dp_tx_skb_cnt_dec();
  478. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  479. qdf_nbuf_free(nbuf);
  480. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[idx] =
  481. (void *)NULL;
  482. }
  483. qdf_mem_free(soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  484. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  485. ipa_res = &pdev->ipa_resource;
  486. if (!ipa_res->is_db_ddr_mapped && ipa_res->tx_alt_comp_doorbell_vaddr)
  487. iounmap(ipa_res->tx_alt_comp_doorbell_vaddr);
  488. qdf_mem_free_sgtable(&ipa_res->tx_alt_ring.sgtable);
  489. qdf_mem_free_sgtable(&ipa_res->tx_alt_comp_ring.sgtable);
  490. }
  491. static int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  492. {
  493. uint32_t tx_buffer_count;
  494. uint32_t ring_base_align = 8;
  495. qdf_dma_addr_t buffer_paddr;
  496. struct hal_srng *wbm_srng = (struct hal_srng *)
  497. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  498. struct hal_srng_params srng_params;
  499. uint32_t wbm_bm_id;
  500. void *ring_entry;
  501. int num_entries;
  502. qdf_nbuf_t nbuf;
  503. int retval = QDF_STATUS_SUCCESS;
  504. int max_alloc_count = 0;
  505. /*
  506. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  507. * unsigned int uc_tx_buf_sz =
  508. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  509. */
  510. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  511. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  512. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  513. IPA_TX_ALT_RING_IDX);
  514. hal_get_srng_params(soc->hal_soc,
  515. hal_srng_to_hal_ring_handle(wbm_srng),
  516. &srng_params);
  517. num_entries = srng_params.num_entries;
  518. max_alloc_count =
  519. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  520. if (max_alloc_count <= 0) {
  521. dp_err("incorrect value for buffer count %u", max_alloc_count);
  522. return -EINVAL;
  523. }
  524. dp_info("requested %d buffers to be posted to wbm ring",
  525. max_alloc_count);
  526. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned =
  527. qdf_mem_malloc(num_entries *
  528. sizeof(*soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned));
  529. if (!soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned) {
  530. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  531. return -ENOMEM;
  532. }
  533. hal_srng_access_start_unlocked(soc->hal_soc,
  534. hal_srng_to_hal_ring_handle(wbm_srng));
  535. /*
  536. * Allocate Tx buffers as many as possible.
  537. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  538. * Populate Tx buffers into WBM2IPA ring
  539. * This initial buffer population will simulate H/W as source ring,
  540. * and update HP
  541. */
  542. for (tx_buffer_count = 0;
  543. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  544. nbuf = qdf_nbuf_alloc(soc->osdev, alloc_size, 0, 256, FALSE);
  545. if (!nbuf)
  546. break;
  547. ring_entry = hal_srng_dst_get_next_hp(
  548. soc->hal_soc,
  549. hal_srng_to_hal_ring_handle(wbm_srng));
  550. if (!ring_entry) {
  551. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  552. "%s: Failed to get WBM ring entry",
  553. __func__);
  554. qdf_nbuf_free(nbuf);
  555. break;
  556. }
  557. qdf_nbuf_map_single(soc->osdev, nbuf,
  558. QDF_DMA_BIDIRECTIONAL);
  559. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  560. qdf_mem_dp_tx_skb_cnt_inc();
  561. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  562. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  563. buffer_paddr, 0, wbm_bm_id);
  564. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned[
  565. tx_buffer_count] = (void *)nbuf;
  566. }
  567. hal_srng_access_end_unlocked(soc->hal_soc,
  568. hal_srng_to_hal_ring_handle(wbm_srng));
  569. soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt = tx_buffer_count;
  570. if (tx_buffer_count) {
  571. dp_info("IPA TX buffer pool2: %d allocated", tx_buffer_count);
  572. } else {
  573. dp_err("Failed to allocate IPA TX buffer pool2");
  574. qdf_mem_free(
  575. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned);
  576. soc->ipa_uc_tx_rsc_alt.tx_buf_pool_vaddr_unaligned = NULL;
  577. retval = -ENOMEM;
  578. }
  579. return retval;
  580. }
  581. static QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  582. {
  583. struct dp_soc *soc = pdev->soc;
  584. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  585. ipa_res->tx_alt_ring_num_alloc_buffer =
  586. (uint32_t)soc->ipa_uc_tx_rsc_alt.alloc_tx_buf_cnt;
  587. dp_ipa_get_shared_mem_info(
  588. soc->osdev, &ipa_res->tx_alt_ring,
  589. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  590. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  591. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  592. dp_ipa_get_shared_mem_info(
  593. soc->osdev, &ipa_res->tx_alt_comp_ring,
  594. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  595. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  596. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  597. if (!qdf_mem_get_dma_addr(soc->osdev,
  598. &ipa_res->tx_alt_comp_ring.mem_info))
  599. return QDF_STATUS_E_FAILURE;
  600. return QDF_STATUS_SUCCESS;
  601. }
  602. static void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  603. {
  604. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  605. struct hal_srng *hal_srng;
  606. struct hal_srng_params srng_params;
  607. unsigned long addr_offset, dev_base_paddr;
  608. /* IPA TCL_DATA Alternative Ring - HAL_SRNG_SW2TCL2 */
  609. hal_srng = (struct hal_srng *)
  610. soc->tcl_data_ring[IPA_TX_ALT_RING_IDX].hal_srng;
  611. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  612. hal_srng_to_hal_ring_handle(hal_srng),
  613. &srng_params);
  614. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr =
  615. srng_params.ring_base_paddr;
  616. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr =
  617. srng_params.ring_base_vaddr;
  618. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size =
  619. (srng_params.num_entries * srng_params.entry_size) << 2;
  620. /*
  621. * For the register backed memory addresses, use the scn->mem_pa to
  622. * calculate the physical address of the shadow registers
  623. */
  624. dev_base_paddr =
  625. (unsigned long)
  626. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  627. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  628. (unsigned long)(hal_soc->dev_base_addr);
  629. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr =
  630. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  631. dp_info("IPA TCL_DATA Alt Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  632. (unsigned int)addr_offset,
  633. (unsigned int)dev_base_paddr,
  634. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr),
  635. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_paddr,
  636. (void *)soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_base_vaddr,
  637. srng_params.num_entries,
  638. soc->ipa_uc_tx_rsc_alt.ipa_tcl_ring_size);
  639. /* IPA TX Alternative COMP Ring - HAL_SRNG_WBM2SW4_RELEASE */
  640. hal_srng = (struct hal_srng *)
  641. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  642. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  643. hal_srng_to_hal_ring_handle(hal_srng),
  644. &srng_params);
  645. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr =
  646. srng_params.ring_base_paddr;
  647. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr =
  648. srng_params.ring_base_vaddr;
  649. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size =
  650. (srng_params.num_entries * srng_params.entry_size) << 2;
  651. soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr =
  652. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  653. hal_srng_to_hal_ring_handle(hal_srng));
  654. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  655. (unsigned long)(hal_soc->dev_base_addr);
  656. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr =
  657. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  658. dp_info("IPA TX Alt COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  659. (unsigned int)addr_offset,
  660. (unsigned int)dev_base_paddr,
  661. (unsigned int)(soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr),
  662. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_paddr,
  663. (void *)soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_base_vaddr,
  664. srng_params.num_entries,
  665. soc->ipa_uc_tx_rsc_alt.ipa_wbm_ring_size);
  666. }
  667. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  668. {
  669. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  670. uint32_t rx_ready_doorbell_dmaaddr;
  671. uint32_t tx_comp_doorbell_dmaaddr;
  672. struct dp_soc *soc = pdev->soc;
  673. int ret = 0;
  674. if (ipa_res->is_db_ddr_mapped)
  675. ipa_res->tx_comp_doorbell_vaddr =
  676. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  677. else
  678. ipa_res->tx_comp_doorbell_vaddr =
  679. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  680. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  681. ret = pld_smmu_map(soc->osdev->dev,
  682. ipa_res->tx_comp_doorbell_paddr,
  683. &tx_comp_doorbell_dmaaddr,
  684. sizeof(uint32_t));
  685. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  686. qdf_assert_always(!ret);
  687. ret = pld_smmu_map(soc->osdev->dev,
  688. ipa_res->rx_ready_doorbell_paddr,
  689. &rx_ready_doorbell_dmaaddr,
  690. sizeof(uint32_t));
  691. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  692. qdf_assert_always(!ret);
  693. }
  694. /* Setup for alternative TX pipe */
  695. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  696. return;
  697. if (ipa_res->is_db_ddr_mapped)
  698. ipa_res->tx_alt_comp_doorbell_vaddr =
  699. phys_to_virt(ipa_res->tx_alt_comp_doorbell_paddr);
  700. else
  701. ipa_res->tx_alt_comp_doorbell_vaddr =
  702. ioremap(ipa_res->tx_alt_comp_doorbell_paddr, 4);
  703. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  704. ret = pld_smmu_map(soc->osdev->dev,
  705. ipa_res->tx_alt_comp_doorbell_paddr,
  706. &tx_comp_doorbell_dmaaddr,
  707. sizeof(uint32_t));
  708. ipa_res->tx_alt_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  709. qdf_assert_always(!ret);
  710. }
  711. }
  712. static void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  713. {
  714. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  715. struct dp_soc *soc = pdev->soc;
  716. int ret = 0;
  717. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  718. return;
  719. /* Unmap must be in reverse order of map */
  720. if (ipa_res->tx_alt_comp_doorbell_paddr) {
  721. ret = pld_smmu_unmap(soc->osdev->dev,
  722. ipa_res->tx_alt_comp_doorbell_paddr,
  723. sizeof(uint32_t));
  724. qdf_assert_always(!ret);
  725. }
  726. ret = pld_smmu_unmap(soc->osdev->dev,
  727. ipa_res->rx_ready_doorbell_paddr,
  728. sizeof(uint32_t));
  729. qdf_assert_always(!ret);
  730. ret = pld_smmu_unmap(soc->osdev->dev,
  731. ipa_res->tx_comp_doorbell_paddr,
  732. sizeof(uint32_t));
  733. qdf_assert_always(!ret);
  734. }
  735. static QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  736. struct dp_pdev *pdev,
  737. bool create, const char *func,
  738. uint32_t line)
  739. {
  740. QDF_STATUS ret = QDF_STATUS_SUCCESS;
  741. struct ipa_dp_tx_rsc *rsc;
  742. uint32_t tx_buffer_cnt;
  743. uint32_t buf_len;
  744. qdf_nbuf_t nbuf;
  745. uint32_t index;
  746. if (!ipa_is_ready()) {
  747. dp_info("IPA is not READY");
  748. return QDF_STATUS_SUCCESS;
  749. }
  750. rsc = &soc->ipa_uc_tx_rsc_alt;
  751. tx_buffer_cnt = rsc->alloc_tx_buf_cnt;
  752. for (index = 0; index < tx_buffer_cnt; index++) {
  753. nbuf = (qdf_nbuf_t)rsc->tx_buf_pool_vaddr_unaligned[index];
  754. if (!nbuf)
  755. continue;
  756. buf_len = qdf_nbuf_get_data_len(nbuf);
  757. ret = __dp_ipa_handle_buf_smmu_mapping(soc, nbuf, buf_len,
  758. create, func, line);
  759. }
  760. return ret;
  761. }
  762. static void dp_ipa_wdi_tx_alt_pipe_params(struct dp_soc *soc,
  763. struct dp_ipa_resources *ipa_res,
  764. qdf_ipa_wdi_pipe_setup_info_t *tx)
  765. {
  766. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS1;
  767. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  768. qdf_mem_get_dma_addr(soc->osdev,
  769. &ipa_res->tx_alt_comp_ring.mem_info);
  770. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  771. qdf_mem_get_dma_size(soc->osdev,
  772. &ipa_res->tx_alt_comp_ring.mem_info);
  773. /* WBM Tail Pointer Address */
  774. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  775. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  776. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  777. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  778. qdf_mem_get_dma_addr(soc->osdev,
  779. &ipa_res->tx_alt_ring.mem_info);
  780. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  781. qdf_mem_get_dma_size(soc->osdev,
  782. &ipa_res->tx_alt_ring.mem_info);
  783. /* TCL Head Pointer Address */
  784. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  785. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  786. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  787. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  788. ipa_res->tx_alt_ring_num_alloc_buffer;
  789. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  790. dp_ipa_setup_tx_params_bank_id(soc, tx);
  791. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  792. dp_ipa_setup_tx_alt_params_pmac_id(soc, tx);
  793. }
  794. static void
  795. dp_ipa_wdi_tx_alt_pipe_smmu_params(struct dp_soc *soc,
  796. struct dp_ipa_resources *ipa_res,
  797. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu)
  798. {
  799. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) = IPA_CLIENT_WLAN2_CONS1;
  800. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  801. &ipa_res->tx_alt_comp_ring.sgtable,
  802. sizeof(sgtable_t));
  803. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  804. qdf_mem_get_dma_size(soc->osdev,
  805. &ipa_res->tx_alt_comp_ring.mem_info);
  806. /* WBM Tail Pointer Address */
  807. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  808. soc->ipa_uc_tx_rsc_alt.ipa_wbm_tp_paddr;
  809. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(tx_smmu) = true;
  810. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  811. &ipa_res->tx_alt_ring.sgtable,
  812. sizeof(sgtable_t));
  813. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  814. qdf_mem_get_dma_size(soc->osdev,
  815. &ipa_res->tx_alt_ring.mem_info);
  816. /* TCL Head Pointer Address */
  817. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  818. soc->ipa_uc_tx_rsc_alt.ipa_tcl_hp_paddr;
  819. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(tx_smmu) = true;
  820. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  821. ipa_res->tx_alt_ring_num_alloc_buffer;
  822. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  823. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  824. /* Set Pmac ID, extract pmac_id from second radio for TX_ALT ring */
  825. dp_ipa_setup_tx_alt_smmu_params_pmac_id(soc, tx_smmu);
  826. }
  827. static void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc,
  828. struct dp_ipa_resources *res,
  829. qdf_ipa_wdi_conn_in_params_t *in)
  830. {
  831. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu = NULL;
  832. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  833. qdf_ipa_ep_cfg_t *tx_cfg;
  834. QDF_IPA_WDI_CONN_IN_PARAMS_IS_TX1_USED(in) = true;
  835. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  836. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE_SMMU(in);
  837. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  838. dp_ipa_wdi_tx_alt_pipe_smmu_params(soc, res, tx_smmu);
  839. } else {
  840. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_ALT_PIPE(in);
  841. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx);
  842. dp_ipa_wdi_tx_alt_pipe_params(soc, res, tx);
  843. }
  844. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  845. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  846. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  847. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  848. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  849. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  850. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  851. }
  852. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  853. qdf_ipa_wdi_conn_out_params_t *out)
  854. {
  855. res->tx_comp_doorbell_paddr =
  856. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  857. res->rx_ready_doorbell_paddr =
  858. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  859. res->tx_alt_comp_doorbell_paddr =
  860. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_ALT_DB_PA(out);
  861. }
  862. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  863. uint8_t session_id)
  864. {
  865. bool is_2g_iface = session_id & IPA_SESSION_ID_SHIFT;
  866. session_id = session_id >> IPA_SESSION_ID_SHIFT;
  867. dp_debug("session_id %u is_2g_iface %d", session_id, is_2g_iface);
  868. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  869. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_TX1_USED(in) = is_2g_iface;
  870. }
  871. static void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  872. struct dp_ipa_resources *res)
  873. {
  874. struct hal_srng *wbm_srng;
  875. /* Init first TX comp ring */
  876. wbm_srng = (struct hal_srng *)
  877. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  878. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  879. res->tx_comp_doorbell_vaddr);
  880. /* Init the alternate TX comp ring */
  881. if (!res->tx_alt_comp_doorbell_paddr)
  882. return;
  883. wbm_srng = (struct hal_srng *)
  884. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  885. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  886. res->tx_alt_comp_doorbell_vaddr);
  887. }
  888. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  889. struct dp_ipa_resources *ipa_res)
  890. {
  891. struct hal_srng *wbm_srng;
  892. wbm_srng = (struct hal_srng *)
  893. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  894. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  895. ipa_res->tx_comp_doorbell_paddr);
  896. dp_info("paddr %pK vaddr %pK",
  897. (void *)ipa_res->tx_comp_doorbell_paddr,
  898. (void *)ipa_res->tx_comp_doorbell_vaddr);
  899. /* Setup for alternative TX comp ring */
  900. if (!ipa_res->tx_alt_comp_doorbell_paddr)
  901. return;
  902. wbm_srng = (struct hal_srng *)
  903. soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  904. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  905. ipa_res->tx_alt_comp_doorbell_paddr);
  906. dp_info("paddr %pK vaddr %pK",
  907. (void *)ipa_res->tx_alt_comp_doorbell_paddr,
  908. (void *)ipa_res->tx_alt_comp_doorbell_vaddr);
  909. }
  910. #ifdef IPA_SET_RESET_TX_DB_PA
  911. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  912. struct dp_ipa_resources *ipa_res)
  913. {
  914. hal_ring_handle_t wbm_srng;
  915. qdf_dma_addr_t hp_addr;
  916. wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  917. if (!wbm_srng)
  918. return QDF_STATUS_E_FAILURE;
  919. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  920. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  921. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  922. /* Reset alternative TX comp ring */
  923. wbm_srng = soc->tx_comp_ring[IPA_TX_ALT_COMP_RING_IDX].hal_srng;
  924. if (!wbm_srng)
  925. return QDF_STATUS_E_FAILURE;
  926. hp_addr = soc->ipa_uc_tx_rsc_alt.ipa_wbm_hp_shadow_paddr;
  927. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  928. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  929. return QDF_STATUS_SUCCESS;
  930. }
  931. #endif /* IPA_SET_RESET_TX_DB_PA */
  932. #else /* !IPA_WDI3_TX_TWO_PIPES */
  933. static inline
  934. void dp_ipa_tx_alt_pool_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  935. {
  936. }
  937. static inline void dp_ipa_tx_alt_ring_resource_setup(struct dp_soc *soc)
  938. {
  939. }
  940. static inline int dp_ipa_tx_alt_pool_attach(struct dp_soc *soc)
  941. {
  942. return 0;
  943. }
  944. static inline QDF_STATUS dp_ipa_tx_alt_ring_get_resource(struct dp_pdev *pdev)
  945. {
  946. return QDF_STATUS_SUCCESS;
  947. }
  948. static void dp_ipa_map_ring_doorbell_paddr(struct dp_pdev *pdev)
  949. {
  950. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  951. uint32_t rx_ready_doorbell_dmaaddr;
  952. uint32_t tx_comp_doorbell_dmaaddr;
  953. struct dp_soc *soc = pdev->soc;
  954. int ret = 0;
  955. if (ipa_res->is_db_ddr_mapped)
  956. ipa_res->tx_comp_doorbell_vaddr =
  957. phys_to_virt(ipa_res->tx_comp_doorbell_paddr);
  958. else
  959. ipa_res->tx_comp_doorbell_vaddr =
  960. ioremap(ipa_res->tx_comp_doorbell_paddr, 4);
  961. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  962. ret = pld_smmu_map(soc->osdev->dev,
  963. ipa_res->tx_comp_doorbell_paddr,
  964. &tx_comp_doorbell_dmaaddr,
  965. sizeof(uint32_t));
  966. ipa_res->tx_comp_doorbell_paddr = tx_comp_doorbell_dmaaddr;
  967. qdf_assert_always(!ret);
  968. ret = pld_smmu_map(soc->osdev->dev,
  969. ipa_res->rx_ready_doorbell_paddr,
  970. &rx_ready_doorbell_dmaaddr,
  971. sizeof(uint32_t));
  972. ipa_res->rx_ready_doorbell_paddr = rx_ready_doorbell_dmaaddr;
  973. qdf_assert_always(!ret);
  974. }
  975. }
  976. static inline void dp_ipa_unmap_ring_doorbell_paddr(struct dp_pdev *pdev)
  977. {
  978. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  979. struct dp_soc *soc = pdev->soc;
  980. int ret = 0;
  981. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  982. return;
  983. ret = pld_smmu_unmap(soc->osdev->dev,
  984. ipa_res->rx_ready_doorbell_paddr,
  985. sizeof(uint32_t));
  986. qdf_assert_always(!ret);
  987. ret = pld_smmu_unmap(soc->osdev->dev,
  988. ipa_res->tx_comp_doorbell_paddr,
  989. sizeof(uint32_t));
  990. qdf_assert_always(!ret);
  991. }
  992. static inline QDF_STATUS dp_ipa_tx_alt_buf_smmu_mapping(struct dp_soc *soc,
  993. struct dp_pdev *pdev,
  994. bool create,
  995. const char *func,
  996. uint32_t line)
  997. {
  998. return QDF_STATUS_SUCCESS;
  999. }
  1000. static inline
  1001. void dp_ipa_setup_tx_alt_pipe(struct dp_soc *soc, struct dp_ipa_resources *res,
  1002. qdf_ipa_wdi_conn_in_params_t *in)
  1003. {
  1004. }
  1005. static void dp_ipa_set_pipe_db(struct dp_ipa_resources *res,
  1006. qdf_ipa_wdi_conn_out_params_t *out)
  1007. {
  1008. res->tx_comp_doorbell_paddr =
  1009. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(out);
  1010. res->rx_ready_doorbell_paddr =
  1011. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(out);
  1012. }
  1013. #ifdef IPA_WDS_EASYMESH_FEATURE
  1014. /**
  1015. * dp_ipa_setup_iface_session_id() - Pass vdev id to IPA
  1016. * @in: ipa in params
  1017. * @session_id: vdev id
  1018. *
  1019. * Pass Vdev id to IPA, IPA metadata order is changed and vdev id
  1020. * is stored at higher nibble so, no shift is required.
  1021. *
  1022. * Return: none
  1023. */
  1024. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1025. uint8_t session_id)
  1026. {
  1027. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id);
  1028. }
  1029. #else
  1030. static void dp_ipa_setup_iface_session_id(qdf_ipa_wdi_reg_intf_in_params_t *in,
  1031. uint8_t session_id)
  1032. {
  1033. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(in) = htonl(session_id << 16);
  1034. }
  1035. #endif
  1036. static inline void dp_ipa_tx_comp_ring_init_hp(struct dp_soc *soc,
  1037. struct dp_ipa_resources *res)
  1038. {
  1039. struct hal_srng *wbm_srng = (struct hal_srng *)
  1040. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1041. hal_srng_dst_init_hp(soc->hal_soc, wbm_srng,
  1042. res->tx_comp_doorbell_vaddr);
  1043. }
  1044. static void dp_ipa_set_tx_doorbell_paddr(struct dp_soc *soc,
  1045. struct dp_ipa_resources *ipa_res)
  1046. {
  1047. struct hal_srng *wbm_srng = (struct hal_srng *)
  1048. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1049. hal_srng_dst_set_hp_paddr_confirm(wbm_srng,
  1050. ipa_res->tx_comp_doorbell_paddr);
  1051. dp_info("paddr %pK vaddr %pK",
  1052. (void *)ipa_res->tx_comp_doorbell_paddr,
  1053. (void *)ipa_res->tx_comp_doorbell_vaddr);
  1054. }
  1055. #ifdef IPA_SET_RESET_TX_DB_PA
  1056. static QDF_STATUS dp_ipa_reset_tx_doorbell_pa(struct dp_soc *soc,
  1057. struct dp_ipa_resources *ipa_res)
  1058. {
  1059. hal_ring_handle_t wbm_srng =
  1060. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1061. qdf_dma_addr_t hp_addr;
  1062. if (!wbm_srng)
  1063. return QDF_STATUS_E_FAILURE;
  1064. hp_addr = soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr;
  1065. hal_srng_dst_set_hp_paddr_confirm((struct hal_srng *)wbm_srng, hp_addr);
  1066. dp_info("Reset WBM HP addr paddr: %pK", (void *)hp_addr);
  1067. return QDF_STATUS_SUCCESS;
  1068. }
  1069. #endif /* IPA_SET_RESET_TX_DB_PA */
  1070. #endif /* IPA_WDI3_TX_TWO_PIPES */
  1071. /**
  1072. * dp_tx_ipa_uc_detach() - Free autonomy TX resources
  1073. * @soc: data path instance
  1074. * @pdev: core txrx pdev context
  1075. *
  1076. * Free allocated TX buffers with WBM SRNG
  1077. *
  1078. * Return: none
  1079. */
  1080. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1081. {
  1082. int idx;
  1083. qdf_nbuf_t nbuf;
  1084. struct dp_ipa_resources *ipa_res;
  1085. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  1086. nbuf = (qdf_nbuf_t)
  1087. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx];
  1088. if (!nbuf)
  1089. continue;
  1090. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_BIDIRECTIONAL);
  1091. qdf_mem_dp_tx_skb_cnt_dec();
  1092. qdf_mem_dp_tx_skb_dec(qdf_nbuf_get_end_offset(nbuf));
  1093. qdf_nbuf_free(nbuf);
  1094. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[idx] =
  1095. (void *)NULL;
  1096. }
  1097. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1098. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1099. ipa_res = &pdev->ipa_resource;
  1100. qdf_mem_free_sgtable(&ipa_res->tx_ring.sgtable);
  1101. qdf_mem_free_sgtable(&ipa_res->tx_comp_ring.sgtable);
  1102. }
  1103. /**
  1104. * dp_rx_ipa_uc_detach() - free autonomy RX resources
  1105. * @soc: data path instance
  1106. * @pdev: core txrx pdev context
  1107. *
  1108. * This function will detach DP RX into main device context
  1109. * will free DP Rx resources.
  1110. *
  1111. * Return: none
  1112. */
  1113. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1114. {
  1115. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1116. qdf_mem_free_sgtable(&ipa_res->rx_rdy_ring.sgtable);
  1117. qdf_mem_free_sgtable(&ipa_res->rx_refill_ring.sgtable);
  1118. }
  1119. /**
  1120. * dp_rx_alt_ipa_uc_detach() - free autonomy RX resources
  1121. * @soc: data path instance
  1122. * @pdev: core txrx pdev context
  1123. *
  1124. * This function will detach DP RX into main device context
  1125. * will free DP Rx resources.
  1126. *
  1127. * Return: none
  1128. */
  1129. #ifdef IPA_WDI3_VLAN_SUPPORT
  1130. static void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1131. {
  1132. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1133. if (!wlan_ipa_is_vlan_enabled())
  1134. return;
  1135. qdf_mem_free_sgtable(&ipa_res->rx_alt_rdy_ring.sgtable);
  1136. qdf_mem_free_sgtable(&ipa_res->rx_alt_refill_ring.sgtable);
  1137. }
  1138. #else
  1139. static inline
  1140. void dp_rx_alt_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1141. { }
  1142. #endif
  1143. /**
  1144. * dp_ipa_opt_wifi_dp_cleanup() - Cleanup ipa opt wifi dp filter setup
  1145. * @soc: data path instance
  1146. * @pdev: core txrx pdev context
  1147. *
  1148. * This function will cleanup filter setup for optional wifi dp.
  1149. *
  1150. * Return: none
  1151. */
  1152. #ifdef IPA_OPT_WIFI_DP
  1153. static void dp_ipa_opt_wifi_dp_cleanup(struct dp_soc *soc, struct dp_pdev *pdev)
  1154. {
  1155. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1156. struct hif_softc *hif = (struct hif_softc *)(hal_soc->hif_handle);
  1157. int count = qdf_atomic_read(&hif->opt_wifi_dp_rtpm_cnt);
  1158. int i;
  1159. for (i = count; i > 0; i--) {
  1160. dp_info("opt_dp: cleanup call pcie link down");
  1161. dp_ipa_pcie_link_down((struct cdp_soc_t *)soc);
  1162. }
  1163. }
  1164. #else
  1165. static inline
  1166. void dp_ipa_opt_wifi_dp_cleanup(struct dp_soc *soc, struct dp_pdev *pdev)
  1167. {
  1168. }
  1169. #endif
  1170. int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  1171. {
  1172. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1173. return QDF_STATUS_SUCCESS;
  1174. /* TX resource detach */
  1175. dp_tx_ipa_uc_detach(soc, pdev);
  1176. /* Cleanup 2nd TX pipe resources */
  1177. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1178. /* RX resource detach */
  1179. dp_rx_ipa_uc_detach(soc, pdev);
  1180. /* Cleanup 2nd RX pipe resources */
  1181. dp_rx_alt_ipa_uc_detach(soc, pdev);
  1182. dp_ipa_opt_wifi_dp_cleanup(soc, pdev);
  1183. return QDF_STATUS_SUCCESS; /* success */
  1184. }
  1185. /**
  1186. * dp_tx_ipa_uc_attach() - Allocate autonomy TX resources
  1187. * @soc: data path instance
  1188. * @pdev: Physical device handle
  1189. *
  1190. * Allocate TX buffer from non-cacheable memory
  1191. * Attach allocated TX buffers with WBM SRNG
  1192. *
  1193. * Return: int
  1194. */
  1195. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1196. {
  1197. uint32_t tx_buffer_count;
  1198. uint32_t ring_base_align = 8;
  1199. qdf_dma_addr_t buffer_paddr;
  1200. struct hal_srng *wbm_srng = (struct hal_srng *)
  1201. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1202. struct hal_srng_params srng_params;
  1203. void *ring_entry;
  1204. int num_entries;
  1205. qdf_nbuf_t nbuf;
  1206. int retval = QDF_STATUS_SUCCESS;
  1207. int max_alloc_count = 0;
  1208. uint32_t wbm_bm_id;
  1209. /*
  1210. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  1211. * unsigned int uc_tx_buf_sz =
  1212. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  1213. */
  1214. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  1215. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  1216. wbm_bm_id = wlan_cfg_get_rbm_id_for_index(soc->wlan_cfg_ctx,
  1217. IPA_TCL_DATA_RING_IDX);
  1218. hal_get_srng_params(soc->hal_soc, hal_srng_to_hal_ring_handle(wbm_srng),
  1219. &srng_params);
  1220. num_entries = srng_params.num_entries;
  1221. max_alloc_count =
  1222. num_entries - DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES;
  1223. if (max_alloc_count <= 0) {
  1224. dp_err("incorrect value for buffer count %u", max_alloc_count);
  1225. return -EINVAL;
  1226. }
  1227. dp_info("requested %d buffers to be posted to wbm ring",
  1228. max_alloc_count);
  1229. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned =
  1230. qdf_mem_malloc(num_entries *
  1231. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned));
  1232. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned) {
  1233. dp_err("IPA WBM Ring Tx buf pool vaddr alloc fail");
  1234. return -ENOMEM;
  1235. }
  1236. hal_srng_access_start_unlocked(soc->hal_soc,
  1237. hal_srng_to_hal_ring_handle(wbm_srng));
  1238. /*
  1239. * Allocate Tx buffers as many as possible.
  1240. * Leave DP_IPA_WAR_WBM2SW_REL_RING_NO_BUF_ENTRIES empty
  1241. * Populate Tx buffers into WBM2IPA ring
  1242. * This initial buffer population will simulate H/W as source ring,
  1243. * and update HP
  1244. */
  1245. for (tx_buffer_count = 0;
  1246. tx_buffer_count < max_alloc_count - 1; tx_buffer_count++) {
  1247. nbuf = qdf_nbuf_alloc(soc->osdev, alloc_size, 0, 256, FALSE);
  1248. if (!nbuf)
  1249. break;
  1250. ring_entry = hal_srng_dst_get_next_hp(soc->hal_soc,
  1251. hal_srng_to_hal_ring_handle(wbm_srng));
  1252. if (!ring_entry) {
  1253. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1254. "%s: Failed to get WBM ring entry",
  1255. __func__);
  1256. qdf_nbuf_free(nbuf);
  1257. break;
  1258. }
  1259. qdf_nbuf_map_single(soc->osdev, nbuf,
  1260. QDF_DMA_BIDIRECTIONAL);
  1261. buffer_paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1262. qdf_mem_dp_tx_skb_cnt_inc();
  1263. qdf_mem_dp_tx_skb_inc(qdf_nbuf_get_end_offset(nbuf));
  1264. /*
  1265. * TODO - KIWI code can directly call the be handler
  1266. * instead of hal soc ops.
  1267. */
  1268. hal_rxdma_buff_addr_info_set(soc->hal_soc, ring_entry,
  1269. buffer_paddr, 0, wbm_bm_id);
  1270. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned[tx_buffer_count]
  1271. = (void *)nbuf;
  1272. }
  1273. hal_srng_access_end_unlocked(soc->hal_soc,
  1274. hal_srng_to_hal_ring_handle(wbm_srng));
  1275. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  1276. if (tx_buffer_count) {
  1277. dp_info("IPA WDI TX buffer: %d allocated", tx_buffer_count);
  1278. } else {
  1279. dp_err("No IPA WDI TX buffer allocated!");
  1280. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned);
  1281. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr_unaligned = NULL;
  1282. retval = -ENOMEM;
  1283. }
  1284. return retval;
  1285. }
  1286. /**
  1287. * dp_rx_ipa_uc_attach() - Allocate autonomy RX resources
  1288. * @soc: data path instance
  1289. * @pdev: core txrx pdev context
  1290. *
  1291. * This function will attach a DP RX instance into the main
  1292. * device (SOC) context.
  1293. *
  1294. * Return: QDF_STATUS_SUCCESS: success
  1295. * QDF_STATUS_E_RESOURCES: Error return
  1296. */
  1297. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1298. {
  1299. return QDF_STATUS_SUCCESS;
  1300. }
  1301. int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  1302. {
  1303. int error;
  1304. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1305. return QDF_STATUS_SUCCESS;
  1306. /* TX resource attach */
  1307. error = dp_tx_ipa_uc_attach(soc, pdev);
  1308. if (error) {
  1309. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1310. "%s: DP IPA UC TX attach fail code %d",
  1311. __func__, error);
  1312. return error;
  1313. }
  1314. /* Setup 2nd TX pipe */
  1315. error = dp_ipa_tx_alt_pool_attach(soc);
  1316. if (error) {
  1317. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1318. "%s: DP IPA TX pool2 attach fail code %d",
  1319. __func__, error);
  1320. dp_tx_ipa_uc_detach(soc, pdev);
  1321. return error;
  1322. }
  1323. /* RX resource attach */
  1324. error = dp_rx_ipa_uc_attach(soc, pdev);
  1325. if (error) {
  1326. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1327. "%s: DP IPA UC RX attach fail code %d",
  1328. __func__, error);
  1329. dp_ipa_tx_alt_pool_detach(soc, pdev);
  1330. dp_tx_ipa_uc_detach(soc, pdev);
  1331. return error;
  1332. }
  1333. return QDF_STATUS_SUCCESS; /* success */
  1334. }
  1335. #ifdef IPA_WDI3_VLAN_SUPPORT
  1336. /**
  1337. * dp_ipa_rx_alt_ring_resource_setup() - setup IPA 2nd RX ring resources
  1338. * @soc: data path SoC handle
  1339. * @pdev: data path pdev handle
  1340. *
  1341. * Return: none
  1342. */
  1343. static
  1344. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1345. {
  1346. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1347. struct hal_srng *hal_srng;
  1348. struct hal_srng_params srng_params;
  1349. unsigned long addr_offset, dev_base_paddr;
  1350. qdf_dma_addr_t hp_addr;
  1351. if (!wlan_ipa_is_vlan_enabled())
  1352. return;
  1353. dev_base_paddr =
  1354. (unsigned long)
  1355. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1356. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW3 */
  1357. hal_srng = (struct hal_srng *)
  1358. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1359. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1360. hal_srng_to_hal_ring_handle(hal_srng),
  1361. &srng_params);
  1362. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr =
  1363. srng_params.ring_base_paddr;
  1364. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr =
  1365. srng_params.ring_base_vaddr;
  1366. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size =
  1367. (srng_params.num_entries * srng_params.entry_size) << 2;
  1368. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1369. (unsigned long)(hal_soc->dev_base_addr);
  1370. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr =
  1371. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1372. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1373. (unsigned int)addr_offset,
  1374. (unsigned int)dev_base_paddr,
  1375. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr),
  1376. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1377. (void *)soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1378. srng_params.num_entries,
  1379. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1380. hal_srng = (struct hal_srng *)
  1381. pdev->rx_refill_buf_ring3.hal_srng;
  1382. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1383. hal_srng_to_hal_ring_handle(hal_srng),
  1384. &srng_params);
  1385. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr =
  1386. srng_params.ring_base_paddr;
  1387. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr =
  1388. srng_params.ring_base_vaddr;
  1389. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size =
  1390. (srng_params.num_entries * srng_params.entry_size) << 2;
  1391. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1392. hal_srng_to_hal_ring_handle(hal_srng));
  1393. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr =
  1394. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1395. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1396. (unsigned int)(soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr),
  1397. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1398. (void *)soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1399. srng_params.num_entries,
  1400. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1401. }
  1402. #else
  1403. static inline
  1404. void dp_ipa_rx_alt_ring_resource_setup(struct dp_soc *soc, struct dp_pdev *pdev)
  1405. { }
  1406. #endif
  1407. int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1408. struct dp_pdev *pdev)
  1409. {
  1410. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  1411. struct hal_srng *hal_srng;
  1412. struct hal_srng_params srng_params;
  1413. qdf_dma_addr_t hp_addr;
  1414. unsigned long addr_offset, dev_base_paddr;
  1415. uint32_t ix0;
  1416. uint8_t ix0_map[8];
  1417. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1418. return QDF_STATUS_SUCCESS;
  1419. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL3 */
  1420. hal_srng = (struct hal_srng *)
  1421. soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1422. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1423. hal_srng_to_hal_ring_handle(hal_srng),
  1424. &srng_params);
  1425. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1426. srng_params.ring_base_paddr;
  1427. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1428. srng_params.ring_base_vaddr;
  1429. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1430. (srng_params.num_entries * srng_params.entry_size) << 2;
  1431. /*
  1432. * For the register backed memory addresses, use the scn->mem_pa to
  1433. * calculate the physical address of the shadow registers
  1434. */
  1435. dev_base_paddr =
  1436. (unsigned long)
  1437. ((struct hif_softc *)(hal_soc->hif_handle))->mem_pa;
  1438. addr_offset = (unsigned long)(hal_srng->u.src_ring.hp_addr) -
  1439. (unsigned long)(hal_soc->dev_base_addr);
  1440. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr =
  1441. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1442. dp_info("IPA TCL_DATA Ring addr_offset=%x, dev_base_paddr=%x, hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1443. (unsigned int)addr_offset,
  1444. (unsigned int)dev_base_paddr,
  1445. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr),
  1446. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1447. (void *)soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1448. srng_params.num_entries,
  1449. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1450. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW2_RELEASE */
  1451. hal_srng = (struct hal_srng *)
  1452. soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1453. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1454. hal_srng_to_hal_ring_handle(hal_srng),
  1455. &srng_params);
  1456. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1457. srng_params.ring_base_paddr;
  1458. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1459. srng_params.ring_base_vaddr;
  1460. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1461. (srng_params.num_entries * srng_params.entry_size) << 2;
  1462. soc->ipa_uc_tx_rsc.ipa_wbm_hp_shadow_paddr =
  1463. hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1464. hal_srng_to_hal_ring_handle(hal_srng));
  1465. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1466. (unsigned long)(hal_soc->dev_base_addr);
  1467. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr =
  1468. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1469. dp_info("IPA TX COMP Ring addr_offset=%x, dev_base_paddr=%x, ipa_wbm_tp_paddr=%x paddr=%pK vaddr=0%pK size= %u(%u bytes)",
  1470. (unsigned int)addr_offset,
  1471. (unsigned int)dev_base_paddr,
  1472. (unsigned int)(soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr),
  1473. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1474. (void *)soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1475. srng_params.num_entries,
  1476. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1477. dp_ipa_tx_alt_ring_resource_setup(soc);
  1478. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1479. hal_srng = (struct hal_srng *)
  1480. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1481. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1482. hal_srng_to_hal_ring_handle(hal_srng),
  1483. &srng_params);
  1484. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1485. srng_params.ring_base_paddr;
  1486. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1487. srng_params.ring_base_vaddr;
  1488. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1489. (srng_params.num_entries * srng_params.entry_size) << 2;
  1490. addr_offset = (unsigned long)(hal_srng->u.dst_ring.tp_addr) -
  1491. (unsigned long)(hal_soc->dev_base_addr);
  1492. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr =
  1493. (qdf_dma_addr_t)(addr_offset + dev_base_paddr);
  1494. dp_info("IPA REO_DEST Ring addr_offset=%x, dev_base_paddr=%x, tp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1495. (unsigned int)addr_offset,
  1496. (unsigned int)dev_base_paddr,
  1497. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr),
  1498. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1499. (void *)soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1500. srng_params.num_entries,
  1501. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1502. hal_srng = (struct hal_srng *)
  1503. pdev->rx_refill_buf_ring2.hal_srng;
  1504. hal_get_srng_params(hal_soc_to_hal_soc_handle(hal_soc),
  1505. hal_srng_to_hal_ring_handle(hal_srng),
  1506. &srng_params);
  1507. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1508. srng_params.ring_base_paddr;
  1509. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1510. srng_params.ring_base_vaddr;
  1511. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1512. (srng_params.num_entries * srng_params.entry_size) << 2;
  1513. hp_addr = hal_srng_get_hp_addr(hal_soc_to_hal_soc_handle(hal_soc),
  1514. hal_srng_to_hal_ring_handle(hal_srng));
  1515. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr =
  1516. qdf_mem_paddr_from_dmaaddr(soc->osdev, hp_addr);
  1517. dp_info("IPA REFILL_BUF Ring hp_paddr=%x paddr=%pK vaddr=%pK size= %u(%u bytes)",
  1518. (unsigned int)(soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr),
  1519. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1520. (void *)soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1521. srng_params.num_entries,
  1522. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1523. /*
  1524. * Set DEST_RING_MAPPING_4 to SW2 as default value for
  1525. * DESTINATION_RING_CTRL_IX_0.
  1526. */
  1527. ix0_map[0] = REO_REMAP_SW1;
  1528. ix0_map[1] = REO_REMAP_SW1;
  1529. ix0_map[2] = REO_REMAP_SW2;
  1530. ix0_map[3] = REO_REMAP_SW3;
  1531. ix0_map[4] = REO_REMAP_SW2;
  1532. ix0_map[5] = REO_REMAP_RELEASE;
  1533. ix0_map[6] = REO_REMAP_FW;
  1534. ix0_map[7] = REO_REMAP_FW;
  1535. dp_ipa_opt_dp_ixo_remap(ix0_map);
  1536. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1537. ix0_map);
  1538. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL, NULL, NULL);
  1539. dp_ipa_rx_alt_ring_resource_setup(soc, pdev);
  1540. return 0;
  1541. }
  1542. #ifdef IPA_WDI3_VLAN_SUPPORT
  1543. /**
  1544. * dp_ipa_rx_alt_ring_get_resource() - get IPA 2nd RX ring resources
  1545. * @pdev: data path pdev handle
  1546. *
  1547. * Return: Success if resourece is found
  1548. */
  1549. static QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1550. {
  1551. struct dp_soc *soc = pdev->soc;
  1552. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1553. if (!wlan_ipa_is_vlan_enabled())
  1554. return QDF_STATUS_SUCCESS;
  1555. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_alt_rdy_ring,
  1556. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_vaddr,
  1557. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_base_paddr,
  1558. soc->ipa_uc_rx_rsc_alt.ipa_reo_ring_size);
  1559. dp_ipa_get_shared_mem_info(
  1560. soc->osdev, &ipa_res->rx_alt_refill_ring,
  1561. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_vaddr,
  1562. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_base_paddr,
  1563. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_ring_size);
  1564. if (!qdf_mem_get_dma_addr(soc->osdev,
  1565. &ipa_res->rx_alt_rdy_ring.mem_info) ||
  1566. !qdf_mem_get_dma_addr(soc->osdev,
  1567. &ipa_res->rx_alt_refill_ring.mem_info))
  1568. return QDF_STATUS_E_FAILURE;
  1569. return QDF_STATUS_SUCCESS;
  1570. }
  1571. #else
  1572. static inline QDF_STATUS dp_ipa_rx_alt_ring_get_resource(struct dp_pdev *pdev)
  1573. {
  1574. return QDF_STATUS_SUCCESS;
  1575. }
  1576. #endif
  1577. QDF_STATUS dp_ipa_get_resource(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1578. {
  1579. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1580. struct dp_pdev *pdev =
  1581. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1582. struct dp_ipa_resources *ipa_res;
  1583. if (!pdev) {
  1584. dp_err("Invalid instance");
  1585. return QDF_STATUS_E_FAILURE;
  1586. }
  1587. ipa_res = &pdev->ipa_resource;
  1588. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1589. return QDF_STATUS_SUCCESS;
  1590. ipa_res->tx_num_alloc_buffer =
  1591. (uint32_t)soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt;
  1592. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_ring,
  1593. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr,
  1594. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr,
  1595. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size);
  1596. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->tx_comp_ring,
  1597. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr,
  1598. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr,
  1599. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size);
  1600. dp_ipa_get_shared_mem_info(soc->osdev, &ipa_res->rx_rdy_ring,
  1601. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr,
  1602. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr,
  1603. soc->ipa_uc_rx_rsc.ipa_reo_ring_size);
  1604. dp_ipa_get_shared_mem_info(
  1605. soc->osdev, &ipa_res->rx_refill_ring,
  1606. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr,
  1607. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr,
  1608. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size);
  1609. if (!qdf_mem_get_dma_addr(soc->osdev, &ipa_res->tx_ring.mem_info) ||
  1610. !qdf_mem_get_dma_addr(soc->osdev,
  1611. &ipa_res->tx_comp_ring.mem_info) ||
  1612. !qdf_mem_get_dma_addr(soc->osdev, &ipa_res->rx_rdy_ring.mem_info) ||
  1613. !qdf_mem_get_dma_addr(soc->osdev,
  1614. &ipa_res->rx_refill_ring.mem_info))
  1615. return QDF_STATUS_E_FAILURE;
  1616. if (dp_ipa_tx_alt_ring_get_resource(pdev))
  1617. return QDF_STATUS_E_FAILURE;
  1618. if (dp_ipa_rx_alt_ring_get_resource(pdev))
  1619. return QDF_STATUS_E_FAILURE;
  1620. return QDF_STATUS_SUCCESS;
  1621. }
  1622. #ifdef IPA_SET_RESET_TX_DB_PA
  1623. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res)
  1624. #else
  1625. #define DP_IPA_SET_TX_DB_PADDR(soc, ipa_res) \
  1626. dp_ipa_set_tx_doorbell_paddr(soc, ipa_res)
  1627. #endif
  1628. #ifdef IPA_WDI3_VLAN_SUPPORT
  1629. /**
  1630. * dp_ipa_map_rx_alt_ring_doorbell_paddr() - Map 2nd rx ring doorbell paddr
  1631. * @pdev: data path pdev handle
  1632. *
  1633. * Return: none
  1634. */
  1635. static void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1636. {
  1637. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1638. uint32_t rx_ready_doorbell_dmaaddr;
  1639. struct dp_soc *soc = pdev->soc;
  1640. struct hal_srng *reo_srng = (struct hal_srng *)
  1641. soc->reo_dest_ring[IPA_ALT_REO_DEST_RING_IDX].hal_srng;
  1642. int ret = 0;
  1643. if (!wlan_ipa_is_vlan_enabled())
  1644. return;
  1645. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  1646. ret = pld_smmu_map(soc->osdev->dev,
  1647. ipa_res->rx_alt_ready_doorbell_paddr,
  1648. &rx_ready_doorbell_dmaaddr,
  1649. sizeof(uint32_t));
  1650. ipa_res->rx_alt_ready_doorbell_paddr =
  1651. rx_ready_doorbell_dmaaddr;
  1652. qdf_assert_always(!ret);
  1653. }
  1654. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1655. ipa_res->rx_alt_ready_doorbell_paddr);
  1656. }
  1657. /**
  1658. * dp_ipa_unmap_rx_alt_ring_doorbell_paddr() - Unmap 2nd rx ring doorbell paddr
  1659. * @pdev: data path pdev handle
  1660. *
  1661. * Return: none
  1662. */
  1663. static void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1664. {
  1665. struct dp_ipa_resources *ipa_res = &pdev->ipa_resource;
  1666. struct dp_soc *soc = pdev->soc;
  1667. int ret = 0;
  1668. if (!wlan_ipa_is_vlan_enabled())
  1669. return;
  1670. if (!qdf_mem_smmu_s1_enabled(soc->osdev))
  1671. return;
  1672. ret = pld_smmu_unmap(soc->osdev->dev,
  1673. ipa_res->rx_alt_ready_doorbell_paddr,
  1674. sizeof(uint32_t));
  1675. qdf_assert_always(!ret);
  1676. }
  1677. #else
  1678. static inline void dp_ipa_map_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1679. { }
  1680. static inline void dp_ipa_unmap_rx_alt_ring_doorbell_paddr(struct dp_pdev *pdev)
  1681. { }
  1682. #endif
  1683. QDF_STATUS dp_ipa_set_doorbell_paddr(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1684. {
  1685. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1686. struct dp_pdev *pdev =
  1687. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1688. struct dp_ipa_resources *ipa_res;
  1689. struct hal_srng *reo_srng = (struct hal_srng *)
  1690. soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1691. if (!pdev) {
  1692. dp_err("Invalid instance");
  1693. return QDF_STATUS_E_FAILURE;
  1694. }
  1695. ipa_res = &pdev->ipa_resource;
  1696. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1697. return QDF_STATUS_SUCCESS;
  1698. dp_ipa_map_ring_doorbell_paddr(pdev);
  1699. dp_ipa_map_rx_alt_ring_doorbell_paddr(pdev);
  1700. DP_IPA_SET_TX_DB_PADDR(soc, ipa_res);
  1701. /*
  1702. * For RX, REO module on Napier/Hastings does reordering on incoming
  1703. * Ethernet packets and writes one or more descriptors to REO2IPA Rx
  1704. * ring.It then updates the ring’s Write/Head ptr and rings a doorbell
  1705. * to IPA.
  1706. * Set the doorbell addr for the REO ring.
  1707. */
  1708. hal_srng_dst_set_hp_paddr_confirm(reo_srng,
  1709. ipa_res->rx_ready_doorbell_paddr);
  1710. return QDF_STATUS_SUCCESS;
  1711. }
  1712. QDF_STATUS dp_ipa_iounmap_doorbell_vaddr(struct cdp_soc_t *soc_hdl,
  1713. uint8_t pdev_id)
  1714. {
  1715. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1716. struct dp_pdev *pdev =
  1717. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1718. struct dp_ipa_resources *ipa_res;
  1719. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1720. return QDF_STATUS_SUCCESS;
  1721. if (!pdev) {
  1722. dp_err("Invalid instance");
  1723. return QDF_STATUS_E_FAILURE;
  1724. }
  1725. ipa_res = &pdev->ipa_resource;
  1726. if (!ipa_res->is_db_ddr_mapped)
  1727. iounmap(ipa_res->tx_comp_doorbell_vaddr);
  1728. return QDF_STATUS_SUCCESS;
  1729. }
  1730. QDF_STATUS dp_ipa_op_response(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1731. uint8_t *op_msg)
  1732. {
  1733. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1734. struct dp_pdev *pdev =
  1735. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1736. if (!pdev) {
  1737. dp_err("Invalid instance");
  1738. return QDF_STATUS_E_FAILURE;
  1739. }
  1740. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1741. return QDF_STATUS_SUCCESS;
  1742. if (pdev->ipa_uc_op_cb) {
  1743. pdev->ipa_uc_op_cb(op_msg, pdev->usr_ctxt);
  1744. } else {
  1745. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1746. "%s: IPA callback function is not registered", __func__);
  1747. qdf_mem_free(op_msg);
  1748. return QDF_STATUS_E_FAILURE;
  1749. }
  1750. return QDF_STATUS_SUCCESS;
  1751. }
  1752. QDF_STATUS dp_ipa_register_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  1753. ipa_uc_op_cb_type op_cb,
  1754. void *usr_ctxt)
  1755. {
  1756. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1757. struct dp_pdev *pdev =
  1758. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1759. if (!pdev) {
  1760. dp_err("Invalid instance");
  1761. return QDF_STATUS_E_FAILURE;
  1762. }
  1763. if (!wlan_cfg_is_ipa_enabled(pdev->soc->wlan_cfg_ctx))
  1764. return QDF_STATUS_SUCCESS;
  1765. pdev->ipa_uc_op_cb = op_cb;
  1766. pdev->usr_ctxt = usr_ctxt;
  1767. return QDF_STATUS_SUCCESS;
  1768. }
  1769. void dp_ipa_deregister_op_cb(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1770. {
  1771. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1772. struct dp_pdev *pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1773. if (!pdev) {
  1774. dp_err("Invalid instance");
  1775. return;
  1776. }
  1777. dp_debug("Deregister OP handler callback");
  1778. pdev->ipa_uc_op_cb = NULL;
  1779. pdev->usr_ctxt = NULL;
  1780. }
  1781. QDF_STATUS dp_ipa_get_stat(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1782. {
  1783. /* TBD */
  1784. return QDF_STATUS_SUCCESS;
  1785. }
  1786. qdf_nbuf_t dp_tx_send_ipa_data_frame(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1787. qdf_nbuf_t skb)
  1788. {
  1789. qdf_nbuf_t ret;
  1790. /* Terminate the (single-element) list of tx frames */
  1791. qdf_nbuf_set_next(skb, NULL);
  1792. ret = dp_tx_send(soc_hdl, vdev_id, skb);
  1793. if (ret) {
  1794. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1795. "%s: Failed to tx", __func__);
  1796. return ret;
  1797. }
  1798. return NULL;
  1799. }
  1800. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  1801. /**
  1802. * dp_ipa_is_target_ready() - check if target is ready or not
  1803. * @soc: datapath soc handle
  1804. *
  1805. * Return: true if target is ready
  1806. */
  1807. static inline
  1808. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1809. {
  1810. if (hif_get_target_status(soc->hif_handle) == TARGET_STATUS_RESET)
  1811. return false;
  1812. else
  1813. return true;
  1814. }
  1815. /**
  1816. * dp_ipa_update_txr_db_status() - Indicate transfer ring DB is SMMU mapped or not
  1817. * @dev: Pointer to device
  1818. * @txrx_smmu: WDI TX/RX configuration
  1819. *
  1820. * Return: None
  1821. */
  1822. static inline
  1823. void dp_ipa_update_txr_db_status(struct device *dev,
  1824. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1825. {
  1826. int pcie_slot = pld_get_pci_slot(dev);
  1827. if (pcie_slot)
  1828. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = false;
  1829. else
  1830. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1831. }
  1832. /**
  1833. * dp_ipa_update_evt_db_status() - Indicate evt ring DB is SMMU mapped or not
  1834. * @dev: Pointer to device
  1835. * @txrx_smmu: WDI TX/RX configuration
  1836. *
  1837. * Return: None
  1838. */
  1839. static inline
  1840. void dp_ipa_update_evt_db_status(struct device *dev,
  1841. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1842. {
  1843. int pcie_slot = pld_get_pci_slot(dev);
  1844. if (pcie_slot)
  1845. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = false;
  1846. else
  1847. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1848. }
  1849. #else
  1850. static inline
  1851. bool dp_ipa_is_target_ready(struct dp_soc *soc)
  1852. {
  1853. return true;
  1854. }
  1855. static inline
  1856. void dp_ipa_update_txr_db_status(struct device *dev,
  1857. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1858. {
  1859. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1860. }
  1861. static inline
  1862. void dp_ipa_update_evt_db_status(struct device *dev,
  1863. qdf_ipa_wdi_pipe_setup_info_smmu_t *txrx_smmu)
  1864. {
  1865. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(txrx_smmu) = true;
  1866. }
  1867. #endif
  1868. QDF_STATUS dp_ipa_enable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1869. {
  1870. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1871. struct dp_pdev *pdev =
  1872. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1873. uint32_t ix0;
  1874. uint32_t ix2;
  1875. uint8_t ix_map[8];
  1876. if (!pdev) {
  1877. dp_err("Invalid instance");
  1878. return QDF_STATUS_E_FAILURE;
  1879. }
  1880. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1881. return QDF_STATUS_SUCCESS;
  1882. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1883. return QDF_STATUS_E_AGAIN;
  1884. if (!dp_ipa_is_target_ready(soc))
  1885. return QDF_STATUS_E_AGAIN;
  1886. /* Call HAL API to remap REO rings to REO2IPA ring */
  1887. ix_map[0] = REO_REMAP_SW1;
  1888. ix_map[1] = REO_REMAP_SW4;
  1889. ix_map[2] = REO_REMAP_SW1;
  1890. if (wlan_ipa_is_vlan_enabled())
  1891. ix_map[3] = REO_REMAP_SW3;
  1892. else
  1893. ix_map[3] = REO_REMAP_SW4;
  1894. ix_map[4] = REO_REMAP_SW4;
  1895. ix_map[5] = REO_REMAP_RELEASE;
  1896. ix_map[6] = REO_REMAP_FW;
  1897. ix_map[7] = REO_REMAP_FW;
  1898. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1899. ix_map);
  1900. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1901. ix_map[0] = REO_REMAP_SW4;
  1902. ix_map[1] = REO_REMAP_SW4;
  1903. ix_map[2] = REO_REMAP_SW4;
  1904. ix_map[3] = REO_REMAP_SW4;
  1905. ix_map[4] = REO_REMAP_SW4;
  1906. ix_map[5] = REO_REMAP_SW4;
  1907. ix_map[6] = REO_REMAP_SW4;
  1908. ix_map[7] = REO_REMAP_SW4;
  1909. ix2 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX2,
  1910. ix_map);
  1911. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1912. &ix2, &ix2);
  1913. dp_ipa_reo_remap_history_add(ix0, ix2, ix2);
  1914. } else {
  1915. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1916. NULL, NULL);
  1917. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1918. }
  1919. return QDF_STATUS_SUCCESS;
  1920. }
  1921. QDF_STATUS dp_ipa_disable_autonomy(struct cdp_soc_t *soc_hdl, uint8_t pdev_id)
  1922. {
  1923. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1924. struct dp_pdev *pdev =
  1925. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  1926. uint8_t ix0_map[8];
  1927. uint32_t ix0;
  1928. uint32_t ix1;
  1929. uint32_t ix2;
  1930. uint32_t ix3;
  1931. if (!pdev) {
  1932. dp_err("Invalid instance");
  1933. return QDF_STATUS_E_FAILURE;
  1934. }
  1935. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  1936. return QDF_STATUS_SUCCESS;
  1937. if (!hif_is_target_ready(HIF_GET_SOFTC(soc->hif_handle)))
  1938. return QDF_STATUS_E_AGAIN;
  1939. if (!dp_ipa_is_target_ready(soc))
  1940. return QDF_STATUS_E_AGAIN;
  1941. ix0_map[0] = REO_REMAP_SW1;
  1942. ix0_map[1] = REO_REMAP_SW1;
  1943. ix0_map[2] = REO_REMAP_SW2;
  1944. ix0_map[3] = REO_REMAP_SW3;
  1945. ix0_map[4] = REO_REMAP_SW2;
  1946. ix0_map[5] = REO_REMAP_RELEASE;
  1947. ix0_map[6] = REO_REMAP_FW;
  1948. ix0_map[7] = REO_REMAP_FW;
  1949. /* Call HAL API to remap REO rings to REO2IPA ring */
  1950. ix0 = hal_gen_reo_remap_val(soc->hal_soc, HAL_REO_REMAP_REG_IX0,
  1951. ix0_map);
  1952. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1953. dp_reo_remap_config(soc, &ix1, &ix2, &ix3);
  1954. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1955. &ix2, &ix3);
  1956. dp_ipa_reo_remap_history_add(ix0, ix2, ix3);
  1957. } else {
  1958. hal_reo_read_write_ctrl_ix(soc->hal_soc, false, &ix0, NULL,
  1959. NULL, NULL);
  1960. dp_ipa_reo_remap_history_add(ix0, 0, 0);
  1961. }
  1962. return QDF_STATUS_SUCCESS;
  1963. }
  1964. /* This should be configurable per H/W configuration enable status */
  1965. #define L3_HEADER_PADDING 2
  1966. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || \
  1967. defined(CONFIG_IPA_WDI_UNIFIED_API)
  1968. #if !defined(QCA_LL_TX_FLOW_CONTROL_V2) && !defined(QCA_IPA_LL_TX_FLOW_CONTROL)
  1969. static inline void dp_setup_mcc_sys_pipes(
  1970. qdf_ipa_sys_connect_params_t *sys_in,
  1971. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  1972. {
  1973. int i = 0;
  1974. /* Setup MCC sys pipe */
  1975. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) =
  1976. DP_IPA_MAX_IFACE;
  1977. for (i = 0; i < DP_IPA_MAX_IFACE; i++)
  1978. memcpy(&QDF_IPA_WDI_CONN_IN_PARAMS_SYS_IN(pipe_in)[i],
  1979. &sys_in[i], sizeof(qdf_ipa_sys_connect_params_t));
  1980. }
  1981. #else
  1982. static inline void dp_setup_mcc_sys_pipes(
  1983. qdf_ipa_sys_connect_params_t *sys_in,
  1984. qdf_ipa_wdi_conn_in_params_t *pipe_in)
  1985. {
  1986. QDF_IPA_WDI_CONN_IN_PARAMS_NUM_SYS_PIPE_NEEDED(pipe_in) = 0;
  1987. }
  1988. #endif
  1989. static void dp_ipa_wdi_tx_params(struct dp_soc *soc,
  1990. struct dp_ipa_resources *ipa_res,
  1991. qdf_ipa_wdi_pipe_setup_info_t *tx,
  1992. bool over_gsi)
  1993. {
  1994. if (over_gsi)
  1995. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN2_CONS;
  1996. else
  1997. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  1998. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  1999. qdf_mem_get_dma_addr(soc->osdev,
  2000. &ipa_res->tx_comp_ring.mem_info);
  2001. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2002. qdf_mem_get_dma_size(soc->osdev,
  2003. &ipa_res->tx_comp_ring.mem_info);
  2004. /* WBM Tail Pointer Address */
  2005. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2006. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2007. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(tx) = true;
  2008. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2009. qdf_mem_get_dma_addr(soc->osdev,
  2010. &ipa_res->tx_ring.mem_info);
  2011. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) =
  2012. qdf_mem_get_dma_size(soc->osdev,
  2013. &ipa_res->tx_ring.mem_info);
  2014. /* TCL Head Pointer Address */
  2015. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2016. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2017. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(tx) = true;
  2018. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2019. ipa_res->tx_num_alloc_buffer;
  2020. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2021. dp_ipa_setup_tx_params_bank_id(soc, tx);
  2022. /* Set Pmac ID, extract pmac_id from pdev_id 0 for TX ring */
  2023. dp_ipa_setup_tx_params_pmac_id(soc, tx);
  2024. }
  2025. static void dp_ipa_wdi_rx_params(struct dp_soc *soc,
  2026. struct dp_ipa_resources *ipa_res,
  2027. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2028. bool over_gsi)
  2029. {
  2030. if (over_gsi)
  2031. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2032. IPA_CLIENT_WLAN2_PROD;
  2033. else
  2034. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2035. IPA_CLIENT_WLAN1_PROD;
  2036. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2037. qdf_mem_get_dma_addr(soc->osdev,
  2038. &ipa_res->rx_rdy_ring.mem_info);
  2039. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2040. qdf_mem_get_dma_size(soc->osdev,
  2041. &ipa_res->rx_rdy_ring.mem_info);
  2042. /* REO Tail Pointer Address */
  2043. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2044. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2045. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2046. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2047. qdf_mem_get_dma_addr(soc->osdev,
  2048. &ipa_res->rx_refill_ring.mem_info);
  2049. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2050. qdf_mem_get_dma_size(soc->osdev,
  2051. &ipa_res->rx_refill_ring.mem_info);
  2052. /* FW Head Pointer Address */
  2053. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2054. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2055. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2056. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2057. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2058. }
  2059. static void
  2060. dp_ipa_wdi_tx_smmu_params(struct dp_soc *soc,
  2061. struct dp_ipa_resources *ipa_res,
  2062. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu,
  2063. bool over_gsi,
  2064. qdf_ipa_wdi_hdl_t hdl)
  2065. {
  2066. if (over_gsi) {
  2067. if (hdl == DP_IPA_HDL_FIRST)
  2068. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2069. IPA_CLIENT_WLAN2_CONS;
  2070. else if (hdl == DP_IPA_HDL_SECOND)
  2071. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2072. IPA_CLIENT_WLAN4_CONS;
  2073. else if (hdl == DP_IPA_HDL_THIRD)
  2074. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2075. IPA_CLIENT_WLAN1_CONS;
  2076. } else {
  2077. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(tx_smmu) =
  2078. IPA_CLIENT_WLAN1_CONS;
  2079. }
  2080. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(tx_smmu),
  2081. &ipa_res->tx_comp_ring.sgtable,
  2082. sizeof(sgtable_t));
  2083. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(tx_smmu) =
  2084. qdf_mem_get_dma_size(soc->osdev,
  2085. &ipa_res->tx_comp_ring.mem_info);
  2086. /* WBM Tail Pointer Address */
  2087. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(tx_smmu) =
  2088. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2089. dp_ipa_update_txr_db_status(soc->osdev->dev, tx_smmu);
  2090. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(tx_smmu),
  2091. &ipa_res->tx_ring.sgtable,
  2092. sizeof(sgtable_t));
  2093. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(tx_smmu) =
  2094. qdf_mem_get_dma_size(soc->osdev,
  2095. &ipa_res->tx_ring.mem_info);
  2096. /* TCL Head Pointer Address */
  2097. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(tx_smmu) =
  2098. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2099. dp_ipa_update_evt_db_status(soc->osdev->dev, tx_smmu);
  2100. QDF_IPA_WDI_SETUP_INFO_SMMU_NUM_PKT_BUFFERS(tx_smmu) =
  2101. ipa_res->tx_num_alloc_buffer;
  2102. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(tx_smmu) = 0;
  2103. dp_ipa_setup_tx_smmu_params_bank_id(soc, tx_smmu);
  2104. /* Set Pmac ID, extract pmac_id from first pdev for TX ring */
  2105. dp_ipa_setup_tx_smmu_params_pmac_id(soc, tx_smmu);
  2106. }
  2107. static void
  2108. dp_ipa_wdi_rx_smmu_params(struct dp_soc *soc,
  2109. struct dp_ipa_resources *ipa_res,
  2110. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2111. bool over_gsi,
  2112. qdf_ipa_wdi_hdl_t hdl)
  2113. {
  2114. if (over_gsi) {
  2115. if (hdl == DP_IPA_HDL_FIRST)
  2116. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2117. IPA_CLIENT_WLAN2_PROD;
  2118. else if (hdl == DP_IPA_HDL_SECOND)
  2119. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2120. IPA_CLIENT_WLAN3_PROD;
  2121. else if (hdl == DP_IPA_HDL_THIRD)
  2122. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2123. IPA_CLIENT_WLAN1_PROD;
  2124. } else {
  2125. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2126. IPA_CLIENT_WLAN1_PROD;
  2127. }
  2128. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2129. &ipa_res->rx_rdy_ring.sgtable,
  2130. sizeof(sgtable_t));
  2131. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2132. qdf_mem_get_dma_size(soc->osdev,
  2133. &ipa_res->rx_rdy_ring.mem_info);
  2134. /* REO Tail Pointer Address */
  2135. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2136. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2137. dp_ipa_update_txr_db_status(soc->osdev->dev, rx_smmu);
  2138. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2139. &ipa_res->rx_refill_ring.sgtable,
  2140. sizeof(sgtable_t));
  2141. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2142. qdf_mem_get_dma_size(soc->osdev,
  2143. &ipa_res->rx_refill_ring.mem_info);
  2144. /* FW Head Pointer Address */
  2145. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2146. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2147. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2148. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2149. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2150. }
  2151. #ifdef IPA_WDI3_VLAN_SUPPORT
  2152. /**
  2153. * dp_ipa_wdi_rx_alt_pipe_smmu_params() - Setup 2nd rx pipe smmu params
  2154. * @soc: data path soc handle
  2155. * @ipa_res: ipa resource pointer
  2156. * @rx_smmu: smmu pipe info handle
  2157. * @over_gsi: flag for IPA offload over gsi
  2158. * @hdl: ipa registered handle
  2159. *
  2160. * Return: none
  2161. */
  2162. static void
  2163. dp_ipa_wdi_rx_alt_pipe_smmu_params(struct dp_soc *soc,
  2164. struct dp_ipa_resources *ipa_res,
  2165. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu,
  2166. bool over_gsi,
  2167. qdf_ipa_wdi_hdl_t hdl)
  2168. {
  2169. if (!wlan_ipa_is_vlan_enabled())
  2170. return;
  2171. if (over_gsi) {
  2172. if (hdl == DP_IPA_HDL_FIRST)
  2173. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2174. IPA_CLIENT_WLAN2_PROD1;
  2175. else if (hdl == DP_IPA_HDL_SECOND)
  2176. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2177. IPA_CLIENT_WLAN3_PROD1;
  2178. else if (hdl == DP_IPA_HDL_THIRD)
  2179. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx_smmu) =
  2180. IPA_CLIENT_WLAN1_PROD1;
  2181. } else {
  2182. QDF_IPA_WDI_SETUP_INFO_SMMU_CLIENT(rx_smmu) =
  2183. IPA_CLIENT_WLAN1_PROD;
  2184. }
  2185. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_BASE(rx_smmu),
  2186. &ipa_res->rx_alt_rdy_ring.sgtable,
  2187. sizeof(sgtable_t));
  2188. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_SIZE(rx_smmu) =
  2189. qdf_mem_get_dma_size(soc->osdev,
  2190. &ipa_res->rx_alt_rdy_ring.mem_info);
  2191. /* REO Tail Pointer Address */
  2192. QDF_IPA_WDI_SETUP_INFO_SMMU_TRANSFER_RING_DOORBELL_PA(rx_smmu) =
  2193. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2194. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_TXR_RN_DB_PCIE_ADDR(rx_smmu) = true;
  2195. qdf_mem_copy(&QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_BASE(rx_smmu),
  2196. &ipa_res->rx_alt_refill_ring.sgtable,
  2197. sizeof(sgtable_t));
  2198. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_SIZE(rx_smmu) =
  2199. qdf_mem_get_dma_size(soc->osdev,
  2200. &ipa_res->rx_alt_refill_ring.mem_info);
  2201. /* FW Head Pointer Address */
  2202. QDF_IPA_WDI_SETUP_INFO_SMMU_EVENT_RING_DOORBELL_PA(rx_smmu) =
  2203. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2204. QDF_IPA_WDI_SETUP_INFO_SMMU_IS_EVT_RN_DB_PCIE_ADDR(rx_smmu) = false;
  2205. QDF_IPA_WDI_SETUP_INFO_SMMU_PKT_OFFSET(rx_smmu) =
  2206. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2207. }
  2208. /**
  2209. * dp_ipa_wdi_rx_alt_pipe_params() - Setup 2nd rx pipe params
  2210. * @soc: data path soc handle
  2211. * @ipa_res: ipa resource pointer
  2212. * @rx: pipe info handle
  2213. * @over_gsi: flag for IPA offload over gsi
  2214. * @hdl: ipa registered handle
  2215. *
  2216. * Return: none
  2217. */
  2218. static void dp_ipa_wdi_rx_alt_pipe_params(struct dp_soc *soc,
  2219. struct dp_ipa_resources *ipa_res,
  2220. qdf_ipa_wdi_pipe_setup_info_t *rx,
  2221. bool over_gsi,
  2222. qdf_ipa_wdi_hdl_t hdl)
  2223. {
  2224. if (!wlan_ipa_is_vlan_enabled())
  2225. return;
  2226. if (over_gsi) {
  2227. if (hdl == DP_IPA_HDL_FIRST)
  2228. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2229. IPA_CLIENT_WLAN2_PROD1;
  2230. else if (hdl == DP_IPA_HDL_SECOND)
  2231. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2232. IPA_CLIENT_WLAN3_PROD1;
  2233. else if (hdl == DP_IPA_HDL_THIRD)
  2234. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2235. IPA_CLIENT_WLAN1_PROD1;
  2236. } else {
  2237. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) =
  2238. IPA_CLIENT_WLAN1_PROD;
  2239. }
  2240. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2241. qdf_mem_get_dma_addr(soc->osdev,
  2242. &ipa_res->rx_alt_rdy_ring.mem_info);
  2243. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2244. qdf_mem_get_dma_size(soc->osdev,
  2245. &ipa_res->rx_alt_rdy_ring.mem_info);
  2246. /* REO Tail Pointer Address */
  2247. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2248. soc->ipa_uc_rx_rsc_alt.ipa_reo_tp_paddr;
  2249. QDF_IPA_WDI_SETUP_INFO_IS_TXR_RN_DB_PCIE_ADDR(rx) = true;
  2250. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2251. qdf_mem_get_dma_addr(soc->osdev,
  2252. &ipa_res->rx_alt_refill_ring.mem_info);
  2253. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2254. qdf_mem_get_dma_size(soc->osdev,
  2255. &ipa_res->rx_alt_refill_ring.mem_info);
  2256. /* FW Head Pointer Address */
  2257. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2258. soc->ipa_uc_rx_rsc_alt.ipa_rx_refill_buf_hp_paddr;
  2259. QDF_IPA_WDI_SETUP_INFO_IS_EVT_RN_DB_PCIE_ADDR(rx) = false;
  2260. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) =
  2261. soc->rx_pkt_tlv_size + L3_HEADER_PADDING;
  2262. }
  2263. /**
  2264. * dp_ipa_setup_rx_alt_pipe() - Setup 2nd rx pipe for IPA offload
  2265. * @soc: data path soc handle
  2266. * @res: ipa resource pointer
  2267. * @in: pipe in handle
  2268. * @over_gsi: flag for IPA offload over gsi
  2269. * @hdl: ipa registered handle
  2270. *
  2271. * Return: none
  2272. */
  2273. static void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2274. struct dp_ipa_resources *res,
  2275. qdf_ipa_wdi_conn_in_params_t *in,
  2276. bool over_gsi,
  2277. qdf_ipa_wdi_hdl_t hdl)
  2278. {
  2279. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2280. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2281. qdf_ipa_ep_cfg_t *rx_cfg;
  2282. if (!wlan_ipa_is_vlan_enabled())
  2283. return;
  2284. QDF_IPA_WDI_CONN_IN_PARAMS_IS_RX1_USED(in) = true;
  2285. if (qdf_mem_smmu_s1_enabled(soc->osdev)) {
  2286. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT_SMMU(in);
  2287. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2288. dp_ipa_wdi_rx_alt_pipe_smmu_params(soc, res, rx_smmu,
  2289. over_gsi, hdl);
  2290. } else {
  2291. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_ALT(in);
  2292. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx);
  2293. dp_ipa_wdi_rx_alt_pipe_params(soc, res, rx, over_gsi, hdl);
  2294. }
  2295. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2296. /* Update with wds len(96) + 4 if wds support is enabled */
  2297. if (ucfg_ipa_is_wds_enabled())
  2298. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST_VLAN;
  2299. else
  2300. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2301. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2302. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2303. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2304. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2305. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2306. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2307. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2308. }
  2309. /**
  2310. * dp_ipa_set_rx_alt_pipe_db() - Setup 2nd rx pipe doorbell
  2311. * @res: ipa resource pointer
  2312. * @out: pipe out handle
  2313. *
  2314. * Return: none
  2315. */
  2316. static void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2317. qdf_ipa_wdi_conn_out_params_t *out)
  2318. {
  2319. if (!wlan_ipa_is_vlan_enabled())
  2320. return;
  2321. res->rx_alt_ready_doorbell_paddr =
  2322. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_ALT_UC_DB_PA(out);
  2323. dp_debug("Setting DB 0x%x for RX alt pipe",
  2324. res->rx_alt_ready_doorbell_paddr);
  2325. }
  2326. #else
  2327. static inline
  2328. void dp_ipa_setup_rx_alt_pipe(struct dp_soc *soc,
  2329. struct dp_ipa_resources *res,
  2330. qdf_ipa_wdi_conn_in_params_t *in,
  2331. bool over_gsi,
  2332. qdf_ipa_wdi_hdl_t hdl)
  2333. { }
  2334. static inline
  2335. void dp_ipa_set_rx_alt_pipe_db(struct dp_ipa_resources *res,
  2336. qdf_ipa_wdi_conn_out_params_t *out)
  2337. { }
  2338. #endif
  2339. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2340. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2341. void *ipa_wdi_meter_notifier_cb,
  2342. uint32_t ipa_desc_size, void *ipa_priv,
  2343. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2344. uint32_t *rx_pipe_handle, bool is_smmu_enabled,
  2345. qdf_ipa_sys_connect_params_t *sys_in, bool over_gsi,
  2346. qdf_ipa_wdi_hdl_t hdl, qdf_ipa_wdi_hdl_t id,
  2347. void *ipa_ast_notify_cb)
  2348. {
  2349. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2350. struct dp_pdev *pdev =
  2351. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2352. struct dp_ipa_resources *ipa_res;
  2353. qdf_ipa_ep_cfg_t *tx_cfg;
  2354. qdf_ipa_ep_cfg_t *rx_cfg;
  2355. qdf_ipa_wdi_pipe_setup_info_t *tx = NULL;
  2356. qdf_ipa_wdi_pipe_setup_info_t *rx = NULL;
  2357. qdf_ipa_wdi_pipe_setup_info_smmu_t *tx_smmu;
  2358. qdf_ipa_wdi_pipe_setup_info_smmu_t *rx_smmu = NULL;
  2359. qdf_ipa_wdi_conn_in_params_t *pipe_in = NULL;
  2360. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2361. int ret;
  2362. if (!pdev) {
  2363. dp_err("Invalid instance");
  2364. return QDF_STATUS_E_FAILURE;
  2365. }
  2366. ipa_res = &pdev->ipa_resource;
  2367. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2368. return QDF_STATUS_SUCCESS;
  2369. pipe_in = qdf_mem_malloc(sizeof(*pipe_in));
  2370. if (!pipe_in)
  2371. return QDF_STATUS_E_NOMEM;
  2372. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2373. if (is_smmu_enabled)
  2374. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = true;
  2375. else
  2376. QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in) = false;
  2377. dp_setup_mcc_sys_pipes(sys_in, pipe_in);
  2378. /* TX PIPE */
  2379. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2380. tx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_TX_SMMU(pipe_in);
  2381. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(tx_smmu);
  2382. } else {
  2383. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(pipe_in);
  2384. tx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(tx);
  2385. }
  2386. QDF_IPA_EP_CFG_NAT_EN(tx_cfg) = IPA_BYPASS_NAT;
  2387. QDF_IPA_EP_CFG_HDR_LEN(tx_cfg) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2388. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(tx_cfg) = 0;
  2389. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(tx_cfg) = 0;
  2390. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(tx_cfg) = 0;
  2391. QDF_IPA_EP_CFG_MODE(tx_cfg) = IPA_BASIC;
  2392. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(tx_cfg) = true;
  2393. /*
  2394. * Transfer Ring: WBM Ring
  2395. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2396. * Event Ring: TCL ring
  2397. * Event Ring Doorbell PA: TCL Head Pointer Address
  2398. */
  2399. if (is_smmu_enabled)
  2400. dp_ipa_wdi_tx_smmu_params(soc, ipa_res, tx_smmu, over_gsi, id);
  2401. else
  2402. dp_ipa_wdi_tx_params(soc, ipa_res, tx, over_gsi);
  2403. dp_ipa_setup_tx_alt_pipe(soc, ipa_res, pipe_in);
  2404. /* RX PIPE */
  2405. if (QDF_IPA_WDI_CONN_IN_PARAMS_SMMU_ENABLED(pipe_in)) {
  2406. rx_smmu = &QDF_IPA_WDI_CONN_IN_PARAMS_RX_SMMU(pipe_in);
  2407. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_SMMU_EP_CFG(rx_smmu);
  2408. } else {
  2409. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(pipe_in);
  2410. rx_cfg = &QDF_IPA_WDI_SETUP_INFO_EP_CFG(rx);
  2411. }
  2412. QDF_IPA_EP_CFG_NAT_EN(rx_cfg) = IPA_BYPASS_NAT;
  2413. if (ucfg_ipa_is_wds_enabled())
  2414. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN_AST;
  2415. else
  2416. QDF_IPA_EP_CFG_HDR_LEN(rx_cfg) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2417. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE_VALID(rx_cfg) = 1;
  2418. QDF_IPA_EP_CFG_HDR_OFST_PKT_SIZE(rx_cfg) = 0;
  2419. QDF_IPA_EP_CFG_HDR_ADDITIONAL_CONST_LEN(rx_cfg) = 0;
  2420. QDF_IPA_EP_CFG_HDR_OFST_METADATA_VALID(rx_cfg) = 0;
  2421. QDF_IPA_EP_CFG_HDR_METADATA_REG_VALID(rx_cfg) = 1;
  2422. QDF_IPA_EP_CFG_MODE(rx_cfg) = IPA_BASIC;
  2423. QDF_IPA_EP_CFG_HDR_LITTLE_ENDIAN(rx_cfg) = true;
  2424. /*
  2425. * Transfer Ring: REO Ring
  2426. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2427. * Event Ring: FW ring
  2428. * Event Ring Doorbell PA: FW Head Pointer Address
  2429. */
  2430. if (is_smmu_enabled)
  2431. dp_ipa_wdi_rx_smmu_params(soc, ipa_res, rx_smmu, over_gsi, id);
  2432. else
  2433. dp_ipa_wdi_rx_params(soc, ipa_res, rx, over_gsi);
  2434. /* setup 2nd rx pipe */
  2435. dp_ipa_setup_rx_alt_pipe(soc, ipa_res, pipe_in, over_gsi, id);
  2436. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(pipe_in) = ipa_w2i_cb;
  2437. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(pipe_in) = ipa_priv;
  2438. QDF_IPA_WDI_CONN_IN_PARAMS_HANDLE(pipe_in) = hdl;
  2439. dp_ipa_ast_notify_cb(pipe_in, ipa_ast_notify_cb);
  2440. /* Connect WDI IPA PIPEs */
  2441. ret = qdf_ipa_wdi_conn_pipes(pipe_in, &pipe_out);
  2442. if (ret) {
  2443. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2444. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2445. __func__, ret);
  2446. qdf_mem_free(pipe_in);
  2447. return QDF_STATUS_E_FAILURE;
  2448. }
  2449. /* IPA uC Doorbell registers */
  2450. dp_info("Tx DB PA=0x%x, Rx DB PA=0x%x",
  2451. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2452. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2453. dp_ipa_set_pipe_db(ipa_res, &pipe_out);
  2454. dp_ipa_set_rx_alt_pipe_db(ipa_res, &pipe_out);
  2455. ipa_res->is_db_ddr_mapped =
  2456. QDF_IPA_WDI_CONN_OUT_PARAMS_IS_DB_DDR_MAPPED(&pipe_out);
  2457. soc->ipa_first_tx_db_access = true;
  2458. qdf_mem_free(pipe_in);
  2459. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2460. soc->ipa_rx_buf_map_lock_initialized = true;
  2461. return QDF_STATUS_SUCCESS;
  2462. }
  2463. #ifdef IPA_WDI3_VLAN_SUPPORT
  2464. /**
  2465. * dp_ipa_set_rx1_used() - Set rx1 used flag for 2nd rx offload ring
  2466. * @in: pipe in handle
  2467. *
  2468. * Return: none
  2469. */
  2470. static inline
  2471. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2472. {
  2473. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_RX1_USED(in) = true;
  2474. }
  2475. /**
  2476. * dp_ipa_set_v4_vlan_hdr() - Set v4 vlan hdr
  2477. * @in: pipe in handle
  2478. * @hdr: pointer to hdr
  2479. *
  2480. * Return: none
  2481. */
  2482. static inline
  2483. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2484. qdf_ipa_wdi_hdr_info_t *hdr)
  2485. {
  2486. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v4_VLAN]),
  2487. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2488. }
  2489. /**
  2490. * dp_ipa_set_v6_vlan_hdr() - Set v6 vlan hdr
  2491. * @in: pipe in handle
  2492. * @hdr: pointer to hdr
  2493. *
  2494. * Return: none
  2495. */
  2496. static inline
  2497. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2498. qdf_ipa_wdi_hdr_info_t *hdr)
  2499. {
  2500. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(in)[IPA_IP_v6_VLAN]),
  2501. hdr, sizeof(qdf_ipa_wdi_hdr_info_t));
  2502. }
  2503. #else
  2504. static inline
  2505. void dp_ipa_set_rx1_used(qdf_ipa_wdi_reg_intf_in_params_t *in)
  2506. { }
  2507. static inline
  2508. void dp_ipa_set_v4_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2509. qdf_ipa_wdi_hdr_info_t *hdr)
  2510. { }
  2511. static inline
  2512. void dp_ipa_set_v6_vlan_hdr(qdf_ipa_wdi_reg_intf_in_params_t *in,
  2513. qdf_ipa_wdi_hdr_info_t *hdr)
  2514. { }
  2515. #endif
  2516. #ifdef IPA_WDS_EASYMESH_FEATURE
  2517. /**
  2518. * dp_ipa_set_wdi_hdr_type() - Set wdi hdr type for IPA
  2519. * @hdr_info: Header info
  2520. *
  2521. * Return: None
  2522. */
  2523. static inline void
  2524. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2525. {
  2526. if (ucfg_ipa_is_wds_enabled())
  2527. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2528. IPA_HDR_L2_ETHERNET_II_AST;
  2529. else
  2530. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2531. IPA_HDR_L2_ETHERNET_II;
  2532. }
  2533. #else
  2534. static inline void
  2535. dp_ipa_set_wdi_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2536. {
  2537. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2538. }
  2539. #endif
  2540. #ifdef IPA_WDI3_VLAN_SUPPORT
  2541. /**
  2542. * dp_ipa_set_wdi_vlan_hdr_type() - Set wdi vlan hdr type for IPA
  2543. * @hdr_info: Header info
  2544. *
  2545. * Return: None
  2546. */
  2547. static inline void
  2548. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2549. {
  2550. if (ucfg_ipa_is_wds_enabled())
  2551. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2552. IPA_HDR_L2_802_1Q_AST;
  2553. else
  2554. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(hdr_info) =
  2555. IPA_HDR_L2_802_1Q;
  2556. }
  2557. #else
  2558. static inline void
  2559. dp_ipa_set_wdi_vlan_hdr_type(qdf_ipa_wdi_hdr_info_t *hdr_info)
  2560. { }
  2561. #endif
  2562. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2563. qdf_ipa_client_type_t prod_client,
  2564. qdf_ipa_client_type_t cons_client,
  2565. uint8_t session_id, bool is_ipv6_enabled,
  2566. qdf_ipa_wdi_hdl_t hdl)
  2567. {
  2568. qdf_ipa_wdi_reg_intf_in_params_t in;
  2569. qdf_ipa_wdi_hdr_info_t hdr_info;
  2570. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2571. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2572. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr;
  2573. struct dp_ipa_uc_tx_vlan_hdr uc_tx_vlan_hdr_v6;
  2574. int ret = -EINVAL;
  2575. qdf_mem_zero(&in, sizeof(qdf_ipa_wdi_reg_intf_in_params_t));
  2576. /* Need to reset the values to 0 as all the fields are not
  2577. * updated in the Header, Unused fields will be set to 0.
  2578. */
  2579. qdf_mem_zero(&uc_tx_vlan_hdr, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2580. qdf_mem_zero(&uc_tx_vlan_hdr_v6, sizeof(struct dp_ipa_uc_tx_vlan_hdr));
  2581. dp_debug("Add Partial hdr: %s, "QDF_MAC_ADDR_FMT, ifname,
  2582. QDF_MAC_ADDR_REF(mac_addr));
  2583. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2584. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2585. /* IPV4 header */
  2586. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2587. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2588. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2589. dp_ipa_set_wdi_hdr_type(&hdr_info);
  2590. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2591. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2592. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2593. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2594. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2595. QDF_IPA_WDI_REG_INTF_IN_PARAMS_ALT_DST_PIPE(&in) = cons_client;
  2596. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2597. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = WLAN_IPA_META_DATA_MASK;
  2598. QDF_IPA_WDI_REG_INTF_IN_PARAMS_HANDLE(&in) = hdl;
  2599. dp_ipa_setup_iface_session_id(&in, session_id);
  2600. dp_debug("registering for session_id: %u", session_id);
  2601. /* IPV6 header */
  2602. if (is_ipv6_enabled) {
  2603. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2604. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2605. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2606. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2607. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2608. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2609. }
  2610. if (wlan_ipa_is_vlan_enabled()) {
  2611. /* Add vlan specific headers if vlan supporti is enabled */
  2612. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2613. dp_ipa_set_rx1_used(&in);
  2614. qdf_ether_addr_copy(uc_tx_vlan_hdr.eth.h_source, mac_addr);
  2615. /* IPV4 Vlan header */
  2616. uc_tx_vlan_hdr.eth.h_vlan_proto = qdf_htons(ETH_P_8021Q);
  2617. uc_tx_vlan_hdr.eth.h_vlan_encapsulated_proto = qdf_htons(ETH_P_IP);
  2618. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2619. (uint8_t *)&uc_tx_vlan_hdr;
  2620. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) =
  2621. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN;
  2622. dp_ipa_set_wdi_vlan_hdr_type(&hdr_info);
  2623. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2624. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2625. dp_ipa_set_v4_vlan_hdr(&in, &hdr_info);
  2626. /* IPV6 Vlan header */
  2627. if (is_ipv6_enabled) {
  2628. qdf_mem_copy(&uc_tx_vlan_hdr_v6, &uc_tx_vlan_hdr,
  2629. DP_IPA_UC_WLAN_TX_VLAN_HDR_LEN);
  2630. uc_tx_vlan_hdr_v6.eth.h_vlan_proto =
  2631. qdf_htons(ETH_P_8021Q);
  2632. uc_tx_vlan_hdr_v6.eth.h_vlan_encapsulated_proto =
  2633. qdf_htons(ETH_P_IPV6);
  2634. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) =
  2635. (uint8_t *)&uc_tx_vlan_hdr_v6;
  2636. dp_ipa_set_v6_vlan_hdr(&in, &hdr_info);
  2637. }
  2638. }
  2639. ret = qdf_ipa_wdi_reg_intf(&in);
  2640. if (ret) {
  2641. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2642. "%s: ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2643. __func__, ret);
  2644. return QDF_STATUS_E_FAILURE;
  2645. }
  2646. return QDF_STATUS_SUCCESS;
  2647. }
  2648. #else /* !CONFIG_IPA_WDI_UNIFIED_API */
  2649. QDF_STATUS dp_ipa_setup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2650. void *ipa_i2w_cb, void *ipa_w2i_cb,
  2651. void *ipa_wdi_meter_notifier_cb,
  2652. uint32_t ipa_desc_size, void *ipa_priv,
  2653. bool is_rm_enabled, uint32_t *tx_pipe_handle,
  2654. uint32_t *rx_pipe_handle)
  2655. {
  2656. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2657. struct dp_pdev *pdev =
  2658. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2659. struct dp_ipa_resources *ipa_res;
  2660. qdf_ipa_wdi_pipe_setup_info_t *tx;
  2661. qdf_ipa_wdi_pipe_setup_info_t *rx;
  2662. qdf_ipa_wdi_conn_in_params_t pipe_in;
  2663. qdf_ipa_wdi_conn_out_params_t pipe_out;
  2664. struct tcl_data_cmd *tcl_desc_ptr;
  2665. uint8_t *desc_addr;
  2666. uint32_t desc_size;
  2667. int ret;
  2668. if (!pdev) {
  2669. dp_err("Invalid instance");
  2670. return QDF_STATUS_E_FAILURE;
  2671. }
  2672. ipa_res = &pdev->ipa_resource;
  2673. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  2674. return QDF_STATUS_SUCCESS;
  2675. qdf_mem_zero(&tx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2676. qdf_mem_zero(&rx, sizeof(qdf_ipa_wdi_pipe_setup_info_t));
  2677. qdf_mem_zero(&pipe_in, sizeof(pipe_in));
  2678. qdf_mem_zero(&pipe_out, sizeof(pipe_out));
  2679. /* TX PIPE */
  2680. /*
  2681. * Transfer Ring: WBM Ring
  2682. * Transfer Ring Doorbell PA: WBM Tail Pointer Address
  2683. * Event Ring: TCL ring
  2684. * Event Ring Doorbell PA: TCL Head Pointer Address
  2685. */
  2686. tx = &QDF_IPA_WDI_CONN_IN_PARAMS_TX(&pipe_in);
  2687. QDF_IPA_WDI_SETUP_INFO_NAT_EN(tx) = IPA_BYPASS_NAT;
  2688. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(tx) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2689. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(tx) = 0;
  2690. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(tx) = 0;
  2691. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(tx) = 0;
  2692. QDF_IPA_WDI_SETUP_INFO_MODE(tx) = IPA_BASIC;
  2693. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(tx) = true;
  2694. QDF_IPA_WDI_SETUP_INFO_CLIENT(tx) = IPA_CLIENT_WLAN1_CONS;
  2695. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx) =
  2696. ipa_res->tx_comp_ring_base_paddr;
  2697. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx) =
  2698. ipa_res->tx_comp_ring_size;
  2699. /* WBM Tail Pointer Address */
  2700. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx) =
  2701. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr;
  2702. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx) =
  2703. ipa_res->tx_ring_base_paddr;
  2704. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx) = ipa_res->tx_ring_size;
  2705. /* TCL Head Pointer Address */
  2706. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx) =
  2707. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr;
  2708. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx) =
  2709. ipa_res->tx_num_alloc_buffer;
  2710. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(tx) = 0;
  2711. /* Preprogram TCL descriptor */
  2712. desc_addr =
  2713. (uint8_t *)QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx);
  2714. desc_size = sizeof(struct tcl_data_cmd);
  2715. HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, desc_size);
  2716. tcl_desc_ptr = (struct tcl_data_cmd *)
  2717. (QDF_IPA_WDI_SETUP_INFO_DESC_FORMAT_TEMPLATE(tx) + 1);
  2718. tcl_desc_ptr->buf_addr_info.return_buffer_manager =
  2719. HAL_RX_BUF_RBM_SW2_BM;
  2720. tcl_desc_ptr->addrx_en = 1; /* Address X search enable in ASE */
  2721. tcl_desc_ptr->encap_type = HAL_TX_ENCAP_TYPE_ETHERNET;
  2722. tcl_desc_ptr->packet_offset = 2; /* padding for alignment */
  2723. /* RX PIPE */
  2724. /*
  2725. * Transfer Ring: REO Ring
  2726. * Transfer Ring Doorbell PA: REO Tail Pointer Address
  2727. * Event Ring: FW ring
  2728. * Event Ring Doorbell PA: FW Head Pointer Address
  2729. */
  2730. rx = &QDF_IPA_WDI_CONN_IN_PARAMS_RX(&pipe_in);
  2731. QDF_IPA_WDI_SETUP_INFO_NAT_EN(rx) = IPA_BYPASS_NAT;
  2732. QDF_IPA_WDI_SETUP_INFO_HDR_LEN(rx) = DP_IPA_UC_WLAN_RX_HDR_LEN;
  2733. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE_VALID(rx) = 0;
  2734. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_PKT_SIZE(rx) = 0;
  2735. QDF_IPA_WDI_SETUP_INFO_HDR_ADDITIONAL_CONST_LEN(rx) = 0;
  2736. QDF_IPA_WDI_SETUP_INFO_HDR_OFST_METADATA_VALID(rx) = 0;
  2737. QDF_IPA_WDI_SETUP_INFO_HDR_METADATA_REG_VALID(rx) = 1;
  2738. QDF_IPA_WDI_SETUP_INFO_MODE(rx) = IPA_BASIC;
  2739. QDF_IPA_WDI_SETUP_INFO_HDR_LITTLE_ENDIAN(rx) = true;
  2740. QDF_IPA_WDI_SETUP_INFO_CLIENT(rx) = IPA_CLIENT_WLAN1_PROD;
  2741. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx) =
  2742. ipa_res->rx_rdy_ring_base_paddr;
  2743. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx) =
  2744. ipa_res->rx_rdy_ring_size;
  2745. /* REO Tail Pointer Address */
  2746. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx) =
  2747. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr;
  2748. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx) =
  2749. ipa_res->rx_refill_ring_base_paddr;
  2750. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx) =
  2751. ipa_res->rx_refill_ring_size;
  2752. /* FW Head Pointer Address */
  2753. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx) =
  2754. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr;
  2755. QDF_IPA_WDI_SETUP_INFO_PKT_OFFSET(rx) = soc->rx_pkt_tlv_size +
  2756. L3_HEADER_PADDING;
  2757. QDF_IPA_WDI_CONN_IN_PARAMS_NOTIFY(&pipe_in) = ipa_w2i_cb;
  2758. QDF_IPA_WDI_CONN_IN_PARAMS_PRIV(&pipe_in) = ipa_priv;
  2759. /* Connect WDI IPA PIPE */
  2760. ret = qdf_ipa_wdi_conn_pipes(&pipe_in, &pipe_out);
  2761. if (ret) {
  2762. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2763. "%s: ipa_wdi_conn_pipes: IPA pipe setup failed: ret=%d",
  2764. __func__, ret);
  2765. return QDF_STATUS_E_FAILURE;
  2766. }
  2767. /* IPA uC Doorbell registers */
  2768. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2769. "%s: Tx DB PA=0x%x, Rx DB PA=0x%x",
  2770. __func__,
  2771. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out),
  2772. (unsigned int)QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out));
  2773. ipa_res->tx_comp_doorbell_paddr =
  2774. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_PA(&pipe_out);
  2775. ipa_res->tx_comp_doorbell_vaddr =
  2776. QDF_IPA_WDI_CONN_OUT_PARAMS_TX_UC_DB_VA(&pipe_out);
  2777. ipa_res->rx_ready_doorbell_paddr =
  2778. QDF_IPA_WDI_CONN_OUT_PARAMS_RX_UC_DB_PA(&pipe_out);
  2779. soc->ipa_first_tx_db_access = true;
  2780. qdf_spinlock_create(&soc->ipa_rx_buf_map_lock);
  2781. soc->ipa_rx_buf_map_lock_initialized = true;
  2782. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2783. "%s: Tx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2784. __func__,
  2785. "transfer_ring_base_pa",
  2786. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(tx),
  2787. "transfer_ring_size",
  2788. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(tx),
  2789. "transfer_ring_doorbell_pa",
  2790. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(tx),
  2791. "event_ring_base_pa",
  2792. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(tx),
  2793. "event_ring_size",
  2794. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(tx),
  2795. "event_ring_doorbell_pa",
  2796. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(tx),
  2797. "num_pkt_buffers",
  2798. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(tx),
  2799. "tx_comp_doorbell_paddr",
  2800. (void *)ipa_res->tx_comp_doorbell_paddr);
  2801. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2802. "%s: Rx: %s=%pK, %s=%d, %s=%pK, %s=%pK, %s=%d, %s=%pK, %s=%d, %s=%pK",
  2803. __func__,
  2804. "transfer_ring_base_pa",
  2805. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_BASE_PA(rx),
  2806. "transfer_ring_size",
  2807. QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_SIZE(rx),
  2808. "transfer_ring_doorbell_pa",
  2809. (void *)QDF_IPA_WDI_SETUP_INFO_TRANSFER_RING_DOORBELL_PA(rx),
  2810. "event_ring_base_pa",
  2811. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_BASE_PA(rx),
  2812. "event_ring_size",
  2813. QDF_IPA_WDI_SETUP_INFO_EVENT_RING_SIZE(rx),
  2814. "event_ring_doorbell_pa",
  2815. (void *)QDF_IPA_WDI_SETUP_INFO_EVENT_RING_DOORBELL_PA(rx),
  2816. "num_pkt_buffers",
  2817. QDF_IPA_WDI_SETUP_INFO_NUM_PKT_BUFFERS(rx),
  2818. "tx_comp_doorbell_paddr",
  2819. (void *)ipa_res->rx_ready_doorbell_paddr);
  2820. return QDF_STATUS_SUCCESS;
  2821. }
  2822. QDF_STATUS dp_ipa_setup_iface(char *ifname, uint8_t *mac_addr,
  2823. qdf_ipa_client_type_t prod_client,
  2824. qdf_ipa_client_type_t cons_client,
  2825. uint8_t session_id, bool is_ipv6_enabled,
  2826. qdf_ipa_wdi_hdl_t hdl)
  2827. {
  2828. qdf_ipa_wdi_reg_intf_in_params_t in;
  2829. qdf_ipa_wdi_hdr_info_t hdr_info;
  2830. struct dp_ipa_uc_tx_hdr uc_tx_hdr;
  2831. struct dp_ipa_uc_tx_hdr uc_tx_hdr_v6;
  2832. int ret = -EINVAL;
  2833. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
  2834. "%s: Add Partial hdr: %s, "QDF_MAC_ADDR_FMT,
  2835. __func__, ifname, QDF_MAC_ADDR_REF(mac_addr));
  2836. qdf_mem_zero(&hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2837. qdf_ether_addr_copy(uc_tx_hdr.eth.h_source, mac_addr);
  2838. /* IPV4 header */
  2839. uc_tx_hdr.eth.h_proto = qdf_htons(ETH_P_IP);
  2840. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr;
  2841. QDF_IPA_WDI_HDR_INFO_HDR_LEN(&hdr_info) = DP_IPA_UC_WLAN_TX_HDR_LEN;
  2842. QDF_IPA_WDI_HDR_INFO_HDR_TYPE(&hdr_info) = IPA_HDR_L2_ETHERNET_II;
  2843. QDF_IPA_WDI_HDR_INFO_DST_MAC_ADDR_OFFSET(&hdr_info) =
  2844. DP_IPA_UC_WLAN_HDR_DES_MAC_OFFSET;
  2845. QDF_IPA_WDI_REG_INTF_IN_PARAMS_NETDEV_NAME(&in) = ifname;
  2846. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v4]),
  2847. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2848. QDF_IPA_WDI_REG_INTF_IN_PARAMS_IS_META_DATA_VALID(&in) = 1;
  2849. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA(&in) =
  2850. htonl(session_id << 16);
  2851. QDF_IPA_WDI_REG_INTF_IN_PARAMS_META_DATA_MASK(&in) = htonl(0x00FF0000);
  2852. /* IPV6 header */
  2853. if (is_ipv6_enabled) {
  2854. qdf_mem_copy(&uc_tx_hdr_v6, &uc_tx_hdr,
  2855. DP_IPA_UC_WLAN_TX_HDR_LEN);
  2856. uc_tx_hdr_v6.eth.h_proto = qdf_htons(ETH_P_IPV6);
  2857. QDF_IPA_WDI_HDR_INFO_HDR(&hdr_info) = (uint8_t *)&uc_tx_hdr_v6;
  2858. qdf_mem_copy(&(QDF_IPA_WDI_REG_INTF_IN_PARAMS_HDR_INFO(&in)[IPA_IP_v6]),
  2859. &hdr_info, sizeof(qdf_ipa_wdi_hdr_info_t));
  2860. }
  2861. ret = qdf_ipa_wdi_reg_intf(&in);
  2862. if (ret) {
  2863. dp_err("ipa_wdi_reg_intf: register IPA interface failed: ret=%d",
  2864. ret);
  2865. return QDF_STATUS_E_FAILURE;
  2866. }
  2867. return QDF_STATUS_SUCCESS;
  2868. }
  2869. #endif /* CONFIG_IPA_WDI_UNIFIED_API */
  2870. QDF_STATUS dp_ipa_cleanup(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2871. uint32_t tx_pipe_handle, uint32_t rx_pipe_handle,
  2872. qdf_ipa_wdi_hdl_t hdl)
  2873. {
  2874. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2875. QDF_STATUS status = QDF_STATUS_SUCCESS;
  2876. struct dp_pdev *pdev;
  2877. int ret;
  2878. ret = qdf_ipa_wdi_disconn_pipes(hdl);
  2879. if (ret) {
  2880. dp_err("ipa_wdi_disconn_pipes: IPA pipe cleanup failed: ret=%d",
  2881. ret);
  2882. status = QDF_STATUS_E_FAILURE;
  2883. }
  2884. if (soc->ipa_rx_buf_map_lock_initialized) {
  2885. qdf_spinlock_destroy(&soc->ipa_rx_buf_map_lock);
  2886. soc->ipa_rx_buf_map_lock_initialized = false;
  2887. }
  2888. pdev = dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2889. if (qdf_unlikely(!pdev)) {
  2890. dp_err_rl("Invalid pdev for pdev_id %d", pdev_id);
  2891. status = QDF_STATUS_E_FAILURE;
  2892. goto exit;
  2893. }
  2894. dp_ipa_unmap_ring_doorbell_paddr(pdev);
  2895. dp_ipa_unmap_rx_alt_ring_doorbell_paddr(pdev);
  2896. exit:
  2897. return status;
  2898. }
  2899. QDF_STATUS dp_ipa_cleanup_iface(char *ifname, bool is_ipv6_enabled,
  2900. qdf_ipa_wdi_hdl_t hdl)
  2901. {
  2902. int ret;
  2903. ret = qdf_ipa_wdi_dereg_intf(ifname, hdl);
  2904. if (ret) {
  2905. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2906. "%s: ipa_wdi_dereg_intf: IPA pipe deregistration failed: ret=%d",
  2907. __func__, ret);
  2908. return QDF_STATUS_E_FAILURE;
  2909. }
  2910. return QDF_STATUS_SUCCESS;
  2911. }
  2912. #ifdef IPA_SET_RESET_TX_DB_PA
  2913. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res) \
  2914. dp_ipa_set_tx_doorbell_paddr((soc), (ipa_res))
  2915. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res) \
  2916. dp_ipa_reset_tx_doorbell_pa((soc), (ipa_res))
  2917. #else
  2918. #define DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res)
  2919. #define DP_IPA_RESET_TX_DB_PA(soc, ipa_res)
  2920. #endif
  2921. QDF_STATUS dp_ipa_enable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2922. qdf_ipa_wdi_hdl_t hdl)
  2923. {
  2924. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2925. struct dp_pdev *pdev =
  2926. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2927. struct dp_ipa_resources *ipa_res;
  2928. QDF_STATUS result;
  2929. if (!pdev) {
  2930. dp_err("Invalid instance");
  2931. return QDF_STATUS_E_FAILURE;
  2932. }
  2933. ipa_res = &pdev->ipa_resource;
  2934. qdf_atomic_set(&soc->ipa_pipes_enabled, 1);
  2935. DP_IPA_EP_SET_TX_DB_PA(soc, ipa_res);
  2936. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, true,
  2937. __func__, __LINE__);
  2938. result = qdf_ipa_wdi_enable_pipes(hdl);
  2939. if (result) {
  2940. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2941. "%s: Enable WDI PIPE fail, code %d",
  2942. __func__, result);
  2943. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  2944. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  2945. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false,
  2946. __func__, __LINE__);
  2947. return QDF_STATUS_E_FAILURE;
  2948. }
  2949. if (soc->ipa_first_tx_db_access) {
  2950. dp_ipa_tx_comp_ring_init_hp(soc, ipa_res);
  2951. soc->ipa_first_tx_db_access = false;
  2952. }
  2953. return QDF_STATUS_SUCCESS;
  2954. }
  2955. QDF_STATUS dp_ipa_disable_pipes(struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  2956. qdf_ipa_wdi_hdl_t hdl)
  2957. {
  2958. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2959. struct dp_pdev *pdev =
  2960. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  2961. QDF_STATUS result;
  2962. struct dp_ipa_resources *ipa_res;
  2963. if (!pdev) {
  2964. dp_err("Invalid instance");
  2965. return QDF_STATUS_E_FAILURE;
  2966. }
  2967. ipa_res = &pdev->ipa_resource;
  2968. qdf_sleep(TX_COMP_DRAIN_WAIT_TIMEOUT_MS);
  2969. /*
  2970. * Reset the tx completion doorbell address before invoking IPA disable
  2971. * pipes API to ensure that there is no access to IPA tx doorbell
  2972. * address post disable pipes.
  2973. */
  2974. DP_IPA_RESET_TX_DB_PA(soc, ipa_res);
  2975. result = qdf_ipa_wdi_disable_pipes(hdl);
  2976. if (result) {
  2977. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2978. "%s: Disable WDI PIPE fail, code %d",
  2979. __func__, result);
  2980. qdf_assert_always(0);
  2981. return QDF_STATUS_E_FAILURE;
  2982. }
  2983. qdf_atomic_set(&soc->ipa_pipes_enabled, 0);
  2984. dp_ipa_handle_rx_buf_pool_smmu_mapping(soc, pdev, false,
  2985. __func__, __LINE__);
  2986. return result ? QDF_STATUS_E_FAILURE : QDF_STATUS_SUCCESS;
  2987. }
  2988. QDF_STATUS dp_ipa_set_perf_level(int client, uint32_t max_supported_bw_mbps,
  2989. qdf_ipa_wdi_hdl_t hdl)
  2990. {
  2991. qdf_ipa_wdi_perf_profile_t profile;
  2992. QDF_STATUS result;
  2993. profile.client = client;
  2994. profile.max_supported_bw_mbps = max_supported_bw_mbps;
  2995. result = qdf_ipa_wdi_set_perf_profile(hdl, &profile);
  2996. if (result) {
  2997. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2998. "%s: ipa_wdi_set_perf_profile fail, code %d",
  2999. __func__, result);
  3000. return QDF_STATUS_E_FAILURE;
  3001. }
  3002. return QDF_STATUS_SUCCESS;
  3003. }
  3004. /**
  3005. * dp_ipa_intrabss_send() - send IPA RX intra-bss frames
  3006. * @pdev: pdev
  3007. * @vdev: vdev
  3008. * @nbuf: skb
  3009. *
  3010. * Return: nbuf if TX fails and NULL if TX succeeds
  3011. */
  3012. static qdf_nbuf_t dp_ipa_intrabss_send(struct dp_pdev *pdev,
  3013. struct dp_vdev *vdev,
  3014. qdf_nbuf_t nbuf)
  3015. {
  3016. struct dp_peer *vdev_peer;
  3017. uint16_t len;
  3018. vdev_peer = dp_vdev_bss_peer_ref_n_get(pdev->soc, vdev, DP_MOD_ID_IPA);
  3019. if (qdf_unlikely(!vdev_peer))
  3020. return nbuf;
  3021. if (qdf_unlikely(!vdev_peer->txrx_peer)) {
  3022. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3023. return nbuf;
  3024. }
  3025. qdf_mem_zero(nbuf->cb, sizeof(nbuf->cb));
  3026. len = qdf_nbuf_len(nbuf);
  3027. if (dp_tx_send((struct cdp_soc_t *)pdev->soc, vdev->vdev_id, nbuf)) {
  3028. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  3029. rx.intra_bss.fail, 1, len,
  3030. 0);
  3031. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3032. return nbuf;
  3033. }
  3034. DP_PEER_PER_PKT_STATS_INC_PKT(vdev_peer->txrx_peer,
  3035. rx.intra_bss.pkts, 1, len, 0);
  3036. dp_peer_unref_delete(vdev_peer, DP_MOD_ID_IPA);
  3037. return NULL;
  3038. }
  3039. #ifdef IPA_OPT_WIFI_DP
  3040. /**
  3041. * dp_ipa_rx_super_rule_setup()- pass cce super rule params to fw from ipa
  3042. *
  3043. * @soc_hdl: cdp soc
  3044. * @flt_params: filter tuple
  3045. *
  3046. * Return: QDF_STATUS
  3047. */
  3048. QDF_STATUS dp_ipa_rx_super_rule_setup(struct cdp_soc_t *soc_hdl,
  3049. void *flt_params)
  3050. {
  3051. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3052. return htt_h2t_rx_cce_super_rule_setup(soc->htt_handle, flt_params);
  3053. }
  3054. /**
  3055. * dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb()- send cce super rule filter
  3056. * add/remove result to ipa
  3057. *
  3058. * @flt0_rslt : result for filter0 add/remove
  3059. * @flt1_rslt : result for filter1 add/remove
  3060. *
  3061. * Return: void
  3062. */
  3063. void dp_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(int flt0_rslt, int flt1_rslt)
  3064. {
  3065. wlan_ipa_wdi_opt_dpath_notify_flt_add_rem_cb(flt0_rslt, flt1_rslt);
  3066. }
  3067. int dp_ipa_pcie_link_up(struct cdp_soc_t *soc_hdl)
  3068. {
  3069. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3070. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  3071. int response = 0;
  3072. response = hif_prevent_l1((hal_soc->hif_handle));
  3073. return response;
  3074. }
  3075. void dp_ipa_pcie_link_down(struct cdp_soc_t *soc_hdl)
  3076. {
  3077. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3078. struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
  3079. hif_allow_l1(hal_soc->hif_handle);
  3080. }
  3081. /**
  3082. * dp_ipa_wdi_opt_dpath_notify_flt_rlsd()- send cce super rule release
  3083. * notification to ipa
  3084. *
  3085. * @flt0_rslt : result for filter0 release
  3086. * @flt1_rslt : result for filter1 release
  3087. *
  3088. *Return: void
  3089. */
  3090. void dp_ipa_wdi_opt_dpath_notify_flt_rlsd(int flt0_rslt, int flt1_rslt)
  3091. {
  3092. wlan_ipa_wdi_opt_dpath_notify_flt_rlsd(flt0_rslt, flt1_rslt);
  3093. }
  3094. /**
  3095. * dp_ipa_wdi_opt_dpath_notify_flt_rsvd()- send cce super rule reserve
  3096. * notification to ipa
  3097. *
  3098. *@is_success : result of filter reservatiom
  3099. *
  3100. *Return: void
  3101. */
  3102. void dp_ipa_wdi_opt_dpath_notify_flt_rsvd(bool is_success)
  3103. {
  3104. wlan_ipa_wdi_opt_dpath_notify_flt_rsvd(is_success);
  3105. }
  3106. #endif
  3107. #ifdef IPA_WDS_EASYMESH_FEATURE
  3108. /**
  3109. * dp_ipa_peer_check() - Check for peer for given mac
  3110. * @soc: dp soc object
  3111. * @peer_mac_addr: peer mac address
  3112. * @vdev_id: vdev id
  3113. *
  3114. * Return: true if peer is found, else false
  3115. */
  3116. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3117. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3118. {
  3119. struct dp_ast_entry *ast_entry = NULL;
  3120. struct dp_peer *peer = NULL;
  3121. qdf_spin_lock_bh(&soc->ast_lock);
  3122. ast_entry = dp_peer_ast_hash_find_soc(soc, peer_mac_addr);
  3123. if ((!ast_entry) ||
  3124. (ast_entry->delete_in_progress && !ast_entry->callback)) {
  3125. qdf_spin_unlock_bh(&soc->ast_lock);
  3126. return false;
  3127. }
  3128. peer = dp_peer_get_ref_by_id(soc, ast_entry->peer_id,
  3129. DP_MOD_ID_IPA);
  3130. if (!peer) {
  3131. qdf_spin_unlock_bh(&soc->ast_lock);
  3132. return false;
  3133. } else {
  3134. if (peer->vdev->vdev_id == vdev_id) {
  3135. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3136. qdf_spin_unlock_bh(&soc->ast_lock);
  3137. return true;
  3138. }
  3139. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3140. qdf_spin_unlock_bh(&soc->ast_lock);
  3141. return false;
  3142. }
  3143. }
  3144. #else
  3145. static inline bool dp_ipa_peer_check(struct dp_soc *soc,
  3146. uint8_t *peer_mac_addr, uint8_t vdev_id)
  3147. {
  3148. struct cdp_peer_info peer_info = {0};
  3149. struct dp_peer *peer = NULL;
  3150. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac_addr, false,
  3151. CDP_WILD_PEER_TYPE);
  3152. peer = dp_peer_hash_find_wrapper(soc, &peer_info, DP_MOD_ID_IPA);
  3153. if (peer) {
  3154. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3155. return true;
  3156. } else {
  3157. return false;
  3158. }
  3159. }
  3160. #endif
  3161. bool dp_ipa_rx_intrabss_fwd(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3162. qdf_nbuf_t nbuf, bool *fwd_success)
  3163. {
  3164. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3165. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3166. DP_MOD_ID_IPA);
  3167. struct dp_pdev *pdev;
  3168. qdf_nbuf_t nbuf_copy;
  3169. uint8_t da_is_bcmc;
  3170. struct ethhdr *eh;
  3171. bool status = false;
  3172. *fwd_success = false; /* set default as failure */
  3173. /*
  3174. * WDI 3.0 skb->cb[] info from IPA driver
  3175. * skb->cb[0] = vdev_id
  3176. * skb->cb[1].bit#1 = da_is_bcmc
  3177. */
  3178. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3179. if (qdf_unlikely(!vdev))
  3180. return false;
  3181. pdev = vdev->pdev;
  3182. if (qdf_unlikely(!pdev))
  3183. goto out;
  3184. /* no fwd for station mode and just pass up to stack */
  3185. if (vdev->opmode == wlan_op_mode_sta)
  3186. goto out;
  3187. if (da_is_bcmc) {
  3188. nbuf_copy = qdf_nbuf_copy(nbuf);
  3189. if (!nbuf_copy)
  3190. goto out;
  3191. if (dp_ipa_intrabss_send(pdev, vdev, nbuf_copy))
  3192. qdf_nbuf_free(nbuf_copy);
  3193. else
  3194. *fwd_success = true;
  3195. /* return false to pass original pkt up to stack */
  3196. goto out;
  3197. }
  3198. eh = (struct ethhdr *)qdf_nbuf_data(nbuf);
  3199. if (!qdf_mem_cmp(eh->h_dest, vdev->mac_addr.raw, QDF_MAC_ADDR_SIZE))
  3200. goto out;
  3201. if (!dp_ipa_peer_check(soc, eh->h_dest, vdev->vdev_id))
  3202. goto out;
  3203. if (!dp_ipa_peer_check(soc, eh->h_source, vdev->vdev_id))
  3204. goto out;
  3205. /*
  3206. * In intra-bss forwarding scenario, skb is allocated by IPA driver.
  3207. * Need to add skb to internal tracking table to avoid nbuf memory
  3208. * leak check for unallocated skb.
  3209. */
  3210. qdf_net_buf_debug_acquire_skb(nbuf, __FILE__, __LINE__);
  3211. if (dp_ipa_intrabss_send(pdev, vdev, nbuf))
  3212. qdf_nbuf_free(nbuf);
  3213. else
  3214. *fwd_success = true;
  3215. status = true;
  3216. out:
  3217. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3218. return status;
  3219. }
  3220. #ifdef MDM_PLATFORM
  3221. bool dp_ipa_is_mdm_platform(void)
  3222. {
  3223. return true;
  3224. }
  3225. #else
  3226. bool dp_ipa_is_mdm_platform(void)
  3227. {
  3228. return false;
  3229. }
  3230. #endif
  3231. /**
  3232. * dp_ipa_frag_nbuf_linearize() - linearize nbuf for IPA
  3233. * @soc: soc
  3234. * @nbuf: source skb
  3235. *
  3236. * Return: new nbuf if success and otherwise NULL
  3237. */
  3238. static qdf_nbuf_t dp_ipa_frag_nbuf_linearize(struct dp_soc *soc,
  3239. qdf_nbuf_t nbuf)
  3240. {
  3241. uint8_t *src_nbuf_data;
  3242. uint8_t *dst_nbuf_data;
  3243. qdf_nbuf_t dst_nbuf;
  3244. qdf_nbuf_t temp_nbuf = nbuf;
  3245. uint32_t nbuf_len = qdf_nbuf_len(nbuf);
  3246. bool is_nbuf_head = true;
  3247. uint32_t copy_len = 0;
  3248. dst_nbuf = qdf_nbuf_alloc(soc->osdev, RX_DATA_BUFFER_SIZE,
  3249. RX_BUFFER_RESERVATION,
  3250. RX_DATA_BUFFER_ALIGNMENT, FALSE);
  3251. if (!dst_nbuf) {
  3252. dp_err_rl("nbuf allocate fail");
  3253. return NULL;
  3254. }
  3255. if ((nbuf_len + L3_HEADER_PADDING) > RX_DATA_BUFFER_SIZE) {
  3256. qdf_nbuf_free(dst_nbuf);
  3257. dp_err_rl("nbuf is jumbo data");
  3258. return NULL;
  3259. }
  3260. /* prepeare to copy all data into new skb */
  3261. dst_nbuf_data = qdf_nbuf_data(dst_nbuf);
  3262. while (temp_nbuf) {
  3263. src_nbuf_data = qdf_nbuf_data(temp_nbuf);
  3264. /* first head nbuf */
  3265. if (is_nbuf_head) {
  3266. qdf_mem_copy(dst_nbuf_data, src_nbuf_data,
  3267. soc->rx_pkt_tlv_size);
  3268. /* leave extra 2 bytes L3_HEADER_PADDING */
  3269. dst_nbuf_data += (soc->rx_pkt_tlv_size +
  3270. L3_HEADER_PADDING);
  3271. src_nbuf_data += soc->rx_pkt_tlv_size;
  3272. copy_len = qdf_nbuf_headlen(temp_nbuf) -
  3273. soc->rx_pkt_tlv_size;
  3274. temp_nbuf = qdf_nbuf_get_ext_list(temp_nbuf);
  3275. is_nbuf_head = false;
  3276. } else {
  3277. copy_len = qdf_nbuf_len(temp_nbuf);
  3278. temp_nbuf = qdf_nbuf_queue_next(temp_nbuf);
  3279. }
  3280. qdf_mem_copy(dst_nbuf_data, src_nbuf_data, copy_len);
  3281. dst_nbuf_data += copy_len;
  3282. }
  3283. qdf_nbuf_set_len(dst_nbuf, nbuf_len);
  3284. /* copy is done, free original nbuf */
  3285. qdf_nbuf_free(nbuf);
  3286. return dst_nbuf;
  3287. }
  3288. qdf_nbuf_t dp_ipa_handle_rx_reo_reinject(struct dp_soc *soc, qdf_nbuf_t nbuf)
  3289. {
  3290. if (!wlan_cfg_is_ipa_enabled(soc->wlan_cfg_ctx))
  3291. return nbuf;
  3292. /* WLAN IPA is run-time disabled */
  3293. if (!qdf_atomic_read(&soc->ipa_pipes_enabled))
  3294. return nbuf;
  3295. if (!qdf_nbuf_is_frag(nbuf))
  3296. return nbuf;
  3297. /* linearize skb for IPA */
  3298. return dp_ipa_frag_nbuf_linearize(soc, nbuf);
  3299. }
  3300. QDF_STATUS dp_ipa_tx_buf_smmu_mapping(
  3301. struct cdp_soc_t *soc_hdl, uint8_t pdev_id,
  3302. const char *func, uint32_t line)
  3303. {
  3304. QDF_STATUS ret;
  3305. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3306. struct dp_pdev *pdev =
  3307. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3308. if (!pdev) {
  3309. dp_err("%s invalid instance", __func__);
  3310. return QDF_STATUS_E_FAILURE;
  3311. }
  3312. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3313. dp_debug("SMMU S1 disabled");
  3314. return QDF_STATUS_SUCCESS;
  3315. }
  3316. ret = __dp_ipa_tx_buf_smmu_mapping(soc, pdev, true, func, line);
  3317. if (ret)
  3318. return ret;
  3319. ret = dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, true, func, line);
  3320. if (ret)
  3321. __dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line);
  3322. return ret;
  3323. }
  3324. QDF_STATUS dp_ipa_tx_buf_smmu_unmapping(
  3325. struct cdp_soc_t *soc_hdl, uint8_t pdev_id, const char *func,
  3326. uint32_t line)
  3327. {
  3328. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3329. struct dp_pdev *pdev =
  3330. dp_get_pdev_from_soc_pdev_id_wifi3(soc, pdev_id);
  3331. if (!pdev) {
  3332. dp_err("%s invalid instance", __func__);
  3333. return QDF_STATUS_E_FAILURE;
  3334. }
  3335. if (!qdf_mem_smmu_s1_enabled(soc->osdev)) {
  3336. dp_debug("SMMU S1 disabled");
  3337. return QDF_STATUS_SUCCESS;
  3338. }
  3339. if (__dp_ipa_tx_buf_smmu_mapping(soc, pdev, false, func, line) ||
  3340. dp_ipa_tx_alt_buf_smmu_mapping(soc, pdev, false, func, line))
  3341. return QDF_STATUS_E_FAILURE;
  3342. return QDF_STATUS_SUCCESS;
  3343. }
  3344. #ifdef IPA_WDS_EASYMESH_FEATURE
  3345. QDF_STATUS dp_ipa_ast_create(struct cdp_soc_t *soc_hdl,
  3346. qdf_ipa_ast_info_type_t *data)
  3347. {
  3348. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3349. uint8_t *rx_tlv_hdr;
  3350. struct dp_peer *peer;
  3351. struct hal_rx_msdu_metadata msdu_metadata;
  3352. qdf_ipa_ast_info_type_t *ast_info;
  3353. if (!data) {
  3354. dp_err("Data is NULL !!!");
  3355. return QDF_STATUS_E_FAILURE;
  3356. }
  3357. ast_info = data;
  3358. rx_tlv_hdr = qdf_nbuf_data(ast_info->skb);
  3359. peer = dp_peer_get_ref_by_id(soc, ast_info->ta_peer_id,
  3360. DP_MOD_ID_IPA);
  3361. if (!peer) {
  3362. dp_err("Peer is NULL !!!!");
  3363. return QDF_STATUS_E_FAILURE;
  3364. }
  3365. hal_rx_msdu_metadata_get(soc->hal_soc, rx_tlv_hdr, &msdu_metadata);
  3366. dp_rx_ipa_wds_srcport_learn(soc, peer, ast_info->skb, msdu_metadata,
  3367. ast_info->mac_addr_ad4_valid,
  3368. ast_info->first_msdu_in_mpdu_flag);
  3369. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3370. return QDF_STATUS_SUCCESS;
  3371. }
  3372. #endif
  3373. #ifdef QCA_ENHANCED_STATS_SUPPORT
  3374. QDF_STATUS dp_ipa_update_peer_rx_stats(struct cdp_soc_t *soc,
  3375. uint8_t vdev_id, uint8_t *peer_mac,
  3376. qdf_nbuf_t nbuf)
  3377. {
  3378. struct dp_peer *peer = dp_peer_find_hash_find((struct dp_soc *)soc,
  3379. peer_mac, 0, vdev_id,
  3380. DP_MOD_ID_IPA);
  3381. struct dp_txrx_peer *txrx_peer;
  3382. uint8_t da_is_bcmc;
  3383. qdf_ether_header_t *eh;
  3384. if (!peer)
  3385. return QDF_STATUS_E_FAILURE;
  3386. txrx_peer = dp_get_txrx_peer(peer);
  3387. if (!txrx_peer) {
  3388. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3389. return QDF_STATUS_E_FAILURE;
  3390. }
  3391. da_is_bcmc = ((uint8_t)nbuf->cb[1]) & 0x2;
  3392. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3393. if (da_is_bcmc) {
  3394. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.multicast, 1,
  3395. qdf_nbuf_len(nbuf), 0);
  3396. if (QDF_IS_ADDR_BROADCAST(eh->ether_dhost))
  3397. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, rx.bcast,
  3398. 1, qdf_nbuf_len(nbuf), 0);
  3399. }
  3400. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3401. return QDF_STATUS_SUCCESS;
  3402. }
  3403. void
  3404. dp_peer_aggregate_tid_stats(struct dp_peer *peer)
  3405. {
  3406. uint8_t i = 0;
  3407. struct dp_rx_tid *rx_tid = NULL;
  3408. struct cdp_pkt_info rx_total = {0};
  3409. struct dp_txrx_peer *txrx_peer = NULL;
  3410. if (!peer->rx_tid)
  3411. return;
  3412. txrx_peer = dp_get_txrx_peer(peer);
  3413. if (!txrx_peer)
  3414. return;
  3415. for (i = 0; i < DP_MAX_TIDS; i++) {
  3416. rx_tid = &peer->rx_tid[i];
  3417. rx_total.num += rx_tid->rx_msdu_cnt.num;
  3418. rx_total.bytes += rx_tid->rx_msdu_cnt.bytes;
  3419. }
  3420. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.num,
  3421. rx_total.num, 0);
  3422. DP_PEER_PER_PKT_STATS_UPD(txrx_peer, rx.rx_total.bytes,
  3423. rx_total.bytes, 0);
  3424. }
  3425. /**
  3426. * dp_ipa_update_vdev_stats(): update vdev stats
  3427. * @soc: soc handle
  3428. * @srcobj: DP_PEER object
  3429. * @arg: point to vdev stats structure
  3430. *
  3431. * Return: void
  3432. */
  3433. static inline
  3434. void dp_ipa_update_vdev_stats(struct dp_soc *soc, struct dp_peer *srcobj,
  3435. void *arg)
  3436. {
  3437. dp_peer_aggregate_tid_stats(srcobj);
  3438. dp_update_vdev_stats(soc, srcobj, arg);
  3439. }
  3440. /**
  3441. * dp_ipa_aggregate_vdev_stats - Aggregate vdev_stats
  3442. * @vdev: Data path vdev
  3443. * @vdev_stats: buffer to hold vdev stats
  3444. *
  3445. * Return: void
  3446. */
  3447. static inline
  3448. void dp_ipa_aggregate_vdev_stats(struct dp_vdev *vdev,
  3449. struct cdp_vdev_stats *vdev_stats)
  3450. {
  3451. struct dp_soc *soc = NULL;
  3452. if (!vdev || !vdev->pdev)
  3453. return;
  3454. soc = vdev->pdev->soc;
  3455. dp_update_vdev_ingress_stats(vdev);
  3456. qdf_mem_copy(vdev_stats, &vdev->stats, sizeof(vdev->stats));
  3457. dp_vdev_iterate_peer(vdev, dp_ipa_update_vdev_stats, vdev_stats,
  3458. DP_MOD_ID_GENERIC_STATS);
  3459. dp_update_vdev_rate_stats(vdev_stats, &vdev->stats);
  3460. vdev_stats->tx.ucast.num = vdev_stats->tx.tx_ucast_total.num;
  3461. vdev_stats->tx.ucast.bytes = vdev_stats->tx.tx_ucast_total.bytes;
  3462. vdev_stats->tx.tx_success.num = vdev_stats->tx.tx_ucast_success.num;
  3463. vdev_stats->tx.tx_success.bytes = vdev_stats->tx.tx_ucast_success.bytes;
  3464. if (vdev_stats->rx.rx_total.num >= vdev_stats->rx.multicast.num)
  3465. vdev_stats->rx.unicast.num = vdev_stats->rx.rx_total.num -
  3466. vdev_stats->rx.multicast.num;
  3467. if (vdev_stats->rx.rx_total.bytes >= vdev_stats->rx.multicast.bytes)
  3468. vdev_stats->rx.unicast.bytes = vdev_stats->rx.rx_total.bytes -
  3469. vdev_stats->rx.multicast.bytes;
  3470. vdev_stats->rx.to_stack.num = vdev_stats->rx.rx_total.num;
  3471. vdev_stats->rx.to_stack.bytes = vdev_stats->rx.rx_total.bytes;
  3472. }
  3473. /**
  3474. * dp_ipa_aggregate_pdev_stats - Aggregate pdev stats
  3475. * @pdev: Data path pdev
  3476. *
  3477. * Return: void
  3478. */
  3479. static inline
  3480. void dp_ipa_aggregate_pdev_stats(struct dp_pdev *pdev)
  3481. {
  3482. struct dp_vdev *vdev = NULL;
  3483. struct dp_soc *soc;
  3484. struct cdp_vdev_stats *vdev_stats =
  3485. qdf_mem_malloc_atomic(sizeof(struct cdp_vdev_stats));
  3486. if (!vdev_stats) {
  3487. dp_err("%pK: DP alloc failure - unable to get alloc vdev stats",
  3488. pdev->soc);
  3489. return;
  3490. }
  3491. soc = pdev->soc;
  3492. qdf_mem_zero(&pdev->stats.tx, sizeof(pdev->stats.tx));
  3493. qdf_mem_zero(&pdev->stats.rx, sizeof(pdev->stats.rx));
  3494. qdf_mem_zero(&pdev->stats.tx_i, sizeof(pdev->stats.tx_i));
  3495. qdf_mem_zero(&pdev->stats.rx_i, sizeof(pdev->stats.rx_i));
  3496. qdf_spin_lock_bh(&pdev->vdev_list_lock);
  3497. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3498. dp_ipa_aggregate_vdev_stats(vdev, vdev_stats);
  3499. dp_update_pdev_stats(pdev, vdev_stats);
  3500. dp_update_pdev_ingress_stats(pdev, vdev);
  3501. }
  3502. qdf_spin_unlock_bh(&pdev->vdev_list_lock);
  3503. qdf_mem_free(vdev_stats);
  3504. }
  3505. /**
  3506. * dp_ipa_get_peer_stats - Get peer stats
  3507. * @peer: Data path peer
  3508. * @peer_stats: buffer to hold peer stats
  3509. *
  3510. * Return: void
  3511. */
  3512. static
  3513. void dp_ipa_get_peer_stats(struct dp_peer *peer,
  3514. struct cdp_peer_stats *peer_stats)
  3515. {
  3516. dp_peer_aggregate_tid_stats(peer);
  3517. dp_get_peer_stats(peer, peer_stats);
  3518. peer_stats->tx.tx_success.num =
  3519. peer_stats->tx.tx_ucast_success.num;
  3520. peer_stats->tx.tx_success.bytes =
  3521. peer_stats->tx.tx_ucast_success.bytes;
  3522. peer_stats->tx.ucast.num =
  3523. peer_stats->tx.tx_ucast_total.num;
  3524. peer_stats->tx.ucast.bytes =
  3525. peer_stats->tx.tx_ucast_total.bytes;
  3526. if (peer_stats->rx.rx_total.num >= peer_stats->rx.multicast.num)
  3527. peer_stats->rx.unicast.num = peer_stats->rx.rx_total.num -
  3528. peer_stats->rx.multicast.num;
  3529. if (peer_stats->rx.rx_total.bytes >= peer_stats->rx.multicast.bytes)
  3530. peer_stats->rx.unicast.bytes = peer_stats->rx.rx_total.bytes -
  3531. peer_stats->rx.multicast.bytes;
  3532. }
  3533. QDF_STATUS
  3534. dp_ipa_txrx_get_pdev_stats(struct cdp_soc_t *soc, uint8_t pdev_id,
  3535. struct cdp_pdev_stats *pdev_stats)
  3536. {
  3537. struct dp_pdev *pdev =
  3538. dp_get_pdev_from_soc_pdev_id_wifi3((struct dp_soc *)soc,
  3539. pdev_id);
  3540. if (!pdev)
  3541. return QDF_STATUS_E_FAILURE;
  3542. dp_ipa_aggregate_pdev_stats(pdev);
  3543. qdf_mem_copy(pdev_stats, &pdev->stats, sizeof(struct cdp_pdev_stats));
  3544. return QDF_STATUS_SUCCESS;
  3545. }
  3546. int dp_ipa_txrx_get_vdev_stats(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3547. void *buf, bool is_aggregate)
  3548. {
  3549. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3550. struct cdp_vdev_stats *vdev_stats;
  3551. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3552. DP_MOD_ID_IPA);
  3553. if (!vdev)
  3554. return 1;
  3555. vdev_stats = (struct cdp_vdev_stats *)buf;
  3556. dp_ipa_aggregate_vdev_stats(vdev, buf);
  3557. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_IPA);
  3558. return 0;
  3559. }
  3560. QDF_STATUS dp_ipa_txrx_get_peer_stats(struct cdp_soc_t *soc, uint8_t vdev_id,
  3561. uint8_t *peer_mac,
  3562. struct cdp_peer_stats *peer_stats)
  3563. {
  3564. struct dp_peer *peer = NULL;
  3565. struct cdp_peer_info peer_info = { 0 };
  3566. DP_PEER_INFO_PARAMS_INIT(&peer_info, vdev_id, peer_mac, false,
  3567. CDP_WILD_PEER_TYPE);
  3568. peer = dp_peer_hash_find_wrapper((struct dp_soc *)soc, &peer_info,
  3569. DP_MOD_ID_IPA);
  3570. qdf_mem_zero(peer_stats, sizeof(struct cdp_peer_stats));
  3571. if (!peer)
  3572. return QDF_STATUS_E_FAILURE;
  3573. dp_ipa_get_peer_stats(peer, peer_stats);
  3574. dp_peer_unref_delete(peer, DP_MOD_ID_IPA);
  3575. return QDF_STATUS_SUCCESS;
  3576. }
  3577. #endif
  3578. /**
  3579. * dp_ipa_get_wdi_version() - Get WDI version
  3580. * @soc_hdl: data path soc handle
  3581. * @wdi_ver: Out parameter for wdi version
  3582. *
  3583. * Get WDI version based on soc arch
  3584. *
  3585. * Return: None
  3586. */
  3587. void dp_ipa_get_wdi_version(struct cdp_soc_t *soc_hdl, uint8_t *wdi_ver)
  3588. {
  3589. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3590. if (soc->arch_ops.ipa_get_wdi_ver)
  3591. soc->arch_ops.ipa_get_wdi_ver(wdi_ver);
  3592. else
  3593. *wdi_ver = IPA_WDI_3;
  3594. }
  3595. #endif