dp_htt.h 37 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _DP_HTT_H_
  20. #define _DP_HTT_H_
  21. #include <qdf_types.h>
  22. #include <qdf_lock.h>
  23. #include <qdf_nbuf.h>
  24. #include <htc_api.h>
  25. #include "cdp_txrx_cmn_struct.h"
  26. #include "dp_types.h"
  27. #ifdef HTT_LOGGER
  28. #include "dp_htt_logger.h"
  29. #else
  30. struct htt_logger;
  31. static inline
  32. void htt_interface_logging_init(struct htt_logger **htt_logger_handle,
  33. struct cdp_ctrl_objmgr_psoc *ctrl_psoc)
  34. {
  35. }
  36. static inline
  37. void htt_interface_logging_deinit(struct htt_logger *htt_logger_handle)
  38. {
  39. }
  40. static inline
  41. int htt_command_record(struct htt_logger *h, uint8_t msg_type,
  42. uint8_t *msg_data)
  43. {
  44. return 0;
  45. }
  46. static inline
  47. int htt_event_record(struct htt_logger *h, uint8_t msg_type,
  48. uint8_t *msg_data)
  49. {
  50. return 0;
  51. }
  52. static inline
  53. int htt_wbm_event_record(struct htt_logger *h, uint8_t tx_status,
  54. uint8_t *msg_data)
  55. {
  56. return 0;
  57. }
  58. #endif
  59. #define HTT_MGMT_CTRL_TLV_HDR_RESERVERD_LEN 16
  60. #define HTT_TLV_HDR_LEN HTT_T2H_EXT_STATS_CONF_TLV_HDR_SIZE
  61. #define HTT_SHIFT_UPPER_TIMESTAMP 32
  62. #define HTT_MASK_UPPER_TIMESTAMP 0xFFFFFFFF00000000
  63. /**
  64. * htt_htc_pkt_pool_free() - Free HTC packet pool
  65. * @soc: HTT SOC handle
  66. */
  67. void htt_htc_pkt_pool_free(struct htt_soc *soc);
  68. #define HTT_TX_MUTEX_TYPE qdf_spinlock_t
  69. #define HTT_TX_MUTEX_INIT(_mutex) \
  70. qdf_spinlock_create(_mutex)
  71. #define HTT_TX_MUTEX_ACQUIRE(_mutex) \
  72. qdf_spin_lock_bh(_mutex)
  73. #define HTT_TX_MUTEX_RELEASE(_mutex) \
  74. qdf_spin_unlock_bh(_mutex)
  75. #define HTT_TX_MUTEX_DESTROY(_mutex) \
  76. qdf_spinlock_destroy(_mutex)
  77. #define DP_HTT_MAX_SEND_QUEUE_DEPTH 64
  78. #ifndef HTT_MAC_ADDR_LEN
  79. #define HTT_MAC_ADDR_LEN 6
  80. #endif
  81. #define HTT_FRAMECTRL_TYPE_MASK 0x0C
  82. #define HTT_GET_FRAME_CTRL_TYPE(_val) \
  83. (((_val) & HTT_FRAMECTRL_TYPE_MASK) >> 2)
  84. #define FRAME_CTRL_TYPE_MGMT 0x0
  85. #define FRAME_CTRL_TYPE_CTRL 0x1
  86. #define FRAME_CTRL_TYPE_DATA 0x2
  87. #define FRAME_CTRL_TYPE_RESV 0x3
  88. #define HTT_FRAMECTRL_DATATYPE 0x08
  89. #define HTT_PPDU_DESC_MAX_DEPTH 16
  90. #define DP_SCAN_PEER_ID 0xFFFF
  91. #define HTT_RX_DELBA_WIN_SIZE_M 0x0000FC00
  92. #define HTT_RX_DELBA_WIN_SIZE_S 10
  93. #define HTT_RX_DELBA_WIN_SIZE_GET(word) \
  94. (((word) & HTT_RX_DELBA_WIN_SIZE_M) >> HTT_RX_DELBA_WIN_SIZE_S)
  95. /*
  96. * Set the base misclist size to HTT copy engine source ring size
  97. * to guarantee that a packet on the misclist won't be freed while it
  98. * is sitting in the copy engine.
  99. */
  100. #define DP_HTT_HTC_PKT_MISCLIST_SIZE 2048
  101. #define HTT_T2H_MAX_MSG_SIZE 2048
  102. #define HTT_T2H_EXT_STATS_TLV_START_OFFSET 3
  103. /*
  104. * Below offset are based on htt_ppdu_stats_common_tlv
  105. * defined in htt_ppdu_stats.h
  106. */
  107. #define HTT_PPDU_STATS_COMMON_TLV_TLV_HDR_OFFSET 0
  108. #define HTT_PPDU_STATS_COMMON_TLV_PPDU_ID_OFFSET 1
  109. #define HTT_PPDU_STATS_COMMON_TLV_RING_ID_SCH_CMD_ID_OFFSET 2
  110. #define HTT_PPDU_STATS_COMMON_TLV_QTYPE_FRM_TYPE_OFFSET 3
  111. #define HTT_PPDU_STATS_COMMON_TLV_CHAIN_MASK_OFFSET 4
  112. #define HTT_PPDU_STATS_COMMON_TLV_FES_DUR_US_OFFSET 5
  113. #define HTT_PPDU_STATS_COMMON_TLV_SCH_EVAL_START_TSTMP_L32_US_OFFSET 6
  114. #define HTT_PPDU_STATS_COMMON_TLV_SCH_END_TSTMP_US_OFFSET 7
  115. #define HTT_PPDU_STATS_COMMON_TLV_START_TSTMP_L32_US_OFFSET 8
  116. #define HTT_PPDU_STATS_COMMON_TLV_CHAN_MHZ_PHY_MODE_OFFSET 9
  117. #define HTT_PPDU_STATS_COMMON_TLV_CCA_DELTA_TIME_US_OFFSET 10
  118. #define HTT_PPDU_STATS_COMMON_TLV_RXFRM_DELTA_TIME_US_OFFSET 11
  119. #define HTT_PPDU_STATS_COMMON_TLV_TXFRM_DELTA_TIME_US_OFFSET 12
  120. #define HTT_PPDU_STATS_COMMON_TLV_RESV_NUM_UL_BEAM_OFFSET 13
  121. #define HTT_PPDU_STATS_COMMON_TLV_START_TSTMP_U32_US_OFFSET 14
  122. #define HTT_PPDU_STATS_COMMON_TLV_BSSCOLOR_OBSS_PSR_OFFSET 15
  123. /* get index for field in htt_ppdu_stats_common_tlv */
  124. #define HTT_GET_STATS_CMN_INDEX(index) \
  125. HTT_PPDU_STATS_COMMON_TLV_##index##_OFFSET
  126. #define HTT_VDEV_STATS_TLV_SOC_DROP_CNT_OFFSET 1
  127. #define HTT_VDEV_STATS_TLV_HDR_OFFSET 0
  128. #define HTT_VDEV_STATS_TLV_VDEV_ID_OFFSET 1
  129. #define HTT_VDEV_STATS_TLV_RX_BYTE_CNT_OFFSET 2
  130. #define HTT_VDEV_STATS_TLV_RX_PKT_CNT_OFFSET 4
  131. #define HTT_VDEV_STATS_TLV_TX_SUCCESS_BYTE_CNT_OFFSET 6
  132. #define HTT_VDEV_STATS_TLV_TX_SUCCESS_PKT_CNT_OFFSET 8
  133. #define HTT_VDEV_STATS_TLV_TX_RETRY_PKT_CNT_OFFSET 10
  134. #define HTT_VDEV_STATS_TLV_TX_DROP_PKT_CNT_OFFSET 12
  135. #define HTT_VDEV_STATS_TLV_TX_AGE_OUT_PKT_CNT_OFFSET 14
  136. #define HTT_VDEV_STATS_TLV_TX_RETRY_BYTE_CNT_OFFSET 16
  137. #define HTT_VDEV_STATS_TLV_TX_DROP_BYTE_CNT_OFFSET 18
  138. #define HTT_VDEV_STATS_TLV_TX_AGE_OUT_BYTE_CNT_OFFSET 20
  139. #define HTT_VDEV_STATS_TLV_TX_TQM_BYPASS_PKT_CNT_OFFSET 22
  140. #define HTT_VDEV_STATS_TLV_TX_TQM_BYPASS_BYTE_CNT_OFFSET 24
  141. #define HTT_VDEV_STATS_GET_INDEX(index) \
  142. HTT_VDEV_STATS_TLV_##index##_OFFSET
  143. #define HTT_VDEV_STATS_U32_SHIFT 0x20
  144. #define HTT_VDEV_STATS_U32_MASK 0xFFFFFFFF00000000
  145. #define HTT_VDEV_STATS_L32_MASK 0x00000000FFFFFFFF
  146. #define HTT_VDEV_GET_STATS_U64(msg_word) \
  147. (((((uint64_t)(*(((uint32_t *)msg_word) + 1))) & HTT_VDEV_STATS_L32_MASK) << \
  148. HTT_VDEV_STATS_U32_SHIFT) | ((*(uint32_t *)msg_word) & HTT_VDEV_STATS_L32_MASK))
  149. #define HTT_VDEV_GET_STATS_U32(msg_word) \
  150. ((*(uint32_t *)msg_word) & HTT_VDEV_STATS_L32_MASK)
  151. #define MAX_SCHED_STARVE 100000
  152. #define WRAP_DROP_TSF_DELTA 10000
  153. #define MAX_TSF_32 0xFFFFFFFF
  154. #define dp_htt_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_HTT, params)
  155. #define dp_htt_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_HTT, params)
  156. #define dp_htt_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_HTT, params)
  157. #define dp_htt_info(params...) \
  158. __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_HTT, ## params)
  159. #define dp_htt_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_HTT, params)
  160. #define dp_htt_tx_stats_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_DP_HTT_TX_STATS, params)
  161. #define dp_htt_tx_stats_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_DP_HTT_TX_STATS, params)
  162. #define dp_htt_tx_stats_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_DP_HTT_TX_STATS, params)
  163. #define dp_htt_tx_stats_info(params...) \
  164. __QDF_TRACE_FL(QDF_TRACE_LEVEL_INFO_HIGH, QDF_MODULE_ID_DP_HTT_TX_STATS, ## params)
  165. #define dp_htt_tx_stats_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_HTT_TX_STATS, params)
  166. #define RXMON_GLOBAL_EN_SHIFT 28
  167. #ifdef IPA_OPT_WIFI_DP
  168. #define MAX_RESERVE_FAIL_ATTEMPT 5
  169. #endif
  170. /**
  171. * enum dp_full_mon_config - enum to enable/disable full monitor mode
  172. *
  173. * @DP_FULL_MON_DISABLE: Disable full monitor mode
  174. * @DP_FULL_MON_ENABLE: Enable full monitor mode
  175. */
  176. enum dp_full_mon_config {
  177. DP_FULL_MON_DISABLE,
  178. DP_FULL_MON_ENABLE,
  179. };
  180. struct dp_htt_htc_pkt {
  181. void *soc_ctxt;
  182. qdf_dma_addr_t nbuf_paddr;
  183. HTC_PACKET htc_pkt;
  184. };
  185. struct dp_htt_htc_pkt_union {
  186. union {
  187. struct dp_htt_htc_pkt pkt;
  188. struct dp_htt_htc_pkt_union *next;
  189. } u;
  190. };
  191. struct bp_handler {
  192. unsigned long bp_start_tt;
  193. unsigned long bp_last_tt;
  194. unsigned long bp_duration;
  195. unsigned long bp_counter;
  196. };
  197. struct dp_htt_timestamp {
  198. struct bp_handler *umac_path;
  199. struct bp_handler *lmac_path;
  200. };
  201. struct htt_soc {
  202. struct cdp_ctrl_objmgr_psoc *ctrl_psoc;
  203. struct dp_soc *dp_soc;
  204. hal_soc_handle_t hal_soc;
  205. struct dp_htt_timestamp pdevid_tt[MAX_PDEV_CNT];
  206. /* htt_logger handle */
  207. struct htt_logger *htt_logger_handle;
  208. HTC_HANDLE htc_soc;
  209. qdf_device_t osdev;
  210. HTC_ENDPOINT_ID htc_endpoint;
  211. struct dp_htt_htc_pkt_union *htt_htc_pkt_freelist;
  212. struct dp_htt_htc_pkt_union *htt_htc_pkt_misclist;
  213. struct {
  214. u_int8_t major;
  215. u_int8_t minor;
  216. } tgt_ver;
  217. struct {
  218. u_int8_t major;
  219. u_int8_t minor;
  220. } wifi_ip_ver;
  221. struct {
  222. int htc_err_cnt;
  223. int htc_pkt_free;
  224. int skip_count;
  225. int fail_count;
  226. /* rtpm put skip count for ver req msg */
  227. int htt_ver_req_put_skip;
  228. int reserve_fail_cnt;
  229. int abort_count;
  230. } stats;
  231. HTT_TX_MUTEX_TYPE htt_tx_mutex;
  232. };
  233. #ifdef QCA_MONITOR_2_0_SUPPORT
  234. /**
  235. * struct dp_tx_mon_downstream_tlv_config - Enable/Disable TxMon
  236. * downstream TLVs
  237. * @tx_fes_setup: TX_FES_SETUP TLV
  238. * @tx_peer_entry: TX_PEER_ENTRY TLV
  239. * @tx_queue_extension: TX_QUEUE_EXTENSION TLV
  240. * @tx_last_mpdu_end: TX_LAST_MPDU_END TLV
  241. * @tx_last_mpdu_fetched: TX_LAST_MPDU_FETCHED TLV
  242. * @tx_data_sync: TX_DATA_SYNC TLV
  243. * @pcu_ppdu_setup_init: PCU_PPDU_SETUP_INIT TLV
  244. * @fw2s_mon: FW2S_MON TLV
  245. * @tx_loopback_setup: TX_LOOPBACK_SETUP TLV
  246. * @sch_critical_tlv_ref: SCH_CRITICAL_TLV_REF TLV
  247. * @ndp_preamble_done: NDP_PREAMBLE_DONE TLV
  248. * @tx_raw_frame_setup: TX_RAW_OR_NATIVE_FRAME_SETUP TLV
  249. * @txpcu_user_setup: TXPCU_USER_SETUP TLV
  250. * @rxpcu_setup: RXPCU_SETUP TLV
  251. * @rxpcu_setup_complete: RXPCU_SETUP_COMPLETE TLV
  252. * @coex_tx_req: COEX_TX_REQ TLV
  253. * @rxpcu_user_setup: RXPCU_USER_SETUP TLV
  254. * @rxpcu_user_setup_ext: RXPCU_USER_SETUP_EXT TLV
  255. * @wur_data: WUR_DATA TLV
  256. * @tqm_mpdu_global_start: TQM_MPDU_GLOBAL_START
  257. * @tx_fes_setup_complete: TX_FES_SETUP_COMPLETE TLV
  258. * @scheduler_end: SCHEDULER_END TLV
  259. * @sch_wait_instr_tx_path: SCH_WAIT_INSTR_TX_PATH TLV
  260. *
  261. */
  262. struct dp_tx_mon_downstream_tlv_config {
  263. uint32_t tx_fes_setup:1,
  264. tx_peer_entry:1,
  265. tx_queue_extension:1,
  266. tx_last_mpdu_end:1,
  267. tx_last_mpdu_fetched:1,
  268. tx_data_sync:1,
  269. pcu_ppdu_setup_init:1,
  270. fw2s_mon:1,
  271. tx_loopback_setup:1,
  272. sch_critical_tlv_ref:1,
  273. ndp_preamble_done:1,
  274. tx_raw_frame_setup:1,
  275. txpcu_user_setup:1,
  276. rxpcu_setup:1,
  277. rxpcu_setup_complete:1,
  278. coex_tx_req:1,
  279. rxpcu_user_setup:1,
  280. rxpcu_user_setup_ext:1,
  281. wur_data:1,
  282. tqm_mpdu_global_start:1,
  283. tx_fes_setup_complete:1,
  284. scheduler_end:1,
  285. sch_wait_instr_tx_path:1;
  286. };
  287. /**
  288. * struct dp_tx_mon_upstream_tlv_config - Enable/Disable TxMon
  289. * upstream TLVs
  290. * @rx_response_required_info: RX_RESPONSE_REQUIRED_INFO
  291. * TLV
  292. * @response_start_status: RESPONSE_START_STATUS TLV
  293. * @response_end_status: RESPONSE_END_STATUS TLV
  294. * @tx_fes_status_start: TX_FES_STATUS_START TLV
  295. * @tx_fes_status_end: TX_FES_STATUS_END TLV
  296. * @tx_fes_status_start_ppdu: TX_FES_STATUS_START_PPDU TLV
  297. * @tx_fes_status_user_ppdu: TX_FES_STATUS_USER_PPDU TLV
  298. * @tx_fes_status_ack_or_ba: TX_FES_STATUS_ACK_OR_BA TLV
  299. * @tx_fes_status_1k_ba: TX_FES_STATUS_1K_BA TLV
  300. * @tx_fes_status_start_prot: TX_FES_STATUS_START_PROTO TLV
  301. * @tx_fes_status_prot: TX_FES_STATUS_PROTO TLV
  302. * @tx_fes_status_user_response: TX_FES_STATUS_USER_RESPONSE TLV
  303. * @rx_frame_bitmap_ack: RX_FRAME_BITMAP_ACK TLV
  304. * @rx_frame_1k_bitmap_ack: RX_FRAME_1K_BITMAP_ACK TLV
  305. * @coex_tx_status: COEX_TX_STATUS TLV
  306. * @received_response_info: RECEIVED_RESPONSE_INFO TLV
  307. * @received_response_info_p2: RECEIVED_RESPONSE_INFO_PART2 TLV
  308. * @ofdma_trigger_details: OFDMA_TRIGGER_DETAILS
  309. * @received_trigger_info: RECEIVED_TRIGGER_INFO
  310. * @pdg_tx_request: PDG_TX_REQUEST
  311. * @pdg_response: PDG_RESPONSE
  312. * @pdg_trig_response: PDG_TRIG_RESPONSE
  313. * @trigger_response_tx_done: TRIGGER_RESPONSE_TX_DONE
  314. * @prot_tx_end: PROT_TX_END
  315. * @ppdu_tx_end: PPDU_TX_END
  316. * @r2r_status_end: R2R_STATUS_END
  317. * @flush_req: FLUSH_REQ
  318. * @mactx_phy_desc: MACTX_PHY_DESC
  319. * @mactx_user_desc_cmn: MACTX_USER_DESC_COMMON
  320. * @mactx_user_desc_per_usr: MACTX_USER_DESC_PER_USER
  321. * @tqm_acked_1k_mpdu: TQM_ACKED_1K_MPDU
  322. * @tqm_acked_mpdu: TQM_ACKED_MPDU
  323. * @tqm_update_tx_mpdu_count: TQM_UPDATE_TX_MPDU_COUNT
  324. * @phytx_ppdu_header_info_request: PHYTX_PPDU_HEADER_INFO_REQUEST
  325. * @u_sig_eht_su_mu: U_SIG_EHT_SU_MU
  326. * @u_sig_eht_su: U_SIG_EHT_SU
  327. * @u_sig_eht_tb: U_SIG_EHT_TB
  328. * @eht_sig_usr_su: EHT_SIG_USR_SU
  329. * @eht_sig_usr_mu_mimo: EHT_SIG_USR_MU_MIMO
  330. * @eht_sig_usr_ofdma: EHT_SIG_USR_MU_MIMO
  331. * @he_sig_a_su: HE_SIG_A_SU
  332. * @he_sig_a_mu_dl: HE_SIG_A_MU_DL
  333. * @he_sig_a_mu_ul: HE_SIG_A_MU_UL
  334. * @he_sig_b1_mu: HE_SIG_B1_MU
  335. * @he_sig_b2_mu: HE_SIG_B2_MU
  336. * @he_sig_b2_ofdma: HE_SIG_B2_OFDMA
  337. * @vht_sig_b_mu160: VHT_SIG_B_MU160
  338. * @vht_sig_b_mu80: VHT_SIG_B_MU80
  339. * @vht_sig_b_mu40: VHT_SIG_B_MU40
  340. * @vht_sig_b_mu20: VHT_SIG_B_MU20
  341. * @vht_sig_b_su160: VHT_SIG_B_SU160
  342. * @vht_sig_b_su80: VHT_SIG_B_SU80
  343. * @vht_sig_b_su40: VHT_SIG_B_SU40
  344. * @vht_sig_b_su20: VHT_SIG_B_SU20
  345. * @vht_sig_a: VHT_SIG_A
  346. * @ht_sig: HT_SIG
  347. * @l_sig_b: L_SIG_B
  348. * @l_sig_a: L_SIG_A
  349. * @tx_service: TX_SERVICE
  350. * @txpcu_buf_status: TXPCU_BUFFER_STATUS
  351. * @txpcu_user_buf_status: TXPCU_USER_BUFFER_STATUS
  352. * @txdma_stop_request: TXDMA_STOP_REQUEST
  353. * @expected_response: EXPECTED_RESPONSE
  354. * @tx_mpdu_count_transfer_end: TX_MPDU_COUNT_TRANSFER_END
  355. * @rx_trig_info: RX_TRIG_INFO
  356. * @rxpcu_tx_setup_clear: RXPCU_TX_SETUP_CLEAR
  357. * @rx_frame_bitmap_req: RX_FRAME_BITMAP_REQ
  358. * @rx_phy_sleep: RX_PHY_SLEEP
  359. * @txpcu_preamble_done: TXPCU_PREAMBLE_DONE
  360. * @txpcu_phytx_debug32: TXPCU_PHYTX_DEBUG32
  361. * @txpcu_phytx_other_transmit_info32: TXPCU_PHYTX_OTHER_TRANSMIT_INFO32
  362. * @rx_ppdu_noack_report: RX_PPDU_NO_ACK_REPORT
  363. * @rx_ppdu_ack_report: RX_PPDU_ACK_REPORT
  364. * @coex_rx_status: COEX_RX_STATUS
  365. * @rx_start_param: RX_START_PARAM
  366. * @tx_cbf_info: TX_CBF_INFO
  367. * @rxpcu_early_rx_indication: RXPCU_EARLY_RX_INDICATION
  368. * @received_response_user_7_0: RECEIVED_RESPONSE_USER_7_0
  369. * @received_response_user_15_8: RECEIVED_RESPONSE_USER_15_8
  370. * @received_response_user_23_16: RECEIVED_RESPONSE_USER_23_16
  371. * @received_response_user_31_24: RECEIVED_RESPONSE_USER_31_24
  372. * @received_response_user_36_32: RECEIVED_RESPONSE_USER_36_32
  373. * @rx_pm_info: RX_PM_INFO
  374. * @rx_preamble: RX_PREAMBLE
  375. * @others: OTHERS
  376. * @mactx_pre_phy_desc: MACTX_PRE_PHY_DESC
  377. *
  378. */
  379. struct dp_tx_mon_upstream_tlv_config {
  380. uint32_t rx_response_required_info:1,
  381. response_start_status:1,
  382. response_end_status:1,
  383. tx_fes_status_start:1,
  384. tx_fes_status_end:1,
  385. tx_fes_status_start_ppdu:1,
  386. tx_fes_status_user_ppdu:1,
  387. tx_fes_status_ack_or_ba:1,
  388. tx_fes_status_1k_ba:1,
  389. tx_fes_status_start_prot:1,
  390. tx_fes_status_prot:1,
  391. tx_fes_status_user_response:1,
  392. rx_frame_bitmap_ack:1,
  393. rx_frame_1k_bitmap_ack:1,
  394. coex_tx_status:1,
  395. received_response_info:1,
  396. received_response_info_p2:1,
  397. ofdma_trigger_details:1,
  398. received_trigger_info:1,
  399. pdg_tx_request:1,
  400. pdg_response:1,
  401. pdg_trig_response:1,
  402. trigger_response_tx_done:1,
  403. prot_tx_end:1,
  404. ppdu_tx_end:1,
  405. r2r_status_end:1,
  406. flush_req:1,
  407. mactx_phy_desc:1,
  408. mactx_user_desc_cmn:1,
  409. mactx_user_desc_per_usr:1;
  410. uint32_t tqm_acked_1k_mpdu:1,
  411. tqm_acked_mpdu:1,
  412. tqm_update_tx_mpdu_count:1,
  413. phytx_ppdu_header_info_request:1,
  414. u_sig_eht_su_mu:1,
  415. u_sig_eht_su:1,
  416. u_sig_eht_tb:1,
  417. eht_sig_usr_su:1,
  418. eht_sig_usr_mu_mimo:1,
  419. eht_sig_usr_ofdma:1,
  420. he_sig_a_su:1,
  421. he_sig_a_mu_dl:1,
  422. he_sig_a_mu_ul:1,
  423. he_sig_b1_mu:1,
  424. he_sig_b2_mu:1,
  425. he_sig_b2_ofdma:1,
  426. vht_sig_b_mu160:1,
  427. vht_sig_b_mu80:1,
  428. vht_sig_b_mu40:1,
  429. vht_sig_b_mu20:1,
  430. vht_sig_b_su160:1,
  431. vht_sig_b_su80:1,
  432. vht_sig_b_su40:1,
  433. vht_sig_b_su20:1,
  434. vht_sig_a:1,
  435. ht_sig:1,
  436. l_sig_b:1,
  437. l_sig_a:1,
  438. tx_service:1;
  439. uint32_t txpcu_buf_status:1,
  440. txpcu_user_buf_status:1,
  441. txdma_stop_request:1,
  442. expected_response:1,
  443. tx_mpdu_count_transfer_end:1,
  444. rx_trig_info:1,
  445. rxpcu_tx_setup_clear:1,
  446. rx_frame_bitmap_req:1,
  447. rx_phy_sleep:1,
  448. txpcu_preamble_done:1,
  449. txpcu_phytx_debug32:1,
  450. txpcu_phytx_other_transmit_info32:1,
  451. rx_ppdu_noack_report:1,
  452. rx_ppdu_ack_report:1,
  453. coex_rx_status:1,
  454. rx_start_param:1,
  455. tx_cbf_info:1,
  456. rxpcu_early_rx_indication:1,
  457. received_response_user_7_0:1,
  458. received_response_user_15_8:1,
  459. received_response_user_23_16:1,
  460. received_response_user_31_24:1,
  461. received_response_user_36_32:1,
  462. rx_pm_info:1,
  463. rx_preamble:1,
  464. others:1,
  465. mactx_pre_phy_desc:1;
  466. };
  467. /**
  468. * struct dp_tx_mon_wordmask_config - Tx monitor word mask
  469. * @pcu_ppdu_setup_init: PCU_PPDU_SETUP TLV word mask
  470. * @tx_peer_entry: TX_PEER_ENTRY TLV word mask
  471. * @tx_queue_ext: TX_QUEUE_EXTENSION TLV word mask
  472. * @tx_fes_status_end: TX_FES_STATUS_END TLV word mask
  473. * @response_end_status: RESPONSE_END_STATUS TLV word mask
  474. * @tx_fes_status_prot: TX_FES_STATUS_PROT TLV word mask
  475. * @tx_fes_setup: TX_FES_SETUP TLV word mask
  476. * @tx_msdu_start: TX_MSDU_START TLV word mask
  477. * @tx_mpdu_start: TX_MPDU_START TLV word mask
  478. * @rxpcu_user_setup: RXPCU_USER_SETUP TLV word mask
  479. */
  480. struct dp_tx_mon_wordmask_config {
  481. uint32_t pcu_ppdu_setup_init;
  482. uint16_t tx_peer_entry;
  483. uint16_t tx_queue_ext;
  484. uint16_t tx_fes_status_end;
  485. uint16_t response_end_status;
  486. uint16_t tx_fes_status_prot;
  487. uint8_t tx_fes_setup;
  488. uint8_t tx_msdu_start;
  489. uint8_t tx_mpdu_start;
  490. uint8_t rxpcu_user_setup;
  491. };
  492. /**
  493. * struct htt_tx_ring_tlv_filter - Tx ring TLV filter
  494. * enable/disable.
  495. * @dtlvs: enable/disable downstream TLVs
  496. * @utlvs: enable/disable upstream TLVs
  497. * @wmask: enable/disable word mask subscription
  498. * @compaction_enable: word mask compaction enable
  499. * @mgmt_filter: enable/disable mgmt packets
  500. * @data_filter: enable/disable data packets
  501. * @ctrl_filter: enable/disable ctrl packets
  502. * @mgmt_dma_length: configure length for mgmt packet
  503. * @ctrl_dma_length: configure length for ctrl packet
  504. * @data_dma_length: configure length for data packet
  505. * @mgmt_mpdu_end: enable mpdu end tlv for mgmt
  506. * @mgmt_msdu_end: enable msdu end tlv for mgmt
  507. * @mgmt_msdu_start: enable msdu start tlv for mgmt
  508. * @mgmt_mpdu_start: enable mpdu start tlv for mgmt
  509. * @ctrl_mpdu_end: enable mpdu end tlv for ctrl
  510. * @ctrl_msdu_end: enable msdu end tlv for ctrl
  511. * @ctrl_msdu_start: enable msdu start tlv for ctrl
  512. * @ctrl_mpdu_start: enable mpdu start tlv for ctrl
  513. * @data_mpdu_end: enable mpdu end tlv for data
  514. * @data_msdu_end: enable msdu end tlv for data
  515. * @data_msdu_start: enable msdu start tlv for data
  516. * @data_mpdu_start: enable mpdu start tlv for data
  517. * @mgmt_mpdu_log: enable mgmt mpdu level logging
  518. * @ctrl_mpdu_log: enable ctrl mpdu level logging
  519. * @data_mpdu_log: enable data mpdu level logging
  520. * @enable: enable tx monitor
  521. *
  522. * NOTE: Do not change the layout of this structure
  523. */
  524. struct htt_tx_ring_tlv_filter {
  525. struct dp_tx_mon_downstream_tlv_config dtlvs;
  526. struct dp_tx_mon_upstream_tlv_config utlvs;
  527. struct dp_tx_mon_wordmask_config wmask;
  528. uint8_t compaction_enable;
  529. uint16_t mgmt_filter;
  530. uint16_t data_filter;
  531. uint16_t ctrl_filter;
  532. uint16_t mgmt_dma_length:3,
  533. ctrl_dma_length:3,
  534. data_dma_length:3;
  535. uint16_t mgmt_mpdu_end:1,
  536. mgmt_msdu_end:1,
  537. mgmt_msdu_start:1,
  538. mgmt_mpdu_start:1,
  539. ctrl_mpdu_end:1,
  540. ctrl_msdu_end:1,
  541. ctrl_msdu_start:1,
  542. ctrl_mpdu_start:1,
  543. data_mpdu_end:1,
  544. data_msdu_end:1,
  545. data_msdu_start:1,
  546. data_mpdu_start:1;
  547. uint8_t mgmt_mpdu_log:1,
  548. ctrl_mpdu_log:1,
  549. data_mpdu_log:1;
  550. uint8_t enable:1;
  551. };
  552. #endif /* QCA_MONITOR_2_0_SUPPORT */
  553. /**
  554. * struct htt_rx_ring_tlv_filter - Rx ring TLV filter
  555. * enable/disable.
  556. * @mpdu_start: enable/disable MPDU start TLV
  557. * @msdu_start: enable/disable MSDU start TLV
  558. * @packet: enable/disable PACKET TLV
  559. * @msdu_end: enable/disable MSDU end TLV
  560. * @mpdu_end: enable/disable MPDU end TLV
  561. * @packet_header: enable/disable PACKET header TLV
  562. * @attention: enable/disable ATTENTION TLV
  563. * @ppdu_start: enable/disable PPDU start TLV
  564. * @ppdu_end: enable/disable PPDU end TLV
  565. * @ppdu_end_user_stats: enable/disable PPDU user stats TLV
  566. * @ppdu_end_user_stats_ext: enable/disable PPDU user stats ext TLV
  567. * @ppdu_end_status_done: enable/disable PPDU end status done TLV
  568. * @ppdu_start_user_info:
  569. * @header_per_msdu:
  570. * @enable_fp: enable/disable FP packet
  571. * @enable_md: enable/disable MD packet
  572. * @enable_mo: enable/disable MO packet
  573. * @fp_mgmt_filter:
  574. * @mo_mgmt_filter:
  575. * @fp_ctrl_filter:
  576. * @mo_ctrl_filter:
  577. * @fp_data_filter:
  578. * @mo_data_filter:
  579. * @md_data_filter:
  580. * @md_mgmt_filter:
  581. * @md_ctrl_filter:
  582. * @offset_valid: Flag to indicate if below offsets are valid
  583. * @rx_packet_offset: Offset of packet payload
  584. * @rx_header_offset: Offset of rx_header tlv
  585. * @rx_mpdu_end_offset: Offset of rx_mpdu_end tlv
  586. * @rx_mpdu_start_offset: Offset of rx_mpdu_start tlv
  587. * @rx_msdu_end_offset: Offset of rx_msdu_end tlv
  588. * @rx_msdu_start_offset: Offset of rx_msdu_start tlv
  589. * @rx_attn_offset: Offset of rx_attention tlv
  590. * @fp_phy_err: Flag to indicate FP PHY status tlv
  591. * @fp_phy_err_buf_src: source ring selection for the FP PHY ERR status tlv
  592. * @fp_phy_err_buf_dest: dest ring selection for the FP PHY ERR status tlv
  593. * @phy_err_filter_valid:
  594. * @phy_err_mask: select the phy errors defined in phyrx_abort_request_reason
  595. * enums 0 to 31.
  596. * @phy_err_mask_cont: select the fp phy errors defined in
  597. * phyrx_abort_request_reason enums 32 to 63
  598. * @rx_mpdu_start_wmask: word mask for mpdu start tlv
  599. * @rx_mpdu_end_wmask: word mask for mpdu end tlv
  600. * @rx_msdu_end_wmask: word mask for msdu end tlv
  601. * @rx_pkt_tlv_offset: rx pkt tlv offset
  602. * @mgmt_dma_length: configure length for mgmt packet
  603. * @ctrl_dma_length: configure length for ctrl packet
  604. * @data_dma_length: configure length for data packet
  605. * @rx_hdr_length: configure length for rx header tlv
  606. * @mgmt_mpdu_log: enable mgmt mpdu level logging
  607. * @ctrl_mpdu_log: enable ctrl mpdu level logging
  608. * @data_mpdu_log: enable data mpdu level logging
  609. * @enable: enable rx monitor
  610. * @enable_fpmo: enable/disable FPMO packet
  611. * @fpmo_data_filter: FPMO mode data filter
  612. * @fpmo_mgmt_filter: FPMO mode mgmt filter
  613. * @fpmo_ctrl_filter: FPMO mode ctrl filter
  614. * @enable_mon_mac_filter: enable/disable mac based filter on scan radio
  615. *
  616. * NOTE: Do not change the layout of this structure
  617. */
  618. struct htt_rx_ring_tlv_filter {
  619. u_int32_t mpdu_start:1,
  620. msdu_start:1,
  621. packet:1,
  622. msdu_end:1,
  623. mpdu_end:1,
  624. packet_header:1,
  625. attention:1,
  626. ppdu_start:1,
  627. ppdu_end:1,
  628. ppdu_end_user_stats:1,
  629. ppdu_end_user_stats_ext:1,
  630. ppdu_end_status_done:1,
  631. ppdu_start_user_info:1,
  632. header_per_msdu:1,
  633. enable_fp:1,
  634. enable_md:1,
  635. enable_mo:1;
  636. u_int32_t fp_mgmt_filter:16,
  637. mo_mgmt_filter:16;
  638. u_int32_t fp_ctrl_filter:16,
  639. mo_ctrl_filter:16;
  640. u_int32_t fp_data_filter:16,
  641. mo_data_filter:16;
  642. u_int16_t md_data_filter;
  643. u_int16_t md_mgmt_filter;
  644. u_int16_t md_ctrl_filter;
  645. bool offset_valid;
  646. uint16_t rx_packet_offset;
  647. uint16_t rx_header_offset;
  648. uint16_t rx_mpdu_end_offset;
  649. uint16_t rx_mpdu_start_offset;
  650. uint16_t rx_msdu_end_offset;
  651. uint16_t rx_msdu_start_offset;
  652. uint16_t rx_attn_offset;
  653. #ifdef QCA_UNDECODED_METADATA_SUPPORT
  654. u_int32_t fp_phy_err:1,
  655. fp_phy_err_buf_src:2,
  656. fp_phy_err_buf_dest:2,
  657. phy_err_filter_valid:1;
  658. u_int32_t phy_err_mask;
  659. u_int32_t phy_err_mask_cont;
  660. #endif
  661. #if defined(QCA_MONITOR_2_0_SUPPORT) || defined(CONFIG_WORD_BASED_TLV) || \
  662. defined(CONFIG_MON_WORD_BASED_TLV)
  663. uint32_t rx_mpdu_start_wmask;
  664. uint16_t rx_mpdu_end_wmask;
  665. uint32_t rx_msdu_end_wmask;
  666. uint16_t rx_pkt_tlv_offset;
  667. uint16_t mgmt_dma_length:3,
  668. ctrl_dma_length:3,
  669. data_dma_length:3,
  670. rx_hdr_length:3,
  671. mgmt_mpdu_log:1,
  672. ctrl_mpdu_log:1,
  673. data_mpdu_log:1,
  674. enable:1;
  675. u_int16_t enable_fpmo:1;
  676. u_int16_t fpmo_data_filter;
  677. u_int16_t fpmo_mgmt_filter;
  678. u_int16_t fpmo_ctrl_filter;
  679. #endif
  680. bool enable_mon_mac_filter;
  681. };
  682. /**
  683. * struct dp_htt_rx_flow_fst_setup - Rx FST setup message
  684. * @pdev_id: DP Pdev identifier
  685. * @max_entries: Size of Rx FST in number of entries
  686. * @max_search: Number of collisions allowed
  687. * @base_addr_lo: lower 32-bit physical address
  688. * @base_addr_hi: upper 32-bit physical address
  689. * @ip_da_sa_prefix: IPv4 prefix to map to IPv6 address scheme
  690. * @hash_key_len: Rx FST hash key size
  691. * @hash_key: Rx FST Toeplitz hash key
  692. */
  693. struct dp_htt_rx_flow_fst_setup {
  694. uint8_t pdev_id;
  695. uint32_t max_entries;
  696. uint32_t max_search;
  697. uint32_t base_addr_lo;
  698. uint32_t base_addr_hi;
  699. uint32_t ip_da_sa_prefix;
  700. uint32_t hash_key_len;
  701. uint8_t *hash_key;
  702. };
  703. /**
  704. * enum dp_htt_flow_fst_operation - FST related operations allowed
  705. * @DP_HTT_FST_CACHE_OP_NONE: Cache no-op
  706. * @DP_HTT_FST_CACHE_INVALIDATE_ENTRY: Invalidate single cache entry
  707. * @DP_HTT_FST_CACHE_INVALIDATE_FULL: Invalidate entire cache
  708. * @DP_HTT_FST_ENABLE: Bypass FST is enabled
  709. * @DP_HTT_FST_DISABLE: Disable bypass FST
  710. */
  711. enum dp_htt_flow_fst_operation {
  712. DP_HTT_FST_CACHE_OP_NONE,
  713. DP_HTT_FST_CACHE_INVALIDATE_ENTRY,
  714. DP_HTT_FST_CACHE_INVALIDATE_FULL,
  715. DP_HTT_FST_ENABLE,
  716. DP_HTT_FST_DISABLE
  717. };
  718. /**
  719. * struct dp_htt_rx_flow_fst_operation - Rx FST operation message
  720. * @pdev_id: DP Pdev identifier
  721. * @op_code: FST operation to be performed by FW/HW
  722. * @rx_flow: Rx Flow information on which operation is to be performed
  723. */
  724. struct dp_htt_rx_flow_fst_operation {
  725. uint8_t pdev_id;
  726. enum dp_htt_flow_fst_operation op_code;
  727. struct cdp_rx_flow_info *rx_flow;
  728. };
  729. /**
  730. * struct dp_htt_rx_fisa_cfg - Rx fisa config
  731. * @pdev_id: DP Pdev identifier
  732. * @fisa_timeout: fisa aggregation timeout
  733. */
  734. struct dp_htt_rx_fisa_cfg {
  735. uint8_t pdev_id;
  736. uint32_t fisa_timeout;
  737. };
  738. /**
  739. * htt_htc_pkt_alloc() - Allocate HTC packet buffer
  740. * @soc: HTT SOC handle
  741. *
  742. * Return: Pointer to htc packet buffer
  743. */
  744. struct dp_htt_htc_pkt *htt_htc_pkt_alloc(struct htt_soc *soc);
  745. /**
  746. * htt_htc_pkt_free() - Free HTC packet buffer
  747. * @soc: HTT SOC handle
  748. * @pkt: packet to free
  749. */
  750. void
  751. htt_htc_pkt_free(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt);
  752. #define HTT_HTC_PKT_STATUS_SUCCESS \
  753. ((pkt->htc_pkt.Status != QDF_STATUS_E_CANCELED) && \
  754. (pkt->htc_pkt.Status != QDF_STATUS_E_RESOURCES))
  755. #ifdef ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST
  756. static void
  757. htt_htc_misc_pkt_list_add(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt)
  758. {
  759. }
  760. #else /* ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST */
  761. /**
  762. * htt_htc_misc_pkt_list_add() - Add pkt to misc list
  763. * @soc: HTT SOC handle
  764. * @pkt: pkt to be added to list
  765. */
  766. void
  767. htt_htc_misc_pkt_list_add(struct htt_soc *soc, struct dp_htt_htc_pkt *pkt);
  768. #endif /* ENABLE_CE4_COMP_DISABLE_HTT_HTC_MISC_LIST */
  769. /**
  770. * DP_HTT_SEND_HTC_PKT() - Send htt packet from host
  771. * @soc : HTT SOC handle
  772. * @pkt: pkt to be send
  773. * @cmd : command to be recorded in dp htt logger
  774. * @buf : Pointer to buffer needs to be recorded for above cmd
  775. *
  776. * Return: None
  777. */
  778. static inline QDF_STATUS DP_HTT_SEND_HTC_PKT(struct htt_soc *soc,
  779. struct dp_htt_htc_pkt *pkt,
  780. uint8_t cmd, uint8_t *buf)
  781. {
  782. QDF_STATUS status;
  783. htt_command_record(soc->htt_logger_handle, cmd, buf);
  784. status = htc_send_pkt(soc->htc_soc, &pkt->htc_pkt);
  785. if (status == QDF_STATUS_SUCCESS && HTT_HTC_PKT_STATUS_SUCCESS)
  786. htt_htc_misc_pkt_list_add(soc, pkt);
  787. else
  788. soc->stats.fail_count++;
  789. return status;
  790. }
  791. /**
  792. * dp_htt_rx_fisa_config(): Send HTT msg to configure FISA
  793. * @pdev: DP pdev handle
  794. * @fisa_config: Flow entry parameters
  795. *
  796. * Return: Success when HTT message is sent, error on failure
  797. */
  798. QDF_STATUS dp_htt_rx_fisa_config(struct dp_pdev *pdev,
  799. struct dp_htt_rx_fisa_cfg *fisa_config);
  800. #ifdef WLAN_SUPPORT_PPEDS
  801. /**
  802. * struct dp_htt_rxdma_rxole_ppe_config - Rx DMA and RxOLE PPE config
  803. * @override: RxDMA override to override the reo_destinatoin_indication
  804. * @reo_destination_indication: REO destination indication value
  805. * @multi_buffer_msdu_override_en: Override the indicatio for SG
  806. * @intra_bss_override: Rx OLE IntraBSS override
  807. * @decap_raw_override: Rx Decap Raw override
  808. * @decap_nwifi_override: Rx Native override
  809. * @ip_frag_override: IP fragments override
  810. * @reserved: Reserved
  811. */
  812. struct dp_htt_rxdma_rxole_ppe_config {
  813. uint32_t override:1,
  814. reo_destination_indication:5,
  815. multi_buffer_msdu_override_en:1,
  816. intra_bss_override:1,
  817. decap_raw_override:1,
  818. decap_nwifi_override:1,
  819. ip_frag_override:1,
  820. reserved:21;
  821. };
  822. /**
  823. * dp_htt_rxdma_rxole_ppe_cfg_set() - Send RxOLE and RxDMA PPE config
  824. * @soc: Data path SoC handle
  825. * @cfg: RxDMA and RxOLE PPE config
  826. *
  827. * Return: Success when HTT message is sent, error on failure
  828. */
  829. QDF_STATUS
  830. dp_htt_rxdma_rxole_ppe_cfg_set(struct dp_soc *soc,
  831. struct dp_htt_rxdma_rxole_ppe_config *cfg);
  832. #endif /* WLAN_SUPPORT_PPEDS */
  833. /**
  834. * htt_soc_initialize() - SOC level HTT initialization
  835. * @htt_soc: Opaque htt SOC handle
  836. * @ctrl_psoc: Opaque ctrl SOC handle
  837. * @htc_soc: SOC level HTC handle
  838. * @hal_soc_hdl: Opaque HAL SOC handle
  839. * @osdev: QDF device
  840. *
  841. * Return: HTT handle on success; NULL on failure
  842. */
  843. void *
  844. htt_soc_initialize(struct htt_soc *htt_soc,
  845. struct cdp_ctrl_objmgr_psoc *ctrl_psoc,
  846. HTC_HANDLE htc_soc,
  847. hal_soc_handle_t hal_soc_hdl, qdf_device_t osdev);
  848. /**
  849. * dp_htt_h2t_full() - Send full handler (called from HTC)
  850. * @context: Opaque context (HTT SOC handle)
  851. * @pkt: HTC packet
  852. *
  853. * Return: enum htc_send_full_action
  854. */
  855. enum htc_send_full_action
  856. dp_htt_h2t_full(void *context, HTC_PACKET *pkt);
  857. /**
  858. * dp_htt_h2t_send_complete() - H2T completion handler
  859. * @context: Opaque context (HTT SOC handle)
  860. * @htc_pkt: HTC packet
  861. */
  862. void
  863. dp_htt_h2t_send_complete(void *context, HTC_PACKET *htc_pkt);
  864. /**
  865. * dp_htt_hif_t2h_hp_callback() - HIF callback for high priority T2H messages
  866. * @context: Opaque context (HTT SOC handle)
  867. * @nbuf: nbuf containing T2H message
  868. * @pipe_id: HIF pipe ID
  869. *
  870. * Return: QDF_STATUS
  871. *
  872. * TODO: Temporary change to bypass HTC connection for this new HIF pipe, which
  873. * will be used for packet log and other high-priority HTT messages. Proper
  874. * HTC connection to be added later once required FW changes are available
  875. */
  876. QDF_STATUS
  877. dp_htt_hif_t2h_hp_callback(void *context, qdf_nbuf_t nbuf, uint8_t pipe_id);
  878. /**
  879. * htt_soc_attach() - attach DP and HTT SOC
  880. * @soc: DP SOC handle
  881. * @htc_hdl: HTC handle
  882. *
  883. * Return: htt_soc handle on Success, NULL on Failure
  884. */
  885. struct htt_soc *htt_soc_attach(struct dp_soc *soc, HTC_HANDLE htc_hdl);
  886. /**
  887. * htt_set_htc_handle() - set HTC handle
  888. * @htt_hdl: HTT handle/SOC
  889. * @htc_soc: HTC handle
  890. *
  891. * Return: None
  892. */
  893. void htt_set_htc_handle(struct htt_soc *htt_hdl, HTC_HANDLE htc_soc);
  894. /**
  895. * htt_get_htc_handle() - set HTC handle
  896. * @htt_hdl: HTT handle/SOC
  897. *
  898. * Return: HTC_HANDLE
  899. */
  900. HTC_HANDLE htt_get_htc_handle(struct htt_soc *htt_hdl);
  901. /**
  902. * htt_soc_htc_dealloc() - HTC memory de-alloc
  903. * @htt_handle: SOC level HTT handle
  904. *
  905. * Return: None
  906. */
  907. void htt_soc_htc_dealloc(struct htt_soc *htt_handle);
  908. /**
  909. * htt_soc_htc_prealloc() - HTC memory prealloc
  910. * @htt_soc: SOC level HTT handle
  911. *
  912. * Return: QDF_STATUS_SUCCESS on success or
  913. * QDF_STATUS_E_NO_MEM on allocation failure
  914. */
  915. QDF_STATUS htt_soc_htc_prealloc(struct htt_soc *htt_soc);
  916. /**
  917. * htt_soc_detach() - Free SOC level HTT handle
  918. * @htt_hdl: HTT SOC handle
  919. */
  920. void htt_soc_detach(struct htt_soc *htt_hdl);
  921. /**
  922. * htt_srng_setup() - Send SRNG setup message to target
  923. * @htt_soc: HTT SOC handle
  924. * @pdev_id: pdev Id
  925. * @hal_ring_hdl: Opaque HAL SRNG pointer
  926. * @hal_ring_type: SRNG ring type
  927. *
  928. * Return: 0 on success; error code on failure
  929. */
  930. int htt_srng_setup(struct htt_soc *htt_soc, int pdev_id,
  931. hal_ring_handle_t hal_ring_hdl,
  932. int hal_ring_type);
  933. /**
  934. * htt_soc_attach_target() - SOC level HTT setup
  935. * @htt_soc: HTT SOC handle
  936. *
  937. * Return: 0 on success; error code on failure
  938. */
  939. int htt_soc_attach_target(struct htt_soc *htt_soc);
  940. /**
  941. * htt_h2t_rx_ring_cfg() - Send SRNG packet and TLV filter
  942. * config message to target
  943. * @htt_soc: HTT SOC handle
  944. * @pdev_id: PDEV Id
  945. * @hal_ring_hdl: Opaque HAL SRNG pointer
  946. * @hal_ring_type: SRNG ring type
  947. * @ring_buf_size: SRNG buffer size
  948. * @htt_tlv_filter: Rx SRNG TLV and filter setting
  949. *
  950. * Return: 0 on success; error code on failure
  951. */
  952. int htt_h2t_rx_ring_cfg(struct htt_soc *htt_soc, int pdev_id,
  953. hal_ring_handle_t hal_ring_hdl,
  954. int hal_ring_type, int ring_buf_size,
  955. struct htt_rx_ring_tlv_filter *htt_tlv_filter);
  956. /**
  957. * dp_htt_t2h_msg_handler() - Generic Target to host Msg/event handler
  958. * @context: Opaque context (HTT SOC handle)
  959. * @pkt: HTC packet
  960. */
  961. void dp_htt_t2h_msg_handler(void *context, HTC_PACKET *pkt);
  962. /**
  963. * htt_t2h_stats_handler() - target to host stats work handler
  964. * @context: context (dp soc context)
  965. *
  966. * Return: void
  967. */
  968. void htt_t2h_stats_handler(void *context);
  969. /**
  970. * struct htt_stats_context - htt stats information
  971. * @soc: Size of each descriptor in the pool
  972. * @msg: T2H Ext stats message queue
  973. * @msg_len: T2H Ext stats message length
  974. */
  975. struct htt_stats_context {
  976. struct dp_soc *soc;
  977. qdf_nbuf_queue_t msg;
  978. uint32_t msg_len;
  979. };
  980. #ifdef DP_UMAC_HW_RESET_SUPPORT
  981. /**
  982. * struct dp_htt_umac_reset_setup_cmd_params - Params for UMAC reset setup cmd
  983. * @msi_data: MSI data to be used for raising the UMAC reset interrupt
  984. * @shmem_addr_low: Lower 32-bits of shared memory
  985. * @shmem_addr_high: Higher 32-bits of shared memory
  986. */
  987. struct dp_htt_umac_reset_setup_cmd_params {
  988. uint32_t msi_data;
  989. uint32_t shmem_addr_low;
  990. uint32_t shmem_addr_high;
  991. };
  992. /**
  993. * dp_htt_umac_reset_send_setup_cmd(): Send the HTT UMAC reset setup command
  994. * @soc: dp soc object
  995. * @setup_params: parameters required by this command
  996. *
  997. * Return: Success when HTT message is sent, error on failure
  998. */
  999. QDF_STATUS dp_htt_umac_reset_send_setup_cmd(
  1000. struct dp_soc *soc,
  1001. const struct dp_htt_umac_reset_setup_cmd_params *setup_params);
  1002. /**
  1003. * dp_htt_umac_reset_send_start_pre_reset_cmd() - Send the HTT UMAC reset start
  1004. * pre reset command
  1005. * @soc: dp soc object
  1006. * @is_initiator: Indicates whether the target needs to execute the
  1007. * UMAC-recovery in context of the Initiator or Non-Initiator. The value zero
  1008. * indicates this target is Non-Initiator.
  1009. * @is_umac_hang: Indicates whether MLO UMAC recovery executed in context of
  1010. * UMAC hang or Target recovery.
  1011. *
  1012. * Return: Success when HTT message is sent, error on failure
  1013. */
  1014. QDF_STATUS dp_htt_umac_reset_send_start_pre_reset_cmd(
  1015. struct dp_soc *soc, bool is_initiator, bool is_umac_hang);
  1016. #endif
  1017. /**
  1018. * dp_htt_rx_flow_fst_setup() - Send HTT Rx FST setup message to FW
  1019. * @pdev: DP pdev handle
  1020. * @fse_setup_info: FST setup parameters
  1021. *
  1022. * Return: Success when HTT message is sent, error on failure
  1023. */
  1024. QDF_STATUS
  1025. dp_htt_rx_flow_fst_setup(struct dp_pdev *pdev,
  1026. struct dp_htt_rx_flow_fst_setup *fse_setup_info);
  1027. /**
  1028. * dp_htt_rx_flow_fse_operation(): Send HTT Flow Search Entry msg to
  1029. * add/del a flow in HW
  1030. * @pdev: DP pdev handle
  1031. * @fse_op_info: Flow entry parameters
  1032. *
  1033. * Return: Success when HTT message is sent, error on failure
  1034. */
  1035. QDF_STATUS
  1036. dp_htt_rx_flow_fse_operation(struct dp_pdev *pdev,
  1037. struct dp_htt_rx_flow_fst_operation *fse_op_info);
  1038. /**
  1039. * htt_h2t_full_mon_cfg() - Send full monitor configuration msg to FW
  1040. *
  1041. * @htt_soc: HTT Soc handle
  1042. * @pdev_id: Radio id
  1043. * @dp_full_mon_config: enabled/disable configuration
  1044. *
  1045. * Return: Success when HTT message is sent, error on failure
  1046. */
  1047. int htt_h2t_full_mon_cfg(struct htt_soc *htt_soc,
  1048. uint8_t pdev_id,
  1049. enum dp_full_mon_config);
  1050. /**
  1051. * dp_h2t_hw_vdev_stats_config_send: Send HTT command to FW for config
  1052. * of HW vdev stats
  1053. * @dpsoc: Datapath soc handle
  1054. * @pdev_id: INVALID_PDEV_ID for all pdevs or 0,1,2 for individual pdev
  1055. * @enable: flag to specify enable/disable of stats
  1056. * @reset: flag to specify if command is for reset of stats
  1057. * @reset_bitmask: bitmask of vdev_id(s) for reset of HW stats
  1058. *
  1059. * Return: QDF_STATUS
  1060. */
  1061. QDF_STATUS dp_h2t_hw_vdev_stats_config_send(struct dp_soc *dpsoc,
  1062. uint8_t pdev_id, bool enable,
  1063. bool reset, uint64_t reset_bitmask);
  1064. static inline enum htt_srng_ring_id
  1065. dp_htt_get_mon_htt_ring_id(struct dp_soc *soc,
  1066. enum hal_ring_type hal_ring_type)
  1067. {
  1068. enum htt_srng_ring_id htt_srng_id = 0;
  1069. if (wlan_cfg_get_txmon_hw_support(soc->wlan_cfg_ctx)) {
  1070. switch (hal_ring_type) {
  1071. case RXDMA_MONITOR_BUF:
  1072. htt_srng_id = HTT_RX_MON_HOST2MON_BUF_RING;
  1073. break;
  1074. case RXDMA_MONITOR_DST:
  1075. htt_srng_id = HTT_RX_MON_MON2HOST_DEST_RING;
  1076. break;
  1077. default:
  1078. dp_err("Invalid ring type %d ", hal_ring_type);
  1079. break;
  1080. }
  1081. } else {
  1082. switch (hal_ring_type) {
  1083. case RXDMA_MONITOR_BUF:
  1084. htt_srng_id = HTT_RXDMA_MONITOR_BUF_RING;
  1085. break;
  1086. case RXDMA_MONITOR_DST:
  1087. htt_srng_id = HTT_RXDMA_MONITOR_DEST_RING;
  1088. break;
  1089. default:
  1090. dp_err("Invalid ring type %d ", hal_ring_type);
  1091. break;
  1092. }
  1093. }
  1094. return htt_srng_id;
  1095. }
  1096. #ifdef IPA_OPT_WIFI_DP
  1097. /**
  1098. * htt_h2t_rx_cce_super_rule_setup() - htt message to set cce super rules
  1099. *
  1100. * @htt_soc: HTT Soc handle
  1101. * @flt_params: Filter tuple
  1102. *
  1103. * Return: QDF_STATUS
  1104. */
  1105. QDF_STATUS htt_h2t_rx_cce_super_rule_setup(struct htt_soc *htt_soc,
  1106. void *flt_params);
  1107. #endif
  1108. #ifdef QCA_SUPPORT_PRIMARY_LINK_MIGRATE
  1109. /**
  1110. * struct dp_peer_info - Primary Peer information
  1111. * @primary_peer_id: Primary peer id
  1112. * @chip_id: Chip id of primary peer
  1113. */
  1114. struct dp_peer_info {
  1115. uint16_t primary_peer_id;
  1116. uint8_t chip_id;
  1117. };
  1118. /**
  1119. * dp_h2t_ptqm_migration_msg_send() - Send H2T PTQM message to FW
  1120. * @dp_soc: DP SOC handle
  1121. * @vdev_id: Vdev id of primary peer
  1122. * @pdev_id: Pdev id of primary peer
  1123. * @chip_id: Chip id of primary peer
  1124. * @peer_id: Peer id of primary peer
  1125. * @ml_peer_id: Peer id of MLD peer
  1126. * @src_info: source info for DS
  1127. * @status: success or failure status of PTQM migration
  1128. *
  1129. * Return: Success when HTT message is sent, error on failure
  1130. */
  1131. QDF_STATUS
  1132. dp_h2t_ptqm_migration_msg_send(struct dp_soc *dp_soc, uint16_t vdev_id,
  1133. uint8_t pdev_id,
  1134. uint8_t chip_id, uint16_t peer_id,
  1135. uint16_t ml_peer_id, uint16_t src_info,
  1136. QDF_STATUS status);
  1137. /**
  1138. * dp_htt_reo_migration() - Reo migration API
  1139. * @soc: DP SOC handle
  1140. * @peer_id: Peer id of primary peer
  1141. * @ml_peer_id: Peer id of MLD peer
  1142. * @vdev_id: Vdev id of primary peer
  1143. * @pdev_id: Pdev id of primary peer
  1144. * @chip_id: Chip id of primary peer
  1145. *
  1146. * Return: Success if migration completes, error on failure
  1147. */
  1148. QDF_STATUS dp_htt_reo_migration(struct dp_soc *soc, uint16_t peer_id,
  1149. uint16_t ml_peer_id, uint16_t vdev_id,
  1150. uint8_t pdev_id, uint8_t chip_id);
  1151. #endif
  1152. #endif /* _DP_HTT_H_ */