dp_be.c 84 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139
  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include "dp_rings.h"
  22. #include <dp_htt.h>
  23. #include "dp_be.h"
  24. #include "dp_be_tx.h"
  25. #include "dp_be_rx.h"
  26. #ifdef WIFI_MONITOR_SUPPORT
  27. #if !defined(DISABLE_MON_CONFIG) && defined(QCA_MONITOR_2_0_SUPPORT)
  28. #include "dp_mon_2.0.h"
  29. #endif
  30. #include "dp_mon.h"
  31. #endif
  32. #include <hal_be_api.h>
  33. #ifdef WLAN_SUPPORT_PPEDS
  34. #include "be/dp_ppeds.h"
  35. #include <ppe_vp_public.h>
  36. #include <ppe_drv_sc.h>
  37. #endif
  38. /* Generic AST entry aging timer value */
  39. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  40. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  41. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  42. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  43. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  44. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  45. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  46. #ifdef QCA_WIFI_KIWI_V2
  47. {3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
  48. {4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
  49. #else
  50. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  51. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  52. #endif
  53. };
  54. #else
  55. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  56. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  57. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  58. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  59. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  60. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  61. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  62. };
  63. #endif
  64. #ifdef WLAN_SUPPORT_PPEDS
  65. static struct cdp_ppeds_txrx_ops dp_ops_ppeds_be = {
  66. .ppeds_entry_attach = dp_ppeds_attach_vdev_be,
  67. .ppeds_entry_detach = dp_ppeds_detach_vdev_be,
  68. .ppeds_set_int_pri2tid = dp_ppeds_set_int_pri2tid_be,
  69. .ppeds_update_int_pri2tid = dp_ppeds_update_int_pri2tid_be,
  70. .ppeds_entry_dump = dp_ppeds_dump_ppe_vp_tbl_be,
  71. .ppeds_enable_pri2tid = dp_ppeds_vdev_enable_pri2tid_be,
  72. .ppeds_vp_setup_recovery = dp_ppeds_vp_setup_on_fw_recovery,
  73. .ppeds_stats_sync = dp_ppeds_stats_sync_be,
  74. };
  75. static void dp_ppeds_rings_status(struct dp_soc *soc)
  76. {
  77. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  78. dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE);
  79. dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL);
  80. dp_print_ring_stat_from_hal(soc, &be_soc->ppeds_wbm_release_ring,
  81. WBM2SW_RELEASE);
  82. }
  83. static void dp_ppeds_inuse_desc(struct dp_soc *soc)
  84. {
  85. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  86. DP_PRINT_STATS("PPE-DS Tx Descriptors in Use = %u num_free %u",
  87. be_soc->ppeds_tx_desc.num_allocated,
  88. be_soc->ppeds_tx_desc.num_free);
  89. }
  90. #endif
  91. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  92. {
  93. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  94. dp_soc_cfg_attach(soc);
  95. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  96. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  97. /* this is used only when dmac mode is enabled */
  98. soc->num_rx_refill_buf_rings = 1;
  99. soc->wlan_cfg_ctx->notify_frame_support =
  100. DP_MARK_NOTIFY_FRAME_SUPPORT;
  101. }
  102. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  103. {
  104. switch (context_type) {
  105. case DP_CONTEXT_TYPE_SOC:
  106. return sizeof(struct dp_soc_be);
  107. case DP_CONTEXT_TYPE_PDEV:
  108. return sizeof(struct dp_pdev_be);
  109. case DP_CONTEXT_TYPE_VDEV:
  110. return sizeof(struct dp_vdev_be);
  111. case DP_CONTEXT_TYPE_PEER:
  112. return sizeof(struct dp_peer_be);
  113. default:
  114. return 0;
  115. }
  116. }
  117. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  118. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  119. /**
  120. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  121. * per wbm2sw ring
  122. *
  123. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  124. *
  125. * Return: None
  126. */
  127. #ifdef IPA_OPT_WIFI_DP
  128. static inline
  129. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  130. {
  131. cc_cfg->wbm2sw6_cc_en = 1;
  132. cc_cfg->wbm2sw5_cc_en = 0;
  133. cc_cfg->wbm2sw4_cc_en = 1;
  134. cc_cfg->wbm2sw3_cc_en = 1;
  135. cc_cfg->wbm2sw2_cc_en = 1;
  136. /* disable wbm2sw1 hw cc as it's for FW */
  137. cc_cfg->wbm2sw1_cc_en = 0;
  138. cc_cfg->wbm2sw0_cc_en = 1;
  139. cc_cfg->wbm2fw_cc_en = 0;
  140. }
  141. #else
  142. static inline
  143. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  144. {
  145. cc_cfg->wbm2sw6_cc_en = 1;
  146. cc_cfg->wbm2sw5_cc_en = 1;
  147. cc_cfg->wbm2sw4_cc_en = 1;
  148. cc_cfg->wbm2sw3_cc_en = 1;
  149. cc_cfg->wbm2sw2_cc_en = 1;
  150. /* disable wbm2sw1 hw cc as it's for FW */
  151. cc_cfg->wbm2sw1_cc_en = 0;
  152. cc_cfg->wbm2sw0_cc_en = 1;
  153. cc_cfg->wbm2fw_cc_en = 0;
  154. }
  155. #endif
  156. #else
  157. static inline
  158. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  159. {
  160. cc_cfg->wbm2sw6_cc_en = 1;
  161. cc_cfg->wbm2sw5_cc_en = 1;
  162. cc_cfg->wbm2sw4_cc_en = 1;
  163. cc_cfg->wbm2sw3_cc_en = 1;
  164. cc_cfg->wbm2sw2_cc_en = 1;
  165. cc_cfg->wbm2sw1_cc_en = 1;
  166. cc_cfg->wbm2sw0_cc_en = 1;
  167. cc_cfg->wbm2fw_cc_en = 0;
  168. }
  169. #endif
  170. #if defined(WLAN_SUPPORT_RX_FISA)
  171. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  172. {
  173. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  174. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  175. /* get CMEM for cookie conversion */
  176. if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
  177. dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
  178. return QDF_STATUS_E_NOMEM;
  179. }
  180. soc->fst_cmem_size = DP_CMEM_FST_SIZE;
  181. soc->fst_cmem_base = soc->cmem_base +
  182. (soc->cmem_total_size - soc->cmem_avail_size);
  183. soc->cmem_avail_size -= soc->fst_cmem_size;
  184. dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
  185. soc->fst_cmem_base, soc->fst_cmem_size);
  186. return QDF_STATUS_SUCCESS;
  187. }
  188. #else /* !WLAN_SUPPORT_RX_FISA */
  189. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  190. {
  191. return QDF_STATUS_SUCCESS;
  192. }
  193. #endif
  194. /**
  195. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  196. * conversion register
  197. *
  198. * @soc: SOC handle
  199. * @is_4k_align: page address 4k aligned
  200. *
  201. * Return: None
  202. */
  203. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  204. bool is_4k_align)
  205. {
  206. struct hal_hw_cc_config cc_cfg = { 0 };
  207. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  208. if (soc->cdp_soc.ol_ops->get_con_mode &&
  209. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  210. return;
  211. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  212. dp_info("INI skip HW CC register setting");
  213. return;
  214. }
  215. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  216. cc_cfg.cc_global_en = true;
  217. cc_cfg.page_4k_align = is_4k_align;
  218. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  219. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  220. /* 36th bit should be 1 then HW know this is CMEM address */
  221. cc_cfg.lut_base_addr_39_32 = 0x10;
  222. cc_cfg.error_path_cookie_conv_en = true;
  223. cc_cfg.release_path_cookie_conv_en = true;
  224. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  225. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  226. }
  227. /**
  228. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  229. * @hal_soc_hdl: HAL SOC handle
  230. * @offset: CMEM address
  231. * @value: value to write
  232. *
  233. * Return: None.
  234. */
  235. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  236. uint32_t offset,
  237. uint32_t value)
  238. {
  239. hal_cmem_write(hal_soc_hdl, offset, value);
  240. }
  241. /**
  242. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  243. * HW cookie conversion
  244. *
  245. * @soc: SOC handle
  246. *
  247. * Return: 0 in case of success, else error value
  248. */
  249. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  250. {
  251. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  252. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  253. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  254. /* get CMEM for cookie conversion */
  255. if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
  256. dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
  257. return QDF_STATUS_E_RESOURCES;
  258. }
  259. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  260. DP_CC_MEM_OFFSET_IN_CMEM);
  261. soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
  262. dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
  263. be_soc->cc_cmem_base, soc->cmem_avail_size);
  264. return QDF_STATUS_SUCCESS;
  265. }
  266. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  267. uint8_t for_feature)
  268. {
  269. QDF_STATUS status = QDF_STATUS_E_NOMEM;
  270. switch (for_feature) {
  271. case COOKIE_CONVERSION:
  272. status = dp_hw_cc_cmem_addr_init(soc);
  273. break;
  274. case FISA_FST:
  275. status = dp_fisa_fst_cmem_addr_init(soc);
  276. break;
  277. default:
  278. dp_err("Invalid CMEM request");
  279. }
  280. return status;
  281. }
  282. #else
  283. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  284. bool is_4k_align) {}
  285. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  286. uint32_t offset,
  287. uint32_t value)
  288. { }
  289. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  290. {
  291. return QDF_STATUS_SUCCESS;
  292. }
  293. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  294. uint8_t for_feature)
  295. {
  296. return QDF_STATUS_SUCCESS;
  297. }
  298. #endif
  299. QDF_STATUS
  300. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  301. struct dp_hw_cookie_conversion_t *cc_ctx,
  302. uint32_t num_descs,
  303. enum dp_desc_type desc_type,
  304. uint8_t desc_pool_id)
  305. {
  306. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  307. uint32_t num_spt_pages, i = 0;
  308. struct dp_spt_page_desc *spt_desc;
  309. struct qdf_mem_dma_page_t *dma_page;
  310. uint8_t chip_id;
  311. /* estimate how many SPT DDR pages needed */
  312. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  313. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  314. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  315. dp_info("num_spt_pages needed %d", num_spt_pages);
  316. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  317. &cc_ctx->page_pool, qdf_page_size,
  318. num_spt_pages, 0, false);
  319. if (!cc_ctx->page_pool.dma_pages) {
  320. dp_err("spt ddr pages allocation failed");
  321. return QDF_STATUS_E_RESOURCES;
  322. }
  323. cc_ctx->page_desc_base = qdf_mem_malloc(
  324. num_spt_pages * sizeof(struct dp_spt_page_desc));
  325. if (!cc_ctx->page_desc_base) {
  326. dp_err("spt page descs allocation failed");
  327. goto fail_0;
  328. }
  329. chip_id = dp_mlo_get_chip_id(soc);
  330. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  331. desc_type);
  332. /* initial page desc */
  333. spt_desc = cc_ctx->page_desc_base;
  334. dma_page = cc_ctx->page_pool.dma_pages;
  335. while (i < num_spt_pages) {
  336. /* check if page address 4K aligned */
  337. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  338. dp_err("non-4k aligned pages addr %pK",
  339. (void *)dma_page[i].page_p_addr);
  340. goto fail_1;
  341. }
  342. spt_desc[i].page_v_addr =
  343. dma_page[i].page_v_addr_start;
  344. spt_desc[i].page_p_addr =
  345. dma_page[i].page_p_addr;
  346. i++;
  347. }
  348. cc_ctx->total_page_num = num_spt_pages;
  349. qdf_spinlock_create(&cc_ctx->cc_lock);
  350. return QDF_STATUS_SUCCESS;
  351. fail_1:
  352. qdf_mem_free(cc_ctx->page_desc_base);
  353. fail_0:
  354. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  355. &cc_ctx->page_pool, 0, false);
  356. return QDF_STATUS_E_FAILURE;
  357. }
  358. QDF_STATUS
  359. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  360. struct dp_hw_cookie_conversion_t *cc_ctx)
  361. {
  362. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  363. qdf_mem_free(cc_ctx->page_desc_base);
  364. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  365. &cc_ctx->page_pool, 0, false);
  366. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  367. return QDF_STATUS_SUCCESS;
  368. }
  369. QDF_STATUS
  370. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  371. struct dp_hw_cookie_conversion_t *cc_ctx)
  372. {
  373. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  374. uint32_t i = 0;
  375. struct dp_spt_page_desc *spt_desc;
  376. uint32_t ppt_index;
  377. uint32_t ppt_id_start;
  378. if (!cc_ctx->total_page_num) {
  379. dp_err("total page num is 0");
  380. return QDF_STATUS_E_INVAL;
  381. }
  382. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  383. spt_desc = cc_ctx->page_desc_base;
  384. while (i < cc_ctx->total_page_num) {
  385. /* write page PA to CMEM */
  386. dp_hw_cc_cmem_write(soc->hal_soc,
  387. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  388. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  389. (spt_desc[i].page_p_addr >>
  390. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  391. ppt_index = ppt_id_start + i;
  392. if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
  393. qdf_assert_always(0);
  394. spt_desc[i].ppt_index = ppt_index;
  395. be_soc->page_desc_base[ppt_index].page_v_addr =
  396. spt_desc[i].page_v_addr;
  397. i++;
  398. }
  399. return QDF_STATUS_SUCCESS;
  400. }
  401. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  402. QDF_STATUS
  403. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  404. struct dp_hw_cookie_conversion_t *cc_ctx)
  405. {
  406. uint32_t ppt_index;
  407. struct dp_spt_page_desc *spt_desc;
  408. int i = 0;
  409. spt_desc = cc_ctx->page_desc_base;
  410. while (i < cc_ctx->total_page_num) {
  411. ppt_index = spt_desc[i].ppt_index;
  412. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  413. i++;
  414. }
  415. return QDF_STATUS_SUCCESS;
  416. }
  417. #else
  418. QDF_STATUS
  419. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  420. struct dp_hw_cookie_conversion_t *cc_ctx)
  421. {
  422. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  423. uint32_t ppt_index;
  424. struct dp_spt_page_desc *spt_desc;
  425. int i = 0;
  426. spt_desc = cc_ctx->page_desc_base;
  427. while (i < cc_ctx->total_page_num) {
  428. /* reset PA in CMEM to NULL */
  429. dp_hw_cc_cmem_write(soc->hal_soc,
  430. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  431. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  432. 0);
  433. ppt_index = spt_desc[i].ppt_index;
  434. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  435. i++;
  436. }
  437. return QDF_STATUS_SUCCESS;
  438. }
  439. #endif
  440. #ifdef WLAN_SUPPORT_PPEDS
  441. static QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  442. {
  443. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  444. int target_type = hal_get_target_type(soc->hal_soc);
  445. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  446. /*
  447. * Check if PPE DS is enabled and wlan soc supports it.
  448. */
  449. if (!wlan_cfg_get_dp_soc_ppeds_enable(soc->wlan_cfg_ctx) ||
  450. !dp_ppeds_target_supported(target_type))
  451. return QDF_STATUS_SUCCESS;
  452. if (dp_ppeds_attach_soc_be(be_soc) != QDF_STATUS_SUCCESS)
  453. return QDF_STATUS_SUCCESS;
  454. cdp_ops->ppeds_ops = &dp_ops_ppeds_be;
  455. return QDF_STATUS_SUCCESS;
  456. }
  457. static QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  458. {
  459. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  460. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  461. if (!be_soc->ppeds_handle)
  462. return QDF_STATUS_E_FAILURE;
  463. dp_ppeds_detach_soc_be(be_soc);
  464. cdp_ops->ppeds_ops = NULL;
  465. return QDF_STATUS_SUCCESS;
  466. }
  467. static QDF_STATUS dp_peer_ppeds_default_route_be(struct dp_soc *soc,
  468. struct dp_peer_be *be_peer,
  469. uint8_t vdev_id,
  470. uint16_t src_info)
  471. {
  472. uint16_t service_code;
  473. uint8_t priority_valid;
  474. uint8_t use_ppe_ds = PEER_ROUTING_USE_PPE;
  475. uint8_t peer_routing_enabled = PEER_ROUTING_ENABLED;
  476. QDF_STATUS status = QDF_STATUS_SUCCESS;
  477. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  478. struct dp_vdev_be *be_vdev;
  479. be_vdev = dp_get_be_vdev_from_dp_vdev(be_peer->peer.vdev);
  480. /*
  481. * Program service code bypass to avoid L2 new mac address
  482. * learning exception when fdb learning is disabled.
  483. */
  484. service_code = PPE_DRV_SC_SPF_BYPASS;
  485. priority_valid = be_peer->priority_valid;
  486. /*
  487. * if FST is enabled then let flow rule take the decision of
  488. * routing the pkt to DS or host
  489. */
  490. if (wlan_cfg_is_rx_flow_tag_enabled(cfg))
  491. use_ppe_ds = 0;
  492. if (soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing) {
  493. status =
  494. soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing
  495. (soc->ctrl_psoc,
  496. be_peer->peer.mac_addr.raw,
  497. service_code, priority_valid,
  498. src_info, vdev_id, use_ppe_ds,
  499. peer_routing_enabled);
  500. if (status != QDF_STATUS_SUCCESS) {
  501. dp_err("vdev_id: %d, PPE peer routing mac:"
  502. QDF_MAC_ADDR_FMT, vdev_id,
  503. QDF_MAC_ADDR_REF(be_peer->peer.mac_addr.raw));
  504. return QDF_STATUS_E_FAILURE;
  505. }
  506. }
  507. return QDF_STATUS_SUCCESS;
  508. }
  509. #ifdef WLAN_FEATURE_11BE_MLO
  510. QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
  511. struct dp_peer *peer,
  512. struct dp_vdev_be *be_vdev,
  513. void *args)
  514. {
  515. struct dp_peer *mld_peer;
  516. struct dp_soc *mld_soc;
  517. struct dp_soc_be *be_soc;
  518. struct cdp_soc_t *cdp_soc;
  519. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  520. struct cdp_ds_vp_params vp_params = {0};
  521. struct dp_ppe_vp_profile *ppe_vp_profile = (struct dp_ppe_vp_profile *)args;
  522. uint16_t src_info = ppe_vp_profile->vp_num;
  523. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  524. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  525. if (!be_peer) {
  526. dp_err("BE peer is null");
  527. return QDF_STATUS_E_NULL_VALUE;
  528. }
  529. if (IS_DP_LEGACY_PEER(peer)) {
  530. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  531. vdev_id, src_info);
  532. } else if (IS_MLO_DP_MLD_PEER(peer)) {
  533. int i;
  534. struct dp_peer *link_peer = NULL;
  535. struct dp_mld_link_peers link_peers_info;
  536. /* get link peers with reference */
  537. dp_get_link_peers_ref_from_mld_peer(soc, peer, &link_peers_info,
  538. DP_MOD_ID_DS);
  539. for (i = 0; i < link_peers_info.num_links; i++) {
  540. link_peer = link_peers_info.link_peers[i];
  541. be_peer = dp_get_be_peer_from_dp_peer(link_peer);
  542. if (!be_peer) {
  543. dp_err("BE peer is null");
  544. continue;
  545. }
  546. be_vdev = dp_get_be_vdev_from_dp_vdev(link_peer->vdev);
  547. if (!be_vdev) {
  548. dp_err("BE vap is null for peer id %d ",
  549. link_peer->peer_id);
  550. continue;
  551. }
  552. vdev_id = be_vdev->vdev.vdev_id;
  553. soc = link_peer->vdev->pdev->soc;
  554. qdf_status = dp_peer_ppeds_default_route_be(soc,
  555. be_peer,
  556. vdev_id,
  557. src_info);
  558. }
  559. dp_release_link_peers_ref(&link_peers_info, DP_MOD_ID_DS);
  560. } else {
  561. mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer);
  562. if (!mld_peer)
  563. return qdf_status;
  564. /*
  565. * In case of MLO link peer,
  566. * Fetch the VP profile from the mld vdev.
  567. */
  568. be_vdev = dp_get_be_vdev_from_dp_vdev(mld_peer->vdev);
  569. if (!be_vdev) {
  570. dp_err("BE vap is null");
  571. return QDF_STATUS_E_NULL_VALUE;
  572. }
  573. /*
  574. * Extract the VP profile from the vap
  575. * in case of MLO peer, we have to get the profile from
  576. * the MLD vdev's osif handle and not the link peer.
  577. */
  578. mld_soc = mld_peer->vdev->pdev->soc;
  579. cdp_soc = &mld_soc->cdp_soc;
  580. if (!cdp_soc->ol_ops->get_ppeds_profile_info_for_vap) {
  581. dp_err("%pK: Register PPEDS profile info API before use\n", cdp_soc);
  582. return QDF_STATUS_E_NULL_VALUE;
  583. }
  584. qdf_status = cdp_soc->ol_ops->get_ppeds_profile_info_for_vap(mld_soc->ctrl_psoc,
  585. mld_peer->vdev->vdev_id,
  586. &vp_params);
  587. if (qdf_status == QDF_STATUS_E_NULL_VALUE) {
  588. dp_err("%pK: Failed to get ppeds profile for mld soc\n", mld_soc);
  589. return qdf_status;
  590. }
  591. /*
  592. * Check if PPE DS routing is enabled on
  593. * the associated vap.
  594. */
  595. if (vp_params.ppe_vp_type != PPE_VP_USER_TYPE_DS)
  596. return qdf_status;
  597. be_soc = dp_get_be_soc_from_dp_soc(mld_soc);
  598. ppe_vp_profile = &be_soc->ppe_vp_profile[vp_params.ppe_vp_profile_idx];
  599. src_info = ppe_vp_profile->vp_num;
  600. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  601. vdev_id, src_info);
  602. }
  603. return qdf_status;
  604. }
  605. #else
  606. static QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
  607. struct dp_peer *peer,
  608. struct dp_vdev_be *be_vdev
  609. void *args)
  610. {
  611. struct dp_ppe_vp_profile *vp_profile = (struct dp_ppe_vp_profile *)args;
  612. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  613. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  614. if (!be_peer) {
  615. dp_err("BE peer is null");
  616. return QDF_STATUS_E_NULL_VALUE;
  617. }
  618. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  619. be_vdev->vdev.vdev_id,
  620. vp_profile->vp_num);
  621. return qdf_status;
  622. }
  623. #endif
  624. #else
  625. static QDF_STATUS dp_ppeds_init_soc_be(struct dp_soc *soc)
  626. {
  627. return QDF_STATUS_SUCCESS;
  628. }
  629. static QDF_STATUS dp_ppeds_deinit_soc_be(struct dp_soc *soc)
  630. {
  631. return QDF_STATUS_SUCCESS;
  632. }
  633. static inline QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  634. {
  635. return QDF_STATUS_SUCCESS;
  636. }
  637. static inline QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  638. {
  639. return QDF_STATUS_SUCCESS;
  640. }
  641. QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc, struct dp_peer *peer,
  642. struct dp_vdev_be *be_vdev,
  643. void *args)
  644. {
  645. return QDF_STATUS_SUCCESS;
  646. }
  647. static inline void dp_ppeds_stop_soc_be(struct dp_soc *soc)
  648. {
  649. }
  650. #endif /* WLAN_SUPPORT_PPEDS */
  651. void dp_reo_shared_qaddr_detach(struct dp_soc *soc)
  652. {
  653. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  654. REO_QUEUE_REF_ML_TABLE_SIZE,
  655. soc->reo_qref.mlo_reo_qref_table_vaddr,
  656. soc->reo_qref.mlo_reo_qref_table_paddr, 0);
  657. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  658. REO_QUEUE_REF_NON_ML_TABLE_SIZE,
  659. soc->reo_qref.non_mlo_reo_qref_table_vaddr,
  660. soc->reo_qref.non_mlo_reo_qref_table_paddr, 0);
  661. }
  662. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  663. {
  664. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  665. int i = 0;
  666. dp_soc_ppeds_detach_be(soc);
  667. dp_reo_shared_qaddr_detach(soc);
  668. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  669. dp_hw_cookie_conversion_detach(be_soc,
  670. &be_soc->tx_cc_ctx[i]);
  671. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  672. dp_hw_cookie_conversion_detach(be_soc,
  673. &be_soc->rx_cc_ctx[i]);
  674. qdf_mem_free(be_soc->page_desc_base);
  675. be_soc->page_desc_base = NULL;
  676. return QDF_STATUS_SUCCESS;
  677. }
  678. #ifdef QCA_SUPPORT_DP_GLOBAL_CTX
  679. static void dp_set_rx_fst_be(struct dp_rx_fst *fst)
  680. {
  681. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  682. if (dp_global)
  683. dp_global->fst_ctx = fst;
  684. }
  685. static struct dp_rx_fst *dp_get_rx_fst_be(void)
  686. {
  687. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  688. if (dp_global)
  689. return dp_global->fst_ctx;
  690. return NULL;
  691. }
  692. static uint32_t dp_rx_fst_release_ref_be(void)
  693. {
  694. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  695. uint32_t rx_fst_ref_cnt;
  696. if (dp_global) {
  697. rx_fst_ref_cnt = qdf_atomic_read(&dp_global->rx_fst_ref_cnt);
  698. qdf_atomic_dec(&dp_global->rx_fst_ref_cnt);
  699. return rx_fst_ref_cnt;
  700. }
  701. return 1;
  702. }
  703. static void dp_rx_fst_get_ref_be(void)
  704. {
  705. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  706. if (dp_global)
  707. qdf_atomic_inc(&dp_global->rx_fst_ref_cnt);
  708. }
  709. #else
  710. static void dp_set_rx_fst_be(struct dp_rx_fst *fst)
  711. {
  712. }
  713. static struct dp_rx_fst *dp_get_rx_fst_be(void)
  714. {
  715. return NULL;
  716. }
  717. static uint32_t dp_rx_fst_release_ref_be(void)
  718. {
  719. return 1;
  720. }
  721. static void dp_rx_fst_get_ref_be(void)
  722. {
  723. }
  724. #endif
  725. #ifdef WLAN_MLO_MULTI_CHIP
  726. #ifdef WLAN_MCAST_MLO
  727. static inline void
  728. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  729. {
  730. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  731. be_vdev->mcast_primary = false;
  732. be_vdev->seq_num = 0;
  733. hal_tx_mcast_mlo_reinject_routing_set(
  734. soc->hal_soc,
  735. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  736. if (vdev->opmode == wlan_op_mode_ap) {
  737. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  738. vdev->vdev_id,
  739. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  740. }
  741. }
  742. static inline void
  743. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  744. {
  745. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  746. be_vdev->seq_num = 0;
  747. be_vdev->mcast_primary = false;
  748. vdev->mlo_vdev = false;
  749. }
  750. #else
  751. static inline void
  752. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  753. {
  754. }
  755. static inline void
  756. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  757. {
  758. }
  759. #endif
  760. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  761. {
  762. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  763. qdf_mem_set(be_vdev->partner_vdev_list,
  764. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  765. CDP_INVALID_VDEV_ID);
  766. }
  767. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  768. struct cdp_lro_hash_config *lro_hash)
  769. {
  770. dp_mlo_get_rx_hash_key(soc, lro_hash);
  771. }
  772. #else
  773. static inline void
  774. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  775. {
  776. }
  777. static inline void
  778. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  779. {
  780. }
  781. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  782. {
  783. }
  784. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  785. struct cdp_lro_hash_config *lro_hash)
  786. {
  787. dp_get_rx_hash_key_bytes(lro_hash);
  788. }
  789. #endif
  790. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  791. struct cdp_soc_attach_params *params)
  792. {
  793. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  794. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  795. uint32_t max_tx_rx_desc_num, num_spt_pages;
  796. uint32_t num_entries;
  797. int i = 0;
  798. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  799. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS +
  800. WLAN_CFG_NUM_PPEDS_TX_DESC_MAX * MAX_PPE_TXDESC_POOLS;
  801. /* estimate how many SPT DDR pages needed */
  802. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  803. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  804. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  805. be_soc->page_desc_base = qdf_mem_malloc(
  806. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  807. if (!be_soc->page_desc_base) {
  808. dp_err("spt page descs allocation failed");
  809. return QDF_STATUS_E_NOMEM;
  810. }
  811. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  812. qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
  813. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  814. goto fail;
  815. dp_soc_mlo_fill_params(soc, params);
  816. qdf_status = dp_soc_ppeds_attach_be(soc);
  817. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  818. goto fail;
  819. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  820. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  821. qdf_status =
  822. dp_hw_cookie_conversion_attach(be_soc,
  823. &be_soc->tx_cc_ctx[i],
  824. num_entries,
  825. DP_TX_DESC_TYPE, i);
  826. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  827. goto fail;
  828. }
  829. qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
  830. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  831. goto fail;
  832. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  833. num_entries =
  834. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  835. qdf_status =
  836. dp_hw_cookie_conversion_attach(be_soc,
  837. &be_soc->rx_cc_ctx[i],
  838. num_entries,
  839. DP_RX_DESC_BUF_TYPE, i);
  840. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  841. goto fail;
  842. }
  843. return qdf_status;
  844. fail:
  845. dp_soc_detach_be(soc);
  846. return qdf_status;
  847. }
  848. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  849. {
  850. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  851. int i = 0;
  852. qdf_atomic_set(&soc->cmn_init_done, 0);
  853. dp_ppeds_stop_soc_be(soc);
  854. dp_tx_deinit_bank_profiles(be_soc);
  855. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  856. dp_hw_cookie_conversion_deinit(be_soc,
  857. &be_soc->tx_cc_ctx[i]);
  858. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  859. dp_hw_cookie_conversion_deinit(be_soc,
  860. &be_soc->rx_cc_ctx[i]);
  861. dp_ppeds_deinit_soc_be(soc);
  862. return QDF_STATUS_SUCCESS;
  863. }
  864. static QDF_STATUS dp_soc_deinit_be_wrapper(struct dp_soc *soc)
  865. {
  866. QDF_STATUS qdf_status;
  867. qdf_status = dp_soc_deinit_be(soc);
  868. if (QDF_IS_STATUS_ERROR(qdf_status))
  869. return qdf_status;
  870. dp_soc_deinit(soc);
  871. return QDF_STATUS_SUCCESS;
  872. }
  873. static void *dp_soc_init_be(struct dp_soc *soc, HTC_HANDLE htc_handle,
  874. struct hif_opaque_softc *hif_handle)
  875. {
  876. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  877. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  878. int i = 0;
  879. void *ret_addr;
  880. wlan_minidump_log(soc, sizeof(*soc), soc->ctrl_psoc,
  881. WLAN_MD_DP_SOC, "dp_soc");
  882. soc->hif_handle = hif_handle;
  883. soc->hal_soc = hif_get_hal_handle(soc->hif_handle);
  884. if (!soc->hal_soc)
  885. return NULL;
  886. dp_ppeds_init_soc_be(soc);
  887. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  888. qdf_status =
  889. dp_hw_cookie_conversion_init(be_soc,
  890. &be_soc->tx_cc_ctx[i]);
  891. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  892. goto fail;
  893. }
  894. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  895. qdf_status =
  896. dp_hw_cookie_conversion_init(be_soc,
  897. &be_soc->rx_cc_ctx[i]);
  898. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  899. goto fail;
  900. }
  901. /* route vdev_id mismatch notification via FW completion */
  902. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  903. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  904. qdf_status = dp_tx_init_bank_profiles(be_soc);
  905. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  906. goto fail;
  907. /* write WBM/REO cookie conversion CFG register */
  908. dp_cc_reg_cfg_init(soc, true);
  909. ret_addr = dp_soc_init(soc, htc_handle, hif_handle);
  910. if (!ret_addr)
  911. goto fail;
  912. return ret_addr;
  913. fail:
  914. dp_soc_deinit_be(soc);
  915. return NULL;
  916. }
  917. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  918. struct cdp_pdev_attach_params *params)
  919. {
  920. dp_pdev_mlo_fill_params(pdev, params);
  921. return QDF_STATUS_SUCCESS;
  922. }
  923. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  924. {
  925. dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
  926. return QDF_STATUS_SUCCESS;
  927. }
  928. #ifdef INTRA_BSS_FWD_OFFLOAD
  929. static
  930. void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable)
  931. {
  932. soc->cdp_soc.ol_ops->vdev_set_intra_bss(soc->ctrl_psoc, vdev_id,
  933. enable);
  934. }
  935. #else
  936. static
  937. void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable)
  938. {
  939. }
  940. #endif
  941. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  942. {
  943. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  944. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  945. struct dp_pdev *pdev = vdev->pdev;
  946. if (vdev->opmode == wlan_op_mode_monitor)
  947. return QDF_STATUS_SUCCESS;
  948. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  949. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  950. vdev->bank_id = be_vdev->bank_id;
  951. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  952. QDF_BUG(0);
  953. return QDF_STATUS_E_FAULT;
  954. }
  955. if (vdev->opmode == wlan_op_mode_sta) {
  956. if (soc->cdp_soc.ol_ops->set_mec_timer)
  957. soc->cdp_soc.ol_ops->set_mec_timer(
  958. soc->ctrl_psoc,
  959. vdev->vdev_id,
  960. DP_AST_AGING_TIMER_DEFAULT_MS);
  961. if (pdev->isolation)
  962. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  963. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  964. else
  965. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  966. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  967. } else if (vdev->ap_bridge_enabled) {
  968. dp_vdev_set_intra_bss(soc, vdev->vdev_id, true);
  969. }
  970. dp_mlo_mcast_init(soc, vdev);
  971. dp_mlo_init_ptnr_list(vdev);
  972. return QDF_STATUS_SUCCESS;
  973. }
  974. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  975. {
  976. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  977. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  978. if (vdev->opmode == wlan_op_mode_monitor)
  979. return QDF_STATUS_SUCCESS;
  980. if (vdev->opmode == wlan_op_mode_ap)
  981. dp_mlo_mcast_deinit(soc, vdev);
  982. dp_tx_put_bank_profile(be_soc, be_vdev);
  983. dp_clr_mlo_ptnr_list(soc, vdev);
  984. return QDF_STATUS_SUCCESS;
  985. }
  986. #ifdef WLAN_SUPPORT_PPEDS
  987. static void dp_soc_txrx_peer_setup_be(struct dp_soc *soc, uint8_t vdev_id,
  988. uint8_t *peer_mac)
  989. {
  990. struct dp_vdev_be *be_vdev;
  991. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  992. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  993. struct cdp_ds_vp_params vp_params = {0};
  994. struct cdp_soc_t *cdp_soc = &soc->cdp_soc;
  995. enum wlan_op_mode vdev_opmode;
  996. struct dp_peer *peer;
  997. peer = dp_peer_find_hash_find(soc, peer_mac, 0, vdev_id, DP_MOD_ID_CDP);
  998. if (!peer)
  999. return;
  1000. vdev_opmode = peer->vdev->opmode;
  1001. if (vdev_opmode != wlan_op_mode_ap &&
  1002. vdev_opmode != wlan_op_mode_sta) {
  1003. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  1004. return;
  1005. }
  1006. be_vdev = dp_get_be_vdev_from_dp_vdev(peer->vdev);
  1007. if (!be_vdev) {
  1008. qdf_err("BE vap is null");
  1009. qdf_status = QDF_STATUS_E_NULL_VALUE;
  1010. goto fail;
  1011. }
  1012. /*
  1013. * Extract the VP profile from the VAP
  1014. */
  1015. if (!cdp_soc->ol_ops->get_ppeds_profile_info_for_vap) {
  1016. dp_err("%pK: Register get ppeds profile info first\n", cdp_soc);
  1017. qdf_status = QDF_STATUS_E_NULL_VALUE;
  1018. goto fail;
  1019. }
  1020. /*
  1021. * Check if PPE DS routing is enabled on the associated vap.
  1022. */
  1023. qdf_status = cdp_soc->ol_ops->get_ppeds_profile_info_for_vap(soc->ctrl_psoc,
  1024. peer->vdev->vdev_id,
  1025. &vp_params);
  1026. if (qdf_status == QDF_STATUS_E_NULL_VALUE) {
  1027. dp_err("%pK: Could not find ppeds profile info vdev\n", be_vdev);
  1028. qdf_status = QDF_STATUS_E_NULL_VALUE;
  1029. goto fail;
  1030. }
  1031. if (vp_params.ppe_vp_type == PPE_VP_USER_TYPE_DS) {
  1032. qdf_status = dp_peer_setup_ppeds_be(soc, peer, be_vdev,
  1033. (void *)&be_soc->ppe_vp_profile[vp_params.ppe_vp_profile_idx]);
  1034. }
  1035. fail:
  1036. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  1037. if (!QDF_IS_STATUS_SUCCESS(qdf_status)) {
  1038. dp_err("Unable to do ppeds peer setup");
  1039. qdf_assert_always(0);
  1040. }
  1041. }
  1042. #else
  1043. static inline
  1044. void dp_soc_txrx_peer_setup_be(struct dp_soc *soc, uint8_t vdev_id,
  1045. uint8_t *peer_mac)
  1046. {
  1047. }
  1048. #endif
  1049. static QDF_STATUS dp_peer_setup_be(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1050. uint8_t *peer_mac,
  1051. struct cdp_peer_setup_info *setup_info)
  1052. {
  1053. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  1054. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  1055. qdf_status = dp_peer_setup_wifi3(soc_hdl, vdev_id, peer_mac,
  1056. setup_info);
  1057. if (!QDF_IS_STATUS_SUCCESS(qdf_status)) {
  1058. dp_err("Unable to dp peer setup");
  1059. return qdf_status;
  1060. }
  1061. dp_soc_txrx_peer_setup_be(soc, vdev_id, peer_mac);
  1062. return QDF_STATUS_SUCCESS;
  1063. }
  1064. qdf_size_t dp_get_soc_context_size_be(void)
  1065. {
  1066. return sizeof(struct dp_soc_be);
  1067. }
  1068. #ifdef CONFIG_WORD_BASED_TLV
  1069. /**
  1070. * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
  1071. * @soc: Common DP soc handle
  1072. * @htt_tlv_filter: Rx SRNG TLV and filter setting
  1073. *
  1074. * Return: none
  1075. */
  1076. static inline void
  1077. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  1078. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  1079. {
  1080. htt_tlv_filter->rx_msdu_end_wmask =
  1081. hal_rx_msdu_end_wmask_get(soc->hal_soc);
  1082. htt_tlv_filter->rx_mpdu_start_wmask =
  1083. hal_rx_mpdu_start_wmask_get(soc->hal_soc);
  1084. }
  1085. #else
  1086. static inline void
  1087. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  1088. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  1089. {
  1090. }
  1091. #endif
  1092. #ifdef WLAN_SUPPORT_PPEDS
  1093. static
  1094. void dp_free_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  1095. int ring_type, int ring_num)
  1096. {
  1097. if (srng->irq >= 0) {
  1098. if (ring_type == WBM2SW_RELEASE &&
  1099. ring_num == WBM2_SW_PPE_REL_RING_ID)
  1100. pld_pfrm_free_irq(soc->osdev->dev, srng->irq, soc);
  1101. else if (ring_type == REO2PPE || ring_type == PPE2TCL)
  1102. pld_pfrm_free_irq(soc->osdev->dev, srng->irq,
  1103. dp_get_ppe_ds_ctxt(soc));
  1104. }
  1105. }
  1106. static
  1107. int dp_register_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  1108. int vector, int ring_type, int ring_num)
  1109. {
  1110. int irq = -1, ret = 0;
  1111. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1112. int pci_slot = pld_get_pci_slot(soc->osdev->dev);
  1113. srng->irq = -1;
  1114. irq = pld_get_msi_irq(soc->osdev->dev, vector);
  1115. if (ring_type == WBM2SW_RELEASE &&
  1116. ring_num == WBM2_SW_PPE_REL_RING_ID) {
  1117. snprintf(be_soc->irq_name[2], DP_PPE_INTR_STRNG_LEN,
  1118. "pci%d_ppe_wbm_rel", pci_slot);
  1119. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  1120. dp_ppeds_handle_tx_comp,
  1121. IRQF_SHARED | IRQF_NO_SUSPEND,
  1122. be_soc->irq_name[2], (void *)soc);
  1123. if (ret)
  1124. goto fail;
  1125. } else if (ring_type == REO2PPE && be_soc->ppeds_int_mode_enabled) {
  1126. snprintf(be_soc->irq_name[0], DP_PPE_INTR_STRNG_LEN,
  1127. "pci%d_reo2ppe", pci_slot);
  1128. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  1129. dp_ppe_ds_reo2ppe_irq_handler,
  1130. IRQF_SHARED | IRQF_NO_SUSPEND,
  1131. be_soc->irq_name[0],
  1132. dp_get_ppe_ds_ctxt(soc));
  1133. if (ret)
  1134. goto fail;
  1135. } else if (ring_type == PPE2TCL && be_soc->ppeds_int_mode_enabled) {
  1136. snprintf(be_soc->irq_name[1], DP_PPE_INTR_STRNG_LEN,
  1137. "pci%d_ppe2tcl", pci_slot);
  1138. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  1139. dp_ppe_ds_ppe2tcl_irq_handler,
  1140. IRQF_NO_SUSPEND,
  1141. be_soc->irq_name[1],
  1142. dp_get_ppe_ds_ctxt(soc));
  1143. if (ret)
  1144. goto fail;
  1145. pld_pfrm_disable_irq_nosync(soc->osdev->dev, irq);
  1146. } else {
  1147. return 0;
  1148. }
  1149. srng->irq = irq;
  1150. dp_info("Registered irq %d for soc %pK ring type %d",
  1151. irq, soc, ring_type);
  1152. return 0;
  1153. fail:
  1154. dp_err("Unable to config irq : ring type %d irq %d vector %d",
  1155. ring_type, irq, vector);
  1156. return ret;
  1157. }
  1158. void dp_ppeds_disable_irq(struct dp_soc *soc, struct dp_srng *srng)
  1159. {
  1160. if (srng->irq >= 0)
  1161. pld_pfrm_disable_irq_nosync(soc->osdev->dev, srng->irq);
  1162. }
  1163. void dp_ppeds_enable_irq(struct dp_soc *soc, struct dp_srng *srng)
  1164. {
  1165. if (srng->irq >= 0)
  1166. pld_pfrm_enable_irq(soc->osdev->dev, srng->irq);
  1167. }
  1168. #endif
  1169. #ifdef NO_RX_PKT_HDR_TLV
  1170. /**
  1171. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  1172. * @soc: Common DP soc handle
  1173. *
  1174. * Return: QDF_STATUS
  1175. */
  1176. static QDF_STATUS
  1177. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  1178. {
  1179. int i;
  1180. int mac_id;
  1181. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  1182. struct dp_srng *rx_mac_srng;
  1183. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1184. /*
  1185. * In Beryllium chipset msdu_start, mpdu_end
  1186. * and rx_attn are part of msdu_end/mpdu_start
  1187. */
  1188. htt_tlv_filter.msdu_start = 0;
  1189. htt_tlv_filter.mpdu_end = 0;
  1190. htt_tlv_filter.attention = 0;
  1191. htt_tlv_filter.mpdu_start = 1;
  1192. htt_tlv_filter.msdu_end = 1;
  1193. htt_tlv_filter.packet = 1;
  1194. htt_tlv_filter.packet_header = 0;
  1195. htt_tlv_filter.ppdu_start = 0;
  1196. htt_tlv_filter.ppdu_end = 0;
  1197. htt_tlv_filter.ppdu_end_user_stats = 0;
  1198. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  1199. htt_tlv_filter.ppdu_end_status_done = 0;
  1200. htt_tlv_filter.enable_fp = 1;
  1201. htt_tlv_filter.enable_md = 0;
  1202. htt_tlv_filter.enable_md = 0;
  1203. htt_tlv_filter.enable_mo = 0;
  1204. htt_tlv_filter.fp_mgmt_filter = 0;
  1205. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  1206. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  1207. FILTER_DATA_DATA);
  1208. htt_tlv_filter.fp_data_filter |=
  1209. hal_rx_en_mcast_fp_data_filter(soc->hal_soc) ?
  1210. FILTER_DATA_MCAST : 0;
  1211. htt_tlv_filter.mo_mgmt_filter = 0;
  1212. htt_tlv_filter.mo_ctrl_filter = 0;
  1213. htt_tlv_filter.mo_data_filter = 0;
  1214. htt_tlv_filter.md_data_filter = 0;
  1215. htt_tlv_filter.offset_valid = true;
  1216. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  1217. htt_tlv_filter.rx_mpdu_end_offset = 0;
  1218. htt_tlv_filter.rx_msdu_start_offset = 0;
  1219. htt_tlv_filter.rx_attn_offset = 0;
  1220. /*
  1221. * For monitor mode, the packet hdr tlv is enabled later during
  1222. * filter update
  1223. */
  1224. if (soc->cdp_soc.ol_ops->get_con_mode &&
  1225. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  1226. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  1227. else
  1228. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  1229. /*Not subscribing rx_pkt_header*/
  1230. htt_tlv_filter.rx_header_offset = 0;
  1231. htt_tlv_filter.rx_mpdu_start_offset =
  1232. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1233. htt_tlv_filter.rx_msdu_end_offset =
  1234. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1235. dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
  1236. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1237. struct dp_pdev *pdev = soc->pdev_list[i];
  1238. if (!pdev)
  1239. continue;
  1240. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1241. int mac_for_pdev =
  1242. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1243. /*
  1244. * Obtain lmac id from pdev to access the LMAC ring
  1245. * in soc context
  1246. */
  1247. int lmac_id =
  1248. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1249. pdev->pdev_id);
  1250. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1251. if (!rx_mac_srng->hal_srng)
  1252. continue;
  1253. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1254. rx_mac_srng->hal_srng,
  1255. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1256. &htt_tlv_filter);
  1257. }
  1258. }
  1259. return status;
  1260. }
  1261. #else
  1262. /**
  1263. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  1264. * @soc: Common DP soc handle
  1265. *
  1266. * Return: QDF_STATUS
  1267. */
  1268. static QDF_STATUS
  1269. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  1270. {
  1271. int i;
  1272. int mac_id;
  1273. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  1274. struct dp_srng *rx_mac_srng;
  1275. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1276. /*
  1277. * In Beryllium chipset msdu_start, mpdu_end
  1278. * and rx_attn are part of msdu_end/mpdu_start
  1279. */
  1280. htt_tlv_filter.msdu_start = 0;
  1281. htt_tlv_filter.mpdu_end = 0;
  1282. htt_tlv_filter.attention = 0;
  1283. htt_tlv_filter.mpdu_start = 1;
  1284. htt_tlv_filter.msdu_end = 1;
  1285. htt_tlv_filter.packet = 1;
  1286. htt_tlv_filter.packet_header = 1;
  1287. htt_tlv_filter.ppdu_start = 0;
  1288. htt_tlv_filter.ppdu_end = 0;
  1289. htt_tlv_filter.ppdu_end_user_stats = 0;
  1290. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  1291. htt_tlv_filter.ppdu_end_status_done = 0;
  1292. htt_tlv_filter.enable_fp = 1;
  1293. htt_tlv_filter.enable_md = 0;
  1294. htt_tlv_filter.enable_md = 0;
  1295. htt_tlv_filter.enable_mo = 0;
  1296. htt_tlv_filter.fp_mgmt_filter = 0;
  1297. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  1298. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  1299. FILTER_DATA_DATA);
  1300. htt_tlv_filter.fp_data_filter |=
  1301. hal_rx_en_mcast_fp_data_filter(soc->hal_soc) ?
  1302. FILTER_DATA_MCAST : 0;
  1303. htt_tlv_filter.mo_mgmt_filter = 0;
  1304. htt_tlv_filter.mo_ctrl_filter = 0;
  1305. htt_tlv_filter.mo_data_filter = 0;
  1306. htt_tlv_filter.md_data_filter = 0;
  1307. htt_tlv_filter.offset_valid = true;
  1308. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  1309. htt_tlv_filter.rx_mpdu_end_offset = 0;
  1310. htt_tlv_filter.rx_msdu_start_offset = 0;
  1311. htt_tlv_filter.rx_attn_offset = 0;
  1312. /*
  1313. * For monitor mode, the packet hdr tlv is enabled later during
  1314. * filter update
  1315. */
  1316. if (soc->cdp_soc.ol_ops->get_con_mode &&
  1317. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  1318. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  1319. else
  1320. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  1321. htt_tlv_filter.rx_header_offset =
  1322. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  1323. htt_tlv_filter.rx_mpdu_start_offset =
  1324. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1325. htt_tlv_filter.rx_msdu_end_offset =
  1326. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1327. dp_info("TLV subscription\n"
  1328. "msdu_start %d, mpdu_end %d, attention %d"
  1329. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  1330. "TLV offsets\n"
  1331. "msdu_start %d, mpdu_end %d, attention %d"
  1332. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  1333. htt_tlv_filter.msdu_start,
  1334. htt_tlv_filter.mpdu_end,
  1335. htt_tlv_filter.attention,
  1336. htt_tlv_filter.mpdu_start,
  1337. htt_tlv_filter.msdu_end,
  1338. htt_tlv_filter.packet_header,
  1339. htt_tlv_filter.packet,
  1340. htt_tlv_filter.rx_msdu_start_offset,
  1341. htt_tlv_filter.rx_mpdu_end_offset,
  1342. htt_tlv_filter.rx_attn_offset,
  1343. htt_tlv_filter.rx_mpdu_start_offset,
  1344. htt_tlv_filter.rx_msdu_end_offset,
  1345. htt_tlv_filter.rx_header_offset,
  1346. htt_tlv_filter.rx_packet_offset);
  1347. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1348. struct dp_pdev *pdev = soc->pdev_list[i];
  1349. if (!pdev)
  1350. continue;
  1351. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1352. int mac_for_pdev =
  1353. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1354. /*
  1355. * Obtain lmac id from pdev to access the LMAC ring
  1356. * in soc context
  1357. */
  1358. int lmac_id =
  1359. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1360. pdev->pdev_id);
  1361. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1362. if (!rx_mac_srng->hal_srng)
  1363. continue;
  1364. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1365. rx_mac_srng->hal_srng,
  1366. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1367. &htt_tlv_filter);
  1368. }
  1369. }
  1370. return status;
  1371. }
  1372. #endif
  1373. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1374. /**
  1375. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  1376. * near-full IRQs.
  1377. * @soc: Datapath SoC handle
  1378. * @int_ctx: Interrupt context
  1379. * @dp_budget: Budget of the work that can be done in the bottom half
  1380. *
  1381. * Return: work done in the handler
  1382. */
  1383. static uint32_t
  1384. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  1385. uint32_t dp_budget)
  1386. {
  1387. int ring = 0;
  1388. int budget = dp_budget;
  1389. uint32_t work_done = 0;
  1390. uint32_t remaining_quota = dp_budget;
  1391. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1392. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  1393. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  1394. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  1395. int rx_near_full_mask = rx_near_full_grp_1_mask |
  1396. rx_near_full_grp_2_mask;
  1397. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  1398. rx_near_full_mask,
  1399. tx_ring_near_full_mask);
  1400. if (rx_near_full_mask) {
  1401. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  1402. if (!(rx_near_full_mask & (1 << ring)))
  1403. continue;
  1404. work_done = dp_rx_nf_process(int_ctx,
  1405. soc->reo_dest_ring[ring].hal_srng,
  1406. ring, remaining_quota);
  1407. if (work_done) {
  1408. intr_stats->num_rx_ring_near_full_masks[ring]++;
  1409. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  1410. rx_near_full_mask, ring,
  1411. work_done,
  1412. budget);
  1413. budget -= work_done;
  1414. if (budget <= 0)
  1415. goto budget_done;
  1416. remaining_quota = budget;
  1417. }
  1418. }
  1419. }
  1420. if (tx_ring_near_full_mask) {
  1421. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  1422. if (!(tx_ring_near_full_mask & (1 << ring)))
  1423. continue;
  1424. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  1425. soc->tx_comp_ring[ring].hal_srng,
  1426. ring, remaining_quota);
  1427. if (work_done) {
  1428. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  1429. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  1430. tx_ring_near_full_mask, ring,
  1431. work_done, budget);
  1432. budget -= work_done;
  1433. if (budget <= 0)
  1434. break;
  1435. remaining_quota = budget;
  1436. }
  1437. }
  1438. }
  1439. intr_stats->num_near_full_masks++;
  1440. budget_done:
  1441. return dp_budget - budget;
  1442. }
  1443. /**
  1444. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  1445. * state and set the reap_limit appropriately
  1446. * as per the near full state
  1447. * @soc: Datapath soc handle
  1448. * @dp_srng: Datapath handle for SRNG
  1449. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  1450. * the srng near-full state
  1451. *
  1452. * Return: 1, if the srng is in near-full state
  1453. * 0, if the srng is not in near-full state
  1454. */
  1455. static int
  1456. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  1457. struct dp_srng *dp_srng,
  1458. int *max_reap_limit)
  1459. {
  1460. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  1461. }
  1462. /**
  1463. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  1464. * near full IRQ handling operations.
  1465. * @arch_ops: arch ops handle
  1466. *
  1467. * Return: none
  1468. */
  1469. static inline void
  1470. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1471. {
  1472. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  1473. arch_ops->dp_srng_test_and_update_nf_params =
  1474. dp_srng_test_and_update_nf_params_be;
  1475. }
  1476. #else
  1477. static inline void
  1478. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1479. {
  1480. }
  1481. #endif
  1482. static inline
  1483. QDF_STATUS dp_srng_init_be(struct dp_soc *soc, struct dp_srng *srng,
  1484. int ring_type, int ring_num, int mac_id)
  1485. {
  1486. return dp_srng_init_idx(soc, srng, ring_type, ring_num, mac_id, 0);
  1487. }
  1488. #ifdef WLAN_SUPPORT_PPEDS
  1489. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1490. {
  1491. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1492. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1493. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1494. if (!be_soc->ppeds_handle)
  1495. return;
  1496. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  1497. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1498. be_soc->ppe2tcl_ring.alloc_size,
  1499. soc->ctrl_psoc,
  1500. WLAN_MD_DP_SRNG_PPE2TCL,
  1501. "ppe2tcl_ring");
  1502. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  1503. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1504. be_soc->reo2ppe_ring.alloc_size,
  1505. soc->ctrl_psoc,
  1506. WLAN_MD_DP_SRNG_REO2PPE,
  1507. "reo2ppe_ring");
  1508. dp_srng_deinit(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1509. WBM2_SW_PPE_REL_RING_ID);
  1510. wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1511. be_soc->ppeds_wbm_release_ring.alloc_size,
  1512. soc->ctrl_psoc,
  1513. WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1514. "ppeds_wbm_release_ring");
  1515. }
  1516. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1517. {
  1518. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1519. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1520. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1521. dp_srng_free(soc, &be_soc->ppeds_wbm_release_ring);
  1522. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  1523. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  1524. }
  1525. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1526. {
  1527. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1528. uint32_t entries;
  1529. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1530. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1531. if (!be_soc->ppeds_handle)
  1532. return QDF_STATUS_SUCCESS;
  1533. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  1534. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  1535. entries, 0)) {
  1536. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  1537. goto fail;
  1538. }
  1539. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  1540. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  1541. entries, 0)) {
  1542. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  1543. goto fail;
  1544. }
  1545. entries = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx);
  1546. if (dp_srng_alloc(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1547. entries, 1)) {
  1548. dp_err("%pK: dp_srng_alloc failed for ppeds_wbm_release_ring",
  1549. soc);
  1550. goto fail;
  1551. }
  1552. return QDF_STATUS_SUCCESS;
  1553. fail:
  1554. dp_soc_ppeds_srng_free(soc);
  1555. return QDF_STATUS_E_NOMEM;
  1556. }
  1557. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1558. {
  1559. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1560. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1561. hal_soc_handle_t hal_soc = soc->hal_soc;
  1562. struct dp_ppe_ds_idxs idx = {0};
  1563. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1564. if (!be_soc->ppeds_handle)
  1565. return QDF_STATUS_SUCCESS;
  1566. if (dp_ppeds_register_soc_be(be_soc, &idx)) {
  1567. dp_err("%pK: ppeds registration failed", soc);
  1568. goto fail;
  1569. }
  1570. if (dp_srng_init_idx(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0,
  1571. idx.reo2ppe_start_idx)) {
  1572. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  1573. goto fail;
  1574. }
  1575. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1576. be_soc->reo2ppe_ring.alloc_size,
  1577. soc->ctrl_psoc,
  1578. WLAN_MD_DP_SRNG_REO2PPE,
  1579. "reo2ppe_ring");
  1580. hal_reo_config_reo2ppe_dest_info(hal_soc);
  1581. if (dp_srng_init_idx(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0,
  1582. idx.ppe2tcl_start_idx)) {
  1583. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  1584. goto fail;
  1585. }
  1586. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1587. be_soc->ppe2tcl_ring.alloc_size,
  1588. soc->ctrl_psoc,
  1589. WLAN_MD_DP_SRNG_PPE2TCL,
  1590. "ppe2tcl_ring");
  1591. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1592. be_soc->ppe2tcl_ring.hal_srng,
  1593. WBM2_SW_PPE_REL_MAP_ID);
  1594. if (dp_srng_init(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1595. WBM2_SW_PPE_REL_RING_ID, 0)) {
  1596. dp_err("%pK: dp_srng_init failed for ppeds_wbm_release_ring",
  1597. soc);
  1598. goto fail;
  1599. }
  1600. wlan_minidump_log(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1601. be_soc->ppeds_wbm_release_ring.alloc_size,
  1602. soc->ctrl_psoc, WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1603. "ppeds_wbm_release_ring");
  1604. return QDF_STATUS_SUCCESS;
  1605. fail:
  1606. dp_soc_ppeds_srng_deinit(soc);
  1607. return QDF_STATUS_E_NOMEM;
  1608. }
  1609. #else
  1610. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1611. {
  1612. }
  1613. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1614. {
  1615. }
  1616. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1617. {
  1618. return QDF_STATUS_SUCCESS;
  1619. }
  1620. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1621. {
  1622. return QDF_STATUS_SUCCESS;
  1623. }
  1624. #endif
  1625. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1626. {
  1627. uint32_t i;
  1628. dp_soc_ppeds_srng_deinit(soc);
  1629. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1630. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1631. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1632. RXDMA_BUF, 0);
  1633. }
  1634. }
  1635. }
  1636. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1637. {
  1638. uint32_t i;
  1639. dp_soc_ppeds_srng_free(soc);
  1640. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1641. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1642. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1643. }
  1644. }
  1645. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1646. {
  1647. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1648. uint32_t ring_size;
  1649. uint32_t i;
  1650. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1651. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1652. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1653. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1654. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1655. RXDMA_BUF, ring_size, 0)) {
  1656. dp_err("%pK: dp_srng_alloc failed refill ring",
  1657. soc);
  1658. goto fail;
  1659. }
  1660. }
  1661. }
  1662. if (dp_soc_ppeds_srng_alloc(soc)) {
  1663. dp_err("%pK: ppe rings alloc failed",
  1664. soc);
  1665. goto fail;
  1666. }
  1667. return QDF_STATUS_SUCCESS;
  1668. fail:
  1669. dp_soc_srng_free_be(soc);
  1670. return QDF_STATUS_E_NOMEM;
  1671. }
  1672. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1673. {
  1674. int i = 0;
  1675. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1676. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1677. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1678. RXDMA_BUF, 0, 0)) {
  1679. dp_err("%pK: dp_srng_init failed refill ring",
  1680. soc);
  1681. goto fail;
  1682. }
  1683. }
  1684. }
  1685. if (dp_soc_ppeds_srng_init(soc)) {
  1686. dp_err("%pK: ppe ds rings init failed",
  1687. soc);
  1688. goto fail;
  1689. }
  1690. return QDF_STATUS_SUCCESS;
  1691. fail:
  1692. dp_soc_srng_deinit_be(soc);
  1693. return QDF_STATUS_E_NOMEM;
  1694. }
  1695. #ifdef WLAN_FEATURE_11BE_MLO
  1696. static inline unsigned
  1697. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1698. union dp_align_mac_addr *mac_addr)
  1699. {
  1700. uint32_t index;
  1701. index =
  1702. mac_addr->align2.bytes_ab ^
  1703. mac_addr->align2.bytes_cd ^
  1704. mac_addr->align2.bytes_ef;
  1705. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1706. index &= mld_hash_obj->mld_peer_hash.mask;
  1707. return index;
  1708. }
  1709. QDF_STATUS
  1710. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1711. int hash_elems)
  1712. {
  1713. int i, log2;
  1714. if (!mld_hash_obj)
  1715. return QDF_STATUS_E_FAILURE;
  1716. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1717. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1718. log2 = dp_log2_ceil(hash_elems);
  1719. hash_elems = 1 << log2;
  1720. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1721. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1722. /* allocate an array of TAILQ peer object lists */
  1723. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1724. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1725. if (!mld_hash_obj->mld_peer_hash.bins)
  1726. return QDF_STATUS_E_NOMEM;
  1727. for (i = 0; i < hash_elems; i++)
  1728. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1729. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1730. return QDF_STATUS_SUCCESS;
  1731. }
  1732. void
  1733. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1734. {
  1735. if (!mld_hash_obj)
  1736. return;
  1737. if (mld_hash_obj->mld_peer_hash.bins) {
  1738. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1739. mld_hash_obj->mld_peer_hash.bins = NULL;
  1740. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1741. }
  1742. }
  1743. #ifdef WLAN_MLO_MULTI_CHIP
  1744. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1745. {
  1746. /* In case of MULTI chip MLO peer hash table when MLO global object
  1747. * is created, avoid from SOC attach path
  1748. */
  1749. return QDF_STATUS_SUCCESS;
  1750. }
  1751. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1752. {
  1753. }
  1754. #else
  1755. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1756. {
  1757. dp_mld_peer_hash_obj_t mld_hash_obj;
  1758. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1759. if (!mld_hash_obj)
  1760. return QDF_STATUS_E_FAILURE;
  1761. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1762. }
  1763. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1764. {
  1765. dp_mld_peer_hash_obj_t mld_hash_obj;
  1766. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1767. if (!mld_hash_obj)
  1768. return;
  1769. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1770. }
  1771. #endif
  1772. #ifdef QCA_ENHANCED_STATS_SUPPORT
  1773. static uint8_t
  1774. dp_get_hw_link_id_be(struct dp_pdev *pdev)
  1775. {
  1776. struct dp_pdev_be *be_pdev = dp_get_be_pdev_from_dp_pdev(pdev);
  1777. return be_pdev->mlo_link_id;
  1778. }
  1779. #else
  1780. static uint8_t
  1781. dp_get_hw_link_id_be(struct dp_pdev *pdev)
  1782. {
  1783. return 0;
  1784. }
  1785. #endif /* QCA_ENHANCED_STATS_SUPPORT */
  1786. static struct dp_peer *
  1787. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1788. uint8_t *peer_mac_addr,
  1789. int mac_addr_is_aligned,
  1790. enum dp_mod_id mod_id,
  1791. uint8_t vdev_id)
  1792. {
  1793. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1794. uint32_t index;
  1795. struct dp_peer *peer;
  1796. struct dp_vdev *vdev;
  1797. dp_mld_peer_hash_obj_t mld_hash_obj;
  1798. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1799. if (!mld_hash_obj)
  1800. return NULL;
  1801. if (!mld_hash_obj->mld_peer_hash.bins)
  1802. return NULL;
  1803. if (mac_addr_is_aligned) {
  1804. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1805. } else {
  1806. qdf_mem_copy(
  1807. &local_mac_addr_aligned.raw[0],
  1808. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1809. mac_addr = &local_mac_addr_aligned;
  1810. }
  1811. if (vdev_id != DP_VDEV_ALL) {
  1812. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1813. if (!vdev) {
  1814. dp_err("vdev is null\n");
  1815. return NULL;
  1816. }
  1817. } else {
  1818. vdev = NULL;
  1819. }
  1820. /* search mld peer table if no link peer for given mac address */
  1821. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1822. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1823. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1824. hash_list_elem) {
  1825. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1826. if ((vdev_id == DP_VDEV_ALL) || (
  1827. dp_peer_find_mac_addr_cmp(
  1828. &peer->vdev->mld_mac_addr,
  1829. &vdev->mld_mac_addr) == 0)) {
  1830. /* take peer reference before returning */
  1831. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1832. QDF_STATUS_SUCCESS)
  1833. peer = NULL;
  1834. if (vdev)
  1835. dp_vdev_unref_delete(soc, vdev, mod_id);
  1836. qdf_spin_unlock_bh(
  1837. &mld_hash_obj->mld_peer_hash_lock);
  1838. return peer;
  1839. }
  1840. }
  1841. }
  1842. if (vdev)
  1843. dp_vdev_unref_delete(soc, vdev, mod_id);
  1844. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1845. return NULL; /* failure */
  1846. }
  1847. static void
  1848. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1849. {
  1850. uint32_t index;
  1851. struct dp_peer *tmppeer = NULL;
  1852. int found = 0;
  1853. dp_mld_peer_hash_obj_t mld_hash_obj;
  1854. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1855. if (!mld_hash_obj)
  1856. return;
  1857. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1858. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1859. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1860. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1861. hash_list_elem) {
  1862. if (tmppeer == peer) {
  1863. found = 1;
  1864. break;
  1865. }
  1866. }
  1867. QDF_ASSERT(found);
  1868. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1869. hash_list_elem);
  1870. dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") removed. (found %u)",
  1871. peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw), found);
  1872. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1873. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1874. }
  1875. static void
  1876. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1877. {
  1878. uint32_t index;
  1879. dp_mld_peer_hash_obj_t mld_hash_obj;
  1880. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1881. if (!mld_hash_obj)
  1882. return;
  1883. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1884. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1885. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1886. DP_MOD_ID_CONFIG))) {
  1887. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1888. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1889. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1890. return;
  1891. }
  1892. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1893. hash_list_elem);
  1894. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1895. dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") added",
  1896. peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1897. }
  1898. void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
  1899. {
  1900. uint32_t index;
  1901. struct dp_peer *peer;
  1902. dp_mld_peer_hash_obj_t mld_hash_obj;
  1903. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1904. if (!mld_hash_obj)
  1905. return;
  1906. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1907. for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
  1908. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1909. hash_list_elem) {
  1910. dp_print_peer_ast_entries(soc, peer, NULL);
  1911. }
  1912. }
  1913. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1914. }
  1915. #endif
  1916. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1917. static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
  1918. struct dp_vdev *vdev)
  1919. {
  1920. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1921. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1922. hal_soc_handle_t hal_soc = soc->hal_soc;
  1923. uint8_t vdev_id = vdev->vdev_id;
  1924. if (vdev->opmode == wlan_op_mode_sta) {
  1925. if (vdev->pdev->isolation)
  1926. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1927. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1928. else
  1929. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1930. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  1931. } else if (vdev->opmode == wlan_op_mode_ap) {
  1932. hal_tx_mcast_mlo_reinject_routing_set(
  1933. hal_soc,
  1934. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  1935. if (vdev->mlo_vdev) {
  1936. hal_tx_vdev_mcast_ctrl_set(
  1937. hal_soc,
  1938. vdev_id,
  1939. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1940. } else {
  1941. hal_tx_vdev_mcast_ctrl_set(hal_soc,
  1942. vdev_id,
  1943. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1944. }
  1945. }
  1946. }
  1947. static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
  1948. {
  1949. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1950. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1951. union hal_tx_bank_config *bank_config;
  1952. if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
  1953. return;
  1954. bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
  1955. hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
  1956. be_vdev->bank_id);
  1957. }
  1958. #endif
  1959. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1960. defined(WLAN_MCAST_MLO)
  1961. static void dp_mlo_mcast_reset_pri_mcast(struct dp_vdev_be *be_vdev,
  1962. struct dp_vdev *ptnr_vdev,
  1963. void *arg)
  1964. {
  1965. struct dp_vdev_be *be_ptnr_vdev =
  1966. dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  1967. be_ptnr_vdev->mcast_primary = false;
  1968. }
  1969. #if defined(CONFIG_MLO_SINGLE_DEV)
  1970. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1971. struct dp_vdev *vdev,
  1972. cdp_config_param_type val)
  1973. {
  1974. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1975. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1976. be_vdev->vdev.pdev->soc);
  1977. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1978. vdev->mlo_vdev = true;
  1979. if (be_vdev->mcast_primary) {
  1980. struct cdp_txrx_peer_params_update params = {0};
  1981. params.chip_id = be_soc->mlo_chip_id;
  1982. params.pdev_id = be_vdev->vdev.pdev->pdev_id;
  1983. params.osif_vdev = be_vdev->vdev.osif_vdev;
  1984. dp_wdi_event_handler(
  1985. WDI_EVENT_MCAST_PRIMARY_UPDATE,
  1986. be_vdev->vdev.pdev->soc,
  1987. (void *)&params, CDP_INVALID_PEER,
  1988. WDI_NO_VAL, params.pdev_id);
  1989. }
  1990. }
  1991. #else
  1992. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1993. struct dp_vdev *vdev,
  1994. cdp_config_param_type val)
  1995. {
  1996. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1997. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1998. be_vdev->vdev.pdev->soc);
  1999. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  2000. vdev->mlo_vdev = true;
  2001. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  2002. vdev->vdev_id,
  2003. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  2004. if (be_vdev->mcast_primary) {
  2005. struct cdp_txrx_peer_params_update params = {0};
  2006. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  2007. dp_mlo_mcast_reset_pri_mcast,
  2008. (void *)&be_vdev->mcast_primary,
  2009. DP_MOD_ID_TX_MCAST);
  2010. params.chip_id = be_soc->mlo_chip_id;
  2011. params.pdev_id = vdev->pdev->pdev_id;
  2012. params.osif_vdev = vdev->osif_vdev;
  2013. dp_wdi_event_handler(
  2014. WDI_EVENT_MCAST_PRIMARY_UPDATE,
  2015. vdev->pdev->soc,
  2016. (void *)&params, CDP_INVALID_PEER,
  2017. WDI_NO_VAL, params.pdev_id);
  2018. }
  2019. }
  2020. #endif
  2021. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  2022. struct dp_vdev *vdev,
  2023. cdp_config_param_type val)
  2024. {
  2025. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2026. be_vdev->mcast_primary = false;
  2027. vdev->mlo_vdev = false;
  2028. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  2029. vdev->vdev_id,
  2030. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  2031. }
  2032. /**
  2033. * dp_txrx_get_vdev_mcast_param_be() - Target specific ops for getting vdev
  2034. * params related to multicast
  2035. * @soc: DP soc handle
  2036. * @vdev: pointer to vdev structure
  2037. * @val: buffer address
  2038. *
  2039. * Return: QDF_STATUS
  2040. */
  2041. static
  2042. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  2043. struct dp_vdev *vdev,
  2044. cdp_config_param_type *val)
  2045. {
  2046. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2047. if (be_vdev->mcast_primary)
  2048. val->cdp_vdev_param_mcast_vdev = true;
  2049. else
  2050. val->cdp_vdev_param_mcast_vdev = false;
  2051. return QDF_STATUS_SUCCESS;
  2052. }
  2053. #else
  2054. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  2055. struct dp_vdev *vdev,
  2056. cdp_config_param_type val)
  2057. {
  2058. }
  2059. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  2060. struct dp_vdev *vdev,
  2061. cdp_config_param_type val)
  2062. {
  2063. }
  2064. static
  2065. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  2066. struct dp_vdev *vdev,
  2067. cdp_config_param_type *val)
  2068. {
  2069. return QDF_STATUS_SUCCESS;
  2070. }
  2071. #endif
  2072. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  2073. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  2074. uint8_t tx_ring_id,
  2075. uint8_t bm_id)
  2076. {
  2077. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  2078. soc->tcl_data_ring[tx_ring_id].hal_srng,
  2079. bm_id);
  2080. }
  2081. #else
  2082. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  2083. uint8_t tx_ring_id,
  2084. uint8_t bm_id)
  2085. {
  2086. }
  2087. #endif
  2088. /**
  2089. * dp_txrx_set_vdev_param_be() - Target specific ops while setting vdev params
  2090. * @soc: DP soc handle
  2091. * @vdev: pointer to vdev structure
  2092. * @param: parameter type to get value
  2093. * @val: value
  2094. *
  2095. * Return: QDF_STATUS
  2096. */
  2097. static
  2098. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  2099. struct dp_vdev *vdev,
  2100. enum cdp_vdev_param_type param,
  2101. cdp_config_param_type val)
  2102. {
  2103. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2104. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2105. switch (param) {
  2106. case CDP_TX_ENCAP_TYPE:
  2107. case CDP_UPDATE_DSCP_TO_TID_MAP:
  2108. case CDP_UPDATE_TDLS_FLAGS:
  2109. dp_tx_update_bank_profile(be_soc, be_vdev);
  2110. break;
  2111. case CDP_ENABLE_CIPHER:
  2112. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  2113. dp_tx_update_bank_profile(be_soc, be_vdev);
  2114. break;
  2115. case CDP_SET_MCAST_VDEV:
  2116. dp_txrx_set_mlo_mcast_primary_vdev_param_be(vdev, val);
  2117. break;
  2118. case CDP_RESET_MLO_MCAST_VDEV:
  2119. dp_txrx_reset_mlo_mcast_primary_vdev_param_be(vdev, val);
  2120. break;
  2121. default:
  2122. dp_warn("invalid param %d", param);
  2123. break;
  2124. }
  2125. return QDF_STATUS_SUCCESS;
  2126. }
  2127. #ifdef WLAN_FEATURE_11BE_MLO
  2128. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  2129. static inline void
  2130. dp_soc_max_peer_id_set(struct dp_soc *soc)
  2131. {
  2132. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  2133. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  2134. /*
  2135. * Double the peers since we use ML indication bit
  2136. * alongwith peer_id to find peers.
  2137. */
  2138. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  2139. }
  2140. #else
  2141. static inline void
  2142. dp_soc_max_peer_id_set(struct dp_soc *soc)
  2143. {
  2144. soc->max_peer_id =
  2145. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  2146. }
  2147. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  2148. #else
  2149. static inline void
  2150. dp_soc_max_peer_id_set(struct dp_soc *soc)
  2151. {
  2152. soc->max_peer_id = soc->max_peers;
  2153. }
  2154. #endif /* WLAN_FEATURE_11BE_MLO */
  2155. static void dp_peer_map_detach_be(struct dp_soc *soc)
  2156. {
  2157. if (soc->host_ast_db_enable)
  2158. dp_peer_ast_hash_detach(soc);
  2159. }
  2160. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  2161. {
  2162. QDF_STATUS status;
  2163. if (soc->host_ast_db_enable) {
  2164. status = dp_peer_ast_hash_attach(soc);
  2165. if (QDF_IS_STATUS_ERROR(status))
  2166. return status;
  2167. }
  2168. dp_soc_max_peer_id_set(soc);
  2169. return QDF_STATUS_SUCCESS;
  2170. }
  2171. static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
  2172. uint8_t *dest_mac,
  2173. uint8_t vdev_id)
  2174. {
  2175. struct dp_peer *peer = NULL;
  2176. struct dp_peer *tgt_peer = NULL;
  2177. struct dp_ast_entry *ast_entry = NULL;
  2178. uint16_t peer_id;
  2179. qdf_spin_lock_bh(&soc->ast_lock);
  2180. ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac);
  2181. if (!ast_entry) {
  2182. qdf_spin_unlock_bh(&soc->ast_lock);
  2183. dp_err("NULL ast entry");
  2184. return NULL;
  2185. }
  2186. peer_id = ast_entry->peer_id;
  2187. qdf_spin_unlock_bh(&soc->ast_lock);
  2188. if (peer_id == HTT_INVALID_PEER)
  2189. return NULL;
  2190. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF);
  2191. if (!peer) {
  2192. dp_err("NULL peer for peer_id:%d", peer_id);
  2193. return NULL;
  2194. }
  2195. tgt_peer = dp_get_tgt_peer_from_peer(peer);
  2196. /*
  2197. * Once tgt_peer is obtained,
  2198. * release the ref taken for original peer.
  2199. */
  2200. dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF);
  2201. dp_peer_unref_delete(peer, DP_MOD_ID_SAWF);
  2202. return tgt_peer;
  2203. }
  2204. #ifdef WLAN_FEATURE_11BE_MLO
  2205. #ifdef WLAN_MCAST_MLO
  2206. static inline void
  2207. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  2208. {
  2209. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  2210. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  2211. arch_ops->dp_tx_is_mcast_primary = dp_tx_mlo_is_mcast_primary_be;
  2212. }
  2213. #else /* WLAN_MCAST_MLO */
  2214. static inline void
  2215. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  2216. {
  2217. }
  2218. #endif /* WLAN_MCAST_MLO */
  2219. #ifdef WLAN_MLO_MULTI_CHIP
  2220. static inline void
  2221. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  2222. {
  2223. arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
  2224. arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
  2225. arch_ops->dp_soc_get_by_idle_bm_id = dp_soc_get_by_idle_bm_id;
  2226. }
  2227. #else
  2228. static inline void
  2229. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  2230. {
  2231. }
  2232. #endif
  2233. static inline void
  2234. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  2235. {
  2236. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  2237. dp_initialize_arch_ops_be_mlo_multi_chip(arch_ops);
  2238. arch_ops->mlo_peer_find_hash_detach =
  2239. dp_mlo_peer_find_hash_detach_wrapper;
  2240. arch_ops->mlo_peer_find_hash_attach =
  2241. dp_mlo_peer_find_hash_attach_wrapper;
  2242. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  2243. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  2244. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  2245. arch_ops->get_hw_link_id = dp_get_hw_link_id_be;
  2246. }
  2247. #else /* WLAN_FEATURE_11BE_MLO */
  2248. static inline void
  2249. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  2250. {
  2251. }
  2252. #endif /* WLAN_FEATURE_11BE_MLO */
  2253. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  2254. #define DP_LMAC_PEER_ID_MSB_LEGACY 2
  2255. #define DP_LMAC_PEER_ID_MSB_MLO 3
  2256. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  2257. struct cdp_peer_setup_info *setup_info,
  2258. enum cdp_host_reo_dest_ring *reo_dest,
  2259. bool *hash_based,
  2260. uint8_t *lmac_peer_id_msb)
  2261. {
  2262. struct dp_soc *soc = vdev->pdev->soc;
  2263. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2264. if (!be_soc->mlo_enabled)
  2265. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  2266. hash_based);
  2267. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2268. *reo_dest = vdev->pdev->reo_dest;
  2269. /* Not a ML link peer use non-mlo */
  2270. if (!setup_info) {
  2271. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  2272. return;
  2273. }
  2274. /* For STA ML VAP we do not have num links info at this point
  2275. * use MLO case always
  2276. */
  2277. if (vdev->opmode == wlan_op_mode_sta) {
  2278. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  2279. return;
  2280. }
  2281. /* For AP ML VAP consider the peer as ML only it associates with
  2282. * multiple links
  2283. */
  2284. if (setup_info->num_links == 1) {
  2285. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  2286. return;
  2287. }
  2288. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  2289. }
  2290. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2291. uint32_t *remap0,
  2292. uint32_t *remap1,
  2293. uint32_t *remap2)
  2294. {
  2295. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2296. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  2297. uint32_t reo_mlo_config =
  2298. wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
  2299. if (!be_soc->mlo_enabled)
  2300. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2301. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2302. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
  2303. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2304. return true;
  2305. }
  2306. #else
  2307. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  2308. struct cdp_peer_setup_info *setup_info,
  2309. enum cdp_host_reo_dest_ring *reo_dest,
  2310. bool *hash_based,
  2311. uint8_t *lmac_peer_id_msb)
  2312. {
  2313. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  2314. }
  2315. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2316. uint32_t *remap0,
  2317. uint32_t *remap1,
  2318. uint32_t *remap2)
  2319. {
  2320. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2321. }
  2322. #endif
  2323. #ifdef CONFIG_MLO_SINGLE_DEV
  2324. static inline
  2325. void dp_initialize_arch_ops_be_single_dev(struct dp_arch_ops *arch_ops)
  2326. {
  2327. arch_ops->dp_tx_mlo_mcast_send = dp_tx_mlo_mcast_send_be;
  2328. }
  2329. #else
  2330. static inline
  2331. void dp_initialize_arch_ops_be_single_dev(struct dp_arch_ops *arch_ops)
  2332. {
  2333. }
  2334. #endif
  2335. #ifdef IPA_OFFLOAD
  2336. static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc)
  2337. {
  2338. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2339. return be_soc->ipa_bank_id;
  2340. }
  2341. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  2342. static void dp_ipa_get_wdi_version_be(uint8_t *wdi_ver)
  2343. {
  2344. *wdi_ver = IPA_WDI_4;
  2345. }
  2346. #else
  2347. static inline void dp_ipa_get_wdi_version_be(uint8_t *wdi_ver)
  2348. {
  2349. }
  2350. #endif
  2351. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2352. {
  2353. arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be;
  2354. arch_ops->ipa_get_wdi_ver = dp_ipa_get_wdi_version_be;
  2355. }
  2356. #else /* !IPA_OFFLOAD */
  2357. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2358. {
  2359. }
  2360. #endif /* IPA_OFFLOAD */
  2361. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  2362. {
  2363. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  2364. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  2365. arch_ops->dp_rx_process = dp_rx_process_be;
  2366. arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
  2367. arch_ops->tx_comp_get_params_from_hal_desc =
  2368. dp_tx_comp_get_params_from_hal_desc_be;
  2369. arch_ops->dp_tx_process_htt_completion =
  2370. dp_tx_process_htt_completion_be;
  2371. arch_ops->dp_tx_desc_pool_alloc = dp_tx_desc_pool_alloc_be;
  2372. arch_ops->dp_tx_desc_pool_free = dp_tx_desc_pool_free_be;
  2373. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  2374. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  2375. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  2376. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  2377. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  2378. dp_wbm_get_rx_desc_from_hal_desc_be;
  2379. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
  2380. arch_ops->dp_rx_chain_msdus = dp_rx_chain_msdus_be;
  2381. arch_ops->dp_rx_wbm_err_reap_desc = dp_rx_wbm_err_reap_desc_be;
  2382. arch_ops->dp_rx_null_q_desc_handle = dp_rx_null_q_desc_handle_be;
  2383. #endif
  2384. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  2385. #ifdef WIFI_MONITOR_SUPPORT
  2386. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  2387. #endif
  2388. arch_ops->dp_rx_desc_cookie_2_va =
  2389. dp_rx_desc_cookie_2_va_be;
  2390. arch_ops->dp_rx_intrabss_mcast_handler =
  2391. dp_rx_intrabss_mcast_handler_be;
  2392. arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
  2393. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  2394. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  2395. arch_ops->txrx_soc_init = dp_soc_init_be;
  2396. arch_ops->txrx_soc_deinit = dp_soc_deinit_be_wrapper;
  2397. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  2398. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  2399. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  2400. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  2401. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  2402. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  2403. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  2404. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  2405. arch_ops->txrx_peer_setup = dp_peer_setup_be;
  2406. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  2407. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  2408. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  2409. arch_ops->dp_rx_peer_metadata_peer_id_get =
  2410. dp_rx_peer_metadata_peer_id_get_be;
  2411. arch_ops->dp_rx_peer_mdata_link_id_get =
  2412. dp_rx_peer_mdata_link_id_get_be;
  2413. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  2414. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  2415. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  2416. dp_initialize_arch_ops_be_mlo(arch_ops);
  2417. arch_ops->dp_rx_replenish_soc_get = dp_rx_replensih_soc_get;
  2418. arch_ops->dp_soc_get_num_soc = dp_soc_get_num_soc_be;
  2419. arch_ops->dp_peer_rx_reorder_queue_setup =
  2420. dp_peer_rx_reorder_queue_setup_be;
  2421. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  2422. arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
  2423. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  2424. arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
  2425. arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
  2426. dp_reconfig_tx_vdev_mcast_ctrl_be;
  2427. arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
  2428. #endif
  2429. #ifdef WLAN_SUPPORT_PPEDS
  2430. arch_ops->ppeds_handle_attached = dp_ppeds_handle_attached;
  2431. arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status;
  2432. arch_ops->txrx_soc_ppeds_start = dp_ppeds_start_soc_be;
  2433. arch_ops->txrx_soc_ppeds_stop = dp_ppeds_stop_soc_be;
  2434. arch_ops->dp_register_ppeds_interrupts = dp_register_ppeds_interrupts;
  2435. arch_ops->dp_free_ppeds_interrupts = dp_free_ppeds_interrupts;
  2436. arch_ops->dp_tx_ppeds_inuse_desc = dp_ppeds_inuse_desc;
  2437. arch_ops->dp_tx_ppeds_cfg_astidx_cache_mapping =
  2438. dp_tx_ppeds_cfg_astidx_cache_mapping;
  2439. #ifdef DP_UMAC_HW_RESET_SUPPORT
  2440. arch_ops->txrx_soc_ppeds_interrupt_stop = dp_ppeds_interrupt_stop_be;
  2441. arch_ops->txrx_soc_ppeds_interrupt_start = dp_ppeds_interrupt_start_be;
  2442. arch_ops->txrx_soc_ppeds_service_status_update =
  2443. dp_ppeds_service_status_update_be;
  2444. arch_ops->txrx_soc_ppeds_enabled_check = dp_ppeds_is_enabled_on_soc;
  2445. arch_ops->txrx_soc_ppeds_txdesc_pool_reset =
  2446. dp_ppeds_tx_desc_pool_reset;
  2447. #endif
  2448. #endif
  2449. dp_init_near_full_arch_ops_be(arch_ops);
  2450. arch_ops->get_reo_qdesc_addr = dp_rx_get_reo_qdesc_addr_be;
  2451. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
  2452. arch_ops->dp_set_rx_fst = dp_set_rx_fst_be;
  2453. arch_ops->dp_get_rx_fst = dp_get_rx_fst_be;
  2454. arch_ops->dp_rx_fst_deref = dp_rx_fst_release_ref_be;
  2455. arch_ops->dp_rx_fst_ref = dp_rx_fst_get_ref_be;
  2456. arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
  2457. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  2458. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  2459. arch_ops->txrx_get_vdev_mcast_param = dp_txrx_get_vdev_mcast_param_be;
  2460. arch_ops->txrx_srng_init = dp_srng_init_be;
  2461. #if defined(DP_POWER_SAVE) || defined(FEATURE_RUNTIME_PM)
  2462. arch_ops->dp_update_ring_hptp = dp_update_ring_hptp;
  2463. #endif
  2464. dp_initialize_arch_ops_be_ipa(arch_ops);
  2465. dp_initialize_arch_ops_be_single_dev(arch_ops);
  2466. }
  2467. #ifdef QCA_SUPPORT_PRIMARY_LINK_MIGRATE
  2468. static void
  2469. dp_primary_link_migration(struct dp_soc *soc, void *cb_ctxt,
  2470. union hal_reo_status *reo_status)
  2471. {
  2472. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2473. struct dp_mlo_ctxt *dp_mlo = be_soc->ml_ctxt;
  2474. struct dp_soc *pr_soc = NULL;
  2475. struct dp_peer_info *pr_peer_info = (struct dp_peer_info *)cb_ctxt;
  2476. struct dp_peer *new_primary_peer = NULL;
  2477. struct dp_peer *mld_peer = NULL;
  2478. uint8_t primary_vdev_id;
  2479. struct cdp_txrx_peer_params_update params = {0};
  2480. pr_soc = dp_mlo_get_soc_ref_by_chip_id(dp_mlo, pr_peer_info->chip_id);
  2481. if (!pr_soc) {
  2482. dp_htt_err("Invalid soc");
  2483. qdf_mem_free(pr_peer_info);
  2484. return;
  2485. }
  2486. new_primary_peer = pr_soc->peer_id_to_obj_map[
  2487. pr_peer_info->primary_peer_id];
  2488. mld_peer = DP_GET_MLD_PEER_FROM_PEER(new_primary_peer);
  2489. if (!mld_peer) {
  2490. dp_htt_err("Invalid peer");
  2491. qdf_mem_free(pr_peer_info);
  2492. return;
  2493. }
  2494. new_primary_peer->primary_link = 1;
  2495. if (pr_soc && pr_soc->cdp_soc.ol_ops->update_primary_link)
  2496. pr_soc->cdp_soc.ol_ops->update_primary_link(pr_soc->ctrl_psoc,
  2497. new_primary_peer->mac_addr.raw);
  2498. primary_vdev_id = new_primary_peer->vdev->vdev_id;
  2499. dp_vdev_unref_delete(soc, mld_peer->vdev, DP_MOD_ID_CHILD);
  2500. mld_peer->vdev = dp_vdev_get_ref_by_id(pr_soc, primary_vdev_id,
  2501. DP_MOD_ID_CHILD);
  2502. mld_peer->txrx_peer->vdev = mld_peer->vdev;
  2503. params.osif_vdev = (void *)new_primary_peer->vdev->osif_vdev;
  2504. params.peer_mac = mld_peer->mac_addr.raw;
  2505. params.chip_id = pr_peer_info->chip_id;
  2506. params.pdev_id = new_primary_peer->vdev->pdev->pdev_id;
  2507. if (new_primary_peer->vdev->opmode == wlan_op_mode_sta) {
  2508. dp_wdi_event_handler(
  2509. WDI_EVENT_STA_PRIMARY_UMAC_UPDATE,
  2510. pr_soc, (void *)&params,
  2511. new_primary_peer->peer_id,
  2512. WDI_NO_VAL, params.pdev_id);
  2513. } else {
  2514. dp_wdi_event_handler(
  2515. WDI_EVENT_PEER_PRIMARY_UMAC_UPDATE,
  2516. pr_soc, (void *)&params,
  2517. new_primary_peer->peer_id,
  2518. WDI_NO_VAL, params.pdev_id);
  2519. }
  2520. qdf_mem_free(pr_peer_info);
  2521. }
  2522. #ifdef WLAN_SUPPORT_PPEDS
  2523. static QDF_STATUS dp_get_ppe_info_for_vap(struct cdp_soc_t *cdp_soc,
  2524. struct dp_soc *mld_soc,
  2525. struct dp_peer *pr_peer,
  2526. uint16_t *src_info)
  2527. {
  2528. struct dp_soc_be *be_soc_mld = NULL;
  2529. struct cdp_ds_vp_params vp_params = {0};
  2530. struct dp_ppe_vp_profile *ppe_vp_profile;
  2531. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  2532. /*
  2533. * Extract the VP profile from the VAP
  2534. */
  2535. if (!cdp_soc->ol_ops->get_ppeds_profile_info_for_vap) {
  2536. dp_err("%pK: Register get ppeds profile info first", cdp_soc);
  2537. return QDF_STATUS_E_NULL_VALUE;
  2538. }
  2539. /*
  2540. * Check if PPE DS routing is enabled on the associated vap.
  2541. */
  2542. qdf_status = cdp_soc->ol_ops->get_ppeds_profile_info_for_vap(
  2543. mld_soc->ctrl_psoc,
  2544. pr_peer->vdev->vdev_id,
  2545. &vp_params);
  2546. if (QDF_IS_STATUS_ERROR(qdf_status)) {
  2547. dp_err("Could not find ppeds profile info");
  2548. return QDF_STATUS_E_NULL_VALUE;
  2549. }
  2550. /* Check if PPE DS routing is enabled on
  2551. * the associated vap.
  2552. */
  2553. if (vp_params.ppe_vp_type != PPE_VP_USER_TYPE_DS)
  2554. return qdf_status;
  2555. be_soc_mld = dp_get_be_soc_from_dp_soc(mld_soc);
  2556. ppe_vp_profile = &be_soc_mld->ppe_vp_profile[
  2557. vp_params.ppe_vp_profile_idx];
  2558. *src_info = ppe_vp_profile->vp_num;
  2559. return qdf_status;
  2560. }
  2561. #else
  2562. static QDF_STATUS dp_get_ppe_info_for_vap(struct cdp_soc_t *cdp_soc,
  2563. struct dp_soc *mld_soc,
  2564. struct dp_peer *pr_peer,
  2565. uint16_t *src_info)
  2566. {
  2567. return QDF_STATUS_E_NOSUPPORT;
  2568. }
  2569. #endif
  2570. QDF_STATUS dp_htt_reo_migration(struct dp_soc *soc, uint16_t peer_id,
  2571. uint16_t ml_peer_id, uint16_t vdev_id,
  2572. uint8_t pdev_id, uint8_t chip_id)
  2573. {
  2574. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2575. struct dp_mlo_ctxt *dp_mlo = be_soc->ml_ctxt;
  2576. uint16_t mld_peer_id = dp_gen_ml_peer_id(soc, ml_peer_id);
  2577. struct dp_soc *pr_soc = NULL;
  2578. struct dp_soc *current_pr_soc = NULL;
  2579. struct hal_reo_cmd_params params;
  2580. struct dp_rx_tid *rx_tid;
  2581. struct dp_peer *pr_peer = NULL;
  2582. struct dp_peer *mld_peer = NULL;
  2583. struct dp_soc *mld_soc = NULL;
  2584. struct dp_peer *current_pr_peer = NULL;
  2585. struct dp_peer_info *peer_info;
  2586. struct dp_vdev_be *be_vdev;
  2587. struct cdp_soc_t *cdp_soc;
  2588. uint16_t src_info = 0;
  2589. QDF_STATUS status;
  2590. if (!dp_mlo) {
  2591. dp_htt_err("Invalid dp_mlo ctxt");
  2592. return QDF_STATUS_E_FAILURE;
  2593. }
  2594. pr_soc = dp_mlo_get_soc_ref_by_chip_id(dp_mlo, chip_id);
  2595. if (!pr_soc) {
  2596. dp_htt_err("Invalid soc");
  2597. return QDF_STATUS_E_FAILURE;
  2598. }
  2599. pr_peer = pr_soc->peer_id_to_obj_map[peer_id];
  2600. if (!pr_peer || !(IS_MLO_DP_LINK_PEER(pr_peer))) {
  2601. dp_htt_err("Invalid peer");
  2602. return QDF_STATUS_E_FAILURE;
  2603. }
  2604. mld_peer = DP_GET_MLD_PEER_FROM_PEER(pr_peer);
  2605. if (!mld_peer || (mld_peer->peer_id != mld_peer_id)) {
  2606. dp_htt_err("Invalid mld peer");
  2607. return QDF_STATUS_E_FAILURE;
  2608. }
  2609. current_pr_peer = dp_get_primary_link_peer_by_id(
  2610. pr_soc,
  2611. mld_peer->peer_id,
  2612. DP_MOD_ID_HTT);
  2613. if (!current_pr_peer || (current_pr_peer == pr_peer)) {
  2614. dp_htt_err("Invalid peer");
  2615. return QDF_STATUS_E_FAILURE;
  2616. }
  2617. be_vdev = dp_get_be_vdev_from_dp_vdev(pr_peer->vdev);
  2618. if (!be_vdev) {
  2619. dp_htt_err("Invalid be vdev");
  2620. return QDF_STATUS_E_FAILURE;
  2621. }
  2622. mld_soc = mld_peer->vdev->pdev->soc;
  2623. cdp_soc = &mld_soc->cdp_soc;
  2624. status = dp_get_ppe_info_for_vap(cdp_soc, mld_soc, pr_peer, &src_info);
  2625. if (status == QDF_STATUS_E_NULL_VALUE) {
  2626. dp_htt_err("Invalid ppe info for the vdev");
  2627. return QDF_STATUS_E_FAILURE;
  2628. }
  2629. current_pr_soc = current_pr_peer->vdev->pdev->soc;
  2630. /* Making existing primary peer as non primary */
  2631. current_pr_peer->primary_link = 0;
  2632. dp_peer_unref_delete(current_pr_peer, DP_MOD_ID_HTT);
  2633. dp_peer_rx_reo_shared_qaddr_delete(current_pr_soc, mld_peer);
  2634. peer_info = qdf_mem_malloc(sizeof(struct dp_peer_info));
  2635. if (!peer_info) {
  2636. dp_htt_err("Malloc failed");
  2637. return QDF_STATUS_E_FAILURE;
  2638. }
  2639. peer_info->primary_peer_id = peer_id;
  2640. peer_info->chip_id = chip_id;
  2641. qdf_mem_zero(&params, sizeof(params));
  2642. rx_tid = &mld_peer->rx_tid[0];
  2643. params.std.need_status = 1;
  2644. params.std.addr_lo = rx_tid->hw_qdesc_paddr & 0xffffffff;
  2645. params.std.addr_hi = (uint64_t)(rx_tid->hw_qdesc_paddr) >> 32;
  2646. params.u.fl_cache_params.flush_no_inval = 0;
  2647. params.u.fl_cache_params.flush_entire_cache = 1;
  2648. status = dp_reo_send_cmd(current_pr_soc, CMD_FLUSH_CACHE, &params,
  2649. dp_primary_link_migration,
  2650. (void *)peer_info);
  2651. if (status != QDF_STATUS_SUCCESS) {
  2652. dp_htt_err("Reo flush failed");
  2653. qdf_mem_free(peer_info);
  2654. dp_h2t_ptqm_migration_msg_send(pr_soc, vdev_id, pdev_id,
  2655. chip_id, peer_id, ml_peer_id,
  2656. src_info, QDF_STATUS_E_FAILURE);
  2657. }
  2658. qdf_mem_zero(&params, sizeof(params));
  2659. params.std.need_status = 0;
  2660. params.std.addr_lo = rx_tid->hw_qdesc_paddr & 0xffffffff;
  2661. params.std.addr_hi = (uint64_t)(rx_tid->hw_qdesc_paddr) >> 32;
  2662. params.u.unblk_cache_params.type = UNBLOCK_CACHE;
  2663. dp_reo_send_cmd(current_pr_soc, CMD_UNBLOCK_CACHE, &params, NULL, NULL);
  2664. dp_h2t_ptqm_migration_msg_send(pr_soc, vdev_id, pdev_id,
  2665. chip_id, peer_id, ml_peer_id,
  2666. src_info, QDF_STATUS_SUCCESS);
  2667. return QDF_STATUS_SUCCESS;
  2668. }
  2669. #endif