dp_parser.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/of_gpio.h>
  6. #include <linux/of_platform.h>
  7. #include "dp_parser.h"
  8. #include "dp_debug.h"
  9. static void dp_parser_unmap_io_resources(struct dp_parser *parser)
  10. {
  11. int i = 0;
  12. struct dp_io *io = &parser->io;
  13. for (i = 0; i < io->len; i++)
  14. msm_dss_iounmap(&io->data[i].io);
  15. }
  16. static int dp_parser_reg(struct dp_parser *parser)
  17. {
  18. int rc = 0, i = 0;
  19. u32 reg_count;
  20. struct platform_device *pdev = parser->pdev;
  21. struct dp_io *io = &parser->io;
  22. struct device *dev = &pdev->dev;
  23. reg_count = of_property_count_strings(dev->of_node, "reg-names");
  24. if (reg_count <= 0) {
  25. DP_ERR("no reg defined\n");
  26. return -EINVAL;
  27. }
  28. io->len = reg_count;
  29. io->data = devm_kzalloc(dev, sizeof(struct dp_io_data) * reg_count,
  30. GFP_KERNEL);
  31. if (!io->data)
  32. return -ENOMEM;
  33. for (i = 0; i < reg_count; i++) {
  34. of_property_read_string_index(dev->of_node,
  35. "reg-names", i, &io->data[i].name);
  36. rc = msm_dss_ioremap_byname(pdev, &io->data[i].io,
  37. io->data[i].name);
  38. if (rc) {
  39. DP_ERR("unable to remap %s resources\n",
  40. io->data[i].name);
  41. goto err;
  42. }
  43. }
  44. return 0;
  45. err:
  46. dp_parser_unmap_io_resources(parser);
  47. return rc;
  48. }
  49. static const char *dp_get_phy_aux_config_property(u32 cfg_type)
  50. {
  51. switch (cfg_type) {
  52. case PHY_AUX_CFG0:
  53. return "qcom,aux-cfg0-settings";
  54. case PHY_AUX_CFG1:
  55. return "qcom,aux-cfg1-settings";
  56. case PHY_AUX_CFG2:
  57. return "qcom,aux-cfg2-settings";
  58. case PHY_AUX_CFG3:
  59. return "qcom,aux-cfg3-settings";
  60. case PHY_AUX_CFG4:
  61. return "qcom,aux-cfg4-settings";
  62. case PHY_AUX_CFG5:
  63. return "qcom,aux-cfg5-settings";
  64. case PHY_AUX_CFG6:
  65. return "qcom,aux-cfg6-settings";
  66. case PHY_AUX_CFG7:
  67. return "qcom,aux-cfg7-settings";
  68. case PHY_AUX_CFG8:
  69. return "qcom,aux-cfg8-settings";
  70. case PHY_AUX_CFG9:
  71. return "qcom,aux-cfg9-settings";
  72. default:
  73. return "unknown";
  74. }
  75. }
  76. static void dp_parser_phy_aux_cfg_reset(struct dp_parser *parser)
  77. {
  78. int i = 0;
  79. for (i = 0; i < PHY_AUX_CFG_MAX; i++)
  80. parser->aux_cfg[i] = (const struct dp_aux_cfg){ 0 };
  81. }
  82. static int dp_parser_aux(struct dp_parser *parser)
  83. {
  84. struct device_node *of_node = parser->pdev->dev.of_node;
  85. int len = 0, i = 0, j = 0, config_count = 0;
  86. const char *data;
  87. int const minimum_config_count = 1;
  88. for (i = 0; i < PHY_AUX_CFG_MAX; i++) {
  89. const char *property = dp_get_phy_aux_config_property(i);
  90. data = of_get_property(of_node, property, &len);
  91. if (!data) {
  92. DP_ERR("Unable to read %s\n", property);
  93. goto error;
  94. }
  95. config_count = len - 1;
  96. if ((config_count < minimum_config_count) ||
  97. (config_count > DP_AUX_CFG_MAX_VALUE_CNT)) {
  98. DP_ERR("Invalid config count (%d) configs for %s\n",
  99. config_count, property);
  100. goto error;
  101. }
  102. parser->aux_cfg[i].offset = data[0];
  103. parser->aux_cfg[i].cfg_cnt = config_count;
  104. DP_DEBUG("%s offset=0x%x, cfg_cnt=%d\n",
  105. property,
  106. parser->aux_cfg[i].offset,
  107. parser->aux_cfg[i].cfg_cnt);
  108. for (j = 1; j < len; j++) {
  109. parser->aux_cfg[i].lut[j - 1] = data[j];
  110. DP_DEBUG("%s lut[%d]=0x%x\n",
  111. property,
  112. i,
  113. parser->aux_cfg[i].lut[j - 1]);
  114. }
  115. }
  116. return 0;
  117. error:
  118. dp_parser_phy_aux_cfg_reset(parser);
  119. return -EINVAL;
  120. }
  121. static int dp_parser_misc(struct dp_parser *parser)
  122. {
  123. int rc = 0, len = 0, i = 0;
  124. const char *data = NULL;
  125. struct device_node *of_node = parser->pdev->dev.of_node;
  126. data = of_get_property(of_node, "qcom,logical2physical-lane-map", &len);
  127. if (data && (len == DP_MAX_PHY_LN)) {
  128. for (i = 0; i < len; i++)
  129. parser->l_map[i] = data[i];
  130. }
  131. data = of_get_property(of_node, "qcom,pn-swap-lane-map", &len);
  132. if (data && (len == DP_MAX_PHY_LN)) {
  133. for (i = 0; i < len; i++)
  134. parser->l_pnswap |= (data[i] & 0x01) << i;
  135. }
  136. rc = of_property_read_u32(of_node,
  137. "qcom,max-pclk-frequency-khz", &parser->max_pclk_khz);
  138. if (rc)
  139. parser->max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ;
  140. rc = of_property_read_u32(of_node,
  141. "qcom,max-lclk-frequency-khz", &parser->max_lclk_khz);
  142. if (rc)
  143. parser->max_lclk_khz = DP_MAX_LINK_CLK_KHZ;
  144. return 0;
  145. }
  146. static int dp_parser_msm_hdcp_dev(struct dp_parser *parser)
  147. {
  148. struct device_node *node;
  149. struct platform_device *pdev;
  150. node = of_find_compatible_node(NULL, NULL, "qcom,msm-hdcp");
  151. if (!node) {
  152. // This is a non-fatal error, module initialization can proceed
  153. DP_WARN("couldn't find msm-hdcp node\n");
  154. return 0;
  155. }
  156. pdev = of_find_device_by_node(node);
  157. if (!pdev) {
  158. // This is a non-fatal error, module initialization can proceed
  159. DP_WARN("couldn't find msm-hdcp pdev\n");
  160. return 0;
  161. }
  162. parser->msm_hdcp_dev = &pdev->dev;
  163. return 0;
  164. }
  165. static int dp_parser_pinctrl(struct dp_parser *parser)
  166. {
  167. int rc = 0;
  168. struct dp_pinctrl *pinctrl = &parser->pinctrl;
  169. pinctrl->pin = devm_pinctrl_get(&parser->pdev->dev);
  170. if (IS_ERR_OR_NULL(pinctrl->pin)) {
  171. DP_DEBUG("failed to get pinctrl, rc=%d\n", rc);
  172. goto error;
  173. }
  174. if (parser->no_aux_switch && parser->lphw_hpd) {
  175. pinctrl->state_hpd_tlmm = pinctrl->state_hpd_ctrl = NULL;
  176. pinctrl->state_hpd_tlmm = pinctrl_lookup_state(pinctrl->pin,
  177. "mdss_dp_hpd_tlmm");
  178. if (!IS_ERR_OR_NULL(pinctrl->state_hpd_tlmm)) {
  179. pinctrl->state_hpd_ctrl = pinctrl_lookup_state(
  180. pinctrl->pin, "mdss_dp_hpd_ctrl");
  181. }
  182. if (!pinctrl->state_hpd_tlmm || !pinctrl->state_hpd_ctrl) {
  183. pinctrl->state_hpd_tlmm = NULL;
  184. pinctrl->state_hpd_ctrl = NULL;
  185. DP_DEBUG("tlmm or ctrl pinctrl state does not exist\n");
  186. }
  187. }
  188. pinctrl->state_active = pinctrl_lookup_state(pinctrl->pin,
  189. "mdss_dp_active");
  190. if (IS_ERR_OR_NULL(pinctrl->state_active)) {
  191. rc = PTR_ERR(pinctrl->state_active);
  192. DP_ERR("failed to get pinctrl active state, rc=%d\n", rc);
  193. goto error;
  194. }
  195. pinctrl->state_suspend = pinctrl_lookup_state(pinctrl->pin,
  196. "mdss_dp_sleep");
  197. if (IS_ERR_OR_NULL(pinctrl->state_suspend)) {
  198. rc = PTR_ERR(pinctrl->state_suspend);
  199. DP_ERR("failed to get pinctrl suspend state, rc=%d\n", rc);
  200. goto error;
  201. }
  202. error:
  203. return rc;
  204. }
  205. static int dp_parser_gpio(struct dp_parser *parser)
  206. {
  207. int i = 0;
  208. struct device *dev = &parser->pdev->dev;
  209. struct device_node *of_node = dev->of_node;
  210. struct dss_module_power *mp = &parser->mp[DP_CORE_PM];
  211. static const char * const dp_gpios[] = {
  212. "qcom,aux-en-gpio",
  213. "qcom,aux-sel-gpio",
  214. "qcom,usbplug-cc-gpio",
  215. };
  216. if (of_find_property(of_node, "qcom,dp-hpd-gpio", NULL)) {
  217. parser->no_aux_switch = true;
  218. parser->lphw_hpd = of_find_property(of_node,
  219. "qcom,dp-low-power-hw-hpd", NULL);
  220. return 0;
  221. }
  222. if (of_find_property(of_node, "qcom,dp-gpio-aux-switch", NULL))
  223. parser->gpio_aux_switch = true;
  224. mp->gpio_config = devm_kzalloc(dev,
  225. sizeof(struct dss_gpio) * ARRAY_SIZE(dp_gpios), GFP_KERNEL);
  226. if (!mp->gpio_config)
  227. return -ENOMEM;
  228. mp->num_gpio = ARRAY_SIZE(dp_gpios);
  229. for (i = 0; i < ARRAY_SIZE(dp_gpios); i++) {
  230. mp->gpio_config[i].gpio = of_get_named_gpio(of_node,
  231. dp_gpios[i], 0);
  232. if (!gpio_is_valid(mp->gpio_config[i].gpio)) {
  233. DP_DEBUG("%s gpio not specified\n", dp_gpios[i]);
  234. /* In case any gpio was not specified, we think gpio
  235. * aux switch also was not specified.
  236. */
  237. parser->gpio_aux_switch = false;
  238. continue;
  239. }
  240. strlcpy(mp->gpio_config[i].gpio_name, dp_gpios[i],
  241. sizeof(mp->gpio_config[i].gpio_name));
  242. mp->gpio_config[i].value = 0;
  243. }
  244. return 0;
  245. }
  246. static const char *dp_parser_supply_node_name(enum dp_pm_type module)
  247. {
  248. switch (module) {
  249. case DP_CORE_PM: return "qcom,core-supply-entries";
  250. case DP_CTRL_PM: return "qcom,ctrl-supply-entries";
  251. case DP_PHY_PM: return "qcom,phy-supply-entries";
  252. case DP_PLL_PM: return "qcom,pll-supply-entries";
  253. default: return "???";
  254. }
  255. }
  256. static int dp_parser_get_vreg(struct dp_parser *parser,
  257. enum dp_pm_type module)
  258. {
  259. int i = 0, rc = 0;
  260. u32 tmp = 0;
  261. const char *pm_supply_name = NULL;
  262. struct device_node *supply_node = NULL;
  263. struct device_node *of_node = parser->pdev->dev.of_node;
  264. struct device_node *supply_root_node = NULL;
  265. struct dss_module_power *mp = &parser->mp[module];
  266. mp->num_vreg = 0;
  267. pm_supply_name = dp_parser_supply_node_name(module);
  268. supply_root_node = of_get_child_by_name(of_node, pm_supply_name);
  269. if (!supply_root_node) {
  270. DP_DEBUG("no supply entry present: %s\n", pm_supply_name);
  271. goto novreg;
  272. }
  273. mp->num_vreg = of_get_available_child_count(supply_root_node);
  274. if (mp->num_vreg == 0) {
  275. DP_DEBUG("no vreg\n");
  276. goto novreg;
  277. } else {
  278. DP_DEBUG("vreg found. count=%d\n", mp->num_vreg);
  279. }
  280. mp->vreg_config = devm_kzalloc(&parser->pdev->dev,
  281. sizeof(struct dss_vreg) * mp->num_vreg, GFP_KERNEL);
  282. if (!mp->vreg_config) {
  283. rc = -ENOMEM;
  284. goto error;
  285. }
  286. for_each_child_of_node(supply_root_node, supply_node) {
  287. const char *st = NULL;
  288. /* vreg-name */
  289. rc = of_property_read_string(supply_node,
  290. "qcom,supply-name", &st);
  291. if (rc) {
  292. DP_ERR("error reading name. rc=%d\n",
  293. rc);
  294. goto error;
  295. }
  296. snprintf(mp->vreg_config[i].vreg_name,
  297. ARRAY_SIZE((mp->vreg_config[i].vreg_name)), "%s", st);
  298. /* vreg-min-voltage */
  299. rc = of_property_read_u32(supply_node,
  300. "qcom,supply-min-voltage", &tmp);
  301. if (rc) {
  302. DP_ERR("error reading min volt. rc=%d\n",
  303. rc);
  304. goto error;
  305. }
  306. mp->vreg_config[i].min_voltage = tmp;
  307. /* vreg-max-voltage */
  308. rc = of_property_read_u32(supply_node,
  309. "qcom,supply-max-voltage", &tmp);
  310. if (rc) {
  311. DP_ERR("error reading max volt. rc=%d\n",
  312. rc);
  313. goto error;
  314. }
  315. mp->vreg_config[i].max_voltage = tmp;
  316. /* enable-load */
  317. rc = of_property_read_u32(supply_node,
  318. "qcom,supply-enable-load", &tmp);
  319. if (rc) {
  320. DP_ERR("error reading enable load. rc=%d\n",
  321. rc);
  322. goto error;
  323. }
  324. mp->vreg_config[i].enable_load = tmp;
  325. /* disable-load */
  326. rc = of_property_read_u32(supply_node,
  327. "qcom,supply-disable-load", &tmp);
  328. if (rc) {
  329. DP_ERR("error reading disable load. rc=%d\n",
  330. rc);
  331. goto error;
  332. }
  333. mp->vreg_config[i].disable_load = tmp;
  334. DP_DEBUG("%s min=%d, max=%d, enable=%d, disable=%d\n",
  335. mp->vreg_config[i].vreg_name,
  336. mp->vreg_config[i].min_voltage,
  337. mp->vreg_config[i].max_voltage,
  338. mp->vreg_config[i].enable_load,
  339. mp->vreg_config[i].disable_load
  340. );
  341. ++i;
  342. }
  343. return rc;
  344. error:
  345. if (mp->vreg_config) {
  346. devm_kfree(&parser->pdev->dev, mp->vreg_config);
  347. mp->vreg_config = NULL;
  348. }
  349. novreg:
  350. mp->num_vreg = 0;
  351. return rc;
  352. }
  353. static void dp_parser_put_vreg_data(struct device *dev,
  354. struct dss_module_power *mp)
  355. {
  356. if (!mp) {
  357. DEV_ERR("invalid input\n");
  358. return;
  359. }
  360. if (mp->vreg_config) {
  361. devm_kfree(dev, mp->vreg_config);
  362. mp->vreg_config = NULL;
  363. }
  364. mp->num_vreg = 0;
  365. }
  366. static int dp_parser_regulator(struct dp_parser *parser)
  367. {
  368. int i, rc = 0;
  369. struct platform_device *pdev = parser->pdev;
  370. /* Parse the regulator information */
  371. for (i = DP_CORE_PM; i < DP_MAX_PM; i++) {
  372. rc = dp_parser_get_vreg(parser, i);
  373. if (rc) {
  374. DP_ERR("get_dt_vreg_data failed for %s. rc=%d\n",
  375. dp_parser_pm_name(i), rc);
  376. i--;
  377. for (; i >= DP_CORE_PM; i--)
  378. dp_parser_put_vreg_data(&pdev->dev,
  379. &parser->mp[i]);
  380. break;
  381. }
  382. }
  383. return rc;
  384. }
  385. static bool dp_parser_check_prefix(const char *clk_prefix, const char *clk_name)
  386. {
  387. return !!strnstr(clk_name, clk_prefix, strlen(clk_name));
  388. }
  389. static void dp_parser_put_clk_data(struct device *dev,
  390. struct dss_module_power *mp)
  391. {
  392. if (!mp) {
  393. DEV_ERR("%s: invalid input\n", __func__);
  394. return;
  395. }
  396. if (mp->clk_config) {
  397. devm_kfree(dev, mp->clk_config);
  398. mp->clk_config = NULL;
  399. }
  400. mp->num_clk = 0;
  401. }
  402. static void dp_parser_put_gpio_data(struct device *dev,
  403. struct dss_module_power *mp)
  404. {
  405. if (!mp) {
  406. DEV_ERR("%s: invalid input\n", __func__);
  407. return;
  408. }
  409. if (mp->gpio_config) {
  410. devm_kfree(dev, mp->gpio_config);
  411. mp->gpio_config = NULL;
  412. }
  413. mp->num_gpio = 0;
  414. }
  415. static int dp_parser_init_clk_data(struct dp_parser *parser)
  416. {
  417. int num_clk = 0, i = 0, rc = 0;
  418. int core_clk_count = 0, link_clk_count = 0;
  419. int strm0_clk_count = 0, strm1_clk_count = 0;
  420. const char *core_clk = "core";
  421. const char *strm0_clk = "strm0";
  422. const char *strm1_clk = "strm1";
  423. const char *link_clk = "link";
  424. const char *clk_name;
  425. struct device *dev = &parser->pdev->dev;
  426. struct dss_module_power *core_power = &parser->mp[DP_CORE_PM];
  427. struct dss_module_power *strm0_power = &parser->mp[DP_STREAM0_PM];
  428. struct dss_module_power *strm1_power = &parser->mp[DP_STREAM1_PM];
  429. struct dss_module_power *link_power = &parser->mp[DP_LINK_PM];
  430. num_clk = of_property_count_strings(dev->of_node, "clock-names");
  431. if (num_clk <= 0) {
  432. DP_ERR("no clocks are defined\n");
  433. rc = -EINVAL;
  434. goto exit;
  435. }
  436. for (i = 0; i < num_clk; i++) {
  437. of_property_read_string_index(dev->of_node,
  438. "clock-names", i, &clk_name);
  439. if (dp_parser_check_prefix(core_clk, clk_name))
  440. core_clk_count++;
  441. if (dp_parser_check_prefix(strm0_clk, clk_name))
  442. strm0_clk_count++;
  443. if (dp_parser_check_prefix(strm1_clk, clk_name))
  444. strm1_clk_count++;
  445. if (dp_parser_check_prefix(link_clk, clk_name))
  446. link_clk_count++;
  447. }
  448. /* Initialize the CORE power module */
  449. if (core_clk_count <= 0) {
  450. DP_ERR("no core clocks are defined\n");
  451. rc = -EINVAL;
  452. goto exit;
  453. }
  454. core_power->num_clk = core_clk_count;
  455. core_power->clk_config = devm_kzalloc(dev,
  456. sizeof(struct dss_clk) * core_power->num_clk,
  457. GFP_KERNEL);
  458. if (!core_power->clk_config) {
  459. rc = -EINVAL;
  460. goto exit;
  461. }
  462. /* Initialize the STREAM0 power module */
  463. if (strm0_clk_count <= 0) {
  464. DP_DEBUG("no strm0 clocks are defined\n");
  465. } else {
  466. strm0_power->num_clk = strm0_clk_count;
  467. strm0_power->clk_config = devm_kzalloc(dev,
  468. sizeof(struct dss_clk) * strm0_power->num_clk,
  469. GFP_KERNEL);
  470. if (!strm0_power->clk_config) {
  471. strm0_power->num_clk = 0;
  472. rc = -EINVAL;
  473. goto strm0_clock_error;
  474. }
  475. }
  476. /* Initialize the STREAM1 power module */
  477. if (strm1_clk_count <= 0) {
  478. DP_DEBUG("no strm1 clocks are defined\n");
  479. } else {
  480. strm1_power->num_clk = strm1_clk_count;
  481. strm1_power->clk_config = devm_kzalloc(dev,
  482. sizeof(struct dss_clk) * strm1_power->num_clk,
  483. GFP_KERNEL);
  484. if (!strm1_power->clk_config) {
  485. strm1_power->num_clk = 0;
  486. rc = -EINVAL;
  487. goto strm1_clock_error;
  488. }
  489. }
  490. /* Initialize the link power module */
  491. if (link_clk_count <= 0) {
  492. DP_ERR("no link clocks are defined\n");
  493. rc = -EINVAL;
  494. goto link_clock_error;
  495. }
  496. link_power->num_clk = link_clk_count;
  497. link_power->clk_config = devm_kzalloc(dev,
  498. sizeof(struct dss_clk) * link_power->num_clk,
  499. GFP_KERNEL);
  500. if (!link_power->clk_config) {
  501. link_power->num_clk = 0;
  502. rc = -EINVAL;
  503. goto link_clock_error;
  504. }
  505. return rc;
  506. link_clock_error:
  507. dp_parser_put_clk_data(dev, strm1_power);
  508. strm1_clock_error:
  509. dp_parser_put_clk_data(dev, strm0_power);
  510. strm0_clock_error:
  511. dp_parser_put_clk_data(dev, core_power);
  512. exit:
  513. return rc;
  514. }
  515. static int dp_parser_clock(struct dp_parser *parser)
  516. {
  517. int rc = 0, i = 0;
  518. int num_clk = 0;
  519. int core_clk_index = 0, link_clk_index = 0;
  520. int core_clk_count = 0, link_clk_count = 0;
  521. int strm0_clk_index = 0, strm1_clk_index = 0;
  522. int strm0_clk_count = 0, strm1_clk_count = 0;
  523. int clock_mmrm = 0;
  524. const char *clk_name;
  525. const char *core_clk = "core";
  526. const char *strm0_clk = "strm0";
  527. const char *strm1_clk = "strm1";
  528. const char *link_clk = "link";
  529. struct device *dev = &parser->pdev->dev;
  530. struct dss_module_power *core_power;
  531. struct dss_module_power *strm0_power;
  532. struct dss_module_power *strm1_power;
  533. struct dss_module_power *link_power;
  534. core_power = &parser->mp[DP_CORE_PM];
  535. strm0_power = &parser->mp[DP_STREAM0_PM];
  536. strm1_power = &parser->mp[DP_STREAM1_PM];
  537. link_power = &parser->mp[DP_LINK_PM];
  538. rc = dp_parser_init_clk_data(parser);
  539. if (rc) {
  540. DP_ERR("failed to initialize power data\n");
  541. rc = -EINVAL;
  542. goto exit;
  543. }
  544. core_clk_count = core_power->num_clk;
  545. link_clk_count = link_power->num_clk;
  546. strm0_clk_count = strm0_power->num_clk;
  547. strm1_clk_count = strm1_power->num_clk;
  548. num_clk = of_property_count_strings(dev->of_node, "clock-names");
  549. for (i = 0; i < num_clk; i++) {
  550. of_property_read_string_index(dev->of_node, "clock-names",
  551. i, &clk_name);
  552. if (dp_parser_check_prefix(core_clk, clk_name) &&
  553. core_clk_index < core_clk_count) {
  554. struct dss_clk *clk =
  555. &core_power->clk_config[core_clk_index];
  556. strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
  557. clk->type = DSS_CLK_AHB;
  558. core_clk_index++;
  559. } else if (dp_parser_check_prefix(link_clk, clk_name) &&
  560. link_clk_index < link_clk_count) {
  561. struct dss_clk *clk =
  562. &link_power->clk_config[link_clk_index];
  563. strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
  564. link_clk_index++;
  565. clock_mmrm = 0;
  566. of_property_read_u32_index(dev->of_node, "clock-mmrm", i, &clock_mmrm);
  567. if (clock_mmrm) {
  568. clk->type = DSS_CLK_MMRM;
  569. clk->mmrm.clk_id = clock_mmrm;
  570. } else if (!strcmp(clk_name, "link_clk_src")) {
  571. clk->type = DSS_CLK_PCLK;
  572. } else {
  573. clk->type = DSS_CLK_AHB;
  574. }
  575. } else if (dp_parser_check_prefix(strm0_clk, clk_name) &&
  576. strm0_clk_index < strm0_clk_count) {
  577. struct dss_clk *clk =
  578. &strm0_power->clk_config[strm0_clk_index];
  579. strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
  580. strm0_clk_index++;
  581. clk->type = DSS_CLK_PCLK;
  582. } else if (dp_parser_check_prefix(strm1_clk, clk_name) &&
  583. strm1_clk_index < strm1_clk_count) {
  584. struct dss_clk *clk =
  585. &strm1_power->clk_config[strm1_clk_index];
  586. strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
  587. strm1_clk_index++;
  588. clk->type = DSS_CLK_PCLK;
  589. }
  590. }
  591. DP_DEBUG("clock parsing successful\n");
  592. exit:
  593. return rc;
  594. }
  595. static int dp_parser_catalog(struct dp_parser *parser)
  596. {
  597. int rc;
  598. u32 version;
  599. struct device *dev = &parser->pdev->dev;
  600. rc = of_property_read_u32(dev->of_node, "qcom,phy-version", &version);
  601. if (!rc)
  602. parser->hw_cfg.phy_version = version;
  603. return 0;
  604. }
  605. static int dp_parser_mst(struct dp_parser *parser)
  606. {
  607. struct device *dev = &parser->pdev->dev;
  608. int i;
  609. parser->has_mst = of_property_read_bool(dev->of_node,
  610. "qcom,mst-enable");
  611. parser->has_mst_sideband = parser->has_mst;
  612. DP_DEBUG("mst parsing successful. mst:%d\n", parser->has_mst);
  613. for (i = 0; i < MAX_DP_MST_STREAMS; i++) {
  614. of_property_read_u32_index(dev->of_node,
  615. "qcom,mst-fixed-topology-ports", i,
  616. &parser->mst_fixed_port[i]);
  617. }
  618. return 0;
  619. }
  620. static void dp_parser_dsc(struct dp_parser *parser)
  621. {
  622. struct device *dev = &parser->pdev->dev;
  623. parser->dsc_feature_enable = of_property_read_bool(dev->of_node,
  624. "qcom,dsc-feature-enable");
  625. parser->dsc_continuous_pps = of_property_read_bool(dev->of_node,
  626. "qcom,dsc-continuous-pps");
  627. DP_DEBUG("dsc parsing successful. dsc:%d\n",
  628. parser->dsc_feature_enable);
  629. DP_DEBUG("cont_pps:%d\n",
  630. parser->dsc_continuous_pps);
  631. }
  632. static void dp_parser_qos(struct dp_parser *parser)
  633. {
  634. struct device *dev = &parser->pdev->dev;
  635. u32 mask, latency;
  636. int rc;
  637. rc = of_property_read_u32(dev->of_node, "qcom,qos-cpu-latency-us", &latency);
  638. if (rc)
  639. return;
  640. rc = of_property_read_u32(dev->of_node, "qcom,qos-cpu-mask", &mask);
  641. if (rc)
  642. return;
  643. parser->qos_cpu_mask = mask;
  644. parser->qos_cpu_latency = latency;
  645. DP_DEBUG("qos parsing successful. mask:%x latency:%ld\n", mask, latency);
  646. }
  647. static void dp_parser_fec(struct dp_parser *parser)
  648. {
  649. struct device *dev = &parser->pdev->dev;
  650. parser->fec_feature_enable = of_property_read_bool(dev->of_node,
  651. "qcom,fec-feature-enable");
  652. DP_DEBUG("fec parsing successful. fec:%d\n",
  653. parser->fec_feature_enable);
  654. }
  655. static void dp_parser_widebus(struct dp_parser *parser)
  656. {
  657. struct device *dev = &parser->pdev->dev;
  658. parser->has_widebus = of_property_read_bool(dev->of_node,
  659. "qcom,widebus-enable");
  660. DP_DEBUG("widebus parsing successful. widebus:%d\n",
  661. parser->has_widebus);
  662. }
  663. static int dp_parser_parse(struct dp_parser *parser)
  664. {
  665. int rc = 0;
  666. if (!parser) {
  667. DP_ERR("invalid input\n");
  668. rc = -EINVAL;
  669. goto err;
  670. }
  671. rc = dp_parser_reg(parser);
  672. if (rc)
  673. goto err;
  674. rc = dp_parser_aux(parser);
  675. if (rc)
  676. goto err;
  677. rc = dp_parser_misc(parser);
  678. if (rc)
  679. goto err;
  680. rc = dp_parser_clock(parser);
  681. if (rc)
  682. goto err;
  683. rc = dp_parser_regulator(parser);
  684. if (rc)
  685. goto err;
  686. rc = dp_parser_gpio(parser);
  687. if (rc)
  688. goto err;
  689. rc = dp_parser_catalog(parser);
  690. if (rc)
  691. goto err;
  692. rc = dp_parser_pinctrl(parser);
  693. if (rc)
  694. goto err;
  695. rc = dp_parser_msm_hdcp_dev(parser);
  696. if (rc)
  697. goto err;
  698. rc = dp_parser_mst(parser);
  699. if (rc)
  700. goto err;
  701. dp_parser_dsc(parser);
  702. dp_parser_fec(parser);
  703. dp_parser_widebus(parser);
  704. dp_parser_qos(parser);
  705. err:
  706. return rc;
  707. }
  708. static struct dp_io_data *dp_parser_get_io(struct dp_parser *dp_parser,
  709. char *name)
  710. {
  711. int i = 0;
  712. struct dp_io *io;
  713. if (!dp_parser) {
  714. DP_ERR("invalid input\n");
  715. goto err;
  716. }
  717. io = &dp_parser->io;
  718. for (i = 0; i < io->len; i++) {
  719. struct dp_io_data *data = &io->data[i];
  720. if (!strcmp(data->name, name))
  721. return data;
  722. }
  723. err:
  724. return NULL;
  725. }
  726. static void dp_parser_get_io_buf(struct dp_parser *dp_parser, char *name)
  727. {
  728. int i = 0;
  729. struct dp_io *io;
  730. if (!dp_parser) {
  731. DP_ERR("invalid input\n");
  732. return;
  733. }
  734. io = &dp_parser->io;
  735. for (i = 0; i < io->len; i++) {
  736. struct dp_io_data *data = &io->data[i];
  737. if (!strcmp(data->name, name)) {
  738. if (!data->buf)
  739. data->buf = devm_kzalloc(&dp_parser->pdev->dev,
  740. data->io.len, GFP_KERNEL);
  741. }
  742. }
  743. }
  744. static void dp_parser_clear_io_buf(struct dp_parser *dp_parser)
  745. {
  746. int i = 0;
  747. struct dp_io *io;
  748. if (!dp_parser) {
  749. DP_ERR("invalid input\n");
  750. return;
  751. }
  752. io = &dp_parser->io;
  753. for (i = 0; i < io->len; i++) {
  754. struct dp_io_data *data = &io->data[i];
  755. if (data->buf)
  756. devm_kfree(&dp_parser->pdev->dev, data->buf);
  757. data->buf = NULL;
  758. }
  759. }
  760. struct dp_parser *dp_parser_get(struct platform_device *pdev)
  761. {
  762. struct dp_parser *parser;
  763. parser = devm_kzalloc(&pdev->dev, sizeof(*parser), GFP_KERNEL);
  764. if (!parser)
  765. return ERR_PTR(-ENOMEM);
  766. parser->parse = dp_parser_parse;
  767. parser->get_io = dp_parser_get_io;
  768. parser->get_io_buf = dp_parser_get_io_buf;
  769. parser->clear_io_buf = dp_parser_clear_io_buf;
  770. parser->pdev = pdev;
  771. return parser;
  772. }
  773. void dp_parser_put(struct dp_parser *parser)
  774. {
  775. int i = 0;
  776. struct dss_module_power *power = NULL;
  777. if (!parser) {
  778. DP_ERR("invalid parser module\n");
  779. return;
  780. }
  781. power = parser->mp;
  782. for (i = 0; i < DP_MAX_PM; i++) {
  783. dp_parser_put_clk_data(&parser->pdev->dev, &power[i]);
  784. dp_parser_put_vreg_data(&parser->pdev->dev, &power[i]);
  785. dp_parser_put_gpio_data(&parser->pdev->dev, &power[i]);
  786. }
  787. dp_parser_clear_io_buf(parser);
  788. devm_kfree(&parser->pdev->dev, parser->io.data);
  789. devm_kfree(&parser->pdev->dev, parser);
  790. }