dp_be.c 85 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185
  1. /*
  2. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include <wlan_utility.h>
  20. #include <dp_internal.h>
  21. #include "dp_rings.h"
  22. #include <dp_htt.h>
  23. #include "dp_be.h"
  24. #include "dp_be_tx.h"
  25. #include "dp_be_rx.h"
  26. #ifdef WIFI_MONITOR_SUPPORT
  27. #if !defined(DISABLE_MON_CONFIG) && (defined(WLAN_PKT_CAPTURE_TX_2_0) || \
  28. defined(WLAN_PKT_CAPTURE_RX_2_0))
  29. #include "dp_mon_2.0.h"
  30. #endif
  31. #include "dp_mon.h"
  32. #endif
  33. #include <hal_be_api.h>
  34. #ifdef WLAN_SUPPORT_PPEDS
  35. #include "be/dp_ppeds.h"
  36. #include <ppe_vp_public.h>
  37. #include <ppe_drv_sc.h>
  38. #endif
  39. /* Generic AST entry aging timer value */
  40. #define DP_AST_AGING_TIMER_DEFAULT_MS 5000
  41. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  42. #define DP_TX_VDEV_ID_CHECK_ENABLE 0
  43. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  44. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  45. {1, 4, HAL_BE_WBM_SW4_BM_ID, 0},
  46. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  47. #ifdef QCA_WIFI_KIWI_V2
  48. {3, 5, HAL_BE_WBM_SW5_BM_ID, 0},
  49. {4, 6, HAL_BE_WBM_SW6_BM_ID, 0}
  50. #else
  51. {3, 6, HAL_BE_WBM_SW5_BM_ID, 0},
  52. {4, 7, HAL_BE_WBM_SW6_BM_ID, 0}
  53. #endif
  54. };
  55. #else
  56. #define DP_TX_VDEV_ID_CHECK_ENABLE 1
  57. static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
  58. {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
  59. {1, 1, HAL_BE_WBM_SW1_BM_ID, 0},
  60. {2, 2, HAL_BE_WBM_SW2_BM_ID, 0},
  61. {3, 3, HAL_BE_WBM_SW3_BM_ID, 0},
  62. {4, 4, HAL_BE_WBM_SW4_BM_ID, 0}
  63. };
  64. #endif
  65. #ifdef WLAN_SUPPORT_PPEDS
  66. static struct cdp_ppeds_txrx_ops dp_ops_ppeds_be = {
  67. .ppeds_entry_attach = dp_ppeds_attach_vdev_be,
  68. .ppeds_entry_detach = dp_ppeds_detach_vdev_be,
  69. .ppeds_set_int_pri2tid = dp_ppeds_set_int_pri2tid_be,
  70. .ppeds_update_int_pri2tid = dp_ppeds_update_int_pri2tid_be,
  71. .ppeds_entry_dump = dp_ppeds_dump_ppe_vp_tbl_be,
  72. .ppeds_enable_pri2tid = dp_ppeds_vdev_enable_pri2tid_be,
  73. .ppeds_vp_setup_recovery = dp_ppeds_vp_setup_on_fw_recovery,
  74. .ppeds_stats_sync = dp_ppeds_stats_sync_be,
  75. };
  76. static void dp_ppeds_rings_status(struct dp_soc *soc)
  77. {
  78. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  79. dp_print_ring_stat_from_hal(soc, &be_soc->reo2ppe_ring, REO2PPE);
  80. dp_print_ring_stat_from_hal(soc, &be_soc->ppe2tcl_ring, PPE2TCL);
  81. dp_print_ring_stat_from_hal(soc, &be_soc->ppeds_wbm_release_ring,
  82. WBM2SW_RELEASE);
  83. }
  84. static void dp_ppeds_inuse_desc(struct dp_soc *soc)
  85. {
  86. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  87. DP_PRINT_STATS("PPE-DS Tx Descriptors in Use = %u num_free %u",
  88. be_soc->ppeds_tx_desc.num_allocated,
  89. be_soc->ppeds_tx_desc.num_free);
  90. }
  91. #endif
  92. static void dp_soc_cfg_attach_be(struct dp_soc *soc)
  93. {
  94. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx = soc->wlan_cfg_ctx;
  95. dp_soc_cfg_attach(soc);
  96. wlan_cfg_set_rx_rel_ring_id(soc_cfg_ctx, WBM2SW_REL_ERR_RING_NUM);
  97. soc->wlan_cfg_ctx->tcl_wbm_map_array = g_tcl_wbm_map_array;
  98. /* this is used only when dmac mode is enabled */
  99. soc->num_rx_refill_buf_rings = 1;
  100. soc->wlan_cfg_ctx->notify_frame_support =
  101. DP_MARK_NOTIFY_FRAME_SUPPORT;
  102. }
  103. qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
  104. {
  105. switch (context_type) {
  106. case DP_CONTEXT_TYPE_SOC:
  107. return sizeof(struct dp_soc_be);
  108. case DP_CONTEXT_TYPE_PDEV:
  109. return sizeof(struct dp_pdev_be);
  110. case DP_CONTEXT_TYPE_VDEV:
  111. return sizeof(struct dp_vdev_be);
  112. case DP_CONTEXT_TYPE_PEER:
  113. return sizeof(struct dp_peer_be);
  114. default:
  115. return 0;
  116. }
  117. }
  118. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  119. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  120. /**
  121. * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
  122. * per wbm2sw ring
  123. *
  124. * @cc_cfg: HAL HW cookie conversion configuration structure pointer
  125. *
  126. * Return: None
  127. */
  128. #ifdef IPA_OPT_WIFI_DP
  129. static inline
  130. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  131. {
  132. cc_cfg->wbm2sw6_cc_en = 1;
  133. cc_cfg->wbm2sw5_cc_en = 0;
  134. cc_cfg->wbm2sw4_cc_en = 1;
  135. cc_cfg->wbm2sw3_cc_en = 1;
  136. cc_cfg->wbm2sw2_cc_en = 1;
  137. /* disable wbm2sw1 hw cc as it's for FW */
  138. cc_cfg->wbm2sw1_cc_en = 0;
  139. cc_cfg->wbm2sw0_cc_en = 1;
  140. cc_cfg->wbm2fw_cc_en = 0;
  141. }
  142. #else
  143. static inline
  144. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  145. {
  146. cc_cfg->wbm2sw6_cc_en = 1;
  147. cc_cfg->wbm2sw5_cc_en = 1;
  148. cc_cfg->wbm2sw4_cc_en = 1;
  149. cc_cfg->wbm2sw3_cc_en = 1;
  150. cc_cfg->wbm2sw2_cc_en = 1;
  151. /* disable wbm2sw1 hw cc as it's for FW */
  152. cc_cfg->wbm2sw1_cc_en = 0;
  153. cc_cfg->wbm2sw0_cc_en = 1;
  154. cc_cfg->wbm2fw_cc_en = 0;
  155. }
  156. #endif
  157. #else
  158. static inline
  159. void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
  160. {
  161. cc_cfg->wbm2sw6_cc_en = 1;
  162. cc_cfg->wbm2sw5_cc_en = 1;
  163. cc_cfg->wbm2sw4_cc_en = 1;
  164. cc_cfg->wbm2sw3_cc_en = 1;
  165. cc_cfg->wbm2sw2_cc_en = 1;
  166. cc_cfg->wbm2sw1_cc_en = 1;
  167. cc_cfg->wbm2sw0_cc_en = 1;
  168. cc_cfg->wbm2fw_cc_en = 0;
  169. }
  170. #endif
  171. #if defined(WLAN_SUPPORT_RX_FISA)
  172. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  173. {
  174. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  175. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  176. /* get CMEM for cookie conversion */
  177. if (soc->cmem_avail_size < DP_CMEM_FST_SIZE) {
  178. dp_err("cmem_size 0x%llx bytes < 16K", soc->cmem_avail_size);
  179. return QDF_STATUS_E_NOMEM;
  180. }
  181. soc->fst_cmem_size = DP_CMEM_FST_SIZE;
  182. soc->fst_cmem_base = soc->cmem_base +
  183. (soc->cmem_total_size - soc->cmem_avail_size);
  184. soc->cmem_avail_size -= soc->fst_cmem_size;
  185. dp_info("fst_cmem_base 0x%llx, fst_cmem_size 0x%llx",
  186. soc->fst_cmem_base, soc->fst_cmem_size);
  187. return QDF_STATUS_SUCCESS;
  188. }
  189. #else /* !WLAN_SUPPORT_RX_FISA */
  190. static QDF_STATUS dp_fisa_fst_cmem_addr_init(struct dp_soc *soc)
  191. {
  192. return QDF_STATUS_SUCCESS;
  193. }
  194. #endif
  195. /**
  196. * dp_cc_reg_cfg_init() - initialize and configure HW cookie
  197. * conversion register
  198. *
  199. * @soc: SOC handle
  200. * @is_4k_align: page address 4k aligned
  201. *
  202. * Return: None
  203. */
  204. static void dp_cc_reg_cfg_init(struct dp_soc *soc,
  205. bool is_4k_align)
  206. {
  207. struct hal_hw_cc_config cc_cfg = { 0 };
  208. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  209. if (soc->cdp_soc.ol_ops->get_con_mode &&
  210. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_FTM_MODE)
  211. return;
  212. if (!soc->wlan_cfg_ctx->hw_cc_enabled) {
  213. dp_info("INI skip HW CC register setting");
  214. return;
  215. }
  216. cc_cfg.lut_base_addr_31_0 = be_soc->cc_cmem_base;
  217. cc_cfg.cc_global_en = true;
  218. cc_cfg.page_4k_align = is_4k_align;
  219. cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
  220. cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
  221. /* 36th bit should be 1 then HW know this is CMEM address */
  222. cc_cfg.lut_base_addr_39_32 = 0x10;
  223. cc_cfg.error_path_cookie_conv_en = true;
  224. cc_cfg.release_path_cookie_conv_en = true;
  225. dp_cc_wbm_sw_en_cfg(&cc_cfg);
  226. hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
  227. }
  228. /**
  229. * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
  230. * @hal_soc_hdl: HAL SOC handle
  231. * @offset: CMEM address
  232. * @value: value to write
  233. *
  234. * Return: None.
  235. */
  236. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  237. uint32_t offset,
  238. uint32_t value)
  239. {
  240. hal_cmem_write(hal_soc_hdl, offset, value);
  241. }
  242. /**
  243. * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
  244. * HW cookie conversion
  245. *
  246. * @soc: SOC handle
  247. *
  248. * Return: 0 in case of success, else error value
  249. */
  250. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  251. {
  252. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  253. dp_info("cmem base 0x%llx, total size 0x%llx avail_size 0x%llx",
  254. soc->cmem_base, soc->cmem_total_size, soc->cmem_avail_size);
  255. /* get CMEM for cookie conversion */
  256. if (soc->cmem_avail_size < DP_CC_PPT_MEM_SIZE) {
  257. dp_err("cmem_size 0x%llx bytes < 4K", soc->cmem_avail_size);
  258. return QDF_STATUS_E_RESOURCES;
  259. }
  260. be_soc->cc_cmem_base = (uint32_t)(soc->cmem_base +
  261. DP_CC_MEM_OFFSET_IN_CMEM);
  262. soc->cmem_avail_size -= DP_CC_PPT_MEM_SIZE;
  263. dp_info("cc_cmem_base 0x%x, cmem_avail_size 0x%llx",
  264. be_soc->cc_cmem_base, soc->cmem_avail_size);
  265. return QDF_STATUS_SUCCESS;
  266. }
  267. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  268. uint8_t for_feature)
  269. {
  270. QDF_STATUS status = QDF_STATUS_E_NOMEM;
  271. switch (for_feature) {
  272. case COOKIE_CONVERSION:
  273. status = dp_hw_cc_cmem_addr_init(soc);
  274. break;
  275. case FISA_FST:
  276. status = dp_fisa_fst_cmem_addr_init(soc);
  277. break;
  278. default:
  279. dp_err("Invalid CMEM request");
  280. }
  281. return status;
  282. }
  283. #else
  284. static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
  285. bool is_4k_align) {}
  286. static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
  287. uint32_t offset,
  288. uint32_t value)
  289. { }
  290. static inline QDF_STATUS dp_hw_cc_cmem_addr_init(struct dp_soc *soc)
  291. {
  292. return QDF_STATUS_SUCCESS;
  293. }
  294. static QDF_STATUS dp_get_cmem_allocation(struct dp_soc *soc,
  295. uint8_t for_feature)
  296. {
  297. return QDF_STATUS_SUCCESS;
  298. }
  299. #endif
  300. QDF_STATUS
  301. dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
  302. struct dp_hw_cookie_conversion_t *cc_ctx,
  303. uint32_t num_descs,
  304. enum dp_desc_type desc_type,
  305. uint8_t desc_pool_id)
  306. {
  307. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  308. uint32_t num_spt_pages, i = 0;
  309. struct dp_spt_page_desc *spt_desc;
  310. struct qdf_mem_dma_page_t *dma_page;
  311. uint8_t chip_id;
  312. /* estimate how many SPT DDR pages needed */
  313. num_spt_pages = num_descs / DP_CC_SPT_PAGE_MAX_ENTRIES;
  314. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  315. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  316. dp_info("num_spt_pages needed %d", num_spt_pages);
  317. dp_desc_multi_pages_mem_alloc(soc, DP_HW_CC_SPT_PAGE_TYPE,
  318. &cc_ctx->page_pool, qdf_page_size,
  319. num_spt_pages, 0, false);
  320. if (!cc_ctx->page_pool.dma_pages) {
  321. dp_err("spt ddr pages allocation failed");
  322. return QDF_STATUS_E_RESOURCES;
  323. }
  324. cc_ctx->page_desc_base = qdf_mem_malloc(
  325. num_spt_pages * sizeof(struct dp_spt_page_desc));
  326. if (!cc_ctx->page_desc_base) {
  327. dp_err("spt page descs allocation failed");
  328. goto fail_0;
  329. }
  330. chip_id = dp_mlo_get_chip_id(soc);
  331. cc_ctx->cmem_offset = dp_desc_pool_get_cmem_base(chip_id, desc_pool_id,
  332. desc_type);
  333. /* initial page desc */
  334. spt_desc = cc_ctx->page_desc_base;
  335. dma_page = cc_ctx->page_pool.dma_pages;
  336. while (i < num_spt_pages) {
  337. /* check if page address 4K aligned */
  338. if (qdf_unlikely(dma_page[i].page_p_addr & 0xFFF)) {
  339. dp_err("non-4k aligned pages addr %pK",
  340. (void *)dma_page[i].page_p_addr);
  341. goto fail_1;
  342. }
  343. spt_desc[i].page_v_addr =
  344. dma_page[i].page_v_addr_start;
  345. spt_desc[i].page_p_addr =
  346. dma_page[i].page_p_addr;
  347. i++;
  348. }
  349. cc_ctx->total_page_num = num_spt_pages;
  350. qdf_spinlock_create(&cc_ctx->cc_lock);
  351. return QDF_STATUS_SUCCESS;
  352. fail_1:
  353. qdf_mem_free(cc_ctx->page_desc_base);
  354. fail_0:
  355. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  356. &cc_ctx->page_pool, 0, false);
  357. return QDF_STATUS_E_FAILURE;
  358. }
  359. QDF_STATUS
  360. dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
  361. struct dp_hw_cookie_conversion_t *cc_ctx)
  362. {
  363. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  364. qdf_mem_free(cc_ctx->page_desc_base);
  365. dp_desc_multi_pages_mem_free(soc, DP_HW_CC_SPT_PAGE_TYPE,
  366. &cc_ctx->page_pool, 0, false);
  367. qdf_spinlock_destroy(&cc_ctx->cc_lock);
  368. return QDF_STATUS_SUCCESS;
  369. }
  370. QDF_STATUS
  371. dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
  372. struct dp_hw_cookie_conversion_t *cc_ctx)
  373. {
  374. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  375. uint32_t i = 0;
  376. struct dp_spt_page_desc *spt_desc;
  377. uint32_t ppt_index;
  378. uint32_t ppt_id_start;
  379. if (!cc_ctx->total_page_num) {
  380. dp_err("total page num is 0");
  381. return QDF_STATUS_E_INVAL;
  382. }
  383. ppt_id_start = DP_CMEM_OFFSET_TO_PPT_ID(cc_ctx->cmem_offset);
  384. spt_desc = cc_ctx->page_desc_base;
  385. while (i < cc_ctx->total_page_num) {
  386. /* write page PA to CMEM */
  387. dp_hw_cc_cmem_write(soc->hal_soc,
  388. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  389. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  390. (spt_desc[i].page_p_addr >>
  391. DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
  392. ppt_index = ppt_id_start + i;
  393. if (ppt_index >= DP_CC_PPT_MAX_ENTRIES)
  394. qdf_assert_always(0);
  395. spt_desc[i].ppt_index = ppt_index;
  396. be_soc->page_desc_base[ppt_index].page_v_addr =
  397. spt_desc[i].page_v_addr;
  398. i++;
  399. }
  400. return QDF_STATUS_SUCCESS;
  401. }
  402. #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
  403. QDF_STATUS
  404. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  405. struct dp_hw_cookie_conversion_t *cc_ctx)
  406. {
  407. uint32_t ppt_index;
  408. struct dp_spt_page_desc *spt_desc;
  409. int i = 0;
  410. spt_desc = cc_ctx->page_desc_base;
  411. while (i < cc_ctx->total_page_num) {
  412. ppt_index = spt_desc[i].ppt_index;
  413. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  414. i++;
  415. }
  416. return QDF_STATUS_SUCCESS;
  417. }
  418. #else
  419. QDF_STATUS
  420. dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
  421. struct dp_hw_cookie_conversion_t *cc_ctx)
  422. {
  423. struct dp_soc *soc = DP_SOC_BE_GET_SOC(be_soc);
  424. uint32_t ppt_index;
  425. struct dp_spt_page_desc *spt_desc;
  426. int i = 0;
  427. spt_desc = cc_ctx->page_desc_base;
  428. while (i < cc_ctx->total_page_num) {
  429. /* reset PA in CMEM to NULL */
  430. dp_hw_cc_cmem_write(soc->hal_soc,
  431. (cc_ctx->cmem_offset + be_soc->cc_cmem_base
  432. + (i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)),
  433. 0);
  434. ppt_index = spt_desc[i].ppt_index;
  435. be_soc->page_desc_base[ppt_index].page_v_addr = NULL;
  436. i++;
  437. }
  438. return QDF_STATUS_SUCCESS;
  439. }
  440. #endif
  441. #ifdef WLAN_SUPPORT_PPEDS
  442. static QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  443. {
  444. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  445. int target_type = hal_get_target_type(soc->hal_soc);
  446. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  447. /*
  448. * Check if PPE DS is enabled and wlan soc supports it.
  449. */
  450. if (!wlan_cfg_get_dp_soc_ppeds_enable(soc->wlan_cfg_ctx) ||
  451. !dp_ppeds_target_supported(target_type))
  452. return QDF_STATUS_SUCCESS;
  453. if (dp_ppeds_attach_soc_be(be_soc) != QDF_STATUS_SUCCESS)
  454. return QDF_STATUS_SUCCESS;
  455. cdp_ops->ppeds_ops = &dp_ops_ppeds_be;
  456. return QDF_STATUS_SUCCESS;
  457. }
  458. static QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  459. {
  460. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  461. struct cdp_ops *cdp_ops = soc->cdp_soc.ops;
  462. if (!be_soc->ppeds_handle)
  463. return QDF_STATUS_E_FAILURE;
  464. dp_ppeds_detach_soc_be(be_soc);
  465. cdp_ops->ppeds_ops = NULL;
  466. return QDF_STATUS_SUCCESS;
  467. }
  468. static QDF_STATUS dp_peer_ppeds_default_route_be(struct dp_soc *soc,
  469. struct dp_peer_be *be_peer,
  470. uint8_t vdev_id,
  471. uint16_t src_info)
  472. {
  473. uint16_t service_code;
  474. uint8_t priority_valid;
  475. uint8_t use_ppe_ds = PEER_ROUTING_USE_PPE;
  476. uint8_t peer_routing_enabled = PEER_ROUTING_ENABLED;
  477. QDF_STATUS status = QDF_STATUS_SUCCESS;
  478. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  479. struct dp_vdev_be *be_vdev;
  480. be_vdev = dp_get_be_vdev_from_dp_vdev(be_peer->peer.vdev);
  481. /*
  482. * Program service code bypass to avoid L2 new mac address
  483. * learning exception when fdb learning is disabled.
  484. */
  485. service_code = PPE_DRV_SC_SPF_BYPASS;
  486. priority_valid = be_peer->priority_valid;
  487. /*
  488. * if FST is enabled then let flow rule take the decision of
  489. * routing the pkt to DS or host
  490. */
  491. if (wlan_cfg_is_rx_flow_tag_enabled(cfg))
  492. use_ppe_ds = 0;
  493. if (soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing) {
  494. status =
  495. soc->cdp_soc.ol_ops->peer_set_ppeds_default_routing
  496. (soc->ctrl_psoc,
  497. be_peer->peer.mac_addr.raw,
  498. service_code, priority_valid,
  499. src_info, vdev_id, use_ppe_ds,
  500. peer_routing_enabled);
  501. if (status != QDF_STATUS_SUCCESS) {
  502. dp_err("vdev_id: %d, PPE peer routing mac:"
  503. QDF_MAC_ADDR_FMT, vdev_id,
  504. QDF_MAC_ADDR_REF(be_peer->peer.mac_addr.raw));
  505. return QDF_STATUS_E_FAILURE;
  506. }
  507. }
  508. return QDF_STATUS_SUCCESS;
  509. }
  510. #ifdef WLAN_FEATURE_11BE_MLO
  511. QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
  512. struct dp_peer *peer,
  513. struct dp_vdev_be *be_vdev,
  514. void *args)
  515. {
  516. struct dp_peer *mld_peer;
  517. struct dp_soc *mld_soc;
  518. struct dp_soc_be *be_soc;
  519. struct cdp_soc_t *cdp_soc;
  520. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  521. struct cdp_ds_vp_params vp_params = {0};
  522. struct dp_ppe_vp_profile *ppe_vp_profile = (struct dp_ppe_vp_profile *)args;
  523. uint16_t src_info = ppe_vp_profile->vp_num;
  524. uint8_t vdev_id = be_vdev->vdev.vdev_id;
  525. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  526. if (!be_peer) {
  527. dp_err("BE peer is null");
  528. return QDF_STATUS_E_NULL_VALUE;
  529. }
  530. if (IS_DP_LEGACY_PEER(peer)) {
  531. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  532. vdev_id, src_info);
  533. } else if (IS_MLO_DP_MLD_PEER(peer)) {
  534. int i;
  535. struct dp_peer *link_peer = NULL;
  536. struct dp_mld_link_peers link_peers_info;
  537. /* get link peers with reference */
  538. dp_get_link_peers_ref_from_mld_peer(soc, peer, &link_peers_info,
  539. DP_MOD_ID_DS);
  540. for (i = 0; i < link_peers_info.num_links; i++) {
  541. link_peer = link_peers_info.link_peers[i];
  542. be_peer = dp_get_be_peer_from_dp_peer(link_peer);
  543. if (!be_peer) {
  544. dp_err("BE peer is null");
  545. continue;
  546. }
  547. be_vdev = dp_get_be_vdev_from_dp_vdev(link_peer->vdev);
  548. if (!be_vdev) {
  549. dp_err("BE vap is null for peer id %d ",
  550. link_peer->peer_id);
  551. continue;
  552. }
  553. vdev_id = be_vdev->vdev.vdev_id;
  554. soc = link_peer->vdev->pdev->soc;
  555. qdf_status = dp_peer_ppeds_default_route_be(soc,
  556. be_peer,
  557. vdev_id,
  558. src_info);
  559. }
  560. dp_release_link_peers_ref(&link_peers_info, DP_MOD_ID_DS);
  561. } else {
  562. mld_peer = DP_GET_MLD_PEER_FROM_PEER(peer);
  563. if (!mld_peer)
  564. return qdf_status;
  565. /*
  566. * In case of MLO link peer,
  567. * Fetch the VP profile from the mld vdev.
  568. */
  569. be_vdev = dp_get_be_vdev_from_dp_vdev(mld_peer->vdev);
  570. if (!be_vdev) {
  571. dp_err("BE vap is null");
  572. return QDF_STATUS_E_NULL_VALUE;
  573. }
  574. /*
  575. * Extract the VP profile from the vap
  576. * in case of MLO peer, we have to get the profile from
  577. * the MLD vdev's osif handle and not the link peer.
  578. */
  579. mld_soc = mld_peer->vdev->pdev->soc;
  580. cdp_soc = &mld_soc->cdp_soc;
  581. if (!cdp_soc->ol_ops->get_ppeds_profile_info_for_vap) {
  582. dp_err("%pK: Register PPEDS profile info API before use", cdp_soc);
  583. return QDF_STATUS_E_NULL_VALUE;
  584. }
  585. qdf_status = cdp_soc->ol_ops->get_ppeds_profile_info_for_vap(mld_soc->ctrl_psoc,
  586. mld_peer->vdev->vdev_id,
  587. &vp_params);
  588. if (qdf_status == QDF_STATUS_E_NULL_VALUE) {
  589. dp_err("%pK: Failed to get ppeds profile for mld soc", mld_soc);
  590. return qdf_status;
  591. }
  592. /*
  593. * Check if PPE DS routing is enabled on
  594. * the associated vap.
  595. */
  596. if (vp_params.ppe_vp_type != PPE_VP_USER_TYPE_DS)
  597. return qdf_status;
  598. be_soc = dp_get_be_soc_from_dp_soc(mld_soc);
  599. ppe_vp_profile = &be_soc->ppe_vp_profile[vp_params.ppe_vp_profile_idx];
  600. src_info = ppe_vp_profile->vp_num;
  601. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  602. vdev_id, src_info);
  603. }
  604. return qdf_status;
  605. }
  606. #else
  607. static QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc,
  608. struct dp_peer *peer,
  609. struct dp_vdev_be *be_vdev
  610. void *args)
  611. {
  612. struct dp_ppe_vp_profile *vp_profile = (struct dp_ppe_vp_profile *)args;
  613. struct dp_peer_be *be_peer = dp_get_be_peer_from_dp_peer(peer);
  614. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  615. if (!be_peer) {
  616. dp_err("BE peer is null");
  617. return QDF_STATUS_E_NULL_VALUE;
  618. }
  619. qdf_status = dp_peer_ppeds_default_route_be(soc, be_peer,
  620. be_vdev->vdev.vdev_id,
  621. vp_profile->vp_num);
  622. return qdf_status;
  623. }
  624. #endif
  625. #else
  626. static QDF_STATUS dp_ppeds_init_soc_be(struct dp_soc *soc)
  627. {
  628. return QDF_STATUS_SUCCESS;
  629. }
  630. static QDF_STATUS dp_ppeds_deinit_soc_be(struct dp_soc *soc)
  631. {
  632. return QDF_STATUS_SUCCESS;
  633. }
  634. static inline QDF_STATUS dp_soc_ppeds_attach_be(struct dp_soc *soc)
  635. {
  636. return QDF_STATUS_SUCCESS;
  637. }
  638. static inline QDF_STATUS dp_soc_ppeds_detach_be(struct dp_soc *soc)
  639. {
  640. return QDF_STATUS_SUCCESS;
  641. }
  642. QDF_STATUS dp_peer_setup_ppeds_be(struct dp_soc *soc, struct dp_peer *peer,
  643. struct dp_vdev_be *be_vdev,
  644. void *args)
  645. {
  646. return QDF_STATUS_SUCCESS;
  647. }
  648. static inline void dp_ppeds_stop_soc_be(struct dp_soc *soc)
  649. {
  650. }
  651. #endif /* WLAN_SUPPORT_PPEDS */
  652. void dp_reo_shared_qaddr_detach(struct dp_soc *soc)
  653. {
  654. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  655. REO_QUEUE_REF_ML_TABLE_SIZE,
  656. soc->reo_qref.mlo_reo_qref_table_vaddr,
  657. soc->reo_qref.mlo_reo_qref_table_paddr, 0);
  658. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  659. REO_QUEUE_REF_NON_ML_TABLE_SIZE,
  660. soc->reo_qref.non_mlo_reo_qref_table_vaddr,
  661. soc->reo_qref.non_mlo_reo_qref_table_paddr, 0);
  662. }
  663. static QDF_STATUS dp_soc_detach_be(struct dp_soc *soc)
  664. {
  665. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  666. int i = 0;
  667. dp_soc_ppeds_detach_be(soc);
  668. dp_reo_shared_qaddr_detach(soc);
  669. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  670. dp_hw_cookie_conversion_detach(be_soc,
  671. &be_soc->tx_cc_ctx[i]);
  672. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  673. dp_hw_cookie_conversion_detach(be_soc,
  674. &be_soc->rx_cc_ctx[i]);
  675. qdf_mem_free(be_soc->page_desc_base);
  676. be_soc->page_desc_base = NULL;
  677. return QDF_STATUS_SUCCESS;
  678. }
  679. #ifdef QCA_SUPPORT_DP_GLOBAL_CTX
  680. static void dp_set_rx_fst_be(struct dp_rx_fst *fst)
  681. {
  682. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  683. if (dp_global)
  684. dp_global->fst_ctx = fst;
  685. }
  686. static struct dp_rx_fst *dp_get_rx_fst_be(void)
  687. {
  688. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  689. if (dp_global)
  690. return dp_global->fst_ctx;
  691. return NULL;
  692. }
  693. static uint32_t dp_rx_fst_release_ref_be(void)
  694. {
  695. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  696. uint32_t rx_fst_ref_cnt;
  697. if (dp_global) {
  698. rx_fst_ref_cnt = qdf_atomic_read(&dp_global->rx_fst_ref_cnt);
  699. qdf_atomic_dec(&dp_global->rx_fst_ref_cnt);
  700. return rx_fst_ref_cnt;
  701. }
  702. return 1;
  703. }
  704. static void dp_rx_fst_get_ref_be(void)
  705. {
  706. struct dp_global_context *dp_global = wlan_objmgr_get_global_ctx();
  707. if (dp_global)
  708. qdf_atomic_inc(&dp_global->rx_fst_ref_cnt);
  709. }
  710. #else
  711. static void dp_set_rx_fst_be(struct dp_rx_fst *fst)
  712. {
  713. }
  714. static struct dp_rx_fst *dp_get_rx_fst_be(void)
  715. {
  716. return NULL;
  717. }
  718. static uint32_t dp_rx_fst_release_ref_be(void)
  719. {
  720. return 1;
  721. }
  722. static void dp_rx_fst_get_ref_be(void)
  723. {
  724. }
  725. #endif
  726. #ifdef WLAN_MLO_MULTI_CHIP
  727. #ifdef WLAN_MCAST_MLO
  728. static inline void
  729. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  730. {
  731. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  732. be_vdev->mcast_primary = false;
  733. be_vdev->seq_num = 0;
  734. hal_tx_mcast_mlo_reinject_routing_set(
  735. soc->hal_soc,
  736. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  737. if (vdev->opmode == wlan_op_mode_ap) {
  738. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  739. vdev->vdev_id,
  740. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  741. }
  742. }
  743. static inline void
  744. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  745. {
  746. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  747. be_vdev->seq_num = 0;
  748. be_vdev->mcast_primary = false;
  749. vdev->mlo_vdev = false;
  750. }
  751. #else
  752. static inline void
  753. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  754. {
  755. }
  756. static inline void
  757. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  758. {
  759. }
  760. #endif
  761. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  762. {
  763. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  764. qdf_mem_set(be_vdev->partner_vdev_list,
  765. WLAN_MAX_MLO_CHIPS * WLAN_MAX_MLO_LINKS_PER_SOC,
  766. CDP_INVALID_VDEV_ID);
  767. }
  768. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  769. struct cdp_lro_hash_config *lro_hash)
  770. {
  771. dp_mlo_get_rx_hash_key(soc, lro_hash);
  772. }
  773. #else
  774. static inline void
  775. dp_mlo_mcast_init(struct dp_soc *soc, struct dp_vdev *vdev)
  776. {
  777. }
  778. static inline void
  779. dp_mlo_mcast_deinit(struct dp_soc *soc, struct dp_vdev *vdev)
  780. {
  781. }
  782. static void dp_mlo_init_ptnr_list(struct dp_vdev *vdev)
  783. {
  784. }
  785. static void dp_get_rx_hash_key_be(struct dp_soc *soc,
  786. struct cdp_lro_hash_config *lro_hash)
  787. {
  788. dp_get_rx_hash_key_bytes(lro_hash);
  789. }
  790. #endif
  791. static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
  792. struct cdp_soc_attach_params *params)
  793. {
  794. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  795. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  796. uint32_t max_tx_rx_desc_num, num_spt_pages;
  797. uint32_t num_entries;
  798. int i = 0;
  799. max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
  800. WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS +
  801. WLAN_CFG_NUM_PPEDS_TX_DESC_MAX * MAX_PPE_TXDESC_POOLS;
  802. /* estimate how many SPT DDR pages needed */
  803. num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
  804. num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
  805. num_spt_pages : DP_CC_PPT_MAX_ENTRIES;
  806. be_soc->page_desc_base = qdf_mem_malloc(
  807. DP_CC_PPT_MAX_ENTRIES * sizeof(struct dp_spt_page_desc));
  808. if (!be_soc->page_desc_base) {
  809. dp_err("spt page descs allocation failed");
  810. return QDF_STATUS_E_NOMEM;
  811. }
  812. soc->wbm_sw0_bm_id = hal_tx_get_wbm_sw0_bm_id();
  813. qdf_status = dp_get_cmem_allocation(soc, COOKIE_CONVERSION);
  814. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  815. goto fail;
  816. dp_soc_mlo_fill_params(soc, params);
  817. qdf_status = dp_soc_ppeds_attach_be(soc);
  818. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  819. goto fail;
  820. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  821. num_entries = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  822. qdf_status =
  823. dp_hw_cookie_conversion_attach(be_soc,
  824. &be_soc->tx_cc_ctx[i],
  825. num_entries,
  826. DP_TX_DESC_TYPE, i);
  827. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  828. goto fail;
  829. }
  830. qdf_status = dp_get_cmem_allocation(soc, FISA_FST);
  831. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  832. goto fail;
  833. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  834. num_entries =
  835. wlan_cfg_get_dp_soc_rx_sw_desc_num(soc->wlan_cfg_ctx);
  836. qdf_status =
  837. dp_hw_cookie_conversion_attach(be_soc,
  838. &be_soc->rx_cc_ctx[i],
  839. num_entries,
  840. DP_RX_DESC_BUF_TYPE, i);
  841. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  842. goto fail;
  843. }
  844. return qdf_status;
  845. fail:
  846. dp_soc_detach_be(soc);
  847. return qdf_status;
  848. }
  849. static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
  850. {
  851. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  852. int i = 0;
  853. qdf_atomic_set(&soc->cmn_init_done, 0);
  854. dp_ppeds_stop_soc_be(soc);
  855. dp_tx_deinit_bank_profiles(be_soc);
  856. for (i = 0; i < MAX_TXDESC_POOLS; i++)
  857. dp_hw_cookie_conversion_deinit(be_soc,
  858. &be_soc->tx_cc_ctx[i]);
  859. for (i = 0; i < MAX_RXDESC_POOLS; i++)
  860. dp_hw_cookie_conversion_deinit(be_soc,
  861. &be_soc->rx_cc_ctx[i]);
  862. dp_ppeds_deinit_soc_be(soc);
  863. return QDF_STATUS_SUCCESS;
  864. }
  865. static QDF_STATUS dp_soc_deinit_be_wrapper(struct dp_soc *soc)
  866. {
  867. QDF_STATUS qdf_status;
  868. qdf_status = dp_soc_deinit_be(soc);
  869. if (QDF_IS_STATUS_ERROR(qdf_status))
  870. return qdf_status;
  871. dp_soc_deinit(soc);
  872. return QDF_STATUS_SUCCESS;
  873. }
  874. static void *dp_soc_init_be(struct dp_soc *soc, HTC_HANDLE htc_handle,
  875. struct hif_opaque_softc *hif_handle)
  876. {
  877. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  878. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  879. int i = 0;
  880. void *ret_addr;
  881. wlan_minidump_log(soc, sizeof(*soc), soc->ctrl_psoc,
  882. WLAN_MD_DP_SOC, "dp_soc");
  883. soc->hif_handle = hif_handle;
  884. soc->hal_soc = hif_get_hal_handle(soc->hif_handle);
  885. if (!soc->hal_soc)
  886. return NULL;
  887. dp_ppeds_init_soc_be(soc);
  888. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  889. qdf_status =
  890. dp_hw_cookie_conversion_init(be_soc,
  891. &be_soc->tx_cc_ctx[i]);
  892. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  893. goto fail;
  894. }
  895. for (i = 0; i < MAX_RXDESC_POOLS; i++) {
  896. qdf_status =
  897. dp_hw_cookie_conversion_init(be_soc,
  898. &be_soc->rx_cc_ctx[i]);
  899. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  900. goto fail;
  901. }
  902. /* route vdev_id mismatch notification via FW completion */
  903. hal_tx_vdev_mismatch_routing_set(soc->hal_soc,
  904. HAL_TX_VDEV_MISMATCH_FW_NOTIFY);
  905. qdf_status = dp_tx_init_bank_profiles(be_soc);
  906. if (!QDF_IS_STATUS_SUCCESS(qdf_status))
  907. goto fail;
  908. /* write WBM/REO cookie conversion CFG register */
  909. dp_cc_reg_cfg_init(soc, true);
  910. ret_addr = dp_soc_init(soc, htc_handle, hif_handle);
  911. if (!ret_addr)
  912. goto fail;
  913. return ret_addr;
  914. fail:
  915. dp_soc_deinit_be(soc);
  916. return NULL;
  917. }
  918. static QDF_STATUS dp_pdev_attach_be(struct dp_pdev *pdev,
  919. struct cdp_pdev_attach_params *params)
  920. {
  921. dp_pdev_mlo_fill_params(pdev, params);
  922. return QDF_STATUS_SUCCESS;
  923. }
  924. static QDF_STATUS dp_pdev_detach_be(struct dp_pdev *pdev)
  925. {
  926. dp_mlo_update_link_to_pdev_unmap(pdev->soc, pdev);
  927. return QDF_STATUS_SUCCESS;
  928. }
  929. #ifdef INTRA_BSS_FWD_OFFLOAD
  930. static
  931. void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable)
  932. {
  933. soc->cdp_soc.ol_ops->vdev_set_intra_bss(soc->ctrl_psoc, vdev_id,
  934. enable);
  935. }
  936. #else
  937. static
  938. void dp_vdev_set_intra_bss(struct dp_soc *soc, uint16_t vdev_id, bool enable)
  939. {
  940. }
  941. #endif
  942. static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  943. {
  944. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  945. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  946. struct dp_pdev *pdev = vdev->pdev;
  947. if (vdev->opmode == wlan_op_mode_monitor)
  948. return QDF_STATUS_SUCCESS;
  949. be_vdev->vdev_id_check_en = DP_TX_VDEV_ID_CHECK_ENABLE;
  950. be_vdev->bank_id = dp_tx_get_bank_profile(be_soc, be_vdev);
  951. vdev->bank_id = be_vdev->bank_id;
  952. if (be_vdev->bank_id == DP_BE_INVALID_BANK_ID) {
  953. QDF_BUG(0);
  954. return QDF_STATUS_E_FAULT;
  955. }
  956. if (vdev->opmode == wlan_op_mode_sta) {
  957. if (soc->cdp_soc.ol_ops->set_mec_timer)
  958. soc->cdp_soc.ol_ops->set_mec_timer(
  959. soc->ctrl_psoc,
  960. vdev->vdev_id,
  961. DP_AST_AGING_TIMER_DEFAULT_MS);
  962. if (pdev->isolation)
  963. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  964. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  965. else
  966. hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
  967. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  968. } else if (vdev->ap_bridge_enabled) {
  969. dp_vdev_set_intra_bss(soc, vdev->vdev_id, true);
  970. }
  971. dp_mlo_mcast_init(soc, vdev);
  972. dp_mlo_init_ptnr_list(vdev);
  973. return QDF_STATUS_SUCCESS;
  974. }
  975. static QDF_STATUS dp_vdev_detach_be(struct dp_soc *soc, struct dp_vdev *vdev)
  976. {
  977. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  978. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  979. if (vdev->opmode == wlan_op_mode_monitor)
  980. return QDF_STATUS_SUCCESS;
  981. if (vdev->opmode == wlan_op_mode_ap)
  982. dp_mlo_mcast_deinit(soc, vdev);
  983. dp_tx_put_bank_profile(be_soc, be_vdev);
  984. dp_clr_mlo_ptnr_list(soc, vdev);
  985. return QDF_STATUS_SUCCESS;
  986. }
  987. #ifdef WLAN_SUPPORT_PPEDS
  988. static void dp_soc_txrx_peer_setup_be(struct dp_soc *soc, uint8_t vdev_id,
  989. uint8_t *peer_mac)
  990. {
  991. struct dp_vdev_be *be_vdev;
  992. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  993. struct dp_soc_be *be_soc;
  994. struct cdp_ds_vp_params vp_params = {0};
  995. struct cdp_soc_t *cdp_soc;
  996. enum wlan_op_mode vdev_opmode;
  997. struct dp_peer *peer;
  998. struct dp_peer *tgt_peer = NULL;
  999. struct dp_soc *tgt_soc = NULL;
  1000. peer = dp_peer_find_hash_find(soc, peer_mac, 0, vdev_id, DP_MOD_ID_CDP);
  1001. if (!peer)
  1002. return;
  1003. vdev_opmode = peer->vdev->opmode;
  1004. if (vdev_opmode != wlan_op_mode_ap &&
  1005. vdev_opmode != wlan_op_mode_sta) {
  1006. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  1007. return;
  1008. }
  1009. tgt_peer = dp_get_tgt_peer_from_peer(peer);
  1010. tgt_soc = tgt_peer->vdev->pdev->soc;
  1011. be_soc = dp_get_be_soc_from_dp_soc(tgt_soc);
  1012. cdp_soc = &tgt_soc->cdp_soc;
  1013. be_vdev = dp_get_be_vdev_from_dp_vdev(tgt_peer->vdev);
  1014. if (!be_vdev) {
  1015. qdf_err("BE vap is null");
  1016. qdf_status = QDF_STATUS_E_NULL_VALUE;
  1017. goto fail;
  1018. }
  1019. /*
  1020. * Extract the VP profile from the VAP
  1021. */
  1022. if (!cdp_soc->ol_ops->get_ppeds_profile_info_for_vap) {
  1023. dp_err("%pK: Register get ppeds profile info first", cdp_soc);
  1024. qdf_status = QDF_STATUS_E_NULL_VALUE;
  1025. goto fail;
  1026. }
  1027. /*
  1028. * Check if PPE DS routing is enabled on the associated vap.
  1029. */
  1030. qdf_status =
  1031. cdp_soc->ol_ops->get_ppeds_profile_info_for_vap(tgt_soc->ctrl_psoc,
  1032. tgt_peer->vdev->vdev_id,
  1033. &vp_params);
  1034. if (qdf_status == QDF_STATUS_E_NULL_VALUE) {
  1035. dp_err("%pK: Could not find ppeds profile info vdev", be_vdev);
  1036. qdf_status = QDF_STATUS_E_NULL_VALUE;
  1037. goto fail;
  1038. }
  1039. if (vp_params.ppe_vp_type == PPE_VP_USER_TYPE_DS) {
  1040. qdf_status = dp_peer_setup_ppeds_be(tgt_soc, tgt_peer, be_vdev,
  1041. (void *)&be_soc->ppe_vp_profile[vp_params.ppe_vp_profile_idx]);
  1042. }
  1043. fail:
  1044. dp_peer_unref_delete(peer, DP_MOD_ID_CDP);
  1045. if (!QDF_IS_STATUS_SUCCESS(qdf_status)) {
  1046. dp_err("Unable to do ppeds peer setup");
  1047. qdf_assert_always(0);
  1048. }
  1049. }
  1050. #else
  1051. static inline
  1052. void dp_soc_txrx_peer_setup_be(struct dp_soc *soc, uint8_t vdev_id,
  1053. uint8_t *peer_mac)
  1054. {
  1055. }
  1056. #endif
  1057. static QDF_STATUS dp_peer_setup_be(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1058. uint8_t *peer_mac,
  1059. struct cdp_peer_setup_info *setup_info)
  1060. {
  1061. struct dp_soc *soc = (struct dp_soc *)soc_hdl;
  1062. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  1063. qdf_status = dp_peer_setup_wifi3(soc_hdl, vdev_id, peer_mac,
  1064. setup_info);
  1065. if (!QDF_IS_STATUS_SUCCESS(qdf_status)) {
  1066. dp_err("Unable to dp peer setup");
  1067. return qdf_status;
  1068. }
  1069. dp_soc_txrx_peer_setup_be(soc, vdev_id, peer_mac);
  1070. return QDF_STATUS_SUCCESS;
  1071. }
  1072. qdf_size_t dp_get_soc_context_size_be(void)
  1073. {
  1074. return sizeof(struct dp_soc_be);
  1075. }
  1076. #ifdef CONFIG_WORD_BASED_TLV
  1077. /**
  1078. * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
  1079. * @soc: Common DP soc handle
  1080. * @htt_tlv_filter: Rx SRNG TLV and filter setting
  1081. *
  1082. * Return: none
  1083. */
  1084. static inline void
  1085. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  1086. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  1087. {
  1088. htt_tlv_filter->rx_msdu_end_wmask =
  1089. hal_rx_msdu_end_wmask_get(soc->hal_soc);
  1090. htt_tlv_filter->rx_mpdu_start_wmask =
  1091. hal_rx_mpdu_start_wmask_get(soc->hal_soc);
  1092. }
  1093. #else
  1094. static inline void
  1095. dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
  1096. struct htt_rx_ring_tlv_filter *htt_tlv_filter)
  1097. {
  1098. }
  1099. #endif
  1100. #ifdef WLAN_SUPPORT_PPEDS
  1101. static
  1102. void dp_free_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  1103. int ring_type, int ring_num)
  1104. {
  1105. if (srng->irq >= 0) {
  1106. if (ring_type == WBM2SW_RELEASE &&
  1107. ring_num == WBM2_SW_PPE_REL_RING_ID)
  1108. pld_pfrm_free_irq(soc->osdev->dev, srng->irq, soc);
  1109. else if (ring_type == REO2PPE || ring_type == PPE2TCL)
  1110. pld_pfrm_free_irq(soc->osdev->dev, srng->irq,
  1111. dp_get_ppe_ds_ctxt(soc));
  1112. }
  1113. }
  1114. static
  1115. int dp_register_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
  1116. int vector, int ring_type, int ring_num)
  1117. {
  1118. int irq = -1, ret = 0;
  1119. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1120. int pci_slot = pld_get_pci_slot(soc->osdev->dev);
  1121. srng->irq = -1;
  1122. irq = pld_get_msi_irq(soc->osdev->dev, vector);
  1123. if (ring_type == WBM2SW_RELEASE &&
  1124. ring_num == WBM2_SW_PPE_REL_RING_ID) {
  1125. snprintf(be_soc->irq_name[2], DP_PPE_INTR_STRNG_LEN,
  1126. "pci%d_ppe_wbm_rel", pci_slot);
  1127. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  1128. dp_ppeds_handle_tx_comp,
  1129. IRQF_SHARED | IRQF_NO_SUSPEND,
  1130. be_soc->irq_name[2], (void *)soc);
  1131. if (ret)
  1132. goto fail;
  1133. } else if (ring_type == REO2PPE && be_soc->ppeds_int_mode_enabled) {
  1134. snprintf(be_soc->irq_name[0], DP_PPE_INTR_STRNG_LEN,
  1135. "pci%d_reo2ppe", pci_slot);
  1136. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  1137. dp_ppe_ds_reo2ppe_irq_handler,
  1138. IRQF_SHARED | IRQF_NO_SUSPEND,
  1139. be_soc->irq_name[0],
  1140. dp_get_ppe_ds_ctxt(soc));
  1141. if (ret)
  1142. goto fail;
  1143. } else if (ring_type == PPE2TCL && be_soc->ppeds_int_mode_enabled) {
  1144. snprintf(be_soc->irq_name[1], DP_PPE_INTR_STRNG_LEN,
  1145. "pci%d_ppe2tcl", pci_slot);
  1146. ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
  1147. dp_ppe_ds_ppe2tcl_irq_handler,
  1148. IRQF_NO_SUSPEND,
  1149. be_soc->irq_name[1],
  1150. dp_get_ppe_ds_ctxt(soc));
  1151. if (ret)
  1152. goto fail;
  1153. pld_pfrm_disable_irq_nosync(soc->osdev->dev, irq);
  1154. } else {
  1155. return 0;
  1156. }
  1157. srng->irq = irq;
  1158. dp_info("Registered irq %d for soc %pK ring type %d",
  1159. irq, soc, ring_type);
  1160. return 0;
  1161. fail:
  1162. dp_err("Unable to config irq : ring type %d irq %d vector %d",
  1163. ring_type, irq, vector);
  1164. return ret;
  1165. }
  1166. void dp_ppeds_disable_irq(struct dp_soc *soc, struct dp_srng *srng)
  1167. {
  1168. if (srng->irq >= 0)
  1169. pld_pfrm_disable_irq_nosync(soc->osdev->dev, srng->irq);
  1170. }
  1171. void dp_ppeds_enable_irq(struct dp_soc *soc, struct dp_srng *srng)
  1172. {
  1173. if (srng->irq >= 0)
  1174. pld_pfrm_enable_irq(soc->osdev->dev, srng->irq);
  1175. }
  1176. #endif
  1177. #ifdef NO_RX_PKT_HDR_TLV
  1178. /**
  1179. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  1180. * @soc: Common DP soc handle
  1181. *
  1182. * Return: QDF_STATUS
  1183. */
  1184. static QDF_STATUS
  1185. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  1186. {
  1187. int i;
  1188. int mac_id;
  1189. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  1190. struct dp_srng *rx_mac_srng;
  1191. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1192. /*
  1193. * In Beryllium chipset msdu_start, mpdu_end
  1194. * and rx_attn are part of msdu_end/mpdu_start
  1195. */
  1196. htt_tlv_filter.msdu_start = 0;
  1197. htt_tlv_filter.mpdu_end = 0;
  1198. htt_tlv_filter.attention = 0;
  1199. htt_tlv_filter.mpdu_start = 1;
  1200. htt_tlv_filter.msdu_end = 1;
  1201. htt_tlv_filter.packet = 1;
  1202. htt_tlv_filter.packet_header = 0;
  1203. htt_tlv_filter.ppdu_start = 0;
  1204. htt_tlv_filter.ppdu_end = 0;
  1205. htt_tlv_filter.ppdu_end_user_stats = 0;
  1206. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  1207. htt_tlv_filter.ppdu_end_status_done = 0;
  1208. htt_tlv_filter.enable_fp = 1;
  1209. htt_tlv_filter.enable_md = 0;
  1210. htt_tlv_filter.enable_md = 0;
  1211. htt_tlv_filter.enable_mo = 0;
  1212. htt_tlv_filter.fp_mgmt_filter = 0;
  1213. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  1214. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  1215. FILTER_DATA_DATA);
  1216. htt_tlv_filter.fp_data_filter |=
  1217. hal_rx_en_mcast_fp_data_filter(soc->hal_soc) ?
  1218. FILTER_DATA_MCAST : 0;
  1219. htt_tlv_filter.mo_mgmt_filter = 0;
  1220. htt_tlv_filter.mo_ctrl_filter = 0;
  1221. htt_tlv_filter.mo_data_filter = 0;
  1222. htt_tlv_filter.md_data_filter = 0;
  1223. htt_tlv_filter.offset_valid = true;
  1224. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  1225. htt_tlv_filter.rx_mpdu_end_offset = 0;
  1226. htt_tlv_filter.rx_msdu_start_offset = 0;
  1227. htt_tlv_filter.rx_attn_offset = 0;
  1228. /*
  1229. * For monitor mode, the packet hdr tlv is enabled later during
  1230. * filter update
  1231. */
  1232. if (soc->cdp_soc.ol_ops->get_con_mode &&
  1233. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  1234. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  1235. else
  1236. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  1237. /*Not subscribing rx_pkt_header*/
  1238. htt_tlv_filter.rx_header_offset = 0;
  1239. htt_tlv_filter.rx_mpdu_start_offset =
  1240. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1241. htt_tlv_filter.rx_msdu_end_offset =
  1242. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1243. dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
  1244. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1245. struct dp_pdev *pdev = soc->pdev_list[i];
  1246. if (!pdev)
  1247. continue;
  1248. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1249. int mac_for_pdev =
  1250. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1251. /*
  1252. * Obtain lmac id from pdev to access the LMAC ring
  1253. * in soc context
  1254. */
  1255. int lmac_id =
  1256. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1257. pdev->pdev_id);
  1258. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1259. if (!rx_mac_srng->hal_srng)
  1260. continue;
  1261. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1262. rx_mac_srng->hal_srng,
  1263. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1264. &htt_tlv_filter);
  1265. }
  1266. }
  1267. return status;
  1268. }
  1269. #else
  1270. /**
  1271. * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
  1272. * @soc: Common DP soc handle
  1273. *
  1274. * Return: QDF_STATUS
  1275. */
  1276. static QDF_STATUS
  1277. dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
  1278. {
  1279. int i;
  1280. int mac_id;
  1281. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  1282. struct dp_srng *rx_mac_srng;
  1283. QDF_STATUS status = QDF_STATUS_SUCCESS;
  1284. /*
  1285. * In Beryllium chipset msdu_start, mpdu_end
  1286. * and rx_attn are part of msdu_end/mpdu_start
  1287. */
  1288. htt_tlv_filter.msdu_start = 0;
  1289. htt_tlv_filter.mpdu_end = 0;
  1290. htt_tlv_filter.attention = 0;
  1291. htt_tlv_filter.mpdu_start = 1;
  1292. htt_tlv_filter.msdu_end = 1;
  1293. htt_tlv_filter.packet = 1;
  1294. htt_tlv_filter.packet_header = 1;
  1295. htt_tlv_filter.ppdu_start = 0;
  1296. htt_tlv_filter.ppdu_end = 0;
  1297. htt_tlv_filter.ppdu_end_user_stats = 0;
  1298. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  1299. htt_tlv_filter.ppdu_end_status_done = 0;
  1300. htt_tlv_filter.enable_fp = 1;
  1301. htt_tlv_filter.enable_md = 0;
  1302. htt_tlv_filter.enable_md = 0;
  1303. htt_tlv_filter.enable_mo = 0;
  1304. htt_tlv_filter.fp_mgmt_filter = 0;
  1305. htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
  1306. htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
  1307. FILTER_DATA_DATA);
  1308. htt_tlv_filter.fp_data_filter |=
  1309. hal_rx_en_mcast_fp_data_filter(soc->hal_soc) ?
  1310. FILTER_DATA_MCAST : 0;
  1311. htt_tlv_filter.mo_mgmt_filter = 0;
  1312. htt_tlv_filter.mo_ctrl_filter = 0;
  1313. htt_tlv_filter.mo_data_filter = 0;
  1314. htt_tlv_filter.md_data_filter = 0;
  1315. htt_tlv_filter.offset_valid = true;
  1316. /* Not subscribing to mpdu_end, msdu_start and rx_attn */
  1317. htt_tlv_filter.rx_mpdu_end_offset = 0;
  1318. htt_tlv_filter.rx_msdu_start_offset = 0;
  1319. htt_tlv_filter.rx_attn_offset = 0;
  1320. /*
  1321. * For monitor mode, the packet hdr tlv is enabled later during
  1322. * filter update
  1323. */
  1324. if (soc->cdp_soc.ol_ops->get_con_mode &&
  1325. soc->cdp_soc.ol_ops->get_con_mode() == QDF_GLOBAL_MONITOR_MODE)
  1326. htt_tlv_filter.rx_packet_offset = soc->rx_mon_pkt_tlv_size;
  1327. else
  1328. htt_tlv_filter.rx_packet_offset = soc->rx_pkt_tlv_size;
  1329. htt_tlv_filter.rx_header_offset =
  1330. hal_rx_pkt_tlv_offset_get(soc->hal_soc);
  1331. htt_tlv_filter.rx_mpdu_start_offset =
  1332. hal_rx_mpdu_start_offset_get(soc->hal_soc);
  1333. htt_tlv_filter.rx_msdu_end_offset =
  1334. hal_rx_msdu_end_offset_get(soc->hal_soc);
  1335. dp_info("TLV subscription\n"
  1336. "msdu_start %d, mpdu_end %d, attention %d"
  1337. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n"
  1338. "TLV offsets\n"
  1339. "msdu_start %d, mpdu_end %d, attention %d"
  1340. "mpdu_start %d, msdu_end %d, pkt_hdr %d, pkt %d\n",
  1341. htt_tlv_filter.msdu_start,
  1342. htt_tlv_filter.mpdu_end,
  1343. htt_tlv_filter.attention,
  1344. htt_tlv_filter.mpdu_start,
  1345. htt_tlv_filter.msdu_end,
  1346. htt_tlv_filter.packet_header,
  1347. htt_tlv_filter.packet,
  1348. htt_tlv_filter.rx_msdu_start_offset,
  1349. htt_tlv_filter.rx_mpdu_end_offset,
  1350. htt_tlv_filter.rx_attn_offset,
  1351. htt_tlv_filter.rx_mpdu_start_offset,
  1352. htt_tlv_filter.rx_msdu_end_offset,
  1353. htt_tlv_filter.rx_header_offset,
  1354. htt_tlv_filter.rx_packet_offset);
  1355. for (i = 0; i < MAX_PDEV_CNT; i++) {
  1356. struct dp_pdev *pdev = soc->pdev_list[i];
  1357. if (!pdev)
  1358. continue;
  1359. for (mac_id = 0; mac_id < NUM_RXDMA_RINGS_PER_PDEV; mac_id++) {
  1360. int mac_for_pdev =
  1361. dp_get_mac_id_for_pdev(mac_id, pdev->pdev_id);
  1362. /*
  1363. * Obtain lmac id from pdev to access the LMAC ring
  1364. * in soc context
  1365. */
  1366. int lmac_id =
  1367. dp_get_lmac_id_for_pdev_id(soc, mac_id,
  1368. pdev->pdev_id);
  1369. rx_mac_srng = dp_get_rxdma_ring(pdev, lmac_id);
  1370. if (!rx_mac_srng->hal_srng)
  1371. continue;
  1372. htt_h2t_rx_ring_cfg(soc->htt_handle, mac_for_pdev,
  1373. rx_mac_srng->hal_srng,
  1374. RXDMA_BUF, RX_DATA_BUFFER_SIZE,
  1375. &htt_tlv_filter);
  1376. }
  1377. }
  1378. return status;
  1379. }
  1380. #endif
  1381. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1382. /**
  1383. * dp_service_near_full_srngs_be() - Main bottom half callback for the
  1384. * near-full IRQs.
  1385. * @soc: Datapath SoC handle
  1386. * @int_ctx: Interrupt context
  1387. * @dp_budget: Budget of the work that can be done in the bottom half
  1388. *
  1389. * Return: work done in the handler
  1390. */
  1391. static uint32_t
  1392. dp_service_near_full_srngs_be(struct dp_soc *soc, struct dp_intr *int_ctx,
  1393. uint32_t dp_budget)
  1394. {
  1395. int ring = 0;
  1396. int budget = dp_budget;
  1397. uint32_t work_done = 0;
  1398. uint32_t remaining_quota = dp_budget;
  1399. struct dp_intr_stats *intr_stats = &int_ctx->intr_stats;
  1400. int tx_ring_near_full_mask = int_ctx->tx_ring_near_full_mask;
  1401. int rx_near_full_grp_1_mask = int_ctx->rx_near_full_grp_1_mask;
  1402. int rx_near_full_grp_2_mask = int_ctx->rx_near_full_grp_2_mask;
  1403. int rx_near_full_mask = rx_near_full_grp_1_mask |
  1404. rx_near_full_grp_2_mask;
  1405. dp_verbose_debug("rx_ring_near_full 0x%x tx_ring_near_full 0x%x",
  1406. rx_near_full_mask,
  1407. tx_ring_near_full_mask);
  1408. if (rx_near_full_mask) {
  1409. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  1410. if (!(rx_near_full_mask & (1 << ring)))
  1411. continue;
  1412. work_done = dp_rx_nf_process(int_ctx,
  1413. soc->reo_dest_ring[ring].hal_srng,
  1414. ring, remaining_quota);
  1415. if (work_done) {
  1416. intr_stats->num_rx_ring_near_full_masks[ring]++;
  1417. dp_verbose_debug("rx NF mask 0x%x ring %d, work_done %d budget %d",
  1418. rx_near_full_mask, ring,
  1419. work_done,
  1420. budget);
  1421. budget -= work_done;
  1422. if (budget <= 0)
  1423. goto budget_done;
  1424. remaining_quota = budget;
  1425. }
  1426. }
  1427. }
  1428. if (tx_ring_near_full_mask) {
  1429. for (ring = 0; ring < soc->num_tcl_data_rings; ring++) {
  1430. if (!(tx_ring_near_full_mask & (1 << ring)))
  1431. continue;
  1432. work_done = dp_tx_comp_nf_handler(int_ctx, soc,
  1433. soc->tx_comp_ring[ring].hal_srng,
  1434. ring, remaining_quota);
  1435. if (work_done) {
  1436. intr_stats->num_tx_comp_ring_near_full_masks[ring]++;
  1437. dp_verbose_debug("tx NF mask 0x%x ring %d, work_done %d budget %d",
  1438. tx_ring_near_full_mask, ring,
  1439. work_done, budget);
  1440. budget -= work_done;
  1441. if (budget <= 0)
  1442. break;
  1443. remaining_quota = budget;
  1444. }
  1445. }
  1446. }
  1447. intr_stats->num_near_full_masks++;
  1448. budget_done:
  1449. return dp_budget - budget;
  1450. }
  1451. /**
  1452. * dp_srng_test_and_update_nf_params_be() - Check if the srng is in near full
  1453. * state and set the reap_limit appropriately
  1454. * as per the near full state
  1455. * @soc: Datapath soc handle
  1456. * @dp_srng: Datapath handle for SRNG
  1457. * @max_reap_limit: [Output Buffer] Buffer to set the max reap limit as per
  1458. * the srng near-full state
  1459. *
  1460. * Return: 1, if the srng is in near-full state
  1461. * 0, if the srng is not in near-full state
  1462. */
  1463. static int
  1464. dp_srng_test_and_update_nf_params_be(struct dp_soc *soc,
  1465. struct dp_srng *dp_srng,
  1466. int *max_reap_limit)
  1467. {
  1468. return _dp_srng_test_and_update_nf_params(soc, dp_srng, max_reap_limit);
  1469. }
  1470. /**
  1471. * dp_init_near_full_arch_ops_be() - Initialize the arch ops handler for the
  1472. * near full IRQ handling operations.
  1473. * @arch_ops: arch ops handle
  1474. *
  1475. * Return: none
  1476. */
  1477. static inline void
  1478. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1479. {
  1480. arch_ops->dp_service_near_full_srngs = dp_service_near_full_srngs_be;
  1481. arch_ops->dp_srng_test_and_update_nf_params =
  1482. dp_srng_test_and_update_nf_params_be;
  1483. }
  1484. #else
  1485. static inline void
  1486. dp_init_near_full_arch_ops_be(struct dp_arch_ops *arch_ops)
  1487. {
  1488. }
  1489. #endif
  1490. static inline
  1491. QDF_STATUS dp_srng_init_be(struct dp_soc *soc, struct dp_srng *srng,
  1492. int ring_type, int ring_num, int mac_id)
  1493. {
  1494. return dp_srng_init_idx(soc, srng, ring_type, ring_num, mac_id, 0);
  1495. }
  1496. #ifdef WLAN_SUPPORT_PPEDS
  1497. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1498. {
  1499. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1500. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1501. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1502. if (!be_soc->ppeds_handle)
  1503. return;
  1504. dp_srng_deinit(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0);
  1505. wlan_minidump_remove(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1506. be_soc->ppe2tcl_ring.alloc_size,
  1507. soc->ctrl_psoc,
  1508. WLAN_MD_DP_SRNG_PPE2TCL,
  1509. "ppe2tcl_ring");
  1510. dp_srng_deinit(soc, &be_soc->reo2ppe_ring, REO2PPE, 0);
  1511. wlan_minidump_remove(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1512. be_soc->reo2ppe_ring.alloc_size,
  1513. soc->ctrl_psoc,
  1514. WLAN_MD_DP_SRNG_REO2PPE,
  1515. "reo2ppe_ring");
  1516. dp_srng_deinit(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1517. WBM2_SW_PPE_REL_RING_ID);
  1518. wlan_minidump_remove(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1519. be_soc->ppeds_wbm_release_ring.alloc_size,
  1520. soc->ctrl_psoc,
  1521. WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1522. "ppeds_wbm_release_ring");
  1523. }
  1524. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1525. {
  1526. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1527. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1528. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1529. dp_srng_free(soc, &be_soc->ppeds_wbm_release_ring);
  1530. dp_srng_free(soc, &be_soc->ppe2tcl_ring);
  1531. dp_srng_free(soc, &be_soc->reo2ppe_ring);
  1532. }
  1533. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1534. {
  1535. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1536. uint32_t entries;
  1537. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1538. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1539. if (!be_soc->ppeds_handle)
  1540. return QDF_STATUS_SUCCESS;
  1541. entries = wlan_cfg_get_dp_soc_reo2ppe_ring_size(soc_cfg_ctx);
  1542. if (dp_srng_alloc(soc, &be_soc->reo2ppe_ring, REO2PPE,
  1543. entries, 0)) {
  1544. dp_err("%pK: dp_srng_alloc failed for reo2ppe", soc);
  1545. goto fail;
  1546. }
  1547. entries = wlan_cfg_get_dp_soc_ppe2tcl_ring_size(soc_cfg_ctx);
  1548. if (dp_srng_alloc(soc, &be_soc->ppe2tcl_ring, PPE2TCL,
  1549. entries, 0)) {
  1550. dp_err("%pK: dp_srng_alloc failed for ppe2tcl_ring", soc);
  1551. goto fail;
  1552. }
  1553. entries = wlan_cfg_tx_comp_ring_size(soc_cfg_ctx);
  1554. if (dp_srng_alloc(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1555. entries, 1)) {
  1556. dp_err("%pK: dp_srng_alloc failed for ppeds_wbm_release_ring",
  1557. soc);
  1558. goto fail;
  1559. }
  1560. return QDF_STATUS_SUCCESS;
  1561. fail:
  1562. dp_soc_ppeds_srng_free(soc);
  1563. return QDF_STATUS_E_NOMEM;
  1564. }
  1565. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1566. {
  1567. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1568. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1569. hal_soc_handle_t hal_soc = soc->hal_soc;
  1570. struct dp_ppe_ds_idxs idx = {0};
  1571. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1572. if (!be_soc->ppeds_handle)
  1573. return QDF_STATUS_SUCCESS;
  1574. if (dp_ppeds_register_soc_be(be_soc, &idx)) {
  1575. dp_err("%pK: ppeds registration failed", soc);
  1576. goto fail;
  1577. }
  1578. if (dp_srng_init_idx(soc, &be_soc->reo2ppe_ring, REO2PPE, 0, 0,
  1579. idx.reo2ppe_start_idx)) {
  1580. dp_err("%pK: dp_srng_init failed for reo2ppe", soc);
  1581. goto fail;
  1582. }
  1583. wlan_minidump_log(be_soc->reo2ppe_ring.base_vaddr_unaligned,
  1584. be_soc->reo2ppe_ring.alloc_size,
  1585. soc->ctrl_psoc,
  1586. WLAN_MD_DP_SRNG_REO2PPE,
  1587. "reo2ppe_ring");
  1588. hal_reo_config_reo2ppe_dest_info(hal_soc);
  1589. if (dp_srng_init_idx(soc, &be_soc->ppe2tcl_ring, PPE2TCL, 0, 0,
  1590. idx.ppe2tcl_start_idx)) {
  1591. dp_err("%pK: dp_srng_init failed for ppe2tcl_ring", soc);
  1592. goto fail;
  1593. }
  1594. wlan_minidump_log(be_soc->ppe2tcl_ring.base_vaddr_unaligned,
  1595. be_soc->ppe2tcl_ring.alloc_size,
  1596. soc->ctrl_psoc,
  1597. WLAN_MD_DP_SRNG_PPE2TCL,
  1598. "ppe2tcl_ring");
  1599. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  1600. be_soc->ppe2tcl_ring.hal_srng,
  1601. WBM2_SW_PPE_REL_MAP_ID);
  1602. if (dp_srng_init(soc, &be_soc->ppeds_wbm_release_ring, WBM2SW_RELEASE,
  1603. WBM2_SW_PPE_REL_RING_ID, 0)) {
  1604. dp_err("%pK: dp_srng_init failed for ppeds_wbm_release_ring",
  1605. soc);
  1606. goto fail;
  1607. }
  1608. wlan_minidump_log(be_soc->ppeds_wbm_release_ring.base_vaddr_unaligned,
  1609. be_soc->ppeds_wbm_release_ring.alloc_size,
  1610. soc->ctrl_psoc, WLAN_MD_DP_SRNG_PPE_WBM2SW_RELEASE,
  1611. "ppeds_wbm_release_ring");
  1612. return QDF_STATUS_SUCCESS;
  1613. fail:
  1614. dp_soc_ppeds_srng_deinit(soc);
  1615. return QDF_STATUS_E_NOMEM;
  1616. }
  1617. #else
  1618. static void dp_soc_ppeds_srng_deinit(struct dp_soc *soc)
  1619. {
  1620. }
  1621. static void dp_soc_ppeds_srng_free(struct dp_soc *soc)
  1622. {
  1623. }
  1624. static QDF_STATUS dp_soc_ppeds_srng_alloc(struct dp_soc *soc)
  1625. {
  1626. return QDF_STATUS_SUCCESS;
  1627. }
  1628. static QDF_STATUS dp_soc_ppeds_srng_init(struct dp_soc *soc)
  1629. {
  1630. return QDF_STATUS_SUCCESS;
  1631. }
  1632. #endif
  1633. static void dp_soc_srng_deinit_be(struct dp_soc *soc)
  1634. {
  1635. uint32_t i;
  1636. dp_soc_ppeds_srng_deinit(soc);
  1637. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1638. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1639. dp_srng_deinit(soc, &soc->rx_refill_buf_ring[i],
  1640. RXDMA_BUF, 0);
  1641. }
  1642. }
  1643. }
  1644. static void dp_soc_srng_free_be(struct dp_soc *soc)
  1645. {
  1646. uint32_t i;
  1647. dp_soc_ppeds_srng_free(soc);
  1648. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1649. for (i = 0; i < soc->num_rx_refill_buf_rings; i++)
  1650. dp_srng_free(soc, &soc->rx_refill_buf_ring[i]);
  1651. }
  1652. }
  1653. static QDF_STATUS dp_soc_srng_alloc_be(struct dp_soc *soc)
  1654. {
  1655. struct wlan_cfg_dp_soc_ctxt *soc_cfg_ctx;
  1656. uint32_t ring_size;
  1657. uint32_t i;
  1658. soc_cfg_ctx = soc->wlan_cfg_ctx;
  1659. ring_size = wlan_cfg_get_dp_soc_rxdma_refill_ring_size(soc_cfg_ctx);
  1660. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1661. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1662. if (dp_srng_alloc(soc, &soc->rx_refill_buf_ring[i],
  1663. RXDMA_BUF, ring_size, 0)) {
  1664. dp_err("%pK: dp_srng_alloc failed refill ring",
  1665. soc);
  1666. goto fail;
  1667. }
  1668. }
  1669. }
  1670. if (dp_soc_ppeds_srng_alloc(soc)) {
  1671. dp_err("%pK: ppe rings alloc failed",
  1672. soc);
  1673. goto fail;
  1674. }
  1675. return QDF_STATUS_SUCCESS;
  1676. fail:
  1677. dp_soc_srng_free_be(soc);
  1678. return QDF_STATUS_E_NOMEM;
  1679. }
  1680. static QDF_STATUS dp_soc_srng_init_be(struct dp_soc *soc)
  1681. {
  1682. int i = 0;
  1683. if (soc->features.dmac_cmn_src_rxbuf_ring_enabled) {
  1684. for (i = 0; i < soc->num_rx_refill_buf_rings; i++) {
  1685. if (dp_srng_init(soc, &soc->rx_refill_buf_ring[i],
  1686. RXDMA_BUF, 0, 0)) {
  1687. dp_err("%pK: dp_srng_init failed refill ring",
  1688. soc);
  1689. goto fail;
  1690. }
  1691. }
  1692. }
  1693. if (dp_soc_ppeds_srng_init(soc)) {
  1694. dp_err("%pK: ppe ds rings init failed",
  1695. soc);
  1696. goto fail;
  1697. }
  1698. return QDF_STATUS_SUCCESS;
  1699. fail:
  1700. dp_soc_srng_deinit_be(soc);
  1701. return QDF_STATUS_E_NOMEM;
  1702. }
  1703. #ifdef WLAN_FEATURE_11BE_MLO
  1704. static inline unsigned
  1705. dp_mlo_peer_find_hash_index(dp_mld_peer_hash_obj_t mld_hash_obj,
  1706. union dp_align_mac_addr *mac_addr)
  1707. {
  1708. uint32_t index;
  1709. index =
  1710. mac_addr->align2.bytes_ab ^
  1711. mac_addr->align2.bytes_cd ^
  1712. mac_addr->align2.bytes_ef;
  1713. index ^= index >> mld_hash_obj->mld_peer_hash.idx_bits;
  1714. index &= mld_hash_obj->mld_peer_hash.mask;
  1715. return index;
  1716. }
  1717. QDF_STATUS
  1718. dp_mlo_peer_find_hash_attach_be(dp_mld_peer_hash_obj_t mld_hash_obj,
  1719. int hash_elems)
  1720. {
  1721. int i, log2;
  1722. if (!mld_hash_obj)
  1723. return QDF_STATUS_E_FAILURE;
  1724. hash_elems *= DP_PEER_HASH_LOAD_MULT;
  1725. hash_elems >>= DP_PEER_HASH_LOAD_SHIFT;
  1726. log2 = dp_log2_ceil(hash_elems);
  1727. hash_elems = 1 << log2;
  1728. mld_hash_obj->mld_peer_hash.mask = hash_elems - 1;
  1729. mld_hash_obj->mld_peer_hash.idx_bits = log2;
  1730. /* allocate an array of TAILQ peer object lists */
  1731. mld_hash_obj->mld_peer_hash.bins = qdf_mem_malloc(
  1732. hash_elems * sizeof(TAILQ_HEAD(anonymous_tail_q, dp_peer)));
  1733. if (!mld_hash_obj->mld_peer_hash.bins)
  1734. return QDF_STATUS_E_NOMEM;
  1735. for (i = 0; i < hash_elems; i++)
  1736. TAILQ_INIT(&mld_hash_obj->mld_peer_hash.bins[i]);
  1737. qdf_spinlock_create(&mld_hash_obj->mld_peer_hash_lock);
  1738. return QDF_STATUS_SUCCESS;
  1739. }
  1740. void
  1741. dp_mlo_peer_find_hash_detach_be(dp_mld_peer_hash_obj_t mld_hash_obj)
  1742. {
  1743. if (!mld_hash_obj)
  1744. return;
  1745. if (mld_hash_obj->mld_peer_hash.bins) {
  1746. qdf_mem_free(mld_hash_obj->mld_peer_hash.bins);
  1747. mld_hash_obj->mld_peer_hash.bins = NULL;
  1748. qdf_spinlock_destroy(&mld_hash_obj->mld_peer_hash_lock);
  1749. }
  1750. }
  1751. #ifdef WLAN_MLO_MULTI_CHIP
  1752. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1753. {
  1754. /* In case of MULTI chip MLO peer hash table when MLO global object
  1755. * is created, avoid from SOC attach path
  1756. */
  1757. return QDF_STATUS_SUCCESS;
  1758. }
  1759. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1760. {
  1761. }
  1762. #else
  1763. static QDF_STATUS dp_mlo_peer_find_hash_attach_wrapper(struct dp_soc *soc)
  1764. {
  1765. dp_mld_peer_hash_obj_t mld_hash_obj;
  1766. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1767. if (!mld_hash_obj)
  1768. return QDF_STATUS_E_FAILURE;
  1769. return dp_mlo_peer_find_hash_attach_be(mld_hash_obj, soc->max_peers);
  1770. }
  1771. static void dp_mlo_peer_find_hash_detach_wrapper(struct dp_soc *soc)
  1772. {
  1773. dp_mld_peer_hash_obj_t mld_hash_obj;
  1774. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1775. if (!mld_hash_obj)
  1776. return;
  1777. return dp_mlo_peer_find_hash_detach_be(mld_hash_obj);
  1778. }
  1779. #endif
  1780. #ifdef QCA_ENHANCED_STATS_SUPPORT
  1781. static uint8_t
  1782. dp_get_hw_link_id_be(struct dp_pdev *pdev)
  1783. {
  1784. struct dp_pdev_be *be_pdev = dp_get_be_pdev_from_dp_pdev(pdev);
  1785. return be_pdev->mlo_link_id;
  1786. }
  1787. #else
  1788. static uint8_t
  1789. dp_get_hw_link_id_be(struct dp_pdev *pdev)
  1790. {
  1791. return 0;
  1792. }
  1793. #endif /* QCA_ENHANCED_STATS_SUPPORT */
  1794. static struct dp_peer *
  1795. dp_mlo_peer_find_hash_find_be(struct dp_soc *soc,
  1796. uint8_t *peer_mac_addr,
  1797. int mac_addr_is_aligned,
  1798. enum dp_mod_id mod_id,
  1799. uint8_t vdev_id)
  1800. {
  1801. union dp_align_mac_addr local_mac_addr_aligned, *mac_addr;
  1802. uint32_t index;
  1803. struct dp_peer *peer;
  1804. struct dp_vdev *vdev;
  1805. dp_mld_peer_hash_obj_t mld_hash_obj;
  1806. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1807. if (!mld_hash_obj)
  1808. return NULL;
  1809. if (!mld_hash_obj->mld_peer_hash.bins)
  1810. return NULL;
  1811. if (mac_addr_is_aligned) {
  1812. mac_addr = (union dp_align_mac_addr *)peer_mac_addr;
  1813. } else {
  1814. qdf_mem_copy(
  1815. &local_mac_addr_aligned.raw[0],
  1816. peer_mac_addr, QDF_MAC_ADDR_SIZE);
  1817. mac_addr = &local_mac_addr_aligned;
  1818. }
  1819. if (vdev_id != DP_VDEV_ALL) {
  1820. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, mod_id);
  1821. if (!vdev) {
  1822. dp_err("vdev is null");
  1823. return NULL;
  1824. }
  1825. } else {
  1826. vdev = NULL;
  1827. }
  1828. /* search mld peer table if no link peer for given mac address */
  1829. index = dp_mlo_peer_find_hash_index(mld_hash_obj, mac_addr);
  1830. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1831. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1832. hash_list_elem) {
  1833. if (dp_peer_find_mac_addr_cmp(mac_addr, &peer->mac_addr) == 0) {
  1834. if ((vdev_id == DP_VDEV_ALL) || (
  1835. dp_peer_find_mac_addr_cmp(
  1836. &peer->vdev->mld_mac_addr,
  1837. &vdev->mld_mac_addr) == 0)) {
  1838. /* take peer reference before returning */
  1839. if (dp_peer_get_ref(NULL, peer, mod_id) !=
  1840. QDF_STATUS_SUCCESS)
  1841. peer = NULL;
  1842. if (vdev)
  1843. dp_vdev_unref_delete(soc, vdev, mod_id);
  1844. qdf_spin_unlock_bh(
  1845. &mld_hash_obj->mld_peer_hash_lock);
  1846. return peer;
  1847. }
  1848. }
  1849. }
  1850. if (vdev)
  1851. dp_vdev_unref_delete(soc, vdev, mod_id);
  1852. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1853. return NULL; /* failure */
  1854. }
  1855. static void
  1856. dp_mlo_peer_find_hash_remove_be(struct dp_soc *soc, struct dp_peer *peer)
  1857. {
  1858. uint32_t index;
  1859. struct dp_peer *tmppeer = NULL;
  1860. int found = 0;
  1861. dp_mld_peer_hash_obj_t mld_hash_obj;
  1862. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1863. if (!mld_hash_obj)
  1864. return;
  1865. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1866. QDF_ASSERT(!TAILQ_EMPTY(&mld_hash_obj->mld_peer_hash.bins[index]));
  1867. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1868. TAILQ_FOREACH(tmppeer, &mld_hash_obj->mld_peer_hash.bins[index],
  1869. hash_list_elem) {
  1870. if (tmppeer == peer) {
  1871. found = 1;
  1872. break;
  1873. }
  1874. }
  1875. QDF_ASSERT(found);
  1876. TAILQ_REMOVE(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1877. hash_list_elem);
  1878. dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") removed. (found %u)",
  1879. peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw), found);
  1880. dp_peer_unref_delete(peer, DP_MOD_ID_CONFIG);
  1881. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1882. }
  1883. static void
  1884. dp_mlo_peer_find_hash_add_be(struct dp_soc *soc, struct dp_peer *peer)
  1885. {
  1886. uint32_t index;
  1887. dp_mld_peer_hash_obj_t mld_hash_obj;
  1888. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1889. if (!mld_hash_obj)
  1890. return;
  1891. index = dp_mlo_peer_find_hash_index(mld_hash_obj, &peer->mac_addr);
  1892. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1893. if (QDF_IS_STATUS_ERROR(dp_peer_get_ref(NULL, peer,
  1894. DP_MOD_ID_CONFIG))) {
  1895. dp_err("fail to get peer ref:" QDF_MAC_ADDR_FMT,
  1896. QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1897. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1898. return;
  1899. }
  1900. TAILQ_INSERT_TAIL(&mld_hash_obj->mld_peer_hash.bins[index], peer,
  1901. hash_list_elem);
  1902. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1903. dp_info("Peer %pK (" QDF_MAC_ADDR_FMT ") added",
  1904. peer, QDF_MAC_ADDR_REF(peer->mac_addr.raw));
  1905. }
  1906. void dp_print_mlo_ast_stats_be(struct dp_soc *soc)
  1907. {
  1908. uint32_t index;
  1909. struct dp_peer *peer;
  1910. dp_mld_peer_hash_obj_t mld_hash_obj;
  1911. mld_hash_obj = dp_mlo_get_peer_hash_obj(soc);
  1912. if (!mld_hash_obj)
  1913. return;
  1914. qdf_spin_lock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1915. for (index = 0; index < mld_hash_obj->mld_peer_hash.mask; index++) {
  1916. TAILQ_FOREACH(peer, &mld_hash_obj->mld_peer_hash.bins[index],
  1917. hash_list_elem) {
  1918. dp_print_peer_ast_entries(soc, peer, NULL);
  1919. }
  1920. }
  1921. qdf_spin_unlock_bh(&mld_hash_obj->mld_peer_hash_lock);
  1922. }
  1923. #endif
  1924. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  1925. static void dp_reconfig_tx_vdev_mcast_ctrl_be(struct dp_soc *soc,
  1926. struct dp_vdev *vdev)
  1927. {
  1928. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1929. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1930. hal_soc_handle_t hal_soc = soc->hal_soc;
  1931. uint8_t vdev_id = vdev->vdev_id;
  1932. if (vdev->opmode == wlan_op_mode_sta) {
  1933. if (vdev->pdev->isolation)
  1934. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1935. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1936. else
  1937. hal_tx_vdev_mcast_ctrl_set(hal_soc, vdev_id,
  1938. HAL_TX_MCAST_CTRL_MEC_NOTIFY);
  1939. } else if (vdev->opmode == wlan_op_mode_ap) {
  1940. hal_tx_mcast_mlo_reinject_routing_set(
  1941. hal_soc,
  1942. HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY);
  1943. if (vdev->mlo_vdev) {
  1944. hal_tx_vdev_mcast_ctrl_set(
  1945. hal_soc,
  1946. vdev_id,
  1947. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  1948. } else {
  1949. hal_tx_vdev_mcast_ctrl_set(hal_soc,
  1950. vdev_id,
  1951. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  1952. }
  1953. }
  1954. }
  1955. static void dp_bank_reconfig_be(struct dp_soc *soc, struct dp_vdev *vdev)
  1956. {
  1957. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  1958. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1959. union hal_tx_bank_config *bank_config;
  1960. if (!be_vdev || be_vdev->bank_id == DP_BE_INVALID_BANK_ID)
  1961. return;
  1962. bank_config = &be_soc->bank_profiles[be_vdev->bank_id].bank_config;
  1963. hal_tx_populate_bank_register(be_soc->soc.hal_soc, bank_config,
  1964. be_vdev->bank_id);
  1965. }
  1966. #endif
  1967. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1968. defined(WLAN_MCAST_MLO)
  1969. static void dp_mlo_mcast_reset_pri_mcast(struct dp_vdev_be *be_vdev,
  1970. struct dp_vdev *ptnr_vdev,
  1971. void *arg)
  1972. {
  1973. struct dp_vdev_be *be_ptnr_vdev =
  1974. dp_get_be_vdev_from_dp_vdev(ptnr_vdev);
  1975. be_ptnr_vdev->mcast_primary = false;
  1976. }
  1977. #if defined(CONFIG_MLO_SINGLE_DEV)
  1978. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  1979. struct dp_vdev *vdev,
  1980. cdp_config_param_type val)
  1981. {
  1982. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  1983. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  1984. be_vdev->vdev.pdev->soc);
  1985. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  1986. vdev->mlo_vdev = true;
  1987. if (be_vdev->mcast_primary) {
  1988. struct cdp_txrx_peer_params_update params = {0};
  1989. params.chip_id = be_soc->mlo_chip_id;
  1990. params.pdev_id = be_vdev->vdev.pdev->pdev_id;
  1991. params.osif_vdev = be_vdev->vdev.osif_vdev;
  1992. dp_wdi_event_handler(
  1993. WDI_EVENT_MCAST_PRIMARY_UPDATE,
  1994. be_vdev->vdev.pdev->soc,
  1995. (void *)&params, CDP_INVALID_PEER,
  1996. WDI_NO_VAL, params.pdev_id);
  1997. }
  1998. }
  1999. static
  2000. void dp_get_vdev_stats_for_unmap_peer_be(struct dp_vdev *vdev,
  2001. struct dp_peer *peer,
  2002. struct cdp_vdev_stats **vdev_stats)
  2003. {
  2004. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2005. if (!IS_DP_LEGACY_PEER(peer))
  2006. *vdev_stats = &be_vdev->mlo_stats;
  2007. }
  2008. #else
  2009. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  2010. struct dp_vdev *vdev,
  2011. cdp_config_param_type val)
  2012. {
  2013. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2014. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(
  2015. be_vdev->vdev.pdev->soc);
  2016. be_vdev->mcast_primary = val.cdp_vdev_param_mcast_vdev;
  2017. vdev->mlo_vdev = true;
  2018. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  2019. vdev->vdev_id,
  2020. HAL_TX_MCAST_CTRL_NO_SPECIAL);
  2021. if (be_vdev->mcast_primary) {
  2022. struct cdp_txrx_peer_params_update params = {0};
  2023. dp_mlo_iter_ptnr_vdev(be_soc, be_vdev,
  2024. dp_mlo_mcast_reset_pri_mcast,
  2025. (void *)&be_vdev->mcast_primary,
  2026. DP_MOD_ID_TX_MCAST);
  2027. params.chip_id = be_soc->mlo_chip_id;
  2028. params.pdev_id = vdev->pdev->pdev_id;
  2029. params.osif_vdev = vdev->osif_vdev;
  2030. dp_wdi_event_handler(
  2031. WDI_EVENT_MCAST_PRIMARY_UPDATE,
  2032. vdev->pdev->soc,
  2033. (void *)&params, CDP_INVALID_PEER,
  2034. WDI_NO_VAL, params.pdev_id);
  2035. }
  2036. }
  2037. #endif
  2038. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  2039. struct dp_vdev *vdev,
  2040. cdp_config_param_type val)
  2041. {
  2042. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2043. be_vdev->mcast_primary = false;
  2044. vdev->mlo_vdev = false;
  2045. hal_tx_vdev_mcast_ctrl_set(vdev->pdev->soc->hal_soc,
  2046. vdev->vdev_id,
  2047. HAL_TX_MCAST_CTRL_FW_EXCEPTION);
  2048. }
  2049. /**
  2050. * dp_txrx_get_vdev_mcast_param_be() - Target specific ops for getting vdev
  2051. * params related to multicast
  2052. * @soc: DP soc handle
  2053. * @vdev: pointer to vdev structure
  2054. * @val: buffer address
  2055. *
  2056. * Return: QDF_STATUS
  2057. */
  2058. static
  2059. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  2060. struct dp_vdev *vdev,
  2061. cdp_config_param_type *val)
  2062. {
  2063. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2064. if (be_vdev->mcast_primary)
  2065. val->cdp_vdev_param_mcast_vdev = true;
  2066. else
  2067. val->cdp_vdev_param_mcast_vdev = false;
  2068. return QDF_STATUS_SUCCESS;
  2069. }
  2070. #else
  2071. static void dp_txrx_set_mlo_mcast_primary_vdev_param_be(
  2072. struct dp_vdev *vdev,
  2073. cdp_config_param_type val)
  2074. {
  2075. }
  2076. static void dp_txrx_reset_mlo_mcast_primary_vdev_param_be(
  2077. struct dp_vdev *vdev,
  2078. cdp_config_param_type val)
  2079. {
  2080. }
  2081. static
  2082. QDF_STATUS dp_txrx_get_vdev_mcast_param_be(struct dp_soc *soc,
  2083. struct dp_vdev *vdev,
  2084. cdp_config_param_type *val)
  2085. {
  2086. return QDF_STATUS_SUCCESS;
  2087. }
  2088. static
  2089. void dp_get_vdev_stats_for_unmap_peer_be(struct dp_vdev *vdev,
  2090. struct dp_peer *peer,
  2091. struct cdp_vdev_stats **vdev_stats)
  2092. {
  2093. }
  2094. #endif
  2095. #ifdef DP_TX_IMPLICIT_RBM_MAPPING
  2096. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  2097. uint8_t tx_ring_id,
  2098. uint8_t bm_id)
  2099. {
  2100. hal_tx_config_rbm_mapping_be(soc->hal_soc,
  2101. soc->tcl_data_ring[tx_ring_id].hal_srng,
  2102. bm_id);
  2103. }
  2104. #else
  2105. static void dp_tx_implicit_rbm_set_be(struct dp_soc *soc,
  2106. uint8_t tx_ring_id,
  2107. uint8_t bm_id)
  2108. {
  2109. }
  2110. #endif
  2111. /**
  2112. * dp_txrx_set_vdev_param_be() - Target specific ops while setting vdev params
  2113. * @soc: DP soc handle
  2114. * @vdev: pointer to vdev structure
  2115. * @param: parameter type to get value
  2116. * @val: value
  2117. *
  2118. * Return: QDF_STATUS
  2119. */
  2120. static
  2121. QDF_STATUS dp_txrx_set_vdev_param_be(struct dp_soc *soc,
  2122. struct dp_vdev *vdev,
  2123. enum cdp_vdev_param_type param,
  2124. cdp_config_param_type val)
  2125. {
  2126. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2127. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  2128. switch (param) {
  2129. case CDP_TX_ENCAP_TYPE:
  2130. case CDP_UPDATE_DSCP_TO_TID_MAP:
  2131. case CDP_UPDATE_TDLS_FLAGS:
  2132. dp_tx_update_bank_profile(be_soc, be_vdev);
  2133. break;
  2134. case CDP_ENABLE_CIPHER:
  2135. if (vdev->tx_encap_type == htt_cmn_pkt_type_raw)
  2136. dp_tx_update_bank_profile(be_soc, be_vdev);
  2137. break;
  2138. case CDP_SET_MCAST_VDEV:
  2139. dp_txrx_set_mlo_mcast_primary_vdev_param_be(vdev, val);
  2140. break;
  2141. case CDP_RESET_MLO_MCAST_VDEV:
  2142. dp_txrx_reset_mlo_mcast_primary_vdev_param_be(vdev, val);
  2143. break;
  2144. default:
  2145. dp_warn("invalid param %d", param);
  2146. break;
  2147. }
  2148. return QDF_STATUS_SUCCESS;
  2149. }
  2150. #ifdef WLAN_FEATURE_11BE_MLO
  2151. #ifdef DP_USE_REDUCED_PEER_ID_FIELD_WIDTH
  2152. static inline void
  2153. dp_soc_max_peer_id_set(struct dp_soc *soc)
  2154. {
  2155. soc->peer_id_shift = dp_log2_ceil(soc->max_peers);
  2156. soc->peer_id_mask = (1 << soc->peer_id_shift) - 1;
  2157. /*
  2158. * Double the peers since we use ML indication bit
  2159. * alongwith peer_id to find peers.
  2160. */
  2161. soc->max_peer_id = 1 << (soc->peer_id_shift + 1);
  2162. }
  2163. #else
  2164. static inline void
  2165. dp_soc_max_peer_id_set(struct dp_soc *soc)
  2166. {
  2167. soc->max_peer_id =
  2168. (1 << (HTT_RX_PEER_META_DATA_V1_ML_PEER_VALID_S + 1)) - 1;
  2169. }
  2170. #endif /* DP_USE_REDUCED_PEER_ID_FIELD_WIDTH */
  2171. #else
  2172. static inline void
  2173. dp_soc_max_peer_id_set(struct dp_soc *soc)
  2174. {
  2175. soc->max_peer_id = soc->max_peers;
  2176. }
  2177. #endif /* WLAN_FEATURE_11BE_MLO */
  2178. static void dp_peer_map_detach_be(struct dp_soc *soc)
  2179. {
  2180. if (soc->host_ast_db_enable)
  2181. dp_peer_ast_hash_detach(soc);
  2182. }
  2183. static QDF_STATUS dp_peer_map_attach_be(struct dp_soc *soc)
  2184. {
  2185. QDF_STATUS status;
  2186. if (soc->host_ast_db_enable) {
  2187. status = dp_peer_ast_hash_attach(soc);
  2188. if (QDF_IS_STATUS_ERROR(status))
  2189. return status;
  2190. }
  2191. dp_soc_max_peer_id_set(soc);
  2192. return QDF_STATUS_SUCCESS;
  2193. }
  2194. static struct dp_peer *dp_find_peer_by_destmac_be(struct dp_soc *soc,
  2195. uint8_t *dest_mac,
  2196. uint8_t vdev_id)
  2197. {
  2198. struct dp_peer *peer = NULL;
  2199. struct dp_peer *tgt_peer = NULL;
  2200. struct dp_ast_entry *ast_entry = NULL;
  2201. uint16_t peer_id;
  2202. qdf_spin_lock_bh(&soc->ast_lock);
  2203. ast_entry = dp_peer_ast_hash_find_soc(soc, dest_mac);
  2204. if (!ast_entry) {
  2205. qdf_spin_unlock_bh(&soc->ast_lock);
  2206. dp_err("NULL ast entry");
  2207. return NULL;
  2208. }
  2209. peer_id = ast_entry->peer_id;
  2210. qdf_spin_unlock_bh(&soc->ast_lock);
  2211. if (peer_id == HTT_INVALID_PEER)
  2212. return NULL;
  2213. peer = dp_peer_get_ref_by_id(soc, peer_id, DP_MOD_ID_SAWF);
  2214. if (!peer) {
  2215. dp_err("NULL peer for peer_id:%d", peer_id);
  2216. return NULL;
  2217. }
  2218. tgt_peer = dp_get_tgt_peer_from_peer(peer);
  2219. /*
  2220. * Once tgt_peer is obtained,
  2221. * release the ref taken for original peer.
  2222. */
  2223. dp_peer_get_ref(NULL, tgt_peer, DP_MOD_ID_SAWF);
  2224. dp_peer_unref_delete(peer, DP_MOD_ID_SAWF);
  2225. return tgt_peer;
  2226. }
  2227. #ifdef WLAN_FEATURE_11BE_MLO
  2228. #ifdef WLAN_MCAST_MLO
  2229. static inline void
  2230. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  2231. {
  2232. arch_ops->dp_tx_mcast_handler = dp_tx_mlo_mcast_handler_be;
  2233. arch_ops->dp_rx_mcast_handler = dp_rx_mlo_igmp_handler;
  2234. arch_ops->dp_tx_is_mcast_primary = dp_tx_mlo_is_mcast_primary_be;
  2235. }
  2236. #else /* WLAN_MCAST_MLO */
  2237. static inline void
  2238. dp_initialize_arch_ops_be_mcast_mlo(struct dp_arch_ops *arch_ops)
  2239. {
  2240. }
  2241. #endif /* WLAN_MCAST_MLO */
  2242. #ifdef WLAN_MLO_MULTI_CHIP
  2243. static inline void
  2244. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  2245. {
  2246. arch_ops->dp_partner_chips_map = dp_mlo_partner_chips_map;
  2247. arch_ops->dp_partner_chips_unmap = dp_mlo_partner_chips_unmap;
  2248. arch_ops->dp_soc_get_by_idle_bm_id = dp_soc_get_by_idle_bm_id;
  2249. }
  2250. #else
  2251. static inline void
  2252. dp_initialize_arch_ops_be_mlo_multi_chip(struct dp_arch_ops *arch_ops)
  2253. {
  2254. }
  2255. #endif
  2256. static inline void
  2257. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  2258. {
  2259. dp_initialize_arch_ops_be_mcast_mlo(arch_ops);
  2260. dp_initialize_arch_ops_be_mlo_multi_chip(arch_ops);
  2261. arch_ops->mlo_peer_find_hash_detach =
  2262. dp_mlo_peer_find_hash_detach_wrapper;
  2263. arch_ops->mlo_peer_find_hash_attach =
  2264. dp_mlo_peer_find_hash_attach_wrapper;
  2265. arch_ops->mlo_peer_find_hash_add = dp_mlo_peer_find_hash_add_be;
  2266. arch_ops->mlo_peer_find_hash_remove = dp_mlo_peer_find_hash_remove_be;
  2267. arch_ops->mlo_peer_find_hash_find = dp_mlo_peer_find_hash_find_be;
  2268. arch_ops->get_hw_link_id = dp_get_hw_link_id_be;
  2269. }
  2270. #else /* WLAN_FEATURE_11BE_MLO */
  2271. static inline void
  2272. dp_initialize_arch_ops_be_mlo(struct dp_arch_ops *arch_ops)
  2273. {
  2274. }
  2275. #endif /* WLAN_FEATURE_11BE_MLO */
  2276. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  2277. #define DP_LMAC_PEER_ID_MSB_LEGACY 2
  2278. #define DP_LMAC_PEER_ID_MSB_MLO 3
  2279. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  2280. struct cdp_peer_setup_info *setup_info,
  2281. enum cdp_host_reo_dest_ring *reo_dest,
  2282. bool *hash_based,
  2283. uint8_t *lmac_peer_id_msb)
  2284. {
  2285. struct dp_soc *soc = vdev->pdev->soc;
  2286. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2287. if (!be_soc->mlo_enabled)
  2288. return dp_vdev_get_default_reo_hash(vdev, reo_dest,
  2289. hash_based);
  2290. *hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2291. *reo_dest = vdev->pdev->reo_dest;
  2292. /* Not a ML link peer use non-mlo */
  2293. if (!setup_info) {
  2294. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  2295. return;
  2296. }
  2297. /* For STA ML VAP we do not have num links info at this point
  2298. * use MLO case always
  2299. */
  2300. if (vdev->opmode == wlan_op_mode_sta) {
  2301. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  2302. return;
  2303. }
  2304. /* For AP ML VAP consider the peer as ML only it associates with
  2305. * multiple links
  2306. */
  2307. if (setup_info->num_links == 1) {
  2308. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_LEGACY;
  2309. return;
  2310. }
  2311. *lmac_peer_id_msb = DP_LMAC_PEER_ID_MSB_MLO;
  2312. }
  2313. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2314. uint32_t *remap0,
  2315. uint32_t *remap1,
  2316. uint32_t *remap2)
  2317. {
  2318. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2319. uint32_t reo_config = wlan_cfg_get_reo_rings_mapping(soc->wlan_cfg_ctx);
  2320. uint32_t reo_mlo_config =
  2321. wlan_cfg_mlo_rx_ring_map_get(soc->wlan_cfg_ctx);
  2322. if (!be_soc->mlo_enabled)
  2323. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2324. *remap0 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2325. *remap1 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_config);
  2326. *remap2 = hal_reo_ix_remap_value_get_be(soc->hal_soc, reo_mlo_config);
  2327. return true;
  2328. }
  2329. #else
  2330. static void dp_peer_get_reo_hash_be(struct dp_vdev *vdev,
  2331. struct cdp_peer_setup_info *setup_info,
  2332. enum cdp_host_reo_dest_ring *reo_dest,
  2333. bool *hash_based,
  2334. uint8_t *lmac_peer_id_msb)
  2335. {
  2336. dp_vdev_get_default_reo_hash(vdev, reo_dest, hash_based);
  2337. }
  2338. static bool dp_reo_remap_config_be(struct dp_soc *soc,
  2339. uint32_t *remap0,
  2340. uint32_t *remap1,
  2341. uint32_t *remap2)
  2342. {
  2343. return dp_reo_remap_config(soc, remap0, remap1, remap2);
  2344. }
  2345. #endif
  2346. #ifdef CONFIG_MLO_SINGLE_DEV
  2347. static inline
  2348. void dp_initialize_arch_ops_be_single_dev(struct dp_arch_ops *arch_ops)
  2349. {
  2350. arch_ops->dp_tx_mlo_mcast_send = dp_tx_mlo_mcast_send_be;
  2351. }
  2352. #else
  2353. static inline
  2354. void dp_initialize_arch_ops_be_single_dev(struct dp_arch_ops *arch_ops)
  2355. {
  2356. }
  2357. #endif
  2358. #ifdef IPA_OFFLOAD
  2359. static int8_t dp_ipa_get_bank_id_be(struct dp_soc *soc)
  2360. {
  2361. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2362. return be_soc->ipa_bank_id;
  2363. }
  2364. #ifdef QCA_IPA_LL_TX_FLOW_CONTROL
  2365. static void dp_ipa_get_wdi_version_be(uint8_t *wdi_ver)
  2366. {
  2367. *wdi_ver = IPA_WDI_4;
  2368. }
  2369. #else
  2370. static inline void dp_ipa_get_wdi_version_be(uint8_t *wdi_ver)
  2371. {
  2372. }
  2373. #endif
  2374. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2375. {
  2376. arch_ops->ipa_get_bank_id = dp_ipa_get_bank_id_be;
  2377. arch_ops->ipa_get_wdi_ver = dp_ipa_get_wdi_version_be;
  2378. }
  2379. #else /* !IPA_OFFLOAD */
  2380. static inline void dp_initialize_arch_ops_be_ipa(struct dp_arch_ops *arch_ops)
  2381. {
  2382. }
  2383. #endif /* IPA_OFFLOAD */
  2384. void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
  2385. {
  2386. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  2387. arch_ops->tx_hw_enqueue = dp_tx_hw_enqueue_be;
  2388. arch_ops->dp_rx_process = dp_rx_process_be;
  2389. arch_ops->dp_tx_send_fast = dp_tx_fast_send_be;
  2390. arch_ops->tx_comp_get_params_from_hal_desc =
  2391. dp_tx_comp_get_params_from_hal_desc_be;
  2392. arch_ops->dp_tx_process_htt_completion =
  2393. dp_tx_process_htt_completion_be;
  2394. arch_ops->dp_tx_desc_pool_alloc = dp_tx_desc_pool_alloc_be;
  2395. arch_ops->dp_tx_desc_pool_free = dp_tx_desc_pool_free_be;
  2396. arch_ops->dp_tx_desc_pool_init = dp_tx_desc_pool_init_be;
  2397. arch_ops->dp_tx_desc_pool_deinit = dp_tx_desc_pool_deinit_be;
  2398. arch_ops->dp_rx_desc_pool_init = dp_rx_desc_pool_init_be;
  2399. arch_ops->dp_rx_desc_pool_deinit = dp_rx_desc_pool_deinit_be;
  2400. arch_ops->dp_wbm_get_rx_desc_from_hal_desc =
  2401. dp_wbm_get_rx_desc_from_hal_desc_be;
  2402. arch_ops->dp_tx_compute_hw_delay = dp_tx_compute_tx_delay_be;
  2403. arch_ops->dp_rx_chain_msdus = dp_rx_chain_msdus_be;
  2404. arch_ops->dp_rx_wbm_err_reap_desc = dp_rx_wbm_err_reap_desc_be;
  2405. arch_ops->dp_rx_null_q_desc_handle = dp_rx_null_q_desc_handle_be;
  2406. #endif
  2407. arch_ops->txrx_get_context_size = dp_get_context_size_be;
  2408. #ifdef WIFI_MONITOR_SUPPORT
  2409. arch_ops->txrx_get_mon_context_size = dp_mon_get_context_size_be;
  2410. #endif
  2411. arch_ops->dp_rx_desc_cookie_2_va =
  2412. dp_rx_desc_cookie_2_va_be;
  2413. arch_ops->dp_rx_intrabss_mcast_handler =
  2414. dp_rx_intrabss_mcast_handler_be;
  2415. arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
  2416. arch_ops->txrx_soc_attach = dp_soc_attach_be;
  2417. arch_ops->txrx_soc_detach = dp_soc_detach_be;
  2418. arch_ops->txrx_soc_init = dp_soc_init_be;
  2419. arch_ops->txrx_soc_deinit = dp_soc_deinit_be_wrapper;
  2420. arch_ops->txrx_soc_srng_alloc = dp_soc_srng_alloc_be;
  2421. arch_ops->txrx_soc_srng_init = dp_soc_srng_init_be;
  2422. arch_ops->txrx_soc_srng_deinit = dp_soc_srng_deinit_be;
  2423. arch_ops->txrx_soc_srng_free = dp_soc_srng_free_be;
  2424. arch_ops->txrx_pdev_attach = dp_pdev_attach_be;
  2425. arch_ops->txrx_pdev_detach = dp_pdev_detach_be;
  2426. arch_ops->txrx_vdev_attach = dp_vdev_attach_be;
  2427. arch_ops->txrx_vdev_detach = dp_vdev_detach_be;
  2428. arch_ops->txrx_peer_setup = dp_peer_setup_be;
  2429. arch_ops->txrx_peer_map_attach = dp_peer_map_attach_be;
  2430. arch_ops->txrx_peer_map_detach = dp_peer_map_detach_be;
  2431. arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_be;
  2432. arch_ops->dp_rx_peer_metadata_peer_id_get =
  2433. dp_rx_peer_metadata_peer_id_get_be;
  2434. arch_ops->soc_cfg_attach = dp_soc_cfg_attach_be;
  2435. arch_ops->tx_implicit_rbm_set = dp_tx_implicit_rbm_set_be;
  2436. arch_ops->txrx_set_vdev_param = dp_txrx_set_vdev_param_be;
  2437. dp_initialize_arch_ops_be_mlo(arch_ops);
  2438. arch_ops->dp_rx_replenish_soc_get = dp_rx_replensih_soc_get;
  2439. arch_ops->dp_soc_get_num_soc = dp_soc_get_num_soc_be;
  2440. arch_ops->dp_peer_rx_reorder_queue_setup =
  2441. dp_peer_rx_reorder_queue_setup_be;
  2442. arch_ops->txrx_print_peer_stats = dp_print_peer_txrx_stats_be;
  2443. arch_ops->dp_find_peer_by_destmac = dp_find_peer_by_destmac_be;
  2444. #if defined(DP_UMAC_HW_HARD_RESET) && defined(DP_UMAC_HW_RESET_SUPPORT)
  2445. arch_ops->dp_bank_reconfig = dp_bank_reconfig_be;
  2446. arch_ops->dp_reconfig_tx_vdev_mcast_ctrl =
  2447. dp_reconfig_tx_vdev_mcast_ctrl_be;
  2448. arch_ops->dp_cc_reg_cfg_init = dp_cc_reg_cfg_init;
  2449. #endif
  2450. #ifdef WLAN_SUPPORT_PPEDS
  2451. arch_ops->ppeds_handle_attached = dp_ppeds_handle_attached;
  2452. arch_ops->dp_txrx_ppeds_rings_status = dp_ppeds_rings_status;
  2453. arch_ops->txrx_soc_ppeds_start = dp_ppeds_start_soc_be;
  2454. arch_ops->txrx_soc_ppeds_stop = dp_ppeds_stop_soc_be;
  2455. arch_ops->dp_register_ppeds_interrupts = dp_register_ppeds_interrupts;
  2456. arch_ops->dp_free_ppeds_interrupts = dp_free_ppeds_interrupts;
  2457. arch_ops->dp_tx_ppeds_inuse_desc = dp_ppeds_inuse_desc;
  2458. arch_ops->dp_tx_ppeds_cfg_astidx_cache_mapping =
  2459. dp_tx_ppeds_cfg_astidx_cache_mapping;
  2460. #ifdef DP_UMAC_HW_RESET_SUPPORT
  2461. arch_ops->txrx_soc_ppeds_interrupt_stop = dp_ppeds_interrupt_stop_be;
  2462. arch_ops->txrx_soc_ppeds_interrupt_start = dp_ppeds_interrupt_start_be;
  2463. arch_ops->txrx_soc_ppeds_service_status_update =
  2464. dp_ppeds_service_status_update_be;
  2465. arch_ops->txrx_soc_ppeds_enabled_check = dp_ppeds_is_enabled_on_soc;
  2466. arch_ops->txrx_soc_ppeds_txdesc_pool_reset =
  2467. dp_ppeds_tx_desc_pool_reset;
  2468. #endif
  2469. #endif
  2470. dp_init_near_full_arch_ops_be(arch_ops);
  2471. arch_ops->get_reo_qdesc_addr = dp_rx_get_reo_qdesc_addr_be;
  2472. arch_ops->get_rx_hash_key = dp_get_rx_hash_key_be;
  2473. arch_ops->dp_set_rx_fst = dp_set_rx_fst_be;
  2474. arch_ops->dp_get_rx_fst = dp_get_rx_fst_be;
  2475. arch_ops->dp_rx_fst_deref = dp_rx_fst_release_ref_be;
  2476. arch_ops->dp_rx_fst_ref = dp_rx_fst_get_ref_be;
  2477. arch_ops->print_mlo_ast_stats = dp_print_mlo_ast_stats_be;
  2478. arch_ops->peer_get_reo_hash = dp_peer_get_reo_hash_be;
  2479. arch_ops->reo_remap_config = dp_reo_remap_config_be;
  2480. arch_ops->txrx_get_vdev_mcast_param = dp_txrx_get_vdev_mcast_param_be;
  2481. arch_ops->txrx_srng_init = dp_srng_init_be;
  2482. arch_ops->dp_get_vdev_stats_for_unmap_peer =
  2483. dp_get_vdev_stats_for_unmap_peer_be;
  2484. #ifdef WLAN_MLO_MULTI_CHIP
  2485. arch_ops->dp_get_interface_stats = dp_get_interface_stats_be;
  2486. #endif
  2487. #if defined(DP_POWER_SAVE) || defined(FEATURE_RUNTIME_PM)
  2488. arch_ops->dp_update_ring_hptp = dp_update_ring_hptp;
  2489. #endif
  2490. dp_initialize_arch_ops_be_ipa(arch_ops);
  2491. dp_initialize_arch_ops_be_single_dev(arch_ops);
  2492. }
  2493. #ifdef QCA_SUPPORT_PRIMARY_LINK_MIGRATE
  2494. static void
  2495. dp_primary_link_migration(struct dp_soc *soc, void *cb_ctxt,
  2496. union hal_reo_status *reo_status)
  2497. {
  2498. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2499. struct dp_mlo_ctxt *dp_mlo = be_soc->ml_ctxt;
  2500. struct dp_soc *pr_soc = NULL;
  2501. struct dp_peer_info *pr_peer_info = (struct dp_peer_info *)cb_ctxt;
  2502. struct dp_peer *new_primary_peer = NULL;
  2503. struct dp_peer *mld_peer = NULL;
  2504. uint8_t primary_vdev_id;
  2505. struct cdp_txrx_peer_params_update params = {0};
  2506. uint8_t tid;
  2507. pr_soc = dp_mlo_get_soc_ref_by_chip_id(dp_mlo, pr_peer_info->chip_id);
  2508. if (!pr_soc) {
  2509. dp_htt_err("Invalid soc");
  2510. qdf_mem_free(pr_peer_info);
  2511. return;
  2512. }
  2513. new_primary_peer = pr_soc->peer_id_to_obj_map[
  2514. pr_peer_info->primary_peer_id];
  2515. mld_peer = DP_GET_MLD_PEER_FROM_PEER(new_primary_peer);
  2516. if (!mld_peer) {
  2517. dp_htt_err("MLD peer is NULL");
  2518. qdf_mem_free(pr_peer_info);
  2519. return;
  2520. }
  2521. new_primary_peer->primary_link = 1;
  2522. /*
  2523. * Check if reo_qref_table_en is set and if
  2524. * rx_tid qdesc for tid 0 is already setup and perform
  2525. * qref write to LUT for Tid 0 and 16.
  2526. *
  2527. */
  2528. if (hal_reo_shared_qaddr_is_enable(pr_soc->hal_soc) &&
  2529. mld_peer->rx_tid[0].hw_qdesc_vaddr_unaligned) {
  2530. for (tid = 0; tid < DP_MAX_TIDS; tid++)
  2531. hal_reo_shared_qaddr_write(pr_soc->hal_soc,
  2532. mld_peer->peer_id,
  2533. tid,
  2534. mld_peer->rx_tid[tid].hw_qdesc_paddr);
  2535. }
  2536. if (pr_soc && pr_soc->cdp_soc.ol_ops->update_primary_link)
  2537. pr_soc->cdp_soc.ol_ops->update_primary_link(pr_soc->ctrl_psoc,
  2538. new_primary_peer->mac_addr.raw);
  2539. primary_vdev_id = new_primary_peer->vdev->vdev_id;
  2540. dp_vdev_unref_delete(soc, mld_peer->vdev, DP_MOD_ID_CHILD);
  2541. mld_peer->vdev = dp_vdev_get_ref_by_id(pr_soc, primary_vdev_id,
  2542. DP_MOD_ID_CHILD);
  2543. mld_peer->txrx_peer->vdev = mld_peer->vdev;
  2544. params.osif_vdev = (void *)new_primary_peer->vdev->osif_vdev;
  2545. params.peer_mac = mld_peer->mac_addr.raw;
  2546. params.chip_id = pr_peer_info->chip_id;
  2547. params.pdev_id = new_primary_peer->vdev->pdev->pdev_id;
  2548. if (new_primary_peer->vdev->opmode == wlan_op_mode_sta) {
  2549. dp_wdi_event_handler(
  2550. WDI_EVENT_STA_PRIMARY_UMAC_UPDATE,
  2551. pr_soc, (void *)&params,
  2552. new_primary_peer->peer_id,
  2553. WDI_NO_VAL, params.pdev_id);
  2554. } else {
  2555. dp_wdi_event_handler(
  2556. WDI_EVENT_PEER_PRIMARY_UMAC_UPDATE,
  2557. pr_soc, (void *)&params,
  2558. new_primary_peer->peer_id,
  2559. WDI_NO_VAL, params.pdev_id);
  2560. }
  2561. qdf_mem_free(pr_peer_info);
  2562. }
  2563. #ifdef WLAN_SUPPORT_PPEDS
  2564. static QDF_STATUS dp_get_ppe_info_for_vap(struct cdp_soc_t *cdp_soc,
  2565. struct dp_soc *mld_soc,
  2566. struct dp_peer *pr_peer,
  2567. uint16_t *src_info)
  2568. {
  2569. struct dp_soc_be *be_soc_mld = NULL;
  2570. struct cdp_ds_vp_params vp_params = {0};
  2571. struct dp_ppe_vp_profile *ppe_vp_profile;
  2572. QDF_STATUS qdf_status = QDF_STATUS_SUCCESS;
  2573. /*
  2574. * Extract the VP profile from the VAP
  2575. */
  2576. if (!cdp_soc->ol_ops->get_ppeds_profile_info_for_vap) {
  2577. dp_err("%pK: Register get ppeds profile info first", cdp_soc);
  2578. return QDF_STATUS_E_NULL_VALUE;
  2579. }
  2580. /*
  2581. * Check if PPE DS routing is enabled on the associated vap.
  2582. */
  2583. qdf_status = cdp_soc->ol_ops->get_ppeds_profile_info_for_vap(
  2584. mld_soc->ctrl_psoc,
  2585. pr_peer->vdev->vdev_id,
  2586. &vp_params);
  2587. if (QDF_IS_STATUS_ERROR(qdf_status)) {
  2588. dp_err("Could not find ppeds profile info");
  2589. return QDF_STATUS_E_NULL_VALUE;
  2590. }
  2591. /* Check if PPE DS routing is enabled on
  2592. * the associated vap.
  2593. */
  2594. if (vp_params.ppe_vp_type != PPE_VP_USER_TYPE_DS)
  2595. return qdf_status;
  2596. be_soc_mld = dp_get_be_soc_from_dp_soc(mld_soc);
  2597. ppe_vp_profile = &be_soc_mld->ppe_vp_profile[
  2598. vp_params.ppe_vp_profile_idx];
  2599. *src_info = ppe_vp_profile->vp_num;
  2600. return qdf_status;
  2601. }
  2602. #else
  2603. static QDF_STATUS dp_get_ppe_info_for_vap(struct cdp_soc_t *cdp_soc,
  2604. struct dp_soc *mld_soc,
  2605. struct dp_peer *pr_peer,
  2606. uint16_t *src_info)
  2607. {
  2608. return QDF_STATUS_E_NOSUPPORT;
  2609. }
  2610. #endif
  2611. QDF_STATUS dp_htt_reo_migration(struct dp_soc *soc, uint16_t peer_id,
  2612. uint16_t ml_peer_id, uint16_t vdev_id,
  2613. uint8_t pdev_id, uint8_t chip_id)
  2614. {
  2615. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  2616. struct dp_mlo_ctxt *dp_mlo = be_soc->ml_ctxt;
  2617. uint16_t mld_peer_id = dp_gen_ml_peer_id(soc, ml_peer_id);
  2618. struct dp_soc *pr_soc = NULL;
  2619. struct dp_soc *current_pr_soc = NULL;
  2620. struct hal_reo_cmd_params params;
  2621. struct dp_rx_tid *rx_tid;
  2622. struct dp_peer *pr_peer = NULL;
  2623. struct dp_peer *mld_peer = NULL;
  2624. struct dp_soc *mld_soc = NULL;
  2625. struct dp_peer *current_pr_peer = NULL;
  2626. struct dp_peer_info *peer_info;
  2627. struct dp_vdev_be *be_vdev;
  2628. struct cdp_soc_t *cdp_soc;
  2629. uint16_t src_info = 0;
  2630. QDF_STATUS status;
  2631. if (!dp_mlo) {
  2632. dp_htt_err("Invalid dp_mlo ctxt");
  2633. return QDF_STATUS_E_FAILURE;
  2634. }
  2635. pr_soc = dp_mlo_get_soc_ref_by_chip_id(dp_mlo, chip_id);
  2636. if (!pr_soc) {
  2637. dp_htt_err("Invalid soc");
  2638. return QDF_STATUS_E_FAILURE;
  2639. }
  2640. pr_peer = pr_soc->peer_id_to_obj_map[peer_id];
  2641. if (!pr_peer || !(IS_MLO_DP_LINK_PEER(pr_peer))) {
  2642. dp_htt_err("Invalid peer");
  2643. return QDF_STATUS_E_FAILURE;
  2644. }
  2645. mld_peer = DP_GET_MLD_PEER_FROM_PEER(pr_peer);
  2646. if (!mld_peer || (mld_peer->peer_id != mld_peer_id)) {
  2647. dp_htt_err("Invalid mld peer");
  2648. return QDF_STATUS_E_FAILURE;
  2649. }
  2650. current_pr_peer = dp_get_primary_link_peer_by_id(
  2651. pr_soc,
  2652. mld_peer->peer_id,
  2653. DP_MOD_ID_HTT);
  2654. if (!current_pr_peer || (current_pr_peer == pr_peer)) {
  2655. dp_htt_err("Invalid peer");
  2656. return QDF_STATUS_E_FAILURE;
  2657. }
  2658. be_vdev = dp_get_be_vdev_from_dp_vdev(pr_peer->vdev);
  2659. if (!be_vdev) {
  2660. dp_htt_err("Invalid be vdev");
  2661. return QDF_STATUS_E_FAILURE;
  2662. }
  2663. mld_soc = mld_peer->vdev->pdev->soc;
  2664. cdp_soc = &mld_soc->cdp_soc;
  2665. status = dp_get_ppe_info_for_vap(cdp_soc, mld_soc, pr_peer, &src_info);
  2666. if (status == QDF_STATUS_E_NULL_VALUE) {
  2667. dp_htt_err("Invalid ppe info for the vdev");
  2668. return QDF_STATUS_E_FAILURE;
  2669. }
  2670. current_pr_soc = current_pr_peer->vdev->pdev->soc;
  2671. /* Making existing primary peer as non primary */
  2672. current_pr_peer->primary_link = 0;
  2673. dp_peer_unref_delete(current_pr_peer, DP_MOD_ID_HTT);
  2674. dp_peer_rx_reo_shared_qaddr_delete(current_pr_soc, mld_peer);
  2675. peer_info = qdf_mem_malloc(sizeof(struct dp_peer_info));
  2676. if (!peer_info) {
  2677. dp_htt_err("Malloc failed");
  2678. return QDF_STATUS_E_FAILURE;
  2679. }
  2680. peer_info->primary_peer_id = peer_id;
  2681. peer_info->chip_id = chip_id;
  2682. qdf_mem_zero(&params, sizeof(params));
  2683. rx_tid = &mld_peer->rx_tid[0];
  2684. params.std.need_status = 1;
  2685. params.std.addr_lo = rx_tid->hw_qdesc_paddr & 0xffffffff;
  2686. params.std.addr_hi = (uint64_t)(rx_tid->hw_qdesc_paddr) >> 32;
  2687. params.u.fl_cache_params.flush_no_inval = 0;
  2688. params.u.fl_cache_params.flush_entire_cache = 1;
  2689. status = dp_reo_send_cmd(current_pr_soc, CMD_FLUSH_CACHE, &params,
  2690. dp_primary_link_migration,
  2691. (void *)peer_info);
  2692. if (status != QDF_STATUS_SUCCESS) {
  2693. dp_htt_err("Reo flush failed");
  2694. qdf_mem_free(peer_info);
  2695. dp_h2t_ptqm_migration_msg_send(pr_soc, vdev_id, pdev_id,
  2696. chip_id, peer_id, ml_peer_id,
  2697. src_info, QDF_STATUS_E_FAILURE);
  2698. }
  2699. qdf_mem_zero(&params, sizeof(params));
  2700. params.std.need_status = 0;
  2701. params.std.addr_lo = rx_tid->hw_qdesc_paddr & 0xffffffff;
  2702. params.std.addr_hi = (uint64_t)(rx_tid->hw_qdesc_paddr) >> 32;
  2703. params.u.unblk_cache_params.type = UNBLOCK_CACHE;
  2704. dp_reo_send_cmd(current_pr_soc, CMD_UNBLOCK_CACHE, &params, NULL, NULL);
  2705. dp_h2t_ptqm_migration_msg_send(pr_soc, vdev_id, pdev_id,
  2706. chip_id, peer_id, ml_peer_id,
  2707. src_info, QDF_STATUS_SUCCESS);
  2708. return QDF_STATUS_SUCCESS;
  2709. }
  2710. #endif