sde_encoder.c 142 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/kthread.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/input.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/sde_rsc.h>
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include <drm/drm_crtc.h>
  27. #include <drm/drm_probe_helper.h>
  28. #include "sde_hwio.h"
  29. #include "sde_hw_catalog.h"
  30. #include "sde_hw_intf.h"
  31. #include "sde_hw_ctl.h"
  32. #include "sde_formats.h"
  33. #include "sde_encoder.h"
  34. #include "sde_encoder_phys.h"
  35. #include "sde_hw_dsc.h"
  36. #include "sde_crtc.h"
  37. #include "sde_trace.h"
  38. #include "sde_core_irq.h"
  39. #include "sde_hw_top.h"
  40. #include "sde_hw_qdss.h"
  41. #include "sde_encoder_dce.h"
  42. #define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
  43. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  44. #define SDE_ERROR_ENC(e, fmt, ...) SDE_ERROR("enc%d " fmt,\
  45. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  46. #define SDE_DEBUG_PHYS(p, fmt, ...) SDE_DEBUG("enc%d intf%d pp%d " fmt,\
  47. (p) ? (p)->parent->base.id : -1, \
  48. (p) ? (p)->intf_idx - INTF_0 : -1, \
  49. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  50. ##__VA_ARGS__)
  51. #define SDE_ERROR_PHYS(p, fmt, ...) SDE_ERROR("enc%d intf%d pp%d " fmt,\
  52. (p) ? (p)->parent->base.id : -1, \
  53. (p) ? (p)->intf_idx - INTF_0 : -1, \
  54. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  55. ##__VA_ARGS__)
  56. #define MISR_BUFF_SIZE 256
  57. #define IDLE_SHORT_TIMEOUT 1
  58. #define EVT_TIME_OUT_SPLIT 2
  59. /* Maximum number of VSYNC wait attempts for RSC state transition */
  60. #define MAX_RSC_WAIT 5
  61. /**
  62. * enum sde_enc_rc_events - events for resource control state machine
  63. * @SDE_ENC_RC_EVENT_KICKOFF:
  64. * This event happens at NORMAL priority.
  65. * Event that signals the start of the transfer. When this event is
  66. * received, enable MDP/DSI core clocks and request RSC with CMD state.
  67. * Regardless of the previous state, the resource should be in ON state
  68. * at the end of this event. At the end of this event, a delayed work is
  69. * scheduled to go to IDLE_PC state after IDLE_POWERCOLLAPSE_DURATION
  70. * ktime.
  71. * @SDE_ENC_RC_EVENT_PRE_STOP:
  72. * This event happens at NORMAL priority.
  73. * This event, when received during the ON state, set RSC to IDLE, and
  74. * and leave the RC STATE in the PRE_OFF state.
  75. * It should be followed by the STOP event as part of encoder disable.
  76. * If received during IDLE or OFF states, it will do nothing.
  77. * @SDE_ENC_RC_EVENT_STOP:
  78. * This event happens at NORMAL priority.
  79. * When this event is received, disable all the MDP/DSI core clocks, and
  80. * disable IRQs. It should be called from the PRE_OFF or IDLE states.
  81. * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  82. * PRE_OFF is expected when PRE_STOP was executed during the ON state.
  83. * Resource state should be in OFF at the end of the event.
  84. * @SDE_ENC_RC_EVENT_PRE_MODESET:
  85. * This event happens at NORMAL priority from a work item.
  86. * Event signals that there is a seamless mode switch is in prgoress. A
  87. * client needs to turn of only irq - leave clocks ON to reduce the mode
  88. * switch latency.
  89. * @SDE_ENC_RC_EVENT_POST_MODESET:
  90. * This event happens at NORMAL priority from a work item.
  91. * Event signals that seamless mode switch is complete and resources are
  92. * acquired. Clients wants to turn on the irq again and update the rsc
  93. * with new vtotal.
  94. * @SDE_ENC_RC_EVENT_ENTER_IDLE:
  95. * This event happens at NORMAL priority from a work item.
  96. * Event signals that there were no frame updates for
  97. * IDLE_POWERCOLLAPSE_DURATION time. This would disable MDP/DSI core clocks
  98. * and request RSC with IDLE state and change the resource state to IDLE.
  99. * @SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  100. * This event is triggered from the input event thread when touch event is
  101. * received from the input device. On receiving this event,
  102. * - If the device is in SDE_ENC_RC_STATE_IDLE state, it turns ON the
  103. clocks and enable RSC.
  104. * - If the device is in SDE_ENC_RC_STATE_ON state, it resets the delayed
  105. * off work since a new commit is imminent.
  106. */
  107. enum sde_enc_rc_events {
  108. SDE_ENC_RC_EVENT_KICKOFF = 1,
  109. SDE_ENC_RC_EVENT_PRE_STOP,
  110. SDE_ENC_RC_EVENT_STOP,
  111. SDE_ENC_RC_EVENT_PRE_MODESET,
  112. SDE_ENC_RC_EVENT_POST_MODESET,
  113. SDE_ENC_RC_EVENT_ENTER_IDLE,
  114. SDE_ENC_RC_EVENT_EARLY_WAKEUP,
  115. };
  116. void sde_encoder_uidle_enable(struct drm_encoder *drm_enc, bool enable)
  117. {
  118. struct sde_encoder_virt *sde_enc;
  119. int i;
  120. sde_enc = to_sde_encoder_virt(drm_enc);
  121. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  122. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  123. if (phys && phys->hw_ctl && phys->hw_ctl->ops.uidle_enable) {
  124. SDE_EVT32(DRMID(drm_enc), enable);
  125. phys->hw_ctl->ops.uidle_enable(phys->hw_ctl, enable);
  126. }
  127. }
  128. }
  129. static void _sde_encoder_pm_qos_add_request(struct drm_encoder *drm_enc)
  130. {
  131. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  132. struct msm_drm_private *priv;
  133. struct sde_kms *sde_kms;
  134. struct device *cpu_dev;
  135. struct cpumask *cpu_mask = NULL;
  136. int cpu = 0;
  137. u32 cpu_dma_latency;
  138. priv = drm_enc->dev->dev_private;
  139. sde_kms = to_sde_kms(priv->kms);
  140. if (!sde_kms->catalog || !sde_kms->catalog->perf.cpu_mask)
  141. return;
  142. cpu_dma_latency = sde_kms->catalog->perf.cpu_dma_latency;
  143. cpumask_clear(&sde_enc->valid_cpu_mask);
  144. if (sde_enc->mode_info.frame_rate > DEFAULT_FPS)
  145. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask_perf);
  146. if (!cpu_mask &&
  147. sde_encoder_check_curr_mode(drm_enc,
  148. MSM_DISPLAY_CMD_MODE))
  149. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask);
  150. if (!cpu_mask)
  151. return;
  152. for_each_cpu(cpu, cpu_mask) {
  153. cpu_dev = get_cpu_device(cpu);
  154. if (!cpu_dev) {
  155. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  156. cpu);
  157. return;
  158. }
  159. cpumask_set_cpu(cpu, &sde_enc->valid_cpu_mask);
  160. dev_pm_qos_add_request(cpu_dev,
  161. &sde_enc->pm_qos_cpu_req[cpu],
  162. DEV_PM_QOS_RESUME_LATENCY, cpu_dma_latency);
  163. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu_dma_latency, cpu);
  164. }
  165. }
  166. static void _sde_encoder_pm_qos_remove_request(struct drm_encoder *drm_enc)
  167. {
  168. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  169. struct device *cpu_dev;
  170. int cpu = 0;
  171. for_each_cpu(cpu, &sde_enc->valid_cpu_mask) {
  172. cpu_dev = get_cpu_device(cpu);
  173. if (!cpu_dev) {
  174. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  175. cpu);
  176. continue;
  177. }
  178. dev_pm_qos_remove_request(&sde_enc->pm_qos_cpu_req[cpu]);
  179. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu);
  180. }
  181. cpumask_clear(&sde_enc->valid_cpu_mask);
  182. }
  183. static bool _sde_encoder_is_autorefresh_enabled(
  184. struct sde_encoder_virt *sde_enc)
  185. {
  186. struct drm_connector *drm_conn;
  187. if (!sde_enc->cur_master ||
  188. !(sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_CMD_MODE))
  189. return false;
  190. drm_conn = sde_enc->cur_master->connector;
  191. if (!drm_conn || !drm_conn->state)
  192. return false;
  193. return sde_connector_get_property(drm_conn->state,
  194. CONNECTOR_PROP_AUTOREFRESH) ? true : false;
  195. }
  196. static void sde_configure_qdss(struct sde_encoder_virt *sde_enc,
  197. struct sde_hw_qdss *hw_qdss,
  198. struct sde_encoder_phys *phys, bool enable)
  199. {
  200. if (sde_enc->qdss_status == enable)
  201. return;
  202. sde_enc->qdss_status = enable;
  203. phys->hw_mdptop->ops.set_mdp_hw_events(phys->hw_mdptop,
  204. sde_enc->qdss_status);
  205. hw_qdss->ops.enable_qdss_events(hw_qdss, sde_enc->qdss_status);
  206. }
  207. static int _sde_encoder_wait_timeout(int32_t drm_id, int32_t hw_id,
  208. s64 timeout_ms, struct sde_encoder_wait_info *info)
  209. {
  210. int rc = 0;
  211. s64 wait_time_jiffies = msecs_to_jiffies(timeout_ms);
  212. ktime_t cur_ktime;
  213. ktime_t exp_ktime = ktime_add_ms(ktime_get(), timeout_ms);
  214. do {
  215. rc = wait_event_timeout(*(info->wq),
  216. atomic_read(info->atomic_cnt) == info->count_check,
  217. wait_time_jiffies);
  218. cur_ktime = ktime_get();
  219. SDE_EVT32(drm_id, hw_id, rc, ktime_to_ms(cur_ktime),
  220. timeout_ms, atomic_read(info->atomic_cnt),
  221. info->count_check);
  222. /* If we timed out, counter is valid and time is less, wait again */
  223. } while ((atomic_read(info->atomic_cnt) != info->count_check) &&
  224. (rc == 0) &&
  225. (ktime_compare_safe(exp_ktime, cur_ktime) > 0));
  226. return rc;
  227. }
  228. bool sde_encoder_is_primary_display(struct drm_encoder *drm_enc)
  229. {
  230. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  231. return sde_enc &&
  232. (sde_enc->disp_info.display_type ==
  233. SDE_CONNECTOR_PRIMARY);
  234. }
  235. bool sde_encoder_is_dsi_display(struct drm_encoder *drm_enc)
  236. {
  237. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  238. return sde_enc &&
  239. (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI);
  240. }
  241. int sde_encoder_in_cont_splash(struct drm_encoder *drm_enc)
  242. {
  243. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  244. return sde_enc && sde_enc->cur_master &&
  245. sde_enc->cur_master->cont_splash_enabled;
  246. }
  247. void sde_encoder_helper_report_irq_timeout(struct sde_encoder_phys *phys_enc,
  248. enum sde_intr_idx intr_idx)
  249. {
  250. SDE_EVT32(DRMID(phys_enc->parent),
  251. phys_enc->intf_idx - INTF_0,
  252. phys_enc->hw_pp->idx - PINGPONG_0,
  253. intr_idx);
  254. SDE_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
  255. if (phys_enc->parent_ops.handle_frame_done)
  256. phys_enc->parent_ops.handle_frame_done(
  257. phys_enc->parent, phys_enc,
  258. SDE_ENCODER_FRAME_EVENT_ERROR);
  259. }
  260. int sde_encoder_helper_wait_for_irq(struct sde_encoder_phys *phys_enc,
  261. enum sde_intr_idx intr_idx,
  262. struct sde_encoder_wait_info *wait_info)
  263. {
  264. struct sde_encoder_irq *irq;
  265. u32 irq_status;
  266. int ret, i;
  267. if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
  268. SDE_ERROR("invalid params\n");
  269. return -EINVAL;
  270. }
  271. irq = &phys_enc->irq[intr_idx];
  272. /* note: do master / slave checking outside */
  273. /* return EWOULDBLOCK since we know the wait isn't necessary */
  274. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  275. SDE_ERROR_PHYS(phys_enc, "encoder is disabled\n");
  276. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  277. irq->irq_idx, intr_idx, SDE_EVTLOG_ERROR);
  278. return -EWOULDBLOCK;
  279. }
  280. if (irq->irq_idx < 0) {
  281. SDE_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
  282. irq->name, irq->hw_idx);
  283. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  284. irq->irq_idx);
  285. return 0;
  286. }
  287. SDE_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
  288. atomic_read(wait_info->atomic_cnt));
  289. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  290. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  291. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_ENTRY);
  292. /*
  293. * Some module X may disable interrupt for longer duration
  294. * and it may trigger all interrupts including timer interrupt
  295. * when module X again enable the interrupt.
  296. * That may cause interrupt wait timeout API in this API.
  297. * It is handled by split the wait timer in two halves.
  298. */
  299. for (i = 0; i < EVT_TIME_OUT_SPLIT; i++) {
  300. ret = _sde_encoder_wait_timeout(DRMID(phys_enc->parent),
  301. irq->hw_idx,
  302. (wait_info->timeout_ms/EVT_TIME_OUT_SPLIT),
  303. wait_info);
  304. if (ret)
  305. break;
  306. }
  307. if (ret <= 0) {
  308. irq_status = sde_core_irq_read(phys_enc->sde_kms,
  309. irq->irq_idx, true);
  310. if (irq_status) {
  311. unsigned long flags;
  312. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  313. irq->hw_idx, irq->irq_idx,
  314. phys_enc->hw_pp->idx - PINGPONG_0,
  315. atomic_read(wait_info->atomic_cnt));
  316. SDE_DEBUG_PHYS(phys_enc,
  317. "done but irq %d not triggered\n",
  318. irq->irq_idx);
  319. local_irq_save(flags);
  320. irq->cb.func(phys_enc, irq->irq_idx);
  321. local_irq_restore(flags);
  322. ret = 0;
  323. } else {
  324. ret = -ETIMEDOUT;
  325. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  326. irq->hw_idx, irq->irq_idx,
  327. phys_enc->hw_pp->idx - PINGPONG_0,
  328. atomic_read(wait_info->atomic_cnt), irq_status,
  329. SDE_EVTLOG_ERROR);
  330. }
  331. } else {
  332. ret = 0;
  333. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  334. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  335. atomic_read(wait_info->atomic_cnt));
  336. }
  337. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  338. irq->irq_idx, ret, phys_enc->hw_pp->idx - PINGPONG_0,
  339. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_EXIT);
  340. return ret;
  341. }
  342. int sde_encoder_helper_register_irq(struct sde_encoder_phys *phys_enc,
  343. enum sde_intr_idx intr_idx)
  344. {
  345. struct sde_encoder_irq *irq;
  346. int ret = 0;
  347. if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
  348. SDE_ERROR("invalid params\n");
  349. return -EINVAL;
  350. }
  351. irq = &phys_enc->irq[intr_idx];
  352. if (irq->irq_idx >= 0) {
  353. SDE_DEBUG_PHYS(phys_enc,
  354. "skipping already registered irq %s type %d\n",
  355. irq->name, irq->intr_type);
  356. return 0;
  357. }
  358. irq->irq_idx = sde_core_irq_idx_lookup(phys_enc->sde_kms,
  359. irq->intr_type, irq->hw_idx);
  360. if (irq->irq_idx < 0) {
  361. SDE_ERROR_PHYS(phys_enc,
  362. "failed to lookup IRQ index for %s type:%d\n",
  363. irq->name, irq->intr_type);
  364. return -EINVAL;
  365. }
  366. ret = sde_core_irq_register_callback(phys_enc->sde_kms, irq->irq_idx,
  367. &irq->cb);
  368. if (ret) {
  369. SDE_ERROR_PHYS(phys_enc,
  370. "failed to register IRQ callback for %s\n",
  371. irq->name);
  372. irq->irq_idx = -EINVAL;
  373. return ret;
  374. }
  375. ret = sde_core_irq_enable(phys_enc->sde_kms, &irq->irq_idx, 1);
  376. if (ret) {
  377. SDE_ERROR_PHYS(phys_enc,
  378. "enable IRQ for intr:%s failed, irq_idx %d\n",
  379. irq->name, irq->irq_idx);
  380. sde_core_irq_unregister_callback(phys_enc->sde_kms,
  381. irq->irq_idx, &irq->cb);
  382. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  383. irq->irq_idx, SDE_EVTLOG_ERROR);
  384. irq->irq_idx = -EINVAL;
  385. return ret;
  386. }
  387. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  388. SDE_DEBUG_PHYS(phys_enc, "registered irq %s idx: %d\n",
  389. irq->name, irq->irq_idx);
  390. return ret;
  391. }
  392. int sde_encoder_helper_unregister_irq(struct sde_encoder_phys *phys_enc,
  393. enum sde_intr_idx intr_idx)
  394. {
  395. struct sde_encoder_irq *irq;
  396. int ret;
  397. if (!phys_enc) {
  398. SDE_ERROR("invalid encoder\n");
  399. return -EINVAL;
  400. }
  401. irq = &phys_enc->irq[intr_idx];
  402. /* silently skip irqs that weren't registered */
  403. if (irq->irq_idx < 0) {
  404. SDE_ERROR(
  405. "extra unregister irq, enc%d intr_idx:0x%x hw_idx:0x%x irq_idx:0x%x\n",
  406. DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  407. irq->irq_idx);
  408. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  409. irq->irq_idx, SDE_EVTLOG_ERROR);
  410. return 0;
  411. }
  412. ret = sde_core_irq_disable(phys_enc->sde_kms, &irq->irq_idx, 1);
  413. if (ret)
  414. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  415. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  416. ret = sde_core_irq_unregister_callback(phys_enc->sde_kms, irq->irq_idx,
  417. &irq->cb);
  418. if (ret)
  419. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  420. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  421. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  422. SDE_DEBUG_PHYS(phys_enc, "unregistered %d\n", irq->irq_idx);
  423. irq->irq_idx = -EINVAL;
  424. return 0;
  425. }
  426. void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
  427. struct sde_encoder_hw_resources *hw_res,
  428. struct drm_connector_state *conn_state)
  429. {
  430. struct sde_encoder_virt *sde_enc = NULL;
  431. int ret, i = 0;
  432. if (!hw_res || !drm_enc || !conn_state || !hw_res->comp_info) {
  433. SDE_ERROR("rc %d, drm_enc %d, res %d, state %d, comp-info %d\n",
  434. -EINVAL, !drm_enc, !hw_res, !conn_state,
  435. hw_res ? !hw_res->comp_info : 0);
  436. return;
  437. }
  438. sde_enc = to_sde_encoder_virt(drm_enc);
  439. SDE_DEBUG_ENC(sde_enc, "\n");
  440. hw_res->display_num_of_h_tiles = sde_enc->display_num_of_h_tiles;
  441. hw_res->display_type = sde_enc->disp_info.display_type;
  442. /* Query resources used by phys encs, expected to be without overlap */
  443. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  444. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  445. if (phys && phys->ops.get_hw_resources)
  446. phys->ops.get_hw_resources(phys, hw_res, conn_state);
  447. }
  448. /*
  449. * NOTE: Do not use sde_encoder_get_mode_info here as this function is
  450. * called from atomic_check phase. Use the below API to get mode
  451. * information of the temporary conn_state passed
  452. */
  453. ret = sde_connector_state_get_topology(conn_state, &hw_res->topology);
  454. if (ret)
  455. SDE_ERROR("failed to get topology ret %d\n", ret);
  456. ret = sde_connector_state_get_compression_info(conn_state,
  457. hw_res->comp_info);
  458. if (ret)
  459. SDE_ERROR("failed to get compression info ret %d\n", ret);
  460. }
  461. void sde_encoder_destroy(struct drm_encoder *drm_enc)
  462. {
  463. struct sde_encoder_virt *sde_enc = NULL;
  464. int i = 0;
  465. unsigned int num_encs;
  466. if (!drm_enc) {
  467. SDE_ERROR("invalid encoder\n");
  468. return;
  469. }
  470. sde_enc = to_sde_encoder_virt(drm_enc);
  471. SDE_DEBUG_ENC(sde_enc, "\n");
  472. num_encs = sde_enc->num_phys_encs;
  473. mutex_lock(&sde_enc->enc_lock);
  474. sde_rsc_client_destroy(sde_enc->rsc_client);
  475. for (i = 0; i < num_encs; i++) {
  476. struct sde_encoder_phys *phys;
  477. phys = sde_enc->phys_vid_encs[i];
  478. if (phys && phys->ops.destroy) {
  479. phys->ops.destroy(phys);
  480. --sde_enc->num_phys_encs;
  481. sde_enc->phys_vid_encs[i] = NULL;
  482. }
  483. phys = sde_enc->phys_cmd_encs[i];
  484. if (phys && phys->ops.destroy) {
  485. phys->ops.destroy(phys);
  486. --sde_enc->num_phys_encs;
  487. sde_enc->phys_cmd_encs[i] = NULL;
  488. }
  489. phys = sde_enc->phys_encs[i];
  490. if (phys && phys->ops.destroy) {
  491. phys->ops.destroy(phys);
  492. --sde_enc->num_phys_encs;
  493. sde_enc->phys_encs[i] = NULL;
  494. }
  495. }
  496. if (sde_enc->num_phys_encs)
  497. SDE_ERROR_ENC(sde_enc, "expected 0 num_phys_encs not %d\n",
  498. sde_enc->num_phys_encs);
  499. sde_enc->num_phys_encs = 0;
  500. mutex_unlock(&sde_enc->enc_lock);
  501. drm_encoder_cleanup(drm_enc);
  502. mutex_destroy(&sde_enc->enc_lock);
  503. kfree(sde_enc->input_handler);
  504. sde_enc->input_handler = NULL;
  505. kfree(sde_enc);
  506. }
  507. void sde_encoder_helper_update_intf_cfg(
  508. struct sde_encoder_phys *phys_enc)
  509. {
  510. struct sde_encoder_virt *sde_enc;
  511. struct sde_hw_intf_cfg_v1 *intf_cfg;
  512. enum sde_3d_blend_mode mode_3d;
  513. if (!phys_enc || !phys_enc->hw_pp) {
  514. SDE_ERROR("invalid args, encoder %d\n", !phys_enc);
  515. return;
  516. }
  517. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  518. intf_cfg = &sde_enc->cur_master->intf_cfg_v1;
  519. SDE_DEBUG_ENC(sde_enc,
  520. "intf_cfg updated for %d at idx %d\n",
  521. phys_enc->intf_idx,
  522. intf_cfg->intf_count);
  523. /* setup interface configuration */
  524. if (intf_cfg->intf_count >= MAX_INTF_PER_CTL_V1) {
  525. pr_err("invalid inf_count %d\n", intf_cfg->intf_count);
  526. return;
  527. }
  528. intf_cfg->intf[intf_cfg->intf_count++] = phys_enc->intf_idx;
  529. if (phys_enc == sde_enc->cur_master) {
  530. if (sde_enc->cur_master->intf_mode == INTF_MODE_CMD)
  531. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
  532. else
  533. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  534. }
  535. /* configure this interface as master for split display */
  536. if (phys_enc->split_role == ENC_ROLE_MASTER)
  537. intf_cfg->intf_master = phys_enc->hw_intf->idx;
  538. /* setup which pp blk will connect to this intf */
  539. if (phys_enc->hw_intf->ops.bind_pingpong_blk)
  540. phys_enc->hw_intf->ops.bind_pingpong_blk(
  541. phys_enc->hw_intf,
  542. true,
  543. phys_enc->hw_pp->idx);
  544. /*setup merge_3d configuration */
  545. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  546. if (mode_3d && phys_enc->hw_pp->merge_3d &&
  547. intf_cfg->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  548. intf_cfg->merge_3d[intf_cfg->merge_3d_count++] =
  549. phys_enc->hw_pp->merge_3d->idx;
  550. if (phys_enc->hw_pp->ops.setup_3d_mode)
  551. phys_enc->hw_pp->ops.setup_3d_mode(phys_enc->hw_pp,
  552. mode_3d);
  553. }
  554. void sde_encoder_helper_split_config(
  555. struct sde_encoder_phys *phys_enc,
  556. enum sde_intf interface)
  557. {
  558. struct sde_encoder_virt *sde_enc;
  559. struct split_pipe_cfg *cfg;
  560. struct sde_hw_mdp *hw_mdptop;
  561. enum sde_rm_topology_name topology;
  562. struct msm_display_info *disp_info;
  563. if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
  564. SDE_ERROR("invalid arg(s), encoder %d\n", !phys_enc);
  565. return;
  566. }
  567. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  568. hw_mdptop = phys_enc->hw_mdptop;
  569. disp_info = &sde_enc->disp_info;
  570. cfg = &phys_enc->hw_intf->cfg;
  571. memset(cfg, 0, sizeof(*cfg));
  572. if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
  573. return;
  574. if (disp_info->capabilities & MSM_DISPLAY_SPLIT_LINK)
  575. cfg->split_link_en = true;
  576. /**
  577. * disable split modes since encoder will be operating in as the only
  578. * encoder, either for the entire use case in the case of, for example,
  579. * single DSI, or for this frame in the case of left/right only partial
  580. * update.
  581. */
  582. if (phys_enc->split_role == ENC_ROLE_SOLO) {
  583. if (hw_mdptop->ops.setup_split_pipe)
  584. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  585. if (hw_mdptop->ops.setup_pp_split)
  586. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  587. return;
  588. }
  589. cfg->en = true;
  590. cfg->mode = phys_enc->intf_mode;
  591. cfg->intf = interface;
  592. if (cfg->en && phys_enc->ops.needs_single_flush &&
  593. phys_enc->ops.needs_single_flush(phys_enc))
  594. cfg->split_flush_en = true;
  595. topology = sde_connector_get_topology_name(phys_enc->connector);
  596. if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
  597. cfg->pp_split_slave = cfg->intf;
  598. else
  599. cfg->pp_split_slave = INTF_MAX;
  600. if (phys_enc->split_role == ENC_ROLE_MASTER) {
  601. SDE_DEBUG_ENC(sde_enc, "enable %d\n", cfg->en);
  602. if (hw_mdptop->ops.setup_split_pipe)
  603. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  604. } else if (sde_enc->hw_pp[0]) {
  605. /*
  606. * slave encoder
  607. * - determine split index from master index,
  608. * assume master is first pp
  609. */
  610. cfg->pp_split_index = sde_enc->hw_pp[0]->idx - PINGPONG_0;
  611. SDE_DEBUG_ENC(sde_enc, "master using pp%d\n",
  612. cfg->pp_split_index);
  613. if (hw_mdptop->ops.setup_pp_split)
  614. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  615. }
  616. }
  617. bool sde_encoder_in_clone_mode(struct drm_encoder *drm_enc)
  618. {
  619. struct sde_encoder_virt *sde_enc;
  620. int i = 0;
  621. if (!drm_enc)
  622. return false;
  623. sde_enc = to_sde_encoder_virt(drm_enc);
  624. if (!sde_enc)
  625. return false;
  626. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  627. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  628. if (phys && phys->in_clone_mode)
  629. return true;
  630. }
  631. return false;
  632. }
  633. static int _sde_encoder_atomic_check_phys_enc(struct sde_encoder_virt *sde_enc,
  634. struct drm_crtc_state *crtc_state,
  635. struct drm_connector_state *conn_state)
  636. {
  637. const struct drm_display_mode *mode;
  638. struct drm_display_mode *adj_mode;
  639. int i = 0;
  640. int ret = 0;
  641. mode = &crtc_state->mode;
  642. adj_mode = &crtc_state->adjusted_mode;
  643. /* perform atomic check on the first physical encoder (master) */
  644. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  645. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  646. if (phys && phys->ops.atomic_check)
  647. ret = phys->ops.atomic_check(phys, crtc_state,
  648. conn_state);
  649. else if (phys && phys->ops.mode_fixup)
  650. if (!phys->ops.mode_fixup(phys, mode, adj_mode))
  651. ret = -EINVAL;
  652. if (ret) {
  653. SDE_ERROR_ENC(sde_enc,
  654. "mode unsupported, phys idx %d\n", i);
  655. break;
  656. }
  657. }
  658. return ret;
  659. }
  660. static int _sde_encoder_atomic_check_pu_roi(struct sde_encoder_virt *sde_enc,
  661. struct drm_crtc_state *crtc_state,
  662. struct drm_connector_state *conn_state,
  663. struct sde_connector_state *sde_conn_state,
  664. struct sde_crtc_state *sde_crtc_state)
  665. {
  666. int ret = 0;
  667. if (crtc_state->mode_changed || crtc_state->active_changed) {
  668. struct sde_rect mode_roi, roi;
  669. mode_roi.x = 0;
  670. mode_roi.y = 0;
  671. mode_roi.w = crtc_state->adjusted_mode.hdisplay;
  672. mode_roi.h = crtc_state->adjusted_mode.vdisplay;
  673. if (sde_conn_state->rois.num_rects) {
  674. sde_kms_rect_merge_rectangles(
  675. &sde_conn_state->rois, &roi);
  676. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  677. SDE_ERROR_ENC(sde_enc,
  678. "roi (%d,%d,%d,%d) on connector invalid during modeset\n",
  679. roi.x, roi.y, roi.w, roi.h);
  680. ret = -EINVAL;
  681. }
  682. }
  683. if (sde_crtc_state->user_roi_list.num_rects) {
  684. sde_kms_rect_merge_rectangles(
  685. &sde_crtc_state->user_roi_list, &roi);
  686. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  687. SDE_ERROR_ENC(sde_enc,
  688. "roi (%d,%d,%d,%d) on crtc invalid during modeset\n",
  689. roi.x, roi.y, roi.w, roi.h);
  690. ret = -EINVAL;
  691. }
  692. }
  693. }
  694. return ret;
  695. }
  696. static int _sde_encoder_atomic_check_reserve(struct drm_encoder *drm_enc,
  697. struct drm_crtc_state *crtc_state,
  698. struct drm_connector_state *conn_state,
  699. struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms,
  700. struct sde_connector *sde_conn,
  701. struct sde_connector_state *sde_conn_state)
  702. {
  703. int ret = 0;
  704. struct drm_display_mode *adj_mode = &crtc_state->adjusted_mode;
  705. if (sde_conn && drm_atomic_crtc_needs_modeset(crtc_state)) {
  706. struct msm_display_topology *topology = NULL;
  707. ret = sde_connector_get_mode_info(&sde_conn->base,
  708. adj_mode, &sde_conn_state->mode_info);
  709. if (ret) {
  710. SDE_ERROR_ENC(sde_enc,
  711. "failed to get mode info, rc = %d\n", ret);
  712. return ret;
  713. }
  714. if (sde_conn_state->mode_info.comp_info.comp_type &&
  715. sde_conn_state->mode_info.comp_info.comp_ratio >=
  716. MSM_DISPLAY_COMPRESSION_RATIO_MAX) {
  717. SDE_ERROR_ENC(sde_enc,
  718. "invalid compression ratio: %d\n",
  719. sde_conn_state->mode_info.comp_info.comp_ratio);
  720. ret = -EINVAL;
  721. return ret;
  722. }
  723. /* Reserve dynamic resources, indicating atomic_check phase */
  724. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
  725. conn_state, true);
  726. if (ret) {
  727. SDE_ERROR_ENC(sde_enc,
  728. "RM failed to reserve resources, rc = %d\n",
  729. ret);
  730. return ret;
  731. }
  732. /**
  733. * Update connector state with the topology selected for the
  734. * resource set validated. Reset the topology if we are
  735. * de-activating crtc.
  736. */
  737. if (crtc_state->active)
  738. topology = &sde_conn_state->mode_info.topology;
  739. ret = sde_rm_update_topology(&sde_kms->rm,
  740. conn_state, topology);
  741. if (ret) {
  742. SDE_ERROR_ENC(sde_enc,
  743. "RM failed to update topology, rc: %d\n", ret);
  744. return ret;
  745. }
  746. ret = sde_connector_set_blob_data(conn_state->connector,
  747. conn_state,
  748. CONNECTOR_PROP_SDE_INFO);
  749. if (ret) {
  750. SDE_ERROR_ENC(sde_enc,
  751. "connector failed to update info, rc: %d\n",
  752. ret);
  753. return ret;
  754. }
  755. }
  756. return ret;
  757. }
  758. static int sde_encoder_virt_atomic_check(
  759. struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state,
  760. struct drm_connector_state *conn_state)
  761. {
  762. struct sde_encoder_virt *sde_enc;
  763. struct sde_kms *sde_kms;
  764. const struct drm_display_mode *mode;
  765. struct drm_display_mode *adj_mode;
  766. struct sde_connector *sde_conn = NULL;
  767. struct sde_connector_state *sde_conn_state = NULL;
  768. struct sde_crtc_state *sde_crtc_state = NULL;
  769. enum sde_rm_topology_name old_top;
  770. int ret = 0;
  771. if (!drm_enc || !crtc_state || !conn_state) {
  772. SDE_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
  773. !drm_enc, !crtc_state, !conn_state);
  774. return -EINVAL;
  775. }
  776. sde_enc = to_sde_encoder_virt(drm_enc);
  777. SDE_DEBUG_ENC(sde_enc, "\n");
  778. sde_kms = sde_encoder_get_kms(drm_enc);
  779. if (!sde_kms)
  780. return -EINVAL;
  781. mode = &crtc_state->mode;
  782. adj_mode = &crtc_state->adjusted_mode;
  783. sde_conn = to_sde_connector(conn_state->connector);
  784. sde_conn_state = to_sde_connector_state(conn_state);
  785. sde_crtc_state = to_sde_crtc_state(crtc_state);
  786. SDE_EVT32(DRMID(drm_enc), crtc_state->mode_changed,
  787. crtc_state->active_changed, crtc_state->connectors_changed);
  788. ret = _sde_encoder_atomic_check_phys_enc(sde_enc, crtc_state,
  789. conn_state);
  790. if (ret)
  791. return ret;
  792. ret = _sde_encoder_atomic_check_pu_roi(sde_enc, crtc_state,
  793. conn_state, sde_conn_state, sde_crtc_state);
  794. if (ret)
  795. return ret;
  796. /**
  797. * record topology in previous atomic state to be able to handle
  798. * topology transitions correctly.
  799. */
  800. old_top = sde_connector_get_property(conn_state,
  801. CONNECTOR_PROP_TOPOLOGY_NAME);
  802. ret = sde_connector_set_old_topology_name(conn_state, old_top);
  803. if (ret)
  804. return ret;
  805. ret = _sde_encoder_atomic_check_reserve(drm_enc, crtc_state,
  806. conn_state, sde_enc, sde_kms, sde_conn, sde_conn_state);
  807. if (ret)
  808. return ret;
  809. ret = sde_connector_roi_v1_check_roi(conn_state);
  810. if (ret) {
  811. SDE_ERROR_ENC(sde_enc, "connector roi check failed, rc: %d",
  812. ret);
  813. return ret;
  814. }
  815. drm_mode_set_crtcinfo(adj_mode, 0);
  816. SDE_EVT32(DRMID(drm_enc), adj_mode->flags, adj_mode->private_flags);
  817. return ret;
  818. }
  819. static void _sde_encoder_get_connector_roi(
  820. struct sde_encoder_virt *sde_enc,
  821. struct sde_rect *merged_conn_roi)
  822. {
  823. struct drm_connector *drm_conn;
  824. struct sde_connector_state *c_state;
  825. if (!sde_enc || !merged_conn_roi)
  826. return;
  827. drm_conn = sde_enc->phys_encs[0]->connector;
  828. if (!drm_conn || !drm_conn->state)
  829. return;
  830. c_state = to_sde_connector_state(drm_conn->state);
  831. sde_kms_rect_merge_rectangles(&c_state->rois, merged_conn_roi);
  832. }
  833. static int _sde_encoder_update_roi(struct drm_encoder *drm_enc)
  834. {
  835. struct sde_encoder_virt *sde_enc;
  836. struct drm_connector *drm_conn;
  837. struct drm_display_mode *adj_mode;
  838. struct sde_rect roi;
  839. if (!drm_enc) {
  840. SDE_ERROR("invalid encoder parameter\n");
  841. return -EINVAL;
  842. }
  843. sde_enc = to_sde_encoder_virt(drm_enc);
  844. if (!sde_enc->crtc || !sde_enc->crtc->state) {
  845. SDE_ERROR("invalid crtc parameter\n");
  846. return -EINVAL;
  847. }
  848. if (!sde_enc->cur_master) {
  849. SDE_ERROR("invalid cur_master parameter\n");
  850. return -EINVAL;
  851. }
  852. adj_mode = &sde_enc->cur_master->cached_mode;
  853. drm_conn = sde_enc->cur_master->connector;
  854. _sde_encoder_get_connector_roi(sde_enc, &roi);
  855. if (sde_kms_rect_is_null(&roi)) {
  856. roi.w = adj_mode->hdisplay;
  857. roi.h = adj_mode->vdisplay;
  858. }
  859. memcpy(&sde_enc->prv_conn_roi, &sde_enc->cur_conn_roi,
  860. sizeof(sde_enc->prv_conn_roi));
  861. memcpy(&sde_enc->cur_conn_roi, &roi, sizeof(sde_enc->cur_conn_roi));
  862. return 0;
  863. }
  864. void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc,
  865. u32 vsync_source, bool is_dummy)
  866. {
  867. struct sde_vsync_source_cfg vsync_cfg = { 0 };
  868. struct sde_kms *sde_kms;
  869. struct sde_hw_mdp *hw_mdptop;
  870. struct sde_encoder_virt *sde_enc;
  871. int i;
  872. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  873. if (!sde_enc) {
  874. SDE_ERROR("invalid param sde_enc:%d\n", sde_enc != NULL);
  875. return;
  876. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  877. SDE_ERROR("invalid num phys enc %d/%d\n",
  878. sde_enc->num_phys_encs,
  879. (int) ARRAY_SIZE(sde_enc->hw_pp));
  880. return;
  881. }
  882. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  883. if (!sde_kms) {
  884. SDE_ERROR("invalid sde_kms\n");
  885. return;
  886. }
  887. hw_mdptop = sde_kms->hw_mdp;
  888. if (!hw_mdptop) {
  889. SDE_ERROR("invalid mdptop\n");
  890. return;
  891. }
  892. if (hw_mdptop->ops.setup_vsync_source) {
  893. for (i = 0; i < sde_enc->num_phys_encs; i++)
  894. vsync_cfg.ppnumber[i] = sde_enc->hw_pp[i]->idx;
  895. vsync_cfg.pp_count = sde_enc->num_phys_encs;
  896. vsync_cfg.frame_rate = sde_enc->mode_info.frame_rate;
  897. vsync_cfg.vsync_source = vsync_source;
  898. vsync_cfg.is_dummy = is_dummy;
  899. hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
  900. }
  901. }
  902. static void _sde_encoder_update_vsync_source(struct sde_encoder_virt *sde_enc,
  903. struct msm_display_info *disp_info, bool is_dummy)
  904. {
  905. struct sde_encoder_phys *phys;
  906. int i;
  907. u32 vsync_source;
  908. if (!sde_enc || !disp_info) {
  909. SDE_ERROR("invalid param sde_enc:%d or disp_info:%d\n",
  910. sde_enc != NULL, disp_info != NULL);
  911. return;
  912. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  913. SDE_ERROR("invalid num phys enc %d/%d\n",
  914. sde_enc->num_phys_encs,
  915. (int) ARRAY_SIZE(sde_enc->hw_pp));
  916. return;
  917. }
  918. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_CMD_MODE)) {
  919. if (is_dummy)
  920. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_0 -
  921. sde_enc->te_source;
  922. else if (disp_info->is_te_using_watchdog_timer)
  923. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_4 +
  924. sde_enc->te_source;
  925. else
  926. vsync_source = sde_enc->te_source;
  927. SDE_EVT32(DRMID(&sde_enc->base), vsync_source, is_dummy,
  928. disp_info->is_te_using_watchdog_timer);
  929. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  930. phys = sde_enc->phys_encs[i];
  931. if (phys && phys->ops.setup_vsync_source)
  932. phys->ops.setup_vsync_source(phys,
  933. vsync_source, is_dummy);
  934. }
  935. }
  936. }
  937. int sde_encoder_helper_switch_vsync(struct drm_encoder *drm_enc,
  938. bool watchdog_te)
  939. {
  940. struct sde_encoder_virt *sde_enc;
  941. struct msm_display_info disp_info;
  942. if (!drm_enc) {
  943. pr_err("invalid drm encoder\n");
  944. return -EINVAL;
  945. }
  946. sde_enc = to_sde_encoder_virt(drm_enc);
  947. sde_encoder_control_te(drm_enc, false);
  948. memcpy(&disp_info, &sde_enc->disp_info, sizeof(disp_info));
  949. disp_info.is_te_using_watchdog_timer = watchdog_te;
  950. _sde_encoder_update_vsync_source(sde_enc, &disp_info, false);
  951. sde_encoder_control_te(drm_enc, true);
  952. return 0;
  953. }
  954. static int _sde_encoder_rsc_client_update_vsync_wait(
  955. struct drm_encoder *drm_enc, struct sde_encoder_virt *sde_enc,
  956. int wait_vblank_crtc_id)
  957. {
  958. int wait_refcount = 0, ret = 0;
  959. int pipe = -1;
  960. int wait_count = 0;
  961. struct drm_crtc *primary_crtc;
  962. struct drm_crtc *crtc;
  963. crtc = sde_enc->crtc;
  964. if (wait_vblank_crtc_id)
  965. wait_refcount =
  966. sde_rsc_client_get_vsync_refcount(sde_enc->rsc_client);
  967. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  968. SDE_EVTLOG_FUNC_ENTRY);
  969. if (crtc->base.id != wait_vblank_crtc_id) {
  970. primary_crtc = drm_crtc_find(drm_enc->dev,
  971. NULL, wait_vblank_crtc_id);
  972. if (!primary_crtc) {
  973. SDE_ERROR_ENC(sde_enc,
  974. "failed to find primary crtc id %d\n",
  975. wait_vblank_crtc_id);
  976. return -EINVAL;
  977. }
  978. pipe = drm_crtc_index(primary_crtc);
  979. }
  980. /**
  981. * note: VBLANK is expected to be enabled at this point in
  982. * resource control state machine if on primary CRTC
  983. */
  984. for (wait_count = 0; wait_count < MAX_RSC_WAIT; wait_count++) {
  985. if (sde_rsc_client_is_state_update_complete(
  986. sde_enc->rsc_client))
  987. break;
  988. if (crtc->base.id == wait_vblank_crtc_id)
  989. ret = sde_encoder_wait_for_event(drm_enc,
  990. MSM_ENC_VBLANK);
  991. else
  992. drm_wait_one_vblank(drm_enc->dev, pipe);
  993. if (ret) {
  994. SDE_ERROR_ENC(sde_enc,
  995. "wait for vblank failed ret:%d\n", ret);
  996. /**
  997. * rsc hardware may hang without vsync. avoid rsc hang
  998. * by generating the vsync from watchdog timer.
  999. */
  1000. if (crtc->base.id == wait_vblank_crtc_id)
  1001. sde_encoder_helper_switch_vsync(drm_enc, true);
  1002. }
  1003. }
  1004. if (wait_count >= MAX_RSC_WAIT)
  1005. SDE_EVT32(DRMID(drm_enc), wait_vblank_crtc_id, wait_count,
  1006. SDE_EVTLOG_ERROR);
  1007. if (wait_refcount)
  1008. sde_rsc_client_reset_vsync_refcount(sde_enc->rsc_client);
  1009. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  1010. SDE_EVTLOG_FUNC_EXIT);
  1011. return ret;
  1012. }
  1013. static int _sde_encoder_update_rsc_client(
  1014. struct drm_encoder *drm_enc, bool enable)
  1015. {
  1016. struct sde_encoder_virt *sde_enc;
  1017. struct drm_crtc *crtc;
  1018. enum sde_rsc_state rsc_state = SDE_RSC_IDLE_STATE;
  1019. struct sde_rsc_cmd_config *rsc_config;
  1020. int ret;
  1021. struct msm_display_info *disp_info;
  1022. struct msm_mode_info *mode_info;
  1023. int wait_vblank_crtc_id = SDE_RSC_INVALID_CRTC_ID;
  1024. u32 qsync_mode = 0, v_front_porch;
  1025. struct drm_display_mode *mode;
  1026. bool is_vid_mode;
  1027. struct drm_encoder *enc;
  1028. if (!drm_enc || !drm_enc->dev) {
  1029. SDE_ERROR("invalid encoder arguments\n");
  1030. return -EINVAL;
  1031. }
  1032. sde_enc = to_sde_encoder_virt(drm_enc);
  1033. mode_info = &sde_enc->mode_info;
  1034. crtc = sde_enc->crtc;
  1035. if (!sde_enc->crtc) {
  1036. SDE_ERROR("invalid crtc parameter\n");
  1037. return -EINVAL;
  1038. }
  1039. disp_info = &sde_enc->disp_info;
  1040. rsc_config = &sde_enc->rsc_config;
  1041. if (!sde_enc->rsc_client) {
  1042. SDE_DEBUG_ENC(sde_enc, "rsc client not created\n");
  1043. return 0;
  1044. }
  1045. /**
  1046. * only primary command mode panel without Qsync can request CMD state.
  1047. * all other panels/displays can request for VID state including
  1048. * secondary command mode panel.
  1049. * Clone mode encoder can request CLK STATE only.
  1050. */
  1051. if (sde_enc->cur_master)
  1052. qsync_mode = sde_connector_get_qsync_mode(
  1053. sde_enc->cur_master->connector);
  1054. if (sde_encoder_in_clone_mode(drm_enc) ||
  1055. (disp_info->display_type != SDE_CONNECTOR_PRIMARY) ||
  1056. (disp_info->display_type && qsync_mode))
  1057. rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
  1058. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1059. rsc_state = enable ? SDE_RSC_CMD_STATE : SDE_RSC_IDLE_STATE;
  1060. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE))
  1061. rsc_state = enable ? SDE_RSC_VID_STATE : SDE_RSC_IDLE_STATE;
  1062. drm_for_each_encoder(enc, drm_enc->dev) {
  1063. if (enc->base.id != drm_enc->base.id &&
  1064. sde_encoder_in_cont_splash(enc))
  1065. rsc_state = SDE_RSC_CLK_STATE;
  1066. }
  1067. SDE_EVT32(rsc_state, qsync_mode);
  1068. is_vid_mode = sde_encoder_check_curr_mode(&sde_enc->base,
  1069. MSM_DISPLAY_VIDEO_MODE);
  1070. mode = &sde_enc->crtc->state->mode;
  1071. v_front_porch = mode->vsync_start - mode->vdisplay;
  1072. /* compare specific items and reconfigure the rsc */
  1073. if ((rsc_config->fps != mode_info->frame_rate) ||
  1074. (rsc_config->vtotal != mode_info->vtotal) ||
  1075. (rsc_config->prefill_lines != mode_info->prefill_lines) ||
  1076. (rsc_config->jitter_numer != mode_info->jitter_numer) ||
  1077. (rsc_config->jitter_denom != mode_info->jitter_denom)) {
  1078. rsc_config->fps = mode_info->frame_rate;
  1079. rsc_config->vtotal = mode_info->vtotal;
  1080. /*
  1081. * for video mode, prefill lines should not go beyond vertical
  1082. * front porch for RSCC configuration. This will ensure bw
  1083. * downvotes are not sent within the active region. Additional
  1084. * -1 is to give one line time for rscc mode min_threshold.
  1085. */
  1086. if (is_vid_mode && (mode_info->prefill_lines >= v_front_porch))
  1087. rsc_config->prefill_lines = v_front_porch - 1;
  1088. else
  1089. rsc_config->prefill_lines = mode_info->prefill_lines;
  1090. rsc_config->jitter_numer = mode_info->jitter_numer;
  1091. rsc_config->jitter_denom = mode_info->jitter_denom;
  1092. sde_enc->rsc_state_init = false;
  1093. }
  1094. if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_init
  1095. && (disp_info->display_type == SDE_CONNECTOR_PRIMARY)) {
  1096. /* update it only once */
  1097. sde_enc->rsc_state_init = true;
  1098. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1099. rsc_state, rsc_config, crtc->base.id,
  1100. &wait_vblank_crtc_id);
  1101. } else {
  1102. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1103. rsc_state, NULL, crtc->base.id,
  1104. &wait_vblank_crtc_id);
  1105. }
  1106. /**
  1107. * if RSC performed a state change that requires a VBLANK wait, it will
  1108. * set wait_vblank_crtc_id to the CRTC whose VBLANK we must wait on.
  1109. *
  1110. * if we are the primary display, we will need to enable and wait
  1111. * locally since we hold the commit thread
  1112. *
  1113. * if we are an external display, we must send a signal to the primary
  1114. * to enable its VBLANK and wait one, since the RSC hardware is driven
  1115. * by the primary panel's VBLANK signals
  1116. */
  1117. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id);
  1118. if (ret) {
  1119. SDE_ERROR_ENC(sde_enc,
  1120. "sde rsc client update failed ret:%d\n", ret);
  1121. return ret;
  1122. } else if (wait_vblank_crtc_id == SDE_RSC_INVALID_CRTC_ID) {
  1123. return ret;
  1124. }
  1125. ret = _sde_encoder_rsc_client_update_vsync_wait(drm_enc,
  1126. sde_enc, wait_vblank_crtc_id);
  1127. return ret;
  1128. }
  1129. void sde_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
  1130. {
  1131. struct sde_encoder_virt *sde_enc;
  1132. int i;
  1133. if (!drm_enc) {
  1134. SDE_ERROR("invalid encoder\n");
  1135. return;
  1136. }
  1137. sde_enc = to_sde_encoder_virt(drm_enc);
  1138. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1139. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1140. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1141. if (phys && phys->ops.irq_control)
  1142. phys->ops.irq_control(phys, enable);
  1143. }
  1144. sde_kms_cpu_vote_for_irq(sde_encoder_get_kms(drm_enc), enable);
  1145. }
  1146. /* keep track of the userspace vblank during modeset */
  1147. static void _sde_encoder_modeset_helper_locked(struct drm_encoder *drm_enc,
  1148. u32 sw_event)
  1149. {
  1150. struct sde_encoder_virt *sde_enc;
  1151. bool enable;
  1152. int i;
  1153. if (!drm_enc) {
  1154. SDE_ERROR("invalid encoder\n");
  1155. return;
  1156. }
  1157. sde_enc = to_sde_encoder_virt(drm_enc);
  1158. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, vblank_enabled:%d\n",
  1159. sw_event, sde_enc->vblank_enabled);
  1160. /* nothing to do if vblank not enabled by userspace */
  1161. if (!sde_enc->vblank_enabled)
  1162. return;
  1163. /* disable vblank on pre_modeset */
  1164. if (sw_event == SDE_ENC_RC_EVENT_PRE_MODESET)
  1165. enable = false;
  1166. /* enable vblank on post_modeset */
  1167. else if (sw_event == SDE_ENC_RC_EVENT_POST_MODESET)
  1168. enable = true;
  1169. else
  1170. return;
  1171. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1172. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1173. if (phys && phys->ops.control_vblank_irq)
  1174. phys->ops.control_vblank_irq(phys, enable);
  1175. }
  1176. }
  1177. struct sde_rsc_client *sde_encoder_get_rsc_client(struct drm_encoder *drm_enc)
  1178. {
  1179. struct sde_encoder_virt *sde_enc;
  1180. if (!drm_enc)
  1181. return NULL;
  1182. sde_enc = to_sde_encoder_virt(drm_enc);
  1183. return sde_enc->rsc_client;
  1184. }
  1185. static int _sde_encoder_resource_control_helper(struct drm_encoder *drm_enc,
  1186. bool enable)
  1187. {
  1188. struct sde_kms *sde_kms;
  1189. struct sde_encoder_virt *sde_enc;
  1190. int rc;
  1191. sde_enc = to_sde_encoder_virt(drm_enc);
  1192. sde_kms = sde_encoder_get_kms(drm_enc);
  1193. if (!sde_kms)
  1194. return -EINVAL;
  1195. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1196. SDE_EVT32(DRMID(drm_enc), enable);
  1197. if (!sde_enc->cur_master) {
  1198. SDE_ERROR("encoder master not set\n");
  1199. return -EINVAL;
  1200. }
  1201. if (enable) {
  1202. /* enable SDE core clks */
  1203. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  1204. if (rc < 0) {
  1205. SDE_ERROR("failed to enable power resource %d\n", rc);
  1206. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  1207. return rc;
  1208. }
  1209. sde_enc->elevated_ahb_vote = true;
  1210. /* enable DSI clks */
  1211. rc = sde_connector_clk_ctrl(sde_enc->cur_master->connector,
  1212. true);
  1213. if (rc) {
  1214. SDE_ERROR("failed to enable clk control %d\n", rc);
  1215. pm_runtime_put_sync(drm_enc->dev->dev);
  1216. return rc;
  1217. }
  1218. /* enable all the irq */
  1219. sde_encoder_irq_control(drm_enc, true);
  1220. _sde_encoder_pm_qos_add_request(drm_enc);
  1221. } else {
  1222. _sde_encoder_pm_qos_remove_request(drm_enc);
  1223. /* disable all the irq */
  1224. sde_encoder_irq_control(drm_enc, false);
  1225. /* disable DSI clks */
  1226. sde_connector_clk_ctrl(sde_enc->cur_master->connector, false);
  1227. /* disable SDE core clks */
  1228. pm_runtime_put_sync(drm_enc->dev->dev);
  1229. }
  1230. return 0;
  1231. }
  1232. static void sde_encoder_misr_configure(struct drm_encoder *drm_enc,
  1233. bool enable, u32 frame_count)
  1234. {
  1235. struct sde_encoder_virt *sde_enc;
  1236. int i;
  1237. if (!drm_enc) {
  1238. SDE_ERROR("invalid encoder\n");
  1239. return;
  1240. }
  1241. sde_enc = to_sde_encoder_virt(drm_enc);
  1242. if (!sde_enc->misr_reconfigure)
  1243. return;
  1244. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1245. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1246. if (!phys || !phys->ops.setup_misr)
  1247. continue;
  1248. phys->ops.setup_misr(phys, enable, frame_count);
  1249. }
  1250. sde_enc->misr_reconfigure = false;
  1251. }
  1252. static void sde_encoder_input_event_handler(struct input_handle *handle,
  1253. unsigned int type, unsigned int code, int value)
  1254. {
  1255. struct drm_encoder *drm_enc = NULL;
  1256. struct sde_encoder_virt *sde_enc = NULL;
  1257. struct msm_drm_thread *disp_thread = NULL;
  1258. struct msm_drm_private *priv = NULL;
  1259. if (!handle || !handle->handler || !handle->handler->private) {
  1260. SDE_ERROR("invalid encoder for the input event\n");
  1261. return;
  1262. }
  1263. drm_enc = (struct drm_encoder *)handle->handler->private;
  1264. if (!drm_enc->dev || !drm_enc->dev->dev_private) {
  1265. SDE_ERROR("invalid parameters\n");
  1266. return;
  1267. }
  1268. priv = drm_enc->dev->dev_private;
  1269. sde_enc = to_sde_encoder_virt(drm_enc);
  1270. if (!sde_enc->crtc || (sde_enc->crtc->index
  1271. >= ARRAY_SIZE(priv->disp_thread))) {
  1272. SDE_DEBUG_ENC(sde_enc,
  1273. "invalid cached CRTC: %d or crtc index: %d\n",
  1274. sde_enc->crtc == NULL,
  1275. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  1276. return;
  1277. }
  1278. SDE_EVT32_VERBOSE(DRMID(drm_enc));
  1279. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1280. kthread_queue_work(&disp_thread->worker,
  1281. &sde_enc->input_event_work);
  1282. }
  1283. void sde_encoder_control_idle_pc(struct drm_encoder *drm_enc, bool enable)
  1284. {
  1285. struct sde_encoder_virt *sde_enc;
  1286. if (!drm_enc) {
  1287. SDE_ERROR("invalid encoder\n");
  1288. return;
  1289. }
  1290. sde_enc = to_sde_encoder_virt(drm_enc);
  1291. /* return early if there is no state change */
  1292. if (sde_enc->idle_pc_enabled == enable)
  1293. return;
  1294. sde_enc->idle_pc_enabled = enable;
  1295. SDE_DEBUG("idle-pc state:%d\n", sde_enc->idle_pc_enabled);
  1296. SDE_EVT32(sde_enc->idle_pc_enabled);
  1297. }
  1298. static void _sde_encoder_rc_restart_delayed(struct sde_encoder_virt *sde_enc,
  1299. u32 sw_event)
  1300. {
  1301. struct drm_encoder *drm_enc = &sde_enc->base;
  1302. struct msm_drm_private *priv;
  1303. unsigned int lp, idle_pc_duration;
  1304. struct msm_drm_thread *disp_thread;
  1305. /* set idle timeout based on master connector's lp value */
  1306. if (sde_enc->cur_master)
  1307. lp = sde_connector_get_lp(
  1308. sde_enc->cur_master->connector);
  1309. else
  1310. lp = SDE_MODE_DPMS_ON;
  1311. if (lp == SDE_MODE_DPMS_LP2)
  1312. idle_pc_duration = IDLE_SHORT_TIMEOUT;
  1313. else
  1314. idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION;
  1315. priv = drm_enc->dev->dev_private;
  1316. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1317. kthread_mod_delayed_work(
  1318. &disp_thread->worker,
  1319. &sde_enc->delayed_off_work,
  1320. msecs_to_jiffies(idle_pc_duration));
  1321. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1322. idle_pc_duration, SDE_EVTLOG_FUNC_CASE2);
  1323. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
  1324. sw_event);
  1325. }
  1326. static void _sde_encoder_rc_cancel_delayed(struct sde_encoder_virt *sde_enc,
  1327. u32 sw_event)
  1328. {
  1329. if (kthread_cancel_delayed_work_sync(
  1330. &sde_enc->delayed_off_work))
  1331. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
  1332. sw_event);
  1333. }
  1334. static void _sde_encoder_rc_kickoff_delayed(struct sde_encoder_virt *sde_enc,
  1335. u32 sw_event)
  1336. {
  1337. if (_sde_encoder_is_autorefresh_enabled(sde_enc))
  1338. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1339. else
  1340. _sde_encoder_rc_restart_delayed(sde_enc, sw_event);
  1341. }
  1342. static int _sde_encoder_rc_kickoff(struct drm_encoder *drm_enc,
  1343. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1344. {
  1345. int ret = 0;
  1346. mutex_lock(&sde_enc->rc_lock);
  1347. /* return if the resource control is already in ON state */
  1348. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1349. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in ON state\n",
  1350. sw_event);
  1351. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1352. SDE_EVTLOG_FUNC_CASE1);
  1353. goto end;
  1354. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_OFF &&
  1355. sde_enc->rc_state != SDE_ENC_RC_STATE_IDLE) {
  1356. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1357. sw_event, sde_enc->rc_state);
  1358. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1359. SDE_EVTLOG_ERROR);
  1360. goto end;
  1361. }
  1362. if (is_vid_mode && sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1363. sde_encoder_irq_control(drm_enc, true);
  1364. } else {
  1365. /* enable all the clks and resources */
  1366. ret = _sde_encoder_resource_control_helper(drm_enc,
  1367. true);
  1368. if (ret) {
  1369. SDE_ERROR_ENC(sde_enc,
  1370. "sw_event:%d, rc in state %d\n",
  1371. sw_event, sde_enc->rc_state);
  1372. SDE_EVT32(DRMID(drm_enc), sw_event,
  1373. sde_enc->rc_state,
  1374. SDE_EVTLOG_ERROR);
  1375. goto end;
  1376. }
  1377. _sde_encoder_update_rsc_client(drm_enc, true);
  1378. }
  1379. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1380. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE1);
  1381. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1382. end:
  1383. _sde_encoder_rc_kickoff_delayed(sde_enc, sw_event);
  1384. mutex_unlock(&sde_enc->rc_lock);
  1385. return ret;
  1386. }
  1387. static int _sde_encoder_rc_pre_stop(struct drm_encoder *drm_enc,
  1388. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1389. {
  1390. /* cancel delayed off work, if any */
  1391. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1392. mutex_lock(&sde_enc->rc_lock);
  1393. if (is_vid_mode &&
  1394. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1395. sde_encoder_irq_control(drm_enc, true);
  1396. }
  1397. /* skip if is already OFF or IDLE, resources are off already */
  1398. else if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF ||
  1399. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1400. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in %d state\n",
  1401. sw_event, sde_enc->rc_state);
  1402. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1403. SDE_EVTLOG_FUNC_CASE3);
  1404. goto end;
  1405. }
  1406. /**
  1407. * IRQs are still enabled currently, which allows wait for
  1408. * VBLANK which RSC may require to correctly transition to OFF
  1409. */
  1410. _sde_encoder_update_rsc_client(drm_enc, false);
  1411. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1412. SDE_ENC_RC_STATE_PRE_OFF,
  1413. SDE_EVTLOG_FUNC_CASE3);
  1414. sde_enc->rc_state = SDE_ENC_RC_STATE_PRE_OFF;
  1415. end:
  1416. mutex_unlock(&sde_enc->rc_lock);
  1417. return 0;
  1418. }
  1419. static int _sde_encoder_rc_stop(struct drm_encoder *drm_enc,
  1420. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1421. {
  1422. int ret = 0;
  1423. mutex_lock(&sde_enc->rc_lock);
  1424. /* return if the resource control is already in OFF state */
  1425. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1426. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1427. sw_event);
  1428. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1429. SDE_EVTLOG_FUNC_CASE4);
  1430. goto end;
  1431. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON ||
  1432. sde_enc->rc_state == SDE_ENC_RC_STATE_MODESET) {
  1433. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1434. sw_event, sde_enc->rc_state);
  1435. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1436. SDE_EVTLOG_ERROR);
  1437. ret = -EINVAL;
  1438. goto end;
  1439. }
  1440. /**
  1441. * expect to arrive here only if in either idle state or pre-off
  1442. * and in IDLE state the resources are already disabled
  1443. */
  1444. if (sde_enc->rc_state == SDE_ENC_RC_STATE_PRE_OFF)
  1445. _sde_encoder_resource_control_helper(drm_enc, false);
  1446. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1447. SDE_ENC_RC_STATE_OFF, SDE_EVTLOG_FUNC_CASE4);
  1448. sde_enc->rc_state = SDE_ENC_RC_STATE_OFF;
  1449. end:
  1450. mutex_unlock(&sde_enc->rc_lock);
  1451. return ret;
  1452. }
  1453. static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc,
  1454. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1455. {
  1456. int ret = 0;
  1457. /* cancel delayed off work, if any */
  1458. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1459. mutex_lock(&sde_enc->rc_lock);
  1460. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1461. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1462. sw_event);
  1463. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1464. SDE_EVTLOG_FUNC_CASE5);
  1465. goto end;
  1466. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1467. /* enable all the clks and resources */
  1468. ret = _sde_encoder_resource_control_helper(drm_enc,
  1469. true);
  1470. if (ret) {
  1471. SDE_ERROR_ENC(sde_enc,
  1472. "sw_event:%d, rc in state %d\n",
  1473. sw_event, sde_enc->rc_state);
  1474. SDE_EVT32(DRMID(drm_enc), sw_event,
  1475. sde_enc->rc_state,
  1476. SDE_EVTLOG_ERROR);
  1477. goto end;
  1478. }
  1479. _sde_encoder_update_rsc_client(drm_enc, true);
  1480. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1481. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE5);
  1482. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1483. }
  1484. ret = sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  1485. if (ret && ret != -EWOULDBLOCK) {
  1486. SDE_ERROR_ENC(sde_enc,
  1487. "wait for commit done returned %d\n",
  1488. ret);
  1489. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1490. ret, SDE_EVTLOG_ERROR);
  1491. ret = -EINVAL;
  1492. goto end;
  1493. }
  1494. sde_encoder_irq_control(drm_enc, false);
  1495. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1496. SDE_ENC_RC_STATE_MODESET, SDE_EVTLOG_FUNC_CASE5);
  1497. sde_enc->rc_state = SDE_ENC_RC_STATE_MODESET;
  1498. _sde_encoder_pm_qos_remove_request(drm_enc);
  1499. end:
  1500. mutex_unlock(&sde_enc->rc_lock);
  1501. return ret;
  1502. }
  1503. static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc,
  1504. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1505. {
  1506. int ret = 0;
  1507. mutex_lock(&sde_enc->rc_lock);
  1508. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1509. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1510. sw_event);
  1511. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1512. SDE_EVTLOG_FUNC_CASE5);
  1513. goto end;
  1514. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_MODESET) {
  1515. SDE_ERROR_ENC(sde_enc,
  1516. "sw_event:%d, rc:%d !MODESET state\n",
  1517. sw_event, sde_enc->rc_state);
  1518. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1519. SDE_EVTLOG_ERROR);
  1520. ret = -EINVAL;
  1521. goto end;
  1522. }
  1523. sde_encoder_irq_control(drm_enc, true);
  1524. _sde_encoder_update_rsc_client(drm_enc, true);
  1525. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1526. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE6);
  1527. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1528. _sde_encoder_pm_qos_add_request(drm_enc);
  1529. end:
  1530. mutex_unlock(&sde_enc->rc_lock);
  1531. return ret;
  1532. }
  1533. static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc,
  1534. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1535. {
  1536. struct msm_drm_private *priv;
  1537. struct sde_kms *sde_kms;
  1538. struct drm_crtc *crtc = drm_enc->crtc;
  1539. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1540. priv = drm_enc->dev->dev_private;
  1541. sde_kms = to_sde_kms(priv->kms);
  1542. mutex_lock(&sde_enc->rc_lock);
  1543. if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1544. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc:%d !ON state\n",
  1545. sw_event, sde_enc->rc_state);
  1546. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1547. SDE_EVTLOG_ERROR);
  1548. goto end;
  1549. } else if (sde_crtc_frame_pending(sde_enc->crtc)) {
  1550. SDE_DEBUG_ENC(sde_enc, "skip idle entry");
  1551. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1552. sde_crtc_frame_pending(sde_enc->crtc),
  1553. SDE_EVTLOG_ERROR);
  1554. _sde_encoder_rc_kickoff_delayed(sde_enc, sw_event);
  1555. goto end;
  1556. }
  1557. if (is_vid_mode) {
  1558. sde_encoder_irq_control(drm_enc, false);
  1559. } else {
  1560. /* disable all the clks and resources */
  1561. _sde_encoder_update_rsc_client(drm_enc, false);
  1562. _sde_encoder_resource_control_helper(drm_enc, false);
  1563. if (!sde_kms->perf.bw_vote_mode)
  1564. memset(&sde_crtc->cur_perf, 0,
  1565. sizeof(struct sde_core_perf_params));
  1566. }
  1567. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1568. SDE_ENC_RC_STATE_IDLE, SDE_EVTLOG_FUNC_CASE7);
  1569. sde_enc->rc_state = SDE_ENC_RC_STATE_IDLE;
  1570. end:
  1571. mutex_unlock(&sde_enc->rc_lock);
  1572. return 0;
  1573. }
  1574. static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
  1575. u32 sw_event, struct sde_encoder_virt *sde_enc,
  1576. struct msm_drm_private *priv, bool is_vid_mode)
  1577. {
  1578. bool autorefresh_enabled = false;
  1579. struct msm_drm_thread *disp_thread;
  1580. int ret = 0;
  1581. if (!sde_enc->crtc ||
  1582. sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
  1583. SDE_DEBUG_ENC(sde_enc,
  1584. "invalid crtc:%d or crtc index:%d , sw_event:%u\n",
  1585. sde_enc->crtc == NULL,
  1586. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL,
  1587. sw_event);
  1588. return -EINVAL;
  1589. }
  1590. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1591. mutex_lock(&sde_enc->rc_lock);
  1592. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1593. if (sde_enc->cur_master &&
  1594. sde_enc->cur_master->ops.is_autorefresh_enabled)
  1595. autorefresh_enabled =
  1596. sde_enc->cur_master->ops.is_autorefresh_enabled(
  1597. sde_enc->cur_master);
  1598. if (autorefresh_enabled) {
  1599. SDE_DEBUG_ENC(sde_enc,
  1600. "not handling early wakeup since auto refresh is enabled\n");
  1601. goto end;
  1602. }
  1603. if (!sde_crtc_frame_pending(sde_enc->crtc))
  1604. kthread_mod_delayed_work(&disp_thread->worker,
  1605. &sde_enc->delayed_off_work,
  1606. msecs_to_jiffies(
  1607. IDLE_POWERCOLLAPSE_DURATION));
  1608. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1609. /* enable all the clks and resources */
  1610. ret = _sde_encoder_resource_control_helper(drm_enc,
  1611. true);
  1612. if (ret) {
  1613. SDE_ERROR_ENC(sde_enc,
  1614. "sw_event:%d, rc in state %d\n",
  1615. sw_event, sde_enc->rc_state);
  1616. SDE_EVT32(DRMID(drm_enc), sw_event,
  1617. sde_enc->rc_state,
  1618. SDE_EVTLOG_ERROR);
  1619. goto end;
  1620. }
  1621. _sde_encoder_update_rsc_client(drm_enc, true);
  1622. /*
  1623. * In some cases, commit comes with slight delay
  1624. * (> 80 ms)after early wake up, prevent clock switch
  1625. * off to avoid jank in next update. So, increase the
  1626. * command mode idle timeout sufficiently to prevent
  1627. * such case.
  1628. */
  1629. kthread_mod_delayed_work(&disp_thread->worker,
  1630. &sde_enc->delayed_off_work,
  1631. msecs_to_jiffies(
  1632. IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP));
  1633. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1634. }
  1635. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1636. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE8);
  1637. end:
  1638. mutex_unlock(&sde_enc->rc_lock);
  1639. return ret;
  1640. }
  1641. static int sde_encoder_resource_control(struct drm_encoder *drm_enc,
  1642. u32 sw_event)
  1643. {
  1644. struct sde_encoder_virt *sde_enc;
  1645. struct msm_drm_private *priv;
  1646. int ret = 0;
  1647. bool is_vid_mode = false;
  1648. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  1649. SDE_ERROR("invalid encoder parameters, sw_event:%u\n",
  1650. sw_event);
  1651. return -EINVAL;
  1652. }
  1653. sde_enc = to_sde_encoder_virt(drm_enc);
  1654. priv = drm_enc->dev->dev_private;
  1655. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  1656. is_vid_mode = true;
  1657. /*
  1658. * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
  1659. * events and return early for other events (ie wb display).
  1660. */
  1661. if (!sde_enc->idle_pc_enabled &&
  1662. (sw_event != SDE_ENC_RC_EVENT_KICKOFF &&
  1663. sw_event != SDE_ENC_RC_EVENT_PRE_MODESET &&
  1664. sw_event != SDE_ENC_RC_EVENT_POST_MODESET &&
  1665. sw_event != SDE_ENC_RC_EVENT_STOP &&
  1666. sw_event != SDE_ENC_RC_EVENT_PRE_STOP))
  1667. return 0;
  1668. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, idle_pc:%d\n",
  1669. sw_event, sde_enc->idle_pc_enabled);
  1670. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1671. sde_enc->rc_state, SDE_EVTLOG_FUNC_ENTRY);
  1672. switch (sw_event) {
  1673. case SDE_ENC_RC_EVENT_KICKOFF:
  1674. ret = _sde_encoder_rc_kickoff(drm_enc, sw_event, sde_enc,
  1675. is_vid_mode);
  1676. break;
  1677. case SDE_ENC_RC_EVENT_PRE_STOP:
  1678. ret = _sde_encoder_rc_pre_stop(drm_enc, sw_event, sde_enc,
  1679. is_vid_mode);
  1680. break;
  1681. case SDE_ENC_RC_EVENT_STOP:
  1682. ret = _sde_encoder_rc_stop(drm_enc, sw_event, sde_enc);
  1683. break;
  1684. case SDE_ENC_RC_EVENT_PRE_MODESET:
  1685. ret = _sde_encoder_rc_pre_modeset(drm_enc, sw_event, sde_enc);
  1686. break;
  1687. case SDE_ENC_RC_EVENT_POST_MODESET:
  1688. ret = _sde_encoder_rc_post_modeset(drm_enc, sw_event, sde_enc);
  1689. break;
  1690. case SDE_ENC_RC_EVENT_ENTER_IDLE:
  1691. ret = _sde_encoder_rc_idle(drm_enc, sw_event, sde_enc,
  1692. is_vid_mode);
  1693. break;
  1694. case SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  1695. ret = _sde_encoder_rc_early_wakeup(drm_enc, sw_event, sde_enc,
  1696. priv, is_vid_mode);
  1697. break;
  1698. default:
  1699. SDE_EVT32(DRMID(drm_enc), sw_event, SDE_EVTLOG_ERROR);
  1700. SDE_ERROR("unexpected sw_event: %d\n", sw_event);
  1701. break;
  1702. }
  1703. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1704. sde_enc->rc_state, SDE_EVTLOG_FUNC_EXIT);
  1705. return ret;
  1706. }
  1707. static void sde_encoder_virt_mode_switch(struct drm_encoder *drm_enc,
  1708. enum sde_intf_mode intf_mode, struct drm_display_mode *adj_mode)
  1709. {
  1710. int i = 0;
  1711. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1712. if (intf_mode == INTF_MODE_CMD)
  1713. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  1714. else if (intf_mode == INTF_MODE_VIDEO)
  1715. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  1716. _sde_encoder_update_rsc_client(drm_enc, true);
  1717. if (intf_mode == INTF_MODE_CMD) {
  1718. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1719. sde_enc->phys_encs[i] = sde_enc->phys_vid_encs[i];
  1720. SDE_DEBUG_ENC(sde_enc, "switch to video physical encoder\n");
  1721. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1722. msm_is_mode_seamless_poms(adj_mode),
  1723. SDE_EVTLOG_FUNC_CASE1);
  1724. } else if (intf_mode == INTF_MODE_VIDEO) {
  1725. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1726. sde_enc->phys_encs[i] = sde_enc->phys_cmd_encs[i];
  1727. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1728. msm_is_mode_seamless_poms(adj_mode),
  1729. SDE_EVTLOG_FUNC_CASE2);
  1730. SDE_DEBUG_ENC(sde_enc, "switch to command physical encoder\n");
  1731. }
  1732. }
  1733. static struct drm_connector *_sde_encoder_get_connector(
  1734. struct drm_device *dev, struct drm_encoder *drm_enc)
  1735. {
  1736. struct drm_connector_list_iter conn_iter;
  1737. struct drm_connector *conn = NULL, *conn_search;
  1738. drm_connector_list_iter_begin(dev, &conn_iter);
  1739. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1740. if (conn_search->encoder == drm_enc) {
  1741. conn = conn_search;
  1742. break;
  1743. }
  1744. }
  1745. drm_connector_list_iter_end(&conn_iter);
  1746. return conn;
  1747. }
  1748. static void _sde_encoder_virt_populate_hw_res(struct drm_encoder *drm_enc)
  1749. {
  1750. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1751. struct sde_kms *sde_kms = sde_encoder_get_kms(drm_enc);
  1752. struct sde_rm_hw_iter pp_iter, qdss_iter;
  1753. struct sde_rm_hw_iter dsc_iter, vdc_iter;
  1754. struct sde_rm_hw_request request_hw;
  1755. int i, j;
  1756. sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
  1757. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1758. sde_enc->hw_pp[i] = NULL;
  1759. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  1760. break;
  1761. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  1762. }
  1763. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1764. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1765. if (phys) {
  1766. sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id,
  1767. SDE_HW_BLK_QDSS);
  1768. for (j = 0; j < QDSS_MAX; j++) {
  1769. if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) {
  1770. phys->hw_qdss =
  1771. (struct sde_hw_qdss *)qdss_iter.hw;
  1772. break;
  1773. }
  1774. }
  1775. }
  1776. }
  1777. sde_rm_init_hw_iter(&dsc_iter, drm_enc->base.id, SDE_HW_BLK_DSC);
  1778. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1779. sde_enc->hw_dsc[i] = NULL;
  1780. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  1781. break;
  1782. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  1783. }
  1784. sde_rm_init_hw_iter(&vdc_iter, drm_enc->base.id, SDE_HW_BLK_VDC);
  1785. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1786. sde_enc->hw_vdc[i] = NULL;
  1787. if (!sde_rm_get_hw(&sde_kms->rm, &vdc_iter))
  1788. break;
  1789. sde_enc->hw_vdc[i] = (struct sde_hw_vdc *) vdc_iter.hw;
  1790. }
  1791. /* Get PP for DSC configuration */
  1792. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1793. struct sde_hw_pingpong *pp = NULL;
  1794. unsigned long features = 0;
  1795. if (!sde_enc->hw_dsc[i])
  1796. continue;
  1797. request_hw.id = sde_enc->hw_dsc[i]->base.id;
  1798. request_hw.type = SDE_HW_BLK_PINGPONG;
  1799. if (!sde_rm_request_hw_blk(&sde_kms->rm, &request_hw))
  1800. break;
  1801. pp = (struct sde_hw_pingpong *) request_hw.hw;
  1802. features = pp->ops.get_hw_caps(pp);
  1803. if (test_bit(SDE_PINGPONG_DSC, &features))
  1804. sde_enc->hw_dsc_pp[i] = pp;
  1805. else
  1806. sde_enc->hw_dsc_pp[i] = NULL;
  1807. }
  1808. }
  1809. static int sde_encoder_virt_modeset_rc(struct drm_encoder *drm_enc,
  1810. struct drm_display_mode *adj_mode, bool pre_modeset)
  1811. {
  1812. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1813. enum sde_intf_mode intf_mode;
  1814. int ret;
  1815. bool is_cmd_mode = false;
  1816. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1817. is_cmd_mode = true;
  1818. if (pre_modeset) {
  1819. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  1820. if (msm_is_mode_seamless_dms(adj_mode) ||
  1821. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1822. is_cmd_mode)) {
  1823. /* restore resource state before releasing them */
  1824. ret = sde_encoder_resource_control(drm_enc,
  1825. SDE_ENC_RC_EVENT_PRE_MODESET);
  1826. if (ret) {
  1827. SDE_ERROR_ENC(sde_enc,
  1828. "sde resource control failed: %d\n",
  1829. ret);
  1830. return ret;
  1831. }
  1832. /*
  1833. * Disable dce before switching the mode and after pre-
  1834. * modeset to guarantee previous kickoff has finished.
  1835. */
  1836. sde_encoder_dce_disable(sde_enc);
  1837. } else if (msm_is_mode_seamless_poms(adj_mode)) {
  1838. _sde_encoder_modeset_helper_locked(drm_enc,
  1839. SDE_ENC_RC_EVENT_PRE_MODESET);
  1840. sde_encoder_virt_mode_switch(drm_enc, intf_mode,
  1841. adj_mode);
  1842. }
  1843. } else {
  1844. if (msm_is_mode_seamless_dms(adj_mode) ||
  1845. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1846. is_cmd_mode))
  1847. sde_encoder_resource_control(&sde_enc->base,
  1848. SDE_ENC_RC_EVENT_POST_MODESET);
  1849. else if (msm_is_mode_seamless_poms(adj_mode))
  1850. _sde_encoder_modeset_helper_locked(drm_enc,
  1851. SDE_ENC_RC_EVENT_POST_MODESET);
  1852. }
  1853. return 0;
  1854. }
  1855. static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
  1856. struct drm_display_mode *mode,
  1857. struct drm_display_mode *adj_mode)
  1858. {
  1859. struct sde_encoder_virt *sde_enc;
  1860. struct sde_kms *sde_kms;
  1861. struct drm_connector *conn;
  1862. int i = 0, ret;
  1863. int num_lm, num_intf, num_pp_per_intf;
  1864. if (!drm_enc) {
  1865. SDE_ERROR("invalid encoder\n");
  1866. return;
  1867. }
  1868. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  1869. SDE_ERROR("power resource is not enabled\n");
  1870. return;
  1871. }
  1872. sde_kms = sde_encoder_get_kms(drm_enc);
  1873. if (!sde_kms)
  1874. return;
  1875. sde_enc = to_sde_encoder_virt(drm_enc);
  1876. SDE_DEBUG_ENC(sde_enc, "\n");
  1877. SDE_EVT32(DRMID(drm_enc));
  1878. /*
  1879. * cache the crtc in sde_enc on enable for duration of use case
  1880. * for correctly servicing asynchronous irq events and timers
  1881. */
  1882. if (!drm_enc->crtc) {
  1883. SDE_ERROR("invalid crtc\n");
  1884. return;
  1885. }
  1886. sde_enc->crtc = drm_enc->crtc;
  1887. sde_crtc_set_qos_dirty(drm_enc->crtc);
  1888. /* get and store the mode_info */
  1889. conn = _sde_encoder_get_connector(sde_kms->dev, drm_enc);
  1890. if (!conn) {
  1891. SDE_ERROR_ENC(sde_enc, "failed to find attached connector\n");
  1892. return;
  1893. } else if (!conn->state) {
  1894. SDE_ERROR_ENC(sde_enc, "invalid connector state\n");
  1895. return;
  1896. }
  1897. sde_connector_state_get_mode_info(conn->state, &sde_enc->mode_info);
  1898. sde_encoder_dce_set_bpp(sde_enc->mode_info, sde_enc->crtc);
  1899. /* release resources before seamless mode change */
  1900. ret = sde_encoder_virt_modeset_rc(drm_enc, adj_mode, true);
  1901. if (ret)
  1902. return;
  1903. /* reserve dynamic resources now, indicating non test-only */
  1904. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state,
  1905. conn->state, false);
  1906. if (ret) {
  1907. SDE_ERROR_ENC(sde_enc,
  1908. "failed to reserve hw resources, %d\n", ret);
  1909. return;
  1910. }
  1911. /* assign the reserved HW blocks to this encoder */
  1912. _sde_encoder_virt_populate_hw_res(drm_enc);
  1913. /* determine left HW PP block to map to INTF */
  1914. num_lm = sde_enc->mode_info.topology.num_lm;
  1915. num_intf = sde_enc->mode_info.topology.num_intf;
  1916. num_pp_per_intf = num_lm / num_intf;
  1917. if (!num_pp_per_intf)
  1918. num_pp_per_intf = 1;
  1919. /* perform mode_set on phys_encs */
  1920. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1921. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1922. if (phys) {
  1923. if (!sde_enc->hw_pp[i * num_pp_per_intf] &&
  1924. sde_enc->topology.num_intf) {
  1925. SDE_ERROR_ENC(sde_enc, "invalid hw_pp[%d]\n",
  1926. i * num_pp_per_intf);
  1927. return;
  1928. }
  1929. phys->hw_pp = sde_enc->hw_pp[i * num_pp_per_intf];
  1930. phys->connector = conn->state->connector;
  1931. if (phys->ops.mode_set)
  1932. phys->ops.mode_set(phys, mode, adj_mode);
  1933. }
  1934. }
  1935. /* update resources after seamless mode change */
  1936. sde_encoder_virt_modeset_rc(drm_enc, adj_mode, false);
  1937. }
  1938. void sde_encoder_control_te(struct drm_encoder *drm_enc, bool enable)
  1939. {
  1940. struct sde_encoder_virt *sde_enc;
  1941. struct sde_encoder_phys *phys;
  1942. int i;
  1943. if (!drm_enc) {
  1944. SDE_ERROR("invalid parameters\n");
  1945. return;
  1946. }
  1947. sde_enc = to_sde_encoder_virt(drm_enc);
  1948. if (!sde_enc) {
  1949. SDE_ERROR("invalid sde encoder\n");
  1950. return;
  1951. }
  1952. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1953. phys = sde_enc->phys_encs[i];
  1954. if (phys && phys->ops.control_te)
  1955. phys->ops.control_te(phys, enable);
  1956. }
  1957. }
  1958. static int _sde_encoder_input_connect(struct input_handler *handler,
  1959. struct input_dev *dev, const struct input_device_id *id)
  1960. {
  1961. struct input_handle *handle;
  1962. int rc = 0;
  1963. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  1964. if (!handle)
  1965. return -ENOMEM;
  1966. handle->dev = dev;
  1967. handle->handler = handler;
  1968. handle->name = handler->name;
  1969. rc = input_register_handle(handle);
  1970. if (rc) {
  1971. pr_err("failed to register input handle\n");
  1972. goto error;
  1973. }
  1974. rc = input_open_device(handle);
  1975. if (rc) {
  1976. pr_err("failed to open input device\n");
  1977. goto error_unregister;
  1978. }
  1979. return 0;
  1980. error_unregister:
  1981. input_unregister_handle(handle);
  1982. error:
  1983. kfree(handle);
  1984. return rc;
  1985. }
  1986. static void _sde_encoder_input_disconnect(struct input_handle *handle)
  1987. {
  1988. input_close_device(handle);
  1989. input_unregister_handle(handle);
  1990. kfree(handle);
  1991. }
  1992. /**
  1993. * Structure for specifying event parameters on which to receive callbacks.
  1994. * This structure will trigger a callback in case of a touch event (specified by
  1995. * EV_ABS) where there is a change in X and Y coordinates,
  1996. */
  1997. static const struct input_device_id sde_input_ids[] = {
  1998. {
  1999. .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
  2000. .evbit = { BIT_MASK(EV_ABS) },
  2001. .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
  2002. BIT_MASK(ABS_MT_POSITION_X) |
  2003. BIT_MASK(ABS_MT_POSITION_Y) },
  2004. },
  2005. { },
  2006. };
  2007. static void _sde_encoder_input_handler_register(
  2008. struct drm_encoder *drm_enc)
  2009. {
  2010. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2011. int rc;
  2012. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE) ||
  2013. !sde_enc->input_event_enabled)
  2014. return;
  2015. if (sde_enc->input_handler && !sde_enc->input_handler->private) {
  2016. sde_enc->input_handler->private = sde_enc;
  2017. /* register input handler if not already registered */
  2018. rc = input_register_handler(sde_enc->input_handler);
  2019. if (rc) {
  2020. SDE_ERROR("input_handler_register failed, rc= %d\n",
  2021. rc);
  2022. kfree(sde_enc->input_handler);
  2023. }
  2024. }
  2025. }
  2026. static void _sde_encoder_input_handler_unregister(
  2027. struct drm_encoder *drm_enc)
  2028. {
  2029. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2030. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE) ||
  2031. !sde_enc->input_event_enabled)
  2032. return;
  2033. if (sde_enc->input_handler && sde_enc->input_handler->private) {
  2034. input_unregister_handler(sde_enc->input_handler);
  2035. sde_enc->input_handler->private = NULL;
  2036. }
  2037. }
  2038. static int _sde_encoder_input_handler(
  2039. struct sde_encoder_virt *sde_enc)
  2040. {
  2041. struct input_handler *input_handler = NULL;
  2042. int rc = 0;
  2043. if (sde_enc->input_handler) {
  2044. SDE_ERROR_ENC(sde_enc,
  2045. "input_handle is active. unexpected\n");
  2046. return -EINVAL;
  2047. }
  2048. input_handler = kzalloc(sizeof(*sde_enc->input_handler), GFP_KERNEL);
  2049. if (!input_handler)
  2050. return -ENOMEM;
  2051. input_handler->event = sde_encoder_input_event_handler;
  2052. input_handler->connect = _sde_encoder_input_connect;
  2053. input_handler->disconnect = _sde_encoder_input_disconnect;
  2054. input_handler->name = "sde";
  2055. input_handler->id_table = sde_input_ids;
  2056. sde_enc->input_handler = input_handler;
  2057. return rc;
  2058. }
  2059. static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
  2060. {
  2061. struct sde_encoder_virt *sde_enc = NULL;
  2062. struct sde_kms *sde_kms;
  2063. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  2064. SDE_ERROR("invalid parameters\n");
  2065. return;
  2066. }
  2067. sde_kms = sde_encoder_get_kms(drm_enc);
  2068. if (!sde_kms)
  2069. return;
  2070. sde_enc = to_sde_encoder_virt(drm_enc);
  2071. if (!sde_enc || !sde_enc->cur_master) {
  2072. SDE_DEBUG("invalid sde encoder/master\n");
  2073. return;
  2074. }
  2075. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
  2076. sde_enc->cur_master->hw_mdptop &&
  2077. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select)
  2078. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select(
  2079. sde_enc->cur_master->hw_mdptop);
  2080. if (sde_enc->cur_master->hw_mdptop &&
  2081. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc)
  2082. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
  2083. sde_enc->cur_master->hw_mdptop,
  2084. sde_kms->catalog);
  2085. if (sde_enc->cur_master->hw_ctl &&
  2086. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1 &&
  2087. !sde_enc->cur_master->cont_splash_enabled)
  2088. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1(
  2089. sde_enc->cur_master->hw_ctl,
  2090. &sde_enc->cur_master->intf_cfg_v1);
  2091. _sde_encoder_update_vsync_source(sde_enc, &sde_enc->disp_info, false);
  2092. sde_encoder_control_te(drm_enc, true);
  2093. memset(&sde_enc->prv_conn_roi, 0, sizeof(sde_enc->prv_conn_roi));
  2094. memset(&sde_enc->cur_conn_roi, 0, sizeof(sde_enc->cur_conn_roi));
  2095. }
  2096. static void _sde_encoder_setup_dither(struct sde_encoder_phys *phys)
  2097. {
  2098. struct sde_kms *sde_kms;
  2099. void *dither_cfg = NULL;
  2100. int ret = 0, i = 0;
  2101. size_t len = 0;
  2102. enum sde_rm_topology_name topology;
  2103. struct drm_encoder *drm_enc;
  2104. struct msm_display_dsc_info *dsc = NULL;
  2105. struct sde_encoder_virt *sde_enc;
  2106. struct sde_hw_pingpong *hw_pp;
  2107. u32 bpp, bpc;
  2108. int num_lm;
  2109. if (!phys || !phys->connector || !phys->hw_pp ||
  2110. !phys->hw_pp->ops.setup_dither || !phys->parent)
  2111. return;
  2112. sde_kms = sde_encoder_get_kms(phys->parent);
  2113. if (!sde_kms)
  2114. return;
  2115. topology = sde_connector_get_topology_name(phys->connector);
  2116. if ((topology == SDE_RM_TOPOLOGY_PPSPLIT) &&
  2117. (phys->split_role == ENC_ROLE_SLAVE))
  2118. return;
  2119. drm_enc = phys->parent;
  2120. sde_enc = to_sde_encoder_virt(drm_enc);
  2121. dsc = &sde_enc->mode_info.comp_info.dsc_info;
  2122. bpc = dsc->config.bits_per_component;
  2123. bpp = dsc->config.bits_per_pixel;
  2124. /* disable dither for 10 bpp or 10bpc dsc config */
  2125. if (bpp == 10 || bpc == 10) {
  2126. phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL, 0);
  2127. return;
  2128. }
  2129. ret = sde_connector_get_dither_cfg(phys->connector,
  2130. phys->connector->state, &dither_cfg,
  2131. &len, sde_enc->idle_pc_restore);
  2132. /* skip reg writes when return values are invalid or no data */
  2133. if (ret && ret == -ENODATA)
  2134. return;
  2135. num_lm = sde_rm_topology_get_num_lm(&sde_kms->rm, topology);
  2136. for (i = 0; i < num_lm; i++) {
  2137. hw_pp = sde_enc->hw_pp[i];
  2138. phys->hw_pp->ops.setup_dither(hw_pp,
  2139. dither_cfg, len);
  2140. }
  2141. }
  2142. void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
  2143. {
  2144. struct sde_encoder_virt *sde_enc = NULL;
  2145. int i;
  2146. if (!drm_enc) {
  2147. SDE_ERROR("invalid encoder\n");
  2148. return;
  2149. }
  2150. sde_enc = to_sde_encoder_virt(drm_enc);
  2151. if (!sde_enc->cur_master) {
  2152. SDE_DEBUG("virt encoder has no master\n");
  2153. return;
  2154. }
  2155. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2156. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2157. sde_enc->idle_pc_restore = true;
  2158. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2159. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2160. if (!phys)
  2161. continue;
  2162. if (phys->hw_ctl && phys->hw_ctl->ops.clear_pending_flush)
  2163. phys->hw_ctl->ops.clear_pending_flush(phys->hw_ctl);
  2164. if ((phys != sde_enc->cur_master) && phys->ops.restore)
  2165. phys->ops.restore(phys);
  2166. _sde_encoder_setup_dither(phys);
  2167. }
  2168. if (sde_enc->cur_master->ops.restore)
  2169. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2170. _sde_encoder_virt_enable_helper(drm_enc);
  2171. }
  2172. static void sde_encoder_off_work(struct kthread_work *work)
  2173. {
  2174. struct sde_encoder_virt *sde_enc = container_of(work,
  2175. struct sde_encoder_virt, delayed_off_work.work);
  2176. struct drm_encoder *drm_enc;
  2177. if (!sde_enc) {
  2178. SDE_ERROR("invalid sde encoder\n");
  2179. return;
  2180. }
  2181. drm_enc = &sde_enc->base;
  2182. SDE_ATRACE_BEGIN("sde_encoder_off_work");
  2183. sde_encoder_idle_request(drm_enc);
  2184. SDE_ATRACE_END("sde_encoder_off_work");
  2185. }
  2186. static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
  2187. {
  2188. struct sde_encoder_virt *sde_enc = NULL;
  2189. int i, ret = 0;
  2190. struct msm_compression_info *comp_info = NULL;
  2191. struct drm_display_mode *cur_mode = NULL;
  2192. struct msm_display_info *disp_info;
  2193. if (!drm_enc || !drm_enc->crtc) {
  2194. SDE_ERROR("invalid encoder\n");
  2195. return;
  2196. }
  2197. sde_enc = to_sde_encoder_virt(drm_enc);
  2198. disp_info = &sde_enc->disp_info;
  2199. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2200. SDE_ERROR("power resource is not enabled\n");
  2201. return;
  2202. }
  2203. if (!sde_enc->crtc)
  2204. sde_enc->crtc = drm_enc->crtc;
  2205. comp_info = &sde_enc->mode_info.comp_info;
  2206. cur_mode = &sde_enc->base.crtc->state->adjusted_mode;
  2207. SDE_DEBUG_ENC(sde_enc, "\n");
  2208. SDE_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);
  2209. sde_enc->cur_master = NULL;
  2210. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2211. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2212. if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
  2213. SDE_DEBUG_ENC(sde_enc, "master is now idx %d\n", i);
  2214. sde_enc->cur_master = phys;
  2215. break;
  2216. }
  2217. }
  2218. if (!sde_enc->cur_master) {
  2219. SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
  2220. return;
  2221. }
  2222. _sde_encoder_input_handler_register(drm_enc);
  2223. if ((drm_enc->crtc->state->connectors_changed &&
  2224. sde_encoder_in_clone_mode(drm_enc)) ||
  2225. !(msm_is_mode_seamless_vrr(cur_mode)
  2226. || msm_is_mode_seamless_dms(cur_mode)
  2227. || msm_is_mode_seamless_dyn_clk(cur_mode)))
  2228. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  2229. sde_encoder_off_work);
  2230. ret = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  2231. if (ret) {
  2232. SDE_ERROR_ENC(sde_enc, "sde resource control failed: %d\n",
  2233. ret);
  2234. return;
  2235. }
  2236. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2237. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2238. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2239. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2240. if (!phys)
  2241. continue;
  2242. phys->comp_type = comp_info->comp_type;
  2243. phys->comp_ratio = comp_info->comp_ratio;
  2244. phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
  2245. phys->poms_align_vsync = disp_info->poms_align_vsync;
  2246. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
  2247. phys->dsc_extra_pclk_cycle_cnt =
  2248. comp_info->dsc_info.pclk_per_line;
  2249. phys->dsc_extra_disp_width =
  2250. comp_info->dsc_info.extra_width;
  2251. phys->dce_bytes_per_line =
  2252. comp_info->dsc_info.bytes_per_pkt *
  2253. comp_info->dsc_info.pkt_per_line;
  2254. } else if (phys->comp_type == MSM_DISPLAY_COMPRESSION_VDC) {
  2255. phys->dce_bytes_per_line =
  2256. comp_info->vdc_info.bytes_per_pkt *
  2257. comp_info->vdc_info.pkt_per_line;
  2258. }
  2259. if (phys != sde_enc->cur_master) {
  2260. /**
  2261. * on DMS request, the encoder will be enabled
  2262. * already. Invoke restore to reconfigure the
  2263. * new mode.
  2264. */
  2265. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2266. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2267. phys->ops.restore)
  2268. phys->ops.restore(phys);
  2269. else if (phys->ops.enable)
  2270. phys->ops.enable(phys);
  2271. }
  2272. if (sde_enc->misr_enable && phys->ops.setup_misr &&
  2273. (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
  2274. phys->ops.setup_misr(phys, true,
  2275. sde_enc->misr_frame_count);
  2276. }
  2277. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2278. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2279. sde_enc->cur_master->ops.restore)
  2280. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2281. else if (sde_enc->cur_master->ops.enable)
  2282. sde_enc->cur_master->ops.enable(sde_enc->cur_master);
  2283. _sde_encoder_virt_enable_helper(drm_enc);
  2284. }
  2285. static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
  2286. {
  2287. struct sde_encoder_virt *sde_enc = NULL;
  2288. struct sde_kms *sde_kms;
  2289. enum sde_intf_mode intf_mode;
  2290. int i = 0;
  2291. if (!drm_enc) {
  2292. SDE_ERROR("invalid encoder\n");
  2293. return;
  2294. } else if (!drm_enc->dev) {
  2295. SDE_ERROR("invalid dev\n");
  2296. return;
  2297. } else if (!drm_enc->dev->dev_private) {
  2298. SDE_ERROR("invalid dev_private\n");
  2299. return;
  2300. }
  2301. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2302. SDE_ERROR("power resource is not enabled\n");
  2303. return;
  2304. }
  2305. sde_enc = to_sde_encoder_virt(drm_enc);
  2306. SDE_DEBUG_ENC(sde_enc, "\n");
  2307. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2308. if (!sde_kms)
  2309. return;
  2310. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2311. SDE_EVT32(DRMID(drm_enc));
  2312. /* wait for idle */
  2313. sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  2314. _sde_encoder_input_handler_unregister(drm_enc);
  2315. /*
  2316. * For primary command mode and video mode encoders, execute the
  2317. * resource control pre-stop operations before the physical encoders
  2318. * are disabled, to allow the rsc to transition its states properly.
  2319. *
  2320. * For other encoder types, rsc should not be enabled until after
  2321. * they have been fully disabled, so delay the pre-stop operations
  2322. * until after the physical disable calls have returned.
  2323. */
  2324. if (sde_enc->disp_info.display_type == SDE_CONNECTOR_PRIMARY &&
  2325. (intf_mode == INTF_MODE_CMD || intf_mode == INTF_MODE_VIDEO)) {
  2326. sde_encoder_resource_control(drm_enc,
  2327. SDE_ENC_RC_EVENT_PRE_STOP);
  2328. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2329. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2330. if (phys && phys->ops.disable)
  2331. phys->ops.disable(phys);
  2332. }
  2333. } else {
  2334. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2335. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2336. if (phys && phys->ops.disable)
  2337. phys->ops.disable(phys);
  2338. }
  2339. sde_encoder_resource_control(drm_enc,
  2340. SDE_ENC_RC_EVENT_PRE_STOP);
  2341. }
  2342. /*
  2343. * disable dce after the transfer is complete (for command mode)
  2344. * and after physical encoder is disabled, to make sure timing
  2345. * engine is already disabled (for video mode).
  2346. */
  2347. if (!sde_in_trusted_vm(sde_kms))
  2348. sde_encoder_dce_disable(sde_enc);
  2349. sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);
  2350. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2351. if (sde_enc->phys_encs[i]) {
  2352. sde_enc->phys_encs[i]->cont_splash_enabled = false;
  2353. sde_enc->phys_encs[i]->connector = NULL;
  2354. }
  2355. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2356. }
  2357. sde_enc->cur_master = NULL;
  2358. /*
  2359. * clear the cached crtc in sde_enc on use case finish, after all the
  2360. * outstanding events and timers have been completed
  2361. */
  2362. sde_enc->crtc = NULL;
  2363. memset(&sde_enc->mode_info, 0, sizeof(sde_enc->mode_info));
  2364. SDE_DEBUG_ENC(sde_enc, "encoder disabled\n");
  2365. sde_rm_release(&sde_kms->rm, drm_enc, false);
  2366. }
  2367. void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
  2368. struct sde_encoder_phys_wb *wb_enc)
  2369. {
  2370. struct sde_encoder_virt *sde_enc;
  2371. phys_enc->hw_ctl->ops.reset(phys_enc->hw_ctl);
  2372. sde_encoder_helper_reset_mixers(phys_enc, NULL);
  2373. if (wb_enc) {
  2374. if (wb_enc->hw_wb->ops.bind_pingpong_blk) {
  2375. wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
  2376. false, phys_enc->hw_pp->idx);
  2377. if (phys_enc->hw_ctl->ops.update_bitmask)
  2378. phys_enc->hw_ctl->ops.update_bitmask(
  2379. phys_enc->hw_ctl,
  2380. SDE_HW_FLUSH_WB,
  2381. wb_enc->hw_wb->idx, true);
  2382. }
  2383. } else {
  2384. if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
  2385. phys_enc->hw_intf->ops.bind_pingpong_blk(
  2386. phys_enc->hw_intf, false,
  2387. phys_enc->hw_pp->idx);
  2388. if (phys_enc->hw_ctl->ops.update_bitmask)
  2389. phys_enc->hw_ctl->ops.update_bitmask(
  2390. phys_enc->hw_ctl,
  2391. SDE_HW_FLUSH_INTF,
  2392. phys_enc->hw_intf->idx, true);
  2393. }
  2394. }
  2395. if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {
  2396. phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);
  2397. if (phys_enc->hw_ctl->ops.update_bitmask &&
  2398. phys_enc->hw_pp->merge_3d)
  2399. phys_enc->hw_ctl->ops.update_bitmask(
  2400. phys_enc->hw_ctl, SDE_HW_FLUSH_MERGE_3D,
  2401. phys_enc->hw_pp->merge_3d->idx, true);
  2402. }
  2403. if (phys_enc->hw_cdm && phys_enc->hw_cdm->ops.bind_pingpong_blk &&
  2404. phys_enc->hw_pp) {
  2405. phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
  2406. false, phys_enc->hw_pp->idx);
  2407. if (phys_enc->hw_ctl->ops.update_bitmask)
  2408. phys_enc->hw_ctl->ops.update_bitmask(
  2409. phys_enc->hw_ctl, SDE_HW_FLUSH_CDM,
  2410. phys_enc->hw_cdm->idx, true);
  2411. }
  2412. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2413. if (phys_enc == sde_enc->cur_master && phys_enc->hw_pp &&
  2414. phys_enc->hw_ctl->ops.reset_post_disable)
  2415. phys_enc->hw_ctl->ops.reset_post_disable(
  2416. phys_enc->hw_ctl, &phys_enc->intf_cfg_v1,
  2417. phys_enc->hw_pp->merge_3d ?
  2418. phys_enc->hw_pp->merge_3d->idx : 0);
  2419. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  2420. phys_enc->hw_ctl->ops.trigger_start(phys_enc->hw_ctl);
  2421. }
  2422. static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
  2423. enum sde_intf_type type, u32 controller_id)
  2424. {
  2425. int i = 0;
  2426. for (i = 0; i < catalog->intf_count; i++) {
  2427. if (catalog->intf[i].type == type
  2428. && catalog->intf[i].controller_id == controller_id) {
  2429. return catalog->intf[i].id;
  2430. }
  2431. }
  2432. return INTF_MAX;
  2433. }
  2434. static enum sde_wb sde_encoder_get_wb(struct sde_mdss_cfg *catalog,
  2435. enum sde_intf_type type, u32 controller_id)
  2436. {
  2437. if (controller_id < catalog->wb_count)
  2438. return catalog->wb[controller_id].id;
  2439. return WB_MAX;
  2440. }
  2441. void sde_encoder_perf_uidle_status(struct sde_kms *sde_kms,
  2442. struct drm_crtc *crtc)
  2443. {
  2444. struct sde_hw_uidle *uidle;
  2445. struct sde_uidle_cntr cntr;
  2446. struct sde_uidle_status status;
  2447. if (!sde_kms || !crtc || !sde_kms->hw_uidle) {
  2448. pr_err("invalid params %d %d\n",
  2449. !sde_kms, !crtc);
  2450. return;
  2451. }
  2452. /* check if perf counters are enabled and setup */
  2453. if (!sde_kms->catalog->uidle_cfg.perf_cntr_en)
  2454. return;
  2455. uidle = sde_kms->hw_uidle;
  2456. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_STATUS)
  2457. && uidle->ops.uidle_get_status) {
  2458. uidle->ops.uidle_get_status(uidle, &status);
  2459. trace_sde_perf_uidle_status(
  2460. crtc->base.id,
  2461. status.uidle_danger_status_0,
  2462. status.uidle_danger_status_1,
  2463. status.uidle_safe_status_0,
  2464. status.uidle_safe_status_1,
  2465. status.uidle_idle_status_0,
  2466. status.uidle_idle_status_1,
  2467. status.uidle_fal_status_0,
  2468. status.uidle_fal_status_1,
  2469. status.uidle_status,
  2470. status.uidle_en_fal10);
  2471. }
  2472. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_CNT)
  2473. && uidle->ops.uidle_get_cntr) {
  2474. uidle->ops.uidle_get_cntr(uidle, &cntr);
  2475. trace_sde_perf_uidle_cntr(
  2476. crtc->base.id,
  2477. cntr.fal1_gate_cntr,
  2478. cntr.fal10_gate_cntr,
  2479. cntr.fal_wait_gate_cntr,
  2480. cntr.fal1_num_transitions_cntr,
  2481. cntr.fal10_num_transitions_cntr,
  2482. cntr.min_gate_cntr,
  2483. cntr.max_gate_cntr);
  2484. }
  2485. }
  2486. static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
  2487. struct sde_encoder_phys *phy_enc)
  2488. {
  2489. struct sde_encoder_virt *sde_enc = NULL;
  2490. unsigned long lock_flags;
  2491. if (!drm_enc || !phy_enc)
  2492. return;
  2493. SDE_ATRACE_BEGIN("encoder_vblank_callback");
  2494. sde_enc = to_sde_encoder_virt(drm_enc);
  2495. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2496. if (sde_enc->crtc_vblank_cb)
  2497. sde_enc->crtc_vblank_cb(sde_enc->crtc_vblank_cb_data);
  2498. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2499. if (phy_enc->sde_kms &&
  2500. phy_enc->sde_kms->catalog->uidle_cfg.debugfs_perf)
  2501. sde_encoder_perf_uidle_status(phy_enc->sde_kms, sde_enc->crtc);
  2502. atomic_inc(&phy_enc->vsync_cnt);
  2503. SDE_ATRACE_END("encoder_vblank_callback");
  2504. }
  2505. static void sde_encoder_underrun_callback(struct drm_encoder *drm_enc,
  2506. struct sde_encoder_phys *phy_enc)
  2507. {
  2508. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2509. if (!phy_enc)
  2510. return;
  2511. SDE_ATRACE_BEGIN("encoder_underrun_callback");
  2512. atomic_inc(&phy_enc->underrun_cnt);
  2513. SDE_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
  2514. if (sde_enc->cur_master->ops.get_underrun_line_count)
  2515. sde_enc->cur_master->ops.get_underrun_line_count(
  2516. sde_enc->cur_master);
  2517. trace_sde_encoder_underrun(DRMID(drm_enc),
  2518. atomic_read(&phy_enc->underrun_cnt));
  2519. SDE_DBG_CTRL("stop_ftrace");
  2520. SDE_DBG_CTRL("panic_underrun");
  2521. SDE_ATRACE_END("encoder_underrun_callback");
  2522. }
  2523. void sde_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
  2524. void (*vbl_cb)(void *), void *vbl_data)
  2525. {
  2526. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2527. unsigned long lock_flags;
  2528. bool enable;
  2529. int i;
  2530. enable = vbl_cb ? true : false;
  2531. if (!drm_enc) {
  2532. SDE_ERROR("invalid encoder\n");
  2533. return;
  2534. }
  2535. SDE_DEBUG_ENC(sde_enc, "\n");
  2536. SDE_EVT32(DRMID(drm_enc), enable);
  2537. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2538. sde_enc->crtc_vblank_cb = vbl_cb;
  2539. sde_enc->crtc_vblank_cb_data = vbl_data;
  2540. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2541. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2542. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2543. if (phys && phys->ops.control_vblank_irq)
  2544. phys->ops.control_vblank_irq(phys, enable);
  2545. }
  2546. sde_enc->vblank_enabled = enable;
  2547. }
  2548. void sde_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
  2549. void (*frame_event_cb)(void *, u32 event),
  2550. struct drm_crtc *crtc)
  2551. {
  2552. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2553. unsigned long lock_flags;
  2554. bool enable;
  2555. enable = frame_event_cb ? true : false;
  2556. if (!drm_enc) {
  2557. SDE_ERROR("invalid encoder\n");
  2558. return;
  2559. }
  2560. SDE_DEBUG_ENC(sde_enc, "\n");
  2561. SDE_EVT32(DRMID(drm_enc), enable, 0);
  2562. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2563. sde_enc->crtc_frame_event_cb = frame_event_cb;
  2564. sde_enc->crtc_frame_event_cb_data.crtc = crtc;
  2565. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2566. }
  2567. static void sde_encoder_frame_done_callback(
  2568. struct drm_encoder *drm_enc,
  2569. struct sde_encoder_phys *ready_phys, u32 event)
  2570. {
  2571. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2572. unsigned int i;
  2573. bool trigger = true;
  2574. bool is_cmd_mode = false;
  2575. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2576. if (!drm_enc || !sde_enc->cur_master) {
  2577. SDE_ERROR("invalid param: drm_enc %pK, cur_master %pK\n",
  2578. drm_enc, drm_enc ? sde_enc->cur_master : 0);
  2579. return;
  2580. }
  2581. sde_enc->crtc_frame_event_cb_data.connector =
  2582. sde_enc->cur_master->connector;
  2583. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2584. is_cmd_mode = true;
  2585. if (event & (SDE_ENCODER_FRAME_EVENT_DONE
  2586. | SDE_ENCODER_FRAME_EVENT_ERROR
  2587. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) && is_cmd_mode) {
  2588. if (ready_phys->connector)
  2589. topology = sde_connector_get_topology_name(
  2590. ready_phys->connector);
  2591. /* One of the physical encoders has become idle */
  2592. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2593. if (sde_enc->phys_encs[i] == ready_phys) {
  2594. SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
  2595. atomic_read(&sde_enc->frame_done_cnt[i]));
  2596. if (!atomic_add_unless(
  2597. &sde_enc->frame_done_cnt[i], 1, 2)) {
  2598. SDE_EVT32(DRMID(drm_enc), event,
  2599. ready_phys->intf_idx,
  2600. SDE_EVTLOG_ERROR);
  2601. SDE_ERROR_ENC(sde_enc,
  2602. "intf idx:%d, event:%d\n",
  2603. ready_phys->intf_idx, event);
  2604. return;
  2605. }
  2606. }
  2607. if (topology != SDE_RM_TOPOLOGY_PPSPLIT &&
  2608. atomic_read(&sde_enc->frame_done_cnt[i]) == 0)
  2609. trigger = false;
  2610. }
  2611. if (trigger) {
  2612. if (sde_enc->crtc_frame_event_cb)
  2613. sde_enc->crtc_frame_event_cb(
  2614. &sde_enc->crtc_frame_event_cb_data,
  2615. event);
  2616. for (i = 0; i < sde_enc->num_phys_encs; i++)
  2617. atomic_add_unless(&sde_enc->frame_done_cnt[i],
  2618. -1, 0);
  2619. }
  2620. } else if (sde_enc->crtc_frame_event_cb) {
  2621. sde_enc->crtc_frame_event_cb(
  2622. &sde_enc->crtc_frame_event_cb_data, event);
  2623. }
  2624. }
  2625. static void sde_encoder_get_qsync_fps_callback(
  2626. struct drm_encoder *drm_enc,
  2627. u32 *qsync_fps)
  2628. {
  2629. struct msm_display_info *disp_info;
  2630. struct sde_encoder_virt *sde_enc;
  2631. if (!qsync_fps)
  2632. return;
  2633. *qsync_fps = 0;
  2634. if (!drm_enc) {
  2635. SDE_ERROR("invalid drm encoder\n");
  2636. return;
  2637. }
  2638. sde_enc = to_sde_encoder_virt(drm_enc);
  2639. disp_info = &sde_enc->disp_info;
  2640. *qsync_fps = disp_info->qsync_min_fps;
  2641. }
  2642. int sde_encoder_idle_request(struct drm_encoder *drm_enc)
  2643. {
  2644. struct sde_encoder_virt *sde_enc;
  2645. if (!drm_enc) {
  2646. SDE_ERROR("invalid drm encoder\n");
  2647. return -EINVAL;
  2648. }
  2649. sde_enc = to_sde_encoder_virt(drm_enc);
  2650. sde_encoder_resource_control(&sde_enc->base,
  2651. SDE_ENC_RC_EVENT_ENTER_IDLE);
  2652. return 0;
  2653. }
  2654. /**
  2655. * _sde_encoder_trigger_flush - trigger flush for a physical encoder
  2656. * drm_enc: Pointer to drm encoder structure
  2657. * phys: Pointer to physical encoder structure
  2658. * extra_flush: Additional bit mask to include in flush trigger
  2659. * config_changed: if true new config is applied, avoid increment of retire
  2660. * count if false
  2661. */
  2662. static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
  2663. struct sde_encoder_phys *phys,
  2664. struct sde_ctl_flush_cfg *extra_flush,
  2665. bool config_changed)
  2666. {
  2667. struct sde_hw_ctl *ctl;
  2668. unsigned long lock_flags;
  2669. struct sde_encoder_virt *sde_enc;
  2670. int pend_ret_fence_cnt;
  2671. struct sde_connector *c_conn;
  2672. if (!drm_enc || !phys) {
  2673. SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
  2674. !drm_enc, !phys);
  2675. return;
  2676. }
  2677. sde_enc = to_sde_encoder_virt(drm_enc);
  2678. c_conn = to_sde_connector(phys->connector);
  2679. if (!phys->hw_pp) {
  2680. SDE_ERROR("invalid pingpong hw\n");
  2681. return;
  2682. }
  2683. ctl = phys->hw_ctl;
  2684. if (!ctl || !phys->ops.trigger_flush) {
  2685. SDE_ERROR("missing ctl/trigger cb\n");
  2686. return;
  2687. }
  2688. if (phys->split_role == ENC_ROLE_SKIP) {
  2689. SDE_DEBUG_ENC(to_sde_encoder_virt(phys->parent),
  2690. "skip flush pp%d ctl%d\n",
  2691. phys->hw_pp->idx - PINGPONG_0,
  2692. ctl->idx - CTL_0);
  2693. return;
  2694. }
  2695. /* update pending counts and trigger kickoff ctl flush atomically */
  2696. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2697. if (phys->ops.is_master && phys->ops.is_master(phys) && config_changed)
  2698. atomic_inc(&phys->pending_retire_fence_cnt);
  2699. pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);
  2700. if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&
  2701. ctl->ops.update_bitmask) {
  2702. /* perform peripheral flush on every frame update for dp dsc */
  2703. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  2704. phys->comp_ratio && c_conn->ops.update_pps) {
  2705. c_conn->ops.update_pps(phys->connector, NULL,
  2706. c_conn->display);
  2707. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2708. phys->hw_intf->idx, 1);
  2709. }
  2710. if (sde_enc->dynamic_hdr_updated)
  2711. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2712. phys->hw_intf->idx, 1);
  2713. }
  2714. if ((extra_flush && extra_flush->pending_flush_mask)
  2715. && ctl->ops.update_pending_flush)
  2716. ctl->ops.update_pending_flush(ctl, extra_flush);
  2717. phys->ops.trigger_flush(phys);
  2718. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2719. if (ctl->ops.get_pending_flush) {
  2720. struct sde_ctl_flush_cfg pending_flush = {0,};
  2721. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2722. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2723. ctl->idx - CTL_0,
  2724. pending_flush.pending_flush_mask,
  2725. pend_ret_fence_cnt);
  2726. } else {
  2727. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2728. ctl->idx - CTL_0,
  2729. pend_ret_fence_cnt);
  2730. }
  2731. }
  2732. /**
  2733. * _sde_encoder_trigger_start - trigger start for a physical encoder
  2734. * phys: Pointer to physical encoder structure
  2735. */
  2736. static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys)
  2737. {
  2738. struct sde_hw_ctl *ctl;
  2739. struct sde_encoder_virt *sde_enc;
  2740. if (!phys) {
  2741. SDE_ERROR("invalid argument(s)\n");
  2742. return;
  2743. }
  2744. if (!phys->hw_pp) {
  2745. SDE_ERROR("invalid pingpong hw\n");
  2746. return;
  2747. }
  2748. if (!phys->parent) {
  2749. SDE_ERROR("invalid parent\n");
  2750. return;
  2751. }
  2752. /* avoid ctrl start for encoder in clone mode */
  2753. if (phys->in_clone_mode)
  2754. return;
  2755. ctl = phys->hw_ctl;
  2756. sde_enc = to_sde_encoder_virt(phys->parent);
  2757. if (phys->split_role == ENC_ROLE_SKIP) {
  2758. SDE_DEBUG_ENC(sde_enc,
  2759. "skip start pp%d ctl%d\n",
  2760. phys->hw_pp->idx - PINGPONG_0,
  2761. ctl->idx - CTL_0);
  2762. return;
  2763. }
  2764. if (phys->ops.trigger_start && phys->enable_state != SDE_ENC_DISABLED)
  2765. phys->ops.trigger_start(phys);
  2766. }
  2767. void sde_encoder_helper_trigger_flush(struct sde_encoder_phys *phys_enc)
  2768. {
  2769. struct sde_hw_ctl *ctl;
  2770. if (!phys_enc) {
  2771. SDE_ERROR("invalid encoder\n");
  2772. return;
  2773. }
  2774. ctl = phys_enc->hw_ctl;
  2775. if (ctl && ctl->ops.trigger_flush)
  2776. ctl->ops.trigger_flush(ctl);
  2777. }
  2778. void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc)
  2779. {
  2780. struct sde_hw_ctl *ctl;
  2781. if (!phys_enc) {
  2782. SDE_ERROR("invalid encoder\n");
  2783. return;
  2784. }
  2785. ctl = phys_enc->hw_ctl;
  2786. if (ctl && ctl->ops.trigger_start) {
  2787. ctl->ops.trigger_start(ctl);
  2788. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx - CTL_0);
  2789. }
  2790. }
  2791. void sde_encoder_helper_hw_reset(struct sde_encoder_phys *phys_enc)
  2792. {
  2793. struct sde_encoder_virt *sde_enc;
  2794. struct sde_connector *sde_con;
  2795. void *sde_con_disp;
  2796. struct sde_hw_ctl *ctl;
  2797. int rc;
  2798. if (!phys_enc) {
  2799. SDE_ERROR("invalid encoder\n");
  2800. return;
  2801. }
  2802. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2803. ctl = phys_enc->hw_ctl;
  2804. if (!ctl || !ctl->ops.reset)
  2805. return;
  2806. SDE_DEBUG_ENC(sde_enc, "ctl %d reset\n", ctl->idx);
  2807. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx);
  2808. if (phys_enc->ops.is_master && phys_enc->ops.is_master(phys_enc) &&
  2809. phys_enc->connector) {
  2810. sde_con = to_sde_connector(phys_enc->connector);
  2811. sde_con_disp = sde_connector_get_display(phys_enc->connector);
  2812. if (sde_con->ops.soft_reset) {
  2813. rc = sde_con->ops.soft_reset(sde_con_disp);
  2814. if (rc) {
  2815. SDE_ERROR_ENC(sde_enc,
  2816. "connector soft reset failure\n");
  2817. SDE_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus",
  2818. "panic");
  2819. }
  2820. }
  2821. }
  2822. phys_enc->enable_state = SDE_ENC_ENABLED;
  2823. }
  2824. /**
  2825. * _sde_encoder_kickoff_phys - handle physical encoder kickoff
  2826. * Iterate through the physical encoders and perform consolidated flush
  2827. * and/or control start triggering as needed. This is done in the virtual
  2828. * encoder rather than the individual physical ones in order to handle
  2829. * use cases that require visibility into multiple physical encoders at
  2830. * a time.
  2831. * sde_enc: Pointer to virtual encoder structure
  2832. * config_changed: if true new config is applied. Avoid regdma_flush and
  2833. * incrementing the retire count if false.
  2834. */
  2835. static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc,
  2836. bool config_changed)
  2837. {
  2838. struct sde_hw_ctl *ctl;
  2839. uint32_t i;
  2840. struct sde_ctl_flush_cfg pending_flush = {0,};
  2841. u32 pending_kickoff_cnt;
  2842. struct msm_drm_private *priv = NULL;
  2843. struct sde_kms *sde_kms = NULL;
  2844. struct sde_crtc_misr_info crtc_misr_info = {false, 0};
  2845. bool is_regdma_blocking = false, is_vid_mode = false;
  2846. struct sde_crtc *sde_crtc;
  2847. if (!sde_enc) {
  2848. SDE_ERROR("invalid encoder\n");
  2849. return;
  2850. }
  2851. sde_crtc = to_sde_crtc(sde_enc->crtc);
  2852. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  2853. is_vid_mode = true;
  2854. is_regdma_blocking = (is_vid_mode ||
  2855. _sde_encoder_is_autorefresh_enabled(sde_enc));
  2856. /* don't perform flush/start operations for slave encoders */
  2857. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2858. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2859. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2860. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2861. continue;
  2862. ctl = phys->hw_ctl;
  2863. if (!ctl)
  2864. continue;
  2865. if (phys->connector)
  2866. topology = sde_connector_get_topology_name(
  2867. phys->connector);
  2868. if (!phys->ops.needs_single_flush ||
  2869. !phys->ops.needs_single_flush(phys)) {
  2870. if (config_changed && ctl->ops.reg_dma_flush)
  2871. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2872. _sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0,
  2873. config_changed);
  2874. } else if (ctl->ops.get_pending_flush) {
  2875. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2876. }
  2877. }
  2878. /* for split flush, combine pending flush masks and send to master */
  2879. if (pending_flush.pending_flush_mask && sde_enc->cur_master) {
  2880. ctl = sde_enc->cur_master->hw_ctl;
  2881. if (config_changed && ctl->ops.reg_dma_flush)
  2882. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2883. _sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master,
  2884. &pending_flush,
  2885. config_changed);
  2886. }
  2887. /* update pending_kickoff_cnt AFTER flush but before trigger start */
  2888. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2889. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2890. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2891. continue;
  2892. if (!phys->ops.needs_single_flush ||
  2893. !phys->ops.needs_single_flush(phys)) {
  2894. pending_kickoff_cnt =
  2895. sde_encoder_phys_inc_pending(phys);
  2896. SDE_EVT32(pending_kickoff_cnt, SDE_EVTLOG_FUNC_CASE1);
  2897. } else {
  2898. pending_kickoff_cnt =
  2899. sde_encoder_phys_inc_pending(phys);
  2900. SDE_EVT32(pending_kickoff_cnt,
  2901. pending_flush.pending_flush_mask,
  2902. SDE_EVTLOG_FUNC_CASE2);
  2903. }
  2904. }
  2905. if (sde_enc->misr_enable)
  2906. sde_encoder_misr_configure(&sde_enc->base, true,
  2907. sde_enc->misr_frame_count);
  2908. sde_crtc_get_misr_info(sde_enc->crtc, &crtc_misr_info);
  2909. if (crtc_misr_info.misr_enable && sde_crtc &&
  2910. sde_crtc->misr_reconfigure) {
  2911. sde_crtc_misr_setup(sde_enc->crtc, true,
  2912. crtc_misr_info.misr_frame_count);
  2913. sde_crtc->misr_reconfigure = false;
  2914. }
  2915. _sde_encoder_trigger_start(sde_enc->cur_master);
  2916. if (sde_enc->elevated_ahb_vote) {
  2917. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2918. priv = sde_enc->base.dev->dev_private;
  2919. if (sde_kms != NULL) {
  2920. sde_power_scale_reg_bus(&priv->phandle,
  2921. VOTE_INDEX_LOW,
  2922. false);
  2923. }
  2924. sde_enc->elevated_ahb_vote = false;
  2925. }
  2926. }
  2927. static void _sde_encoder_ppsplit_swap_intf_for_right_only_update(
  2928. struct drm_encoder *drm_enc,
  2929. unsigned long *affected_displays,
  2930. int num_active_phys)
  2931. {
  2932. struct sde_encoder_virt *sde_enc;
  2933. struct sde_encoder_phys *master;
  2934. enum sde_rm_topology_name topology;
  2935. bool is_right_only;
  2936. if (!drm_enc || !affected_displays)
  2937. return;
  2938. sde_enc = to_sde_encoder_virt(drm_enc);
  2939. master = sde_enc->cur_master;
  2940. if (!master || !master->connector)
  2941. return;
  2942. topology = sde_connector_get_topology_name(master->connector);
  2943. if (topology != SDE_RM_TOPOLOGY_PPSPLIT)
  2944. return;
  2945. /*
  2946. * For pingpong split, the slave pingpong won't generate IRQs. For
  2947. * right-only updates, we can't swap pingpongs, or simply swap the
  2948. * master/slave assignment, we actually have to swap the interfaces
  2949. * so that the master physical encoder will use a pingpong/interface
  2950. * that generates irqs on which to wait.
  2951. */
  2952. is_right_only = !test_bit(0, affected_displays) &&
  2953. test_bit(1, affected_displays);
  2954. if (is_right_only && !sde_enc->intfs_swapped) {
  2955. /* right-only update swap interfaces */
  2956. swap(sde_enc->phys_encs[0]->intf_idx,
  2957. sde_enc->phys_encs[1]->intf_idx);
  2958. sde_enc->intfs_swapped = true;
  2959. } else if (!is_right_only && sde_enc->intfs_swapped) {
  2960. /* left-only or full update, swap back */
  2961. swap(sde_enc->phys_encs[0]->intf_idx,
  2962. sde_enc->phys_encs[1]->intf_idx);
  2963. sde_enc->intfs_swapped = false;
  2964. }
  2965. SDE_DEBUG_ENC(sde_enc,
  2966. "right_only %d swapped %d phys0->intf%d, phys1->intf%d\n",
  2967. is_right_only, sde_enc->intfs_swapped,
  2968. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2969. sde_enc->phys_encs[1]->intf_idx - INTF_0);
  2970. SDE_EVT32(DRMID(drm_enc), is_right_only, sde_enc->intfs_swapped,
  2971. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2972. sde_enc->phys_encs[1]->intf_idx - INTF_0,
  2973. *affected_displays);
  2974. /* ppsplit always uses master since ppslave invalid for irqs*/
  2975. if (num_active_phys == 1)
  2976. *affected_displays = BIT(0);
  2977. }
  2978. static void _sde_encoder_update_master(struct drm_encoder *drm_enc,
  2979. struct sde_encoder_kickoff_params *params)
  2980. {
  2981. struct sde_encoder_virt *sde_enc;
  2982. struct sde_encoder_phys *phys;
  2983. int i, num_active_phys;
  2984. bool master_assigned = false;
  2985. if (!drm_enc || !params)
  2986. return;
  2987. sde_enc = to_sde_encoder_virt(drm_enc);
  2988. if (sde_enc->num_phys_encs <= 1)
  2989. return;
  2990. /* count bits set */
  2991. num_active_phys = hweight_long(params->affected_displays);
  2992. SDE_DEBUG_ENC(sde_enc, "affected_displays 0x%lx num_active_phys %d\n",
  2993. params->affected_displays, num_active_phys);
  2994. SDE_EVT32_VERBOSE(DRMID(drm_enc), params->affected_displays,
  2995. num_active_phys);
  2996. /* for left/right only update, ppsplit master switches interface */
  2997. _sde_encoder_ppsplit_swap_intf_for_right_only_update(drm_enc,
  2998. &params->affected_displays, num_active_phys);
  2999. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3000. enum sde_enc_split_role prv_role, new_role;
  3001. bool active = false;
  3002. phys = sde_enc->phys_encs[i];
  3003. if (!phys || !phys->ops.update_split_role || !phys->hw_pp)
  3004. continue;
  3005. active = test_bit(i, &params->affected_displays);
  3006. prv_role = phys->split_role;
  3007. if (active && num_active_phys == 1)
  3008. new_role = ENC_ROLE_SOLO;
  3009. else if (active && !master_assigned)
  3010. new_role = ENC_ROLE_MASTER;
  3011. else if (active)
  3012. new_role = ENC_ROLE_SLAVE;
  3013. else
  3014. new_role = ENC_ROLE_SKIP;
  3015. phys->ops.update_split_role(phys, new_role);
  3016. if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
  3017. sde_enc->cur_master = phys;
  3018. master_assigned = true;
  3019. }
  3020. SDE_DEBUG_ENC(sde_enc, "pp %d role prv %d new %d active %d\n",
  3021. phys->hw_pp->idx - PINGPONG_0, prv_role,
  3022. phys->split_role, active);
  3023. SDE_EVT32(DRMID(drm_enc), params->affected_displays,
  3024. phys->hw_pp->idx - PINGPONG_0, prv_role,
  3025. phys->split_role, active, num_active_phys);
  3026. }
  3027. }
  3028. bool sde_encoder_check_curr_mode(struct drm_encoder *drm_enc, u32 mode)
  3029. {
  3030. struct sde_encoder_virt *sde_enc;
  3031. struct msm_display_info *disp_info;
  3032. if (!drm_enc) {
  3033. SDE_ERROR("invalid encoder\n");
  3034. return false;
  3035. }
  3036. sde_enc = to_sde_encoder_virt(drm_enc);
  3037. disp_info = &sde_enc->disp_info;
  3038. return (disp_info->curr_panel_mode == mode);
  3039. }
  3040. void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
  3041. {
  3042. struct sde_encoder_virt *sde_enc;
  3043. struct sde_encoder_phys *phys;
  3044. unsigned int i;
  3045. struct sde_hw_ctl *ctl;
  3046. if (!drm_enc) {
  3047. SDE_ERROR("invalid encoder\n");
  3048. return;
  3049. }
  3050. sde_enc = to_sde_encoder_virt(drm_enc);
  3051. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3052. phys = sde_enc->phys_encs[i];
  3053. if (phys && phys->hw_ctl && (phys == sde_enc->cur_master) &&
  3054. sde_encoder_check_curr_mode(drm_enc,
  3055. MSM_DISPLAY_CMD_MODE)) {
  3056. ctl = phys->hw_ctl;
  3057. if (ctl->ops.trigger_pending)
  3058. /* update only for command mode primary ctl */
  3059. ctl->ops.trigger_pending(ctl);
  3060. }
  3061. }
  3062. sde_enc->idle_pc_restore = false;
  3063. }
  3064. static void sde_encoder_esd_trigger_work_handler(struct kthread_work *work)
  3065. {
  3066. struct sde_encoder_virt *sde_enc = container_of(work,
  3067. struct sde_encoder_virt, esd_trigger_work);
  3068. if (!sde_enc) {
  3069. SDE_ERROR("invalid sde encoder\n");
  3070. return;
  3071. }
  3072. sde_encoder_resource_control(&sde_enc->base,
  3073. SDE_ENC_RC_EVENT_KICKOFF);
  3074. }
  3075. static void sde_encoder_input_event_work_handler(struct kthread_work *work)
  3076. {
  3077. struct sde_encoder_virt *sde_enc = container_of(work,
  3078. struct sde_encoder_virt, input_event_work);
  3079. if (!sde_enc) {
  3080. SDE_ERROR("invalid sde encoder\n");
  3081. return;
  3082. }
  3083. sde_encoder_resource_control(&sde_enc->base,
  3084. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3085. }
  3086. static void sde_encoder_early_wakeup_work_handler(struct kthread_work *work)
  3087. {
  3088. struct sde_encoder_virt *sde_enc = container_of(work,
  3089. struct sde_encoder_virt, early_wakeup_work);
  3090. if (!sde_enc) {
  3091. SDE_ERROR("invalid sde encoder\n");
  3092. return;
  3093. }
  3094. SDE_ATRACE_BEGIN("encoder_early_wakeup");
  3095. sde_encoder_resource_control(&sde_enc->base,
  3096. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3097. SDE_ATRACE_END("encoder_early_wakeup");
  3098. }
  3099. void sde_encoder_early_wakeup(struct drm_encoder *drm_enc)
  3100. {
  3101. struct sde_encoder_virt *sde_enc = NULL;
  3102. struct msm_drm_thread *disp_thread = NULL;
  3103. struct msm_drm_private *priv = NULL;
  3104. priv = drm_enc->dev->dev_private;
  3105. sde_enc = to_sde_encoder_virt(drm_enc);
  3106. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE)) {
  3107. SDE_DEBUG_ENC(sde_enc,
  3108. "should only early wake up command mode display\n");
  3109. return;
  3110. }
  3111. if (!sde_enc->crtc || (sde_enc->crtc->index
  3112. >= ARRAY_SIZE(priv->event_thread))) {
  3113. SDE_DEBUG_ENC(sde_enc, "invalid CRTC: %d or crtc index: %d\n",
  3114. sde_enc->crtc == NULL,
  3115. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  3116. return;
  3117. }
  3118. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  3119. SDE_ATRACE_BEGIN("queue_early_wakeup_work");
  3120. kthread_queue_work(&disp_thread->worker,
  3121. &sde_enc->early_wakeup_work);
  3122. SDE_ATRACE_END("queue_early_wakeup_work");
  3123. }
  3124. int sde_encoder_poll_line_counts(struct drm_encoder *drm_enc)
  3125. {
  3126. static const uint64_t timeout_us = 50000;
  3127. static const uint64_t sleep_us = 20;
  3128. struct sde_encoder_virt *sde_enc;
  3129. ktime_t cur_ktime, exp_ktime;
  3130. uint32_t line_count, tmp, i;
  3131. if (!drm_enc) {
  3132. SDE_ERROR("invalid encoder\n");
  3133. return -EINVAL;
  3134. }
  3135. sde_enc = to_sde_encoder_virt(drm_enc);
  3136. if (!sde_enc->cur_master ||
  3137. !sde_enc->cur_master->ops.get_line_count) {
  3138. SDE_DEBUG_ENC(sde_enc, "can't get master line count\n");
  3139. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  3140. return -EINVAL;
  3141. }
  3142. exp_ktime = ktime_add_ms(ktime_get(), timeout_us / 1000);
  3143. line_count = sde_enc->cur_master->ops.get_line_count(
  3144. sde_enc->cur_master);
  3145. for (i = 0; i < (timeout_us * 2 / sleep_us); ++i) {
  3146. tmp = line_count;
  3147. line_count = sde_enc->cur_master->ops.get_line_count(
  3148. sde_enc->cur_master);
  3149. if (line_count < tmp) {
  3150. SDE_EVT32(DRMID(drm_enc), line_count);
  3151. return 0;
  3152. }
  3153. cur_ktime = ktime_get();
  3154. if (ktime_compare_safe(exp_ktime, cur_ktime) <= 0)
  3155. break;
  3156. usleep_range(sleep_us / 2, sleep_us);
  3157. }
  3158. SDE_EVT32(DRMID(drm_enc), line_count, SDE_EVTLOG_ERROR);
  3159. return -ETIMEDOUT;
  3160. }
  3161. static int _helper_flush_qsync(struct sde_encoder_phys *phys_enc)
  3162. {
  3163. struct drm_encoder *drm_enc;
  3164. struct sde_rm_hw_iter rm_iter;
  3165. bool lm_valid = false;
  3166. bool intf_valid = false;
  3167. if (!phys_enc || !phys_enc->parent) {
  3168. SDE_ERROR("invalid encoder\n");
  3169. return -EINVAL;
  3170. }
  3171. drm_enc = phys_enc->parent;
  3172. /* Flush the interfaces for AVR update or Qsync with INTF TE */
  3173. if (phys_enc->intf_mode == INTF_MODE_VIDEO ||
  3174. (phys_enc->intf_mode == INTF_MODE_CMD &&
  3175. phys_enc->has_intf_te)) {
  3176. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id,
  3177. SDE_HW_BLK_INTF);
  3178. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3179. struct sde_hw_intf *hw_intf =
  3180. (struct sde_hw_intf *)rm_iter.hw;
  3181. if (!hw_intf)
  3182. continue;
  3183. if (phys_enc->hw_ctl->ops.update_bitmask)
  3184. phys_enc->hw_ctl->ops.update_bitmask(
  3185. phys_enc->hw_ctl,
  3186. SDE_HW_FLUSH_INTF,
  3187. hw_intf->idx, 1);
  3188. intf_valid = true;
  3189. }
  3190. if (!intf_valid) {
  3191. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3192. "intf not found to flush\n");
  3193. return -EFAULT;
  3194. }
  3195. } else {
  3196. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3197. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3198. struct sde_hw_mixer *hw_lm =
  3199. (struct sde_hw_mixer *)rm_iter.hw;
  3200. if (!hw_lm)
  3201. continue;
  3202. /* update LM flush for HW without INTF TE */
  3203. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3204. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3205. phys_enc->hw_ctl,
  3206. hw_lm->idx, 1);
  3207. lm_valid = true;
  3208. }
  3209. if (!lm_valid) {
  3210. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3211. "lm not found to flush\n");
  3212. return -EFAULT;
  3213. }
  3214. }
  3215. return 0;
  3216. }
  3217. static void _sde_encoder_helper_hdr_plus_mempool_update(
  3218. struct sde_encoder_virt *sde_enc)
  3219. {
  3220. struct sde_connector_dyn_hdr_metadata *dhdr_meta = NULL;
  3221. struct sde_hw_mdp *mdptop = NULL;
  3222. sde_enc->dynamic_hdr_updated = false;
  3223. if (sde_enc->cur_master) {
  3224. mdptop = sde_enc->cur_master->hw_mdptop;
  3225. dhdr_meta = sde_connector_get_dyn_hdr_meta(
  3226. sde_enc->cur_master->connector);
  3227. }
  3228. if (!mdptop || !dhdr_meta || !dhdr_meta->dynamic_hdr_update)
  3229. return;
  3230. if (mdptop->ops.set_hdr_plus_metadata) {
  3231. sde_enc->dynamic_hdr_updated = true;
  3232. mdptop->ops.set_hdr_plus_metadata(
  3233. mdptop, dhdr_meta->dynamic_hdr_payload,
  3234. dhdr_meta->dynamic_hdr_payload_size,
  3235. sde_enc->cur_master->intf_idx == INTF_0 ?
  3236. 0 : 1);
  3237. }
  3238. }
  3239. void sde_encoder_needs_hw_reset(struct drm_encoder *drm_enc)
  3240. {
  3241. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  3242. struct sde_encoder_phys *phys;
  3243. int i;
  3244. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3245. phys = sde_enc->phys_encs[i];
  3246. if (phys && phys->ops.hw_reset)
  3247. phys->ops.hw_reset(phys);
  3248. }
  3249. }
  3250. int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
  3251. struct sde_encoder_kickoff_params *params)
  3252. {
  3253. struct sde_encoder_virt *sde_enc;
  3254. struct sde_encoder_phys *phys;
  3255. struct sde_kms *sde_kms = NULL;
  3256. struct sde_crtc *sde_crtc;
  3257. bool needs_hw_reset = false, is_cmd_mode;
  3258. int i, rc, ret = 0;
  3259. struct msm_display_info *disp_info;
  3260. if (!drm_enc || !params || !drm_enc->dev ||
  3261. !drm_enc->dev->dev_private) {
  3262. SDE_ERROR("invalid args\n");
  3263. return -EINVAL;
  3264. }
  3265. sde_enc = to_sde_encoder_virt(drm_enc);
  3266. sde_kms = sde_encoder_get_kms(drm_enc);
  3267. if (!sde_kms)
  3268. return -EINVAL;
  3269. disp_info = &sde_enc->disp_info;
  3270. sde_crtc = to_sde_crtc(sde_enc->crtc);
  3271. SDE_DEBUG_ENC(sde_enc, "\n");
  3272. SDE_EVT32(DRMID(drm_enc));
  3273. is_cmd_mode = sde_encoder_check_curr_mode(drm_enc,
  3274. MSM_DISPLAY_CMD_MODE);
  3275. if (sde_enc->cur_master && sde_enc->cur_master->connector
  3276. && is_cmd_mode)
  3277. sde_enc->frame_trigger_mode = sde_connector_get_property(
  3278. sde_enc->cur_master->connector->state,
  3279. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE);
  3280. _sde_encoder_helper_hdr_plus_mempool_update(sde_enc);
  3281. /* prepare for next kickoff, may include waiting on previous kickoff */
  3282. SDE_ATRACE_BEGIN("sde_encoder_prepare_for_kickoff");
  3283. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3284. phys = sde_enc->phys_encs[i];
  3285. params->frame_trigger_mode = sde_enc->frame_trigger_mode;
  3286. params->recovery_events_enabled =
  3287. sde_enc->recovery_events_enabled;
  3288. if (phys) {
  3289. if (phys->ops.prepare_for_kickoff) {
  3290. rc = phys->ops.prepare_for_kickoff(
  3291. phys, params);
  3292. if (rc)
  3293. ret = rc;
  3294. }
  3295. if (phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3296. needs_hw_reset = true;
  3297. _sde_encoder_setup_dither(phys);
  3298. if (sde_enc->cur_master &&
  3299. sde_connector_is_qsync_updated(
  3300. sde_enc->cur_master->connector)) {
  3301. _helper_flush_qsync(phys);
  3302. }
  3303. }
  3304. }
  3305. rc = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  3306. if (rc) {
  3307. SDE_ERROR_ENC(sde_enc, "resource kickoff failed rc %d\n", rc);
  3308. ret = rc;
  3309. goto end;
  3310. }
  3311. /* if any phys needs reset, reset all phys, in-order */
  3312. if (needs_hw_reset)
  3313. sde_encoder_needs_hw_reset(drm_enc);
  3314. _sde_encoder_update_master(drm_enc, params);
  3315. _sde_encoder_update_roi(drm_enc);
  3316. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3317. rc = sde_connector_pre_kickoff(sde_enc->cur_master->connector);
  3318. if (rc) {
  3319. SDE_ERROR_ENC(sde_enc, "kickoff conn%d failed rc %d\n",
  3320. sde_enc->cur_master->connector->base.id,
  3321. rc);
  3322. ret = rc;
  3323. }
  3324. }
  3325. if (sde_enc->cur_master &&
  3326. ((is_cmd_mode && sde_enc->cur_master->cont_splash_enabled) ||
  3327. !sde_enc->cur_master->cont_splash_enabled)) {
  3328. rc = sde_encoder_dce_setup(sde_enc, params);
  3329. if (rc) {
  3330. SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n", rc);
  3331. ret = rc;
  3332. }
  3333. }
  3334. sde_encoder_dce_flush(sde_enc);
  3335. if (sde_enc->cur_master && !sde_enc->cur_master->cont_splash_enabled)
  3336. sde_configure_qdss(sde_enc, sde_enc->cur_master->hw_qdss,
  3337. sde_enc->cur_master, sde_kms->qdss_enabled);
  3338. end:
  3339. SDE_ATRACE_END("sde_encoder_prepare_for_kickoff");
  3340. return ret;
  3341. }
  3342. /**
  3343. * _sde_encoder_reset_ctl_hw - reset h/w configuration for all ctl's associated
  3344. * with the specified encoder, and unstage all pipes from it
  3345. * @encoder: encoder pointer
  3346. * Returns: 0 on success
  3347. */
  3348. static int _sde_encoder_reset_ctl_hw(struct drm_encoder *drm_enc)
  3349. {
  3350. struct sde_encoder_virt *sde_enc;
  3351. struct sde_encoder_phys *phys;
  3352. unsigned int i;
  3353. int rc = 0;
  3354. if (!drm_enc) {
  3355. SDE_ERROR("invalid encoder\n");
  3356. return -EINVAL;
  3357. }
  3358. sde_enc = to_sde_encoder_virt(drm_enc);
  3359. SDE_ATRACE_BEGIN("encoder_release_lm");
  3360. SDE_DEBUG_ENC(sde_enc, "\n");
  3361. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3362. phys = sde_enc->phys_encs[i];
  3363. if (!phys)
  3364. continue;
  3365. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0);
  3366. rc = sde_encoder_helper_reset_mixers(phys, NULL);
  3367. if (rc)
  3368. SDE_EVT32(DRMID(drm_enc), rc, SDE_EVTLOG_ERROR);
  3369. }
  3370. SDE_ATRACE_END("encoder_release_lm");
  3371. return rc;
  3372. }
  3373. void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool is_error,
  3374. bool config_changed)
  3375. {
  3376. struct sde_encoder_virt *sde_enc;
  3377. struct sde_encoder_phys *phys;
  3378. unsigned int i;
  3379. if (!drm_enc) {
  3380. SDE_ERROR("invalid encoder\n");
  3381. return;
  3382. }
  3383. SDE_ATRACE_BEGIN("encoder_kickoff");
  3384. sde_enc = to_sde_encoder_virt(drm_enc);
  3385. SDE_DEBUG_ENC(sde_enc, "\n");
  3386. /* create a 'no pipes' commit to release buffers on errors */
  3387. if (is_error)
  3388. _sde_encoder_reset_ctl_hw(drm_enc);
  3389. /* All phys encs are ready to go, trigger the kickoff */
  3390. _sde_encoder_kickoff_phys(sde_enc, config_changed);
  3391. /* allow phys encs to handle any post-kickoff business */
  3392. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3393. phys = sde_enc->phys_encs[i];
  3394. if (phys && phys->ops.handle_post_kickoff)
  3395. phys->ops.handle_post_kickoff(phys);
  3396. }
  3397. SDE_ATRACE_END("encoder_kickoff");
  3398. }
  3399. void sde_encoder_helper_get_pp_line_count(struct drm_encoder *drm_enc,
  3400. struct sde_hw_pp_vsync_info *info)
  3401. {
  3402. struct sde_encoder_virt *sde_enc;
  3403. struct sde_encoder_phys *phys;
  3404. int i, ret;
  3405. if (!drm_enc || !info)
  3406. return;
  3407. sde_enc = to_sde_encoder_virt(drm_enc);
  3408. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3409. phys = sde_enc->phys_encs[i];
  3410. if (phys && phys->hw_intf && phys->hw_pp
  3411. && phys->hw_intf->ops.get_vsync_info) {
  3412. ret = phys->hw_intf->ops.get_vsync_info(
  3413. phys->hw_intf, &info[i]);
  3414. if (!ret) {
  3415. info[i].pp_idx = phys->hw_pp->idx - PINGPONG_0;
  3416. info[i].intf_idx = phys->hw_intf->idx - INTF_0;
  3417. }
  3418. }
  3419. }
  3420. }
  3421. void sde_encoder_helper_get_transfer_time(struct drm_encoder *drm_enc,
  3422. u32 *transfer_time_us)
  3423. {
  3424. struct sde_encoder_virt *sde_enc;
  3425. struct msm_mode_info *info;
  3426. if (!drm_enc || !transfer_time_us) {
  3427. SDE_ERROR("bad arg: encoder:%d transfer_time:%d\n", !drm_enc,
  3428. !transfer_time_us);
  3429. return;
  3430. }
  3431. sde_enc = to_sde_encoder_virt(drm_enc);
  3432. info = &sde_enc->mode_info;
  3433. *transfer_time_us = info->mdp_transfer_time_us;
  3434. }
  3435. int sde_encoder_helper_reset_mixers(struct sde_encoder_phys *phys_enc,
  3436. struct drm_framebuffer *fb)
  3437. {
  3438. struct drm_encoder *drm_enc;
  3439. struct sde_hw_mixer_cfg mixer;
  3440. struct sde_rm_hw_iter lm_iter;
  3441. bool lm_valid = false;
  3442. if (!phys_enc || !phys_enc->parent) {
  3443. SDE_ERROR("invalid encoder\n");
  3444. return -EINVAL;
  3445. }
  3446. drm_enc = phys_enc->parent;
  3447. memset(&mixer, 0, sizeof(mixer));
  3448. /* reset associated CTL/LMs */
  3449. if (phys_enc->hw_ctl->ops.clear_all_blendstages)
  3450. phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
  3451. sde_rm_init_hw_iter(&lm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3452. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &lm_iter)) {
  3453. struct sde_hw_mixer *hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  3454. if (!hw_lm)
  3455. continue;
  3456. /* need to flush LM to remove it */
  3457. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3458. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3459. phys_enc->hw_ctl,
  3460. hw_lm->idx, 1);
  3461. if (fb) {
  3462. /* assume a single LM if targeting a frame buffer */
  3463. if (lm_valid)
  3464. continue;
  3465. mixer.out_height = fb->height;
  3466. mixer.out_width = fb->width;
  3467. if (hw_lm->ops.setup_mixer_out)
  3468. hw_lm->ops.setup_mixer_out(hw_lm, &mixer);
  3469. }
  3470. lm_valid = true;
  3471. /* only enable border color on LM */
  3472. if (phys_enc->hw_ctl->ops.setup_blendstage)
  3473. phys_enc->hw_ctl->ops.setup_blendstage(
  3474. phys_enc->hw_ctl, hw_lm->idx, NULL, false);
  3475. }
  3476. if (!lm_valid) {
  3477. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc), "lm not found\n");
  3478. return -EFAULT;
  3479. }
  3480. return 0;
  3481. }
  3482. int sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
  3483. {
  3484. struct sde_encoder_virt *sde_enc;
  3485. struct sde_encoder_phys *phys;
  3486. int i, rc = 0, ret = 0;
  3487. struct sde_hw_ctl *ctl;
  3488. if (!drm_enc) {
  3489. SDE_ERROR("invalid encoder\n");
  3490. return -EINVAL;
  3491. }
  3492. sde_enc = to_sde_encoder_virt(drm_enc);
  3493. /* update the qsync parameters for the current frame */
  3494. if (sde_enc->cur_master)
  3495. sde_connector_set_qsync_params(
  3496. sde_enc->cur_master->connector);
  3497. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3498. phys = sde_enc->phys_encs[i];
  3499. if (phys && phys->ops.prepare_commit)
  3500. phys->ops.prepare_commit(phys);
  3501. if (phys && phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3502. ret = -ETIMEDOUT;
  3503. if (phys && phys->hw_ctl) {
  3504. ctl = phys->hw_ctl;
  3505. /*
  3506. * avoid clearing the pending flush during the first
  3507. * frame update after idle power collpase as the
  3508. * restore path would have updated the pending flush
  3509. */
  3510. if (!sde_enc->idle_pc_restore &&
  3511. ctl->ops.clear_pending_flush)
  3512. ctl->ops.clear_pending_flush(ctl);
  3513. }
  3514. }
  3515. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3516. rc = sde_connector_prepare_commit(
  3517. sde_enc->cur_master->connector);
  3518. if (rc)
  3519. SDE_ERROR_ENC(sde_enc,
  3520. "prepare commit failed conn %d rc %d\n",
  3521. sde_enc->cur_master->connector->base.id,
  3522. rc);
  3523. }
  3524. return ret;
  3525. }
  3526. void sde_encoder_helper_setup_misr(struct sde_encoder_phys *phys_enc,
  3527. bool enable, u32 frame_count)
  3528. {
  3529. if (!phys_enc)
  3530. return;
  3531. if (phys_enc->hw_intf && phys_enc->hw_intf->ops.setup_misr)
  3532. phys_enc->hw_intf->ops.setup_misr(phys_enc->hw_intf,
  3533. enable, frame_count);
  3534. }
  3535. int sde_encoder_helper_collect_misr(struct sde_encoder_phys *phys_enc,
  3536. bool nonblock, u32 *misr_value)
  3537. {
  3538. if (!phys_enc)
  3539. return -EINVAL;
  3540. return phys_enc->hw_intf && phys_enc->hw_intf->ops.collect_misr ?
  3541. phys_enc->hw_intf->ops.collect_misr(phys_enc->hw_intf,
  3542. nonblock, misr_value) : -ENOTSUPP;
  3543. }
  3544. #ifdef CONFIG_DEBUG_FS
  3545. static int _sde_encoder_status_show(struct seq_file *s, void *data)
  3546. {
  3547. struct sde_encoder_virt *sde_enc;
  3548. int i;
  3549. if (!s || !s->private)
  3550. return -EINVAL;
  3551. sde_enc = s->private;
  3552. mutex_lock(&sde_enc->enc_lock);
  3553. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3554. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3555. if (!phys)
  3556. continue;
  3557. seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
  3558. phys->intf_idx - INTF_0,
  3559. atomic_read(&phys->vsync_cnt),
  3560. atomic_read(&phys->underrun_cnt));
  3561. switch (phys->intf_mode) {
  3562. case INTF_MODE_VIDEO:
  3563. seq_puts(s, "mode: video\n");
  3564. break;
  3565. case INTF_MODE_CMD:
  3566. seq_puts(s, "mode: command\n");
  3567. break;
  3568. case INTF_MODE_WB_BLOCK:
  3569. seq_puts(s, "mode: wb block\n");
  3570. break;
  3571. case INTF_MODE_WB_LINE:
  3572. seq_puts(s, "mode: wb line\n");
  3573. break;
  3574. default:
  3575. seq_puts(s, "mode: ???\n");
  3576. break;
  3577. }
  3578. }
  3579. mutex_unlock(&sde_enc->enc_lock);
  3580. return 0;
  3581. }
  3582. static int _sde_encoder_debugfs_status_open(struct inode *inode,
  3583. struct file *file)
  3584. {
  3585. return single_open(file, _sde_encoder_status_show, inode->i_private);
  3586. }
  3587. static ssize_t _sde_encoder_misr_setup(struct file *file,
  3588. const char __user *user_buf, size_t count, loff_t *ppos)
  3589. {
  3590. struct sde_encoder_virt *sde_enc;
  3591. char buf[MISR_BUFF_SIZE + 1];
  3592. size_t buff_copy;
  3593. u32 frame_count, enable;
  3594. struct sde_kms *sde_kms = NULL;
  3595. struct drm_encoder *drm_enc;
  3596. if (!file || !file->private_data)
  3597. return -EINVAL;
  3598. sde_enc = file->private_data;
  3599. if (!sde_enc)
  3600. return -EINVAL;
  3601. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3602. if (!sde_kms)
  3603. return -EINVAL;
  3604. drm_enc = &sde_enc->base;
  3605. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3606. SDE_DEBUG_ENC(sde_enc, "misr enable/disable not allowed\n");
  3607. return -ENOTSUPP;
  3608. }
  3609. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  3610. if (copy_from_user(buf, user_buf, buff_copy))
  3611. return -EINVAL;
  3612. buf[buff_copy] = 0; /* end of string */
  3613. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  3614. return -EINVAL;
  3615. sde_enc->misr_enable = enable;
  3616. sde_enc->misr_reconfigure = true;
  3617. sde_enc->misr_frame_count = frame_count;
  3618. return count;
  3619. }
  3620. static ssize_t _sde_encoder_misr_read(struct file *file,
  3621. char __user *user_buff, size_t count, loff_t *ppos)
  3622. {
  3623. struct sde_encoder_virt *sde_enc;
  3624. struct sde_kms *sde_kms = NULL;
  3625. struct drm_encoder *drm_enc;
  3626. int i = 0, len = 0;
  3627. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  3628. int rc;
  3629. if (*ppos)
  3630. return 0;
  3631. if (!file || !file->private_data)
  3632. return -EINVAL;
  3633. sde_enc = file->private_data;
  3634. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3635. if (!sde_kms)
  3636. return -EINVAL;
  3637. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3638. SDE_DEBUG_ENC(sde_enc, "misr read not allowed\n");
  3639. return -ENOTSUPP;
  3640. }
  3641. drm_enc = &sde_enc->base;
  3642. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3643. if (rc < 0)
  3644. return rc;
  3645. if (!sde_enc->misr_enable) {
  3646. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3647. "disabled\n");
  3648. goto buff_check;
  3649. }
  3650. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3651. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3652. u32 misr_value = 0;
  3653. if (!phys || !phys->ops.collect_misr) {
  3654. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3655. "invalid\n");
  3656. SDE_ERROR_ENC(sde_enc, "invalid misr ops\n");
  3657. continue;
  3658. }
  3659. rc = phys->ops.collect_misr(phys, false, &misr_value);
  3660. if (rc) {
  3661. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3662. "invalid\n");
  3663. SDE_ERROR_ENC(sde_enc, "failed to collect misr %d\n",
  3664. rc);
  3665. continue;
  3666. } else {
  3667. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3668. "Intf idx:%d\n",
  3669. phys->intf_idx - INTF_0);
  3670. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3671. "0x%x\n", misr_value);
  3672. }
  3673. }
  3674. buff_check:
  3675. if (count <= len) {
  3676. len = 0;
  3677. goto end;
  3678. }
  3679. if (copy_to_user(user_buff, buf, len)) {
  3680. len = -EFAULT;
  3681. goto end;
  3682. }
  3683. *ppos += len; /* increase offset */
  3684. end:
  3685. pm_runtime_put_sync(drm_enc->dev->dev);
  3686. return len;
  3687. }
  3688. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3689. {
  3690. struct sde_encoder_virt *sde_enc;
  3691. struct sde_kms *sde_kms;
  3692. int i;
  3693. static const struct file_operations debugfs_status_fops = {
  3694. .open = _sde_encoder_debugfs_status_open,
  3695. .read = seq_read,
  3696. .llseek = seq_lseek,
  3697. .release = single_release,
  3698. };
  3699. static const struct file_operations debugfs_misr_fops = {
  3700. .open = simple_open,
  3701. .read = _sde_encoder_misr_read,
  3702. .write = _sde_encoder_misr_setup,
  3703. };
  3704. char name[SDE_NAME_SIZE];
  3705. if (!drm_enc) {
  3706. SDE_ERROR("invalid encoder\n");
  3707. return -EINVAL;
  3708. }
  3709. sde_enc = to_sde_encoder_virt(drm_enc);
  3710. sde_kms = sde_encoder_get_kms(drm_enc);
  3711. if (!sde_kms) {
  3712. SDE_ERROR("invalid sde_kms\n");
  3713. return -EINVAL;
  3714. }
  3715. snprintf(name, SDE_NAME_SIZE, "encoder%u", drm_enc->base.id);
  3716. /* create overall sub-directory for the encoder */
  3717. sde_enc->debugfs_root = debugfs_create_dir(name,
  3718. drm_enc->dev->primary->debugfs_root);
  3719. if (!sde_enc->debugfs_root)
  3720. return -ENOMEM;
  3721. /* don't error check these */
  3722. debugfs_create_file("status", 0400,
  3723. sde_enc->debugfs_root, sde_enc, &debugfs_status_fops);
  3724. debugfs_create_file("misr_data", 0600,
  3725. sde_enc->debugfs_root, sde_enc, &debugfs_misr_fops);
  3726. debugfs_create_bool("idle_power_collapse", 0600, sde_enc->debugfs_root,
  3727. &sde_enc->idle_pc_enabled);
  3728. debugfs_create_u32("frame_trigger_mode", 0400, sde_enc->debugfs_root,
  3729. &sde_enc->frame_trigger_mode);
  3730. for (i = 0; i < sde_enc->num_phys_encs; i++)
  3731. if (sde_enc->phys_encs[i] &&
  3732. sde_enc->phys_encs[i]->ops.late_register)
  3733. sde_enc->phys_encs[i]->ops.late_register(
  3734. sde_enc->phys_encs[i],
  3735. sde_enc->debugfs_root);
  3736. return 0;
  3737. }
  3738. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3739. {
  3740. struct sde_encoder_virt *sde_enc;
  3741. if (!drm_enc)
  3742. return;
  3743. sde_enc = to_sde_encoder_virt(drm_enc);
  3744. debugfs_remove_recursive(sde_enc->debugfs_root);
  3745. }
  3746. #else
  3747. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3748. {
  3749. return 0;
  3750. }
  3751. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3752. {
  3753. }
  3754. #endif
  3755. static int sde_encoder_late_register(struct drm_encoder *encoder)
  3756. {
  3757. return _sde_encoder_init_debugfs(encoder);
  3758. }
  3759. static void sde_encoder_early_unregister(struct drm_encoder *encoder)
  3760. {
  3761. _sde_encoder_destroy_debugfs(encoder);
  3762. }
  3763. static int sde_encoder_virt_add_phys_encs(
  3764. struct msm_display_info *disp_info,
  3765. struct sde_encoder_virt *sde_enc,
  3766. struct sde_enc_phys_init_params *params)
  3767. {
  3768. struct sde_encoder_phys *enc = NULL;
  3769. u32 display_caps = disp_info->capabilities;
  3770. SDE_DEBUG_ENC(sde_enc, "\n");
  3771. /*
  3772. * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
  3773. * in this function, check up-front.
  3774. */
  3775. if (sde_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
  3776. ARRAY_SIZE(sde_enc->phys_encs)) {
  3777. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3778. sde_enc->num_phys_encs);
  3779. return -EINVAL;
  3780. }
  3781. if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
  3782. enc = sde_encoder_phys_vid_init(params);
  3783. if (IS_ERR_OR_NULL(enc)) {
  3784. SDE_ERROR_ENC(sde_enc, "failed to init vid enc: %ld\n",
  3785. PTR_ERR(enc));
  3786. return !enc ? -EINVAL : PTR_ERR(enc);
  3787. }
  3788. sde_enc->phys_vid_encs[sde_enc->num_phys_encs] = enc;
  3789. }
  3790. if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
  3791. enc = sde_encoder_phys_cmd_init(params);
  3792. if (IS_ERR_OR_NULL(enc)) {
  3793. SDE_ERROR_ENC(sde_enc, "failed to init cmd enc: %ld\n",
  3794. PTR_ERR(enc));
  3795. return !enc ? -EINVAL : PTR_ERR(enc);
  3796. }
  3797. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs] = enc;
  3798. }
  3799. if (disp_info->curr_panel_mode == MSM_DISPLAY_VIDEO_MODE)
  3800. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3801. sde_enc->phys_vid_encs[sde_enc->num_phys_encs];
  3802. else
  3803. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3804. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs];
  3805. ++sde_enc->num_phys_encs;
  3806. return 0;
  3807. }
  3808. static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc,
  3809. struct sde_enc_phys_init_params *params)
  3810. {
  3811. struct sde_encoder_phys *enc = NULL;
  3812. if (!sde_enc) {
  3813. SDE_ERROR("invalid encoder\n");
  3814. return -EINVAL;
  3815. }
  3816. SDE_DEBUG_ENC(sde_enc, "\n");
  3817. if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) {
  3818. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3819. sde_enc->num_phys_encs);
  3820. return -EINVAL;
  3821. }
  3822. enc = sde_encoder_phys_wb_init(params);
  3823. if (IS_ERR_OR_NULL(enc)) {
  3824. SDE_ERROR_ENC(sde_enc, "failed to init wb enc: %ld\n",
  3825. PTR_ERR(enc));
  3826. return !enc ? -EINVAL : PTR_ERR(enc);
  3827. }
  3828. sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
  3829. ++sde_enc->num_phys_encs;
  3830. return 0;
  3831. }
  3832. static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
  3833. struct sde_kms *sde_kms,
  3834. struct msm_display_info *disp_info,
  3835. int *drm_enc_mode)
  3836. {
  3837. int ret = 0;
  3838. int i = 0;
  3839. enum sde_intf_type intf_type;
  3840. struct sde_encoder_virt_ops parent_ops = {
  3841. sde_encoder_vblank_callback,
  3842. sde_encoder_underrun_callback,
  3843. sde_encoder_frame_done_callback,
  3844. sde_encoder_get_qsync_fps_callback,
  3845. };
  3846. struct sde_enc_phys_init_params phys_params;
  3847. if (!sde_enc || !sde_kms) {
  3848. SDE_ERROR("invalid arg(s), enc %d kms %d\n",
  3849. !sde_enc, !sde_kms);
  3850. return -EINVAL;
  3851. }
  3852. memset(&phys_params, 0, sizeof(phys_params));
  3853. phys_params.sde_kms = sde_kms;
  3854. phys_params.parent = &sde_enc->base;
  3855. phys_params.parent_ops = parent_ops;
  3856. phys_params.enc_spinlock = &sde_enc->enc_spinlock;
  3857. phys_params.vblank_ctl_lock = &sde_enc->vblank_ctl_lock;
  3858. SDE_DEBUG("\n");
  3859. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
  3860. *drm_enc_mode = DRM_MODE_ENCODER_DSI;
  3861. intf_type = INTF_DSI;
  3862. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
  3863. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3864. intf_type = INTF_HDMI;
  3865. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_DisplayPort) {
  3866. if (disp_info->capabilities & MSM_DISPLAY_CAP_MST_MODE)
  3867. *drm_enc_mode = DRM_MODE_ENCODER_DPMST;
  3868. else
  3869. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3870. intf_type = INTF_DP;
  3871. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_VIRTUAL) {
  3872. *drm_enc_mode = DRM_MODE_ENCODER_VIRTUAL;
  3873. intf_type = INTF_WB;
  3874. } else {
  3875. SDE_ERROR_ENC(sde_enc, "unsupported display interface type\n");
  3876. return -EINVAL;
  3877. }
  3878. WARN_ON(disp_info->num_of_h_tiles < 1);
  3879. sde_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
  3880. sde_enc->te_source = disp_info->te_source;
  3881. SDE_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
  3882. if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
  3883. (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
  3884. sde_enc->idle_pc_enabled = sde_kms->catalog->has_idle_pc;
  3885. sde_enc->input_event_enabled = sde_kms->catalog->wakeup_with_touch;
  3886. mutex_lock(&sde_enc->enc_lock);
  3887. for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
  3888. /*
  3889. * Left-most tile is at index 0, content is controller id
  3890. * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
  3891. * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
  3892. */
  3893. u32 controller_id = disp_info->h_tile_instance[i];
  3894. if (disp_info->num_of_h_tiles > 1) {
  3895. if (i == 0)
  3896. phys_params.split_role = ENC_ROLE_MASTER;
  3897. else
  3898. phys_params.split_role = ENC_ROLE_SLAVE;
  3899. } else {
  3900. phys_params.split_role = ENC_ROLE_SOLO;
  3901. }
  3902. SDE_DEBUG("h_tile_instance %d = %d, split_role %d\n",
  3903. i, controller_id, phys_params.split_role);
  3904. if (sde_enc->ops.phys_init) {
  3905. struct sde_encoder_phys *enc;
  3906. enc = sde_enc->ops.phys_init(intf_type,
  3907. controller_id,
  3908. &phys_params);
  3909. if (enc) {
  3910. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3911. enc;
  3912. ++sde_enc->num_phys_encs;
  3913. } else
  3914. SDE_ERROR_ENC(sde_enc,
  3915. "failed to add phys encs\n");
  3916. continue;
  3917. }
  3918. if (intf_type == INTF_WB) {
  3919. phys_params.intf_idx = INTF_MAX;
  3920. phys_params.wb_idx = sde_encoder_get_wb(
  3921. sde_kms->catalog,
  3922. intf_type, controller_id);
  3923. if (phys_params.wb_idx == WB_MAX) {
  3924. SDE_ERROR_ENC(sde_enc,
  3925. "could not get wb: type %d, id %d\n",
  3926. intf_type, controller_id);
  3927. ret = -EINVAL;
  3928. }
  3929. } else {
  3930. phys_params.wb_idx = WB_MAX;
  3931. phys_params.intf_idx = sde_encoder_get_intf(
  3932. sde_kms->catalog, intf_type,
  3933. controller_id);
  3934. if (phys_params.intf_idx == INTF_MAX) {
  3935. SDE_ERROR_ENC(sde_enc,
  3936. "could not get wb: type %d, id %d\n",
  3937. intf_type, controller_id);
  3938. ret = -EINVAL;
  3939. }
  3940. }
  3941. if (!ret) {
  3942. if (intf_type == INTF_WB)
  3943. ret = sde_encoder_virt_add_phys_enc_wb(sde_enc,
  3944. &phys_params);
  3945. else
  3946. ret = sde_encoder_virt_add_phys_encs(
  3947. disp_info,
  3948. sde_enc,
  3949. &phys_params);
  3950. if (ret)
  3951. SDE_ERROR_ENC(sde_enc,
  3952. "failed to add phys encs\n");
  3953. }
  3954. }
  3955. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3956. struct sde_encoder_phys *vid_phys = sde_enc->phys_vid_encs[i];
  3957. struct sde_encoder_phys *cmd_phys = sde_enc->phys_cmd_encs[i];
  3958. if (vid_phys) {
  3959. atomic_set(&vid_phys->vsync_cnt, 0);
  3960. atomic_set(&vid_phys->underrun_cnt, 0);
  3961. }
  3962. if (cmd_phys) {
  3963. atomic_set(&cmd_phys->vsync_cnt, 0);
  3964. atomic_set(&cmd_phys->underrun_cnt, 0);
  3965. }
  3966. }
  3967. mutex_unlock(&sde_enc->enc_lock);
  3968. return ret;
  3969. }
  3970. static const struct drm_encoder_helper_funcs sde_encoder_helper_funcs = {
  3971. .mode_set = sde_encoder_virt_mode_set,
  3972. .disable = sde_encoder_virt_disable,
  3973. .enable = sde_encoder_virt_enable,
  3974. .atomic_check = sde_encoder_virt_atomic_check,
  3975. };
  3976. static const struct drm_encoder_funcs sde_encoder_funcs = {
  3977. .destroy = sde_encoder_destroy,
  3978. .late_register = sde_encoder_late_register,
  3979. .early_unregister = sde_encoder_early_unregister,
  3980. };
  3981. struct drm_encoder *sde_encoder_init_with_ops(
  3982. struct drm_device *dev,
  3983. struct msm_display_info *disp_info,
  3984. const struct sde_encoder_ops *ops)
  3985. {
  3986. struct msm_drm_private *priv = dev->dev_private;
  3987. struct sde_kms *sde_kms = to_sde_kms(priv->kms);
  3988. struct drm_encoder *drm_enc = NULL;
  3989. struct sde_encoder_virt *sde_enc = NULL;
  3990. int drm_enc_mode = DRM_MODE_ENCODER_NONE;
  3991. char name[SDE_NAME_SIZE];
  3992. int ret = 0, i, intf_index = INTF_MAX;
  3993. struct sde_encoder_phys *phys = NULL;
  3994. sde_enc = kzalloc(sizeof(*sde_enc), GFP_KERNEL);
  3995. if (!sde_enc) {
  3996. ret = -ENOMEM;
  3997. goto fail;
  3998. }
  3999. if (ops)
  4000. sde_enc->ops = *ops;
  4001. mutex_init(&sde_enc->enc_lock);
  4002. ret = sde_encoder_setup_display(sde_enc, sde_kms, disp_info,
  4003. &drm_enc_mode);
  4004. if (ret)
  4005. goto fail;
  4006. sde_enc->cur_master = NULL;
  4007. spin_lock_init(&sde_enc->enc_spinlock);
  4008. mutex_init(&sde_enc->vblank_ctl_lock);
  4009. for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
  4010. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  4011. drm_enc = &sde_enc->base;
  4012. drm_encoder_init(dev, drm_enc, &sde_encoder_funcs, drm_enc_mode, NULL);
  4013. drm_encoder_helper_add(drm_enc, &sde_encoder_helper_funcs);
  4014. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4015. phys = sde_enc->phys_encs[i];
  4016. if (!phys)
  4017. continue;
  4018. if (phys->ops.is_master && phys->ops.is_master(phys))
  4019. intf_index = phys->intf_idx - INTF_0;
  4020. }
  4021. snprintf(name, SDE_NAME_SIZE, "rsc_enc%u", drm_enc->base.id);
  4022. sde_enc->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX, name,
  4023. (disp_info->display_type == SDE_CONNECTOR_PRIMARY) ?
  4024. SDE_RSC_PRIMARY_DISP_CLIENT :
  4025. SDE_RSC_EXTERNAL_DISP_CLIENT, intf_index + 1);
  4026. if (IS_ERR_OR_NULL(sde_enc->rsc_client)) {
  4027. SDE_DEBUG("sde rsc client create failed :%ld\n",
  4028. PTR_ERR(sde_enc->rsc_client));
  4029. sde_enc->rsc_client = NULL;
  4030. }
  4031. if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE &&
  4032. sde_enc->input_event_enabled) {
  4033. ret = _sde_encoder_input_handler(sde_enc);
  4034. if (ret)
  4035. SDE_ERROR(
  4036. "input handler registration failed, rc = %d\n", ret);
  4037. }
  4038. mutex_init(&sde_enc->rc_lock);
  4039. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  4040. sde_encoder_off_work);
  4041. sde_enc->vblank_enabled = false;
  4042. sde_enc->qdss_status = false;
  4043. kthread_init_work(&sde_enc->input_event_work,
  4044. sde_encoder_input_event_work_handler);
  4045. kthread_init_work(&sde_enc->early_wakeup_work,
  4046. sde_encoder_early_wakeup_work_handler);
  4047. kthread_init_work(&sde_enc->esd_trigger_work,
  4048. sde_encoder_esd_trigger_work_handler);
  4049. memcpy(&sde_enc->disp_info, disp_info, sizeof(*disp_info));
  4050. SDE_DEBUG_ENC(sde_enc, "created\n");
  4051. return drm_enc;
  4052. fail:
  4053. SDE_ERROR("failed to create encoder\n");
  4054. if (drm_enc)
  4055. sde_encoder_destroy(drm_enc);
  4056. return ERR_PTR(ret);
  4057. }
  4058. struct drm_encoder *sde_encoder_init(
  4059. struct drm_device *dev,
  4060. struct msm_display_info *disp_info)
  4061. {
  4062. return sde_encoder_init_with_ops(dev, disp_info, NULL);
  4063. }
  4064. int sde_encoder_wait_for_event(struct drm_encoder *drm_enc,
  4065. enum msm_event_wait event)
  4066. {
  4067. int (*fn_wait)(struct sde_encoder_phys *phys_enc) = NULL;
  4068. struct sde_encoder_virt *sde_enc = NULL;
  4069. int i, ret = 0;
  4070. char atrace_buf[32];
  4071. if (!drm_enc) {
  4072. SDE_ERROR("invalid encoder\n");
  4073. return -EINVAL;
  4074. }
  4075. sde_enc = to_sde_encoder_virt(drm_enc);
  4076. SDE_DEBUG_ENC(sde_enc, "\n");
  4077. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4078. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4079. switch (event) {
  4080. case MSM_ENC_COMMIT_DONE:
  4081. fn_wait = phys->ops.wait_for_commit_done;
  4082. break;
  4083. case MSM_ENC_TX_COMPLETE:
  4084. fn_wait = phys->ops.wait_for_tx_complete;
  4085. break;
  4086. case MSM_ENC_VBLANK:
  4087. fn_wait = phys->ops.wait_for_vblank;
  4088. break;
  4089. case MSM_ENC_ACTIVE_REGION:
  4090. fn_wait = phys->ops.wait_for_active;
  4091. break;
  4092. default:
  4093. SDE_ERROR_ENC(sde_enc, "unknown wait event %d\n",
  4094. event);
  4095. return -EINVAL;
  4096. }
  4097. if (phys && fn_wait) {
  4098. snprintf(atrace_buf, sizeof(atrace_buf),
  4099. "wait_completion_event_%d", event);
  4100. SDE_ATRACE_BEGIN(atrace_buf);
  4101. ret = fn_wait(phys);
  4102. SDE_ATRACE_END(atrace_buf);
  4103. if (ret)
  4104. return ret;
  4105. }
  4106. }
  4107. return ret;
  4108. }
  4109. void sde_encoder_helper_get_jitter_bounds_ns(struct drm_encoder *drm_enc,
  4110. u64 *l_bound, u64 *u_bound)
  4111. {
  4112. struct sde_encoder_virt *sde_enc;
  4113. u64 jitter_ns, frametime_ns;
  4114. struct msm_mode_info *info;
  4115. if (!drm_enc) {
  4116. SDE_ERROR("invalid encoder\n");
  4117. return;
  4118. }
  4119. sde_enc = to_sde_encoder_virt(drm_enc);
  4120. info = &sde_enc->mode_info;
  4121. frametime_ns = (1 * 1000000000) / info->frame_rate;
  4122. jitter_ns = info->jitter_numer * frametime_ns;
  4123. do_div(jitter_ns, info->jitter_denom * 100);
  4124. *l_bound = frametime_ns - jitter_ns;
  4125. *u_bound = frametime_ns + jitter_ns;
  4126. }
  4127. u32 sde_encoder_get_fps(struct drm_encoder *drm_enc)
  4128. {
  4129. struct sde_encoder_virt *sde_enc;
  4130. if (!drm_enc) {
  4131. SDE_ERROR("invalid encoder\n");
  4132. return 0;
  4133. }
  4134. sde_enc = to_sde_encoder_virt(drm_enc);
  4135. return sde_enc->mode_info.frame_rate;
  4136. }
  4137. enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder)
  4138. {
  4139. struct sde_encoder_virt *sde_enc = NULL;
  4140. int i;
  4141. if (!encoder) {
  4142. SDE_ERROR("invalid encoder\n");
  4143. return INTF_MODE_NONE;
  4144. }
  4145. sde_enc = to_sde_encoder_virt(encoder);
  4146. if (sde_enc->cur_master)
  4147. return sde_enc->cur_master->intf_mode;
  4148. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4149. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4150. if (phys)
  4151. return phys->intf_mode;
  4152. }
  4153. return INTF_MODE_NONE;
  4154. }
  4155. static void _sde_encoder_cache_hw_res_cont_splash(
  4156. struct drm_encoder *encoder,
  4157. struct sde_kms *sde_kms)
  4158. {
  4159. int i, idx;
  4160. struct sde_encoder_virt *sde_enc;
  4161. struct sde_encoder_phys *phys_enc;
  4162. struct sde_rm_hw_iter dsc_iter, pp_iter, ctl_iter, intf_iter;
  4163. sde_enc = to_sde_encoder_virt(encoder);
  4164. sde_rm_init_hw_iter(&pp_iter, encoder->base.id, SDE_HW_BLK_PINGPONG);
  4165. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4166. sde_enc->hw_pp[i] = NULL;
  4167. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  4168. break;
  4169. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  4170. }
  4171. sde_rm_init_hw_iter(&dsc_iter, encoder->base.id, SDE_HW_BLK_DSC);
  4172. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4173. sde_enc->hw_dsc[i] = NULL;
  4174. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  4175. break;
  4176. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  4177. }
  4178. /*
  4179. * If we have multiple phys encoders with one controller, make
  4180. * sure to populate the controller pointer in both phys encoders.
  4181. */
  4182. for (idx = 0; idx < sde_enc->num_phys_encs; idx++) {
  4183. phys_enc = sde_enc->phys_encs[idx];
  4184. phys_enc->hw_ctl = NULL;
  4185. sde_rm_init_hw_iter(&ctl_iter, encoder->base.id,
  4186. SDE_HW_BLK_CTL);
  4187. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4188. if (sde_rm_get_hw(&sde_kms->rm, &ctl_iter)) {
  4189. phys_enc->hw_ctl =
  4190. (struct sde_hw_ctl *) ctl_iter.hw;
  4191. pr_debug("HW CTL intf_idx:%d hw_ctl:[0x%pK]\n",
  4192. phys_enc->intf_idx, phys_enc->hw_ctl);
  4193. }
  4194. }
  4195. }
  4196. sde_rm_init_hw_iter(&intf_iter, encoder->base.id, SDE_HW_BLK_INTF);
  4197. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4198. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4199. phys->hw_intf = NULL;
  4200. if (!sde_rm_get_hw(&sde_kms->rm, &intf_iter))
  4201. break;
  4202. phys->hw_intf = (struct sde_hw_intf *) intf_iter.hw;
  4203. }
  4204. }
  4205. /**
  4206. * sde_encoder_update_caps_for_cont_splash - update encoder settings during
  4207. * device bootup when cont_splash is enabled
  4208. * @drm_enc: Pointer to drm encoder structure
  4209. * @splash_display: Pointer to sde_splash_display corresponding to this encoder
  4210. * @enable: boolean indicates enable or displae state of splash
  4211. * @Return: true if successful in updating the encoder structure
  4212. */
  4213. int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder,
  4214. struct sde_splash_display *splash_display, bool enable)
  4215. {
  4216. struct sde_encoder_virt *sde_enc;
  4217. struct msm_drm_private *priv;
  4218. struct sde_kms *sde_kms;
  4219. struct drm_connector *conn = NULL;
  4220. struct sde_connector *sde_conn = NULL;
  4221. struct sde_connector_state *sde_conn_state = NULL;
  4222. struct drm_display_mode *drm_mode = NULL;
  4223. struct sde_encoder_phys *phys_enc;
  4224. int ret = 0, i;
  4225. if (!encoder) {
  4226. SDE_ERROR("invalid drm enc\n");
  4227. return -EINVAL;
  4228. }
  4229. sde_enc = to_sde_encoder_virt(encoder);
  4230. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  4231. if (!sde_kms) {
  4232. SDE_ERROR("invalid sde_kms\n");
  4233. return -EINVAL;
  4234. }
  4235. priv = encoder->dev->dev_private;
  4236. if (!priv->num_connectors) {
  4237. SDE_ERROR_ENC(sde_enc, "No connectors registered\n");
  4238. return -EINVAL;
  4239. }
  4240. SDE_DEBUG_ENC(sde_enc,
  4241. "num of connectors: %d\n", priv->num_connectors);
  4242. SDE_DEBUG_ENC(sde_enc, "enable: %d\n", enable);
  4243. if (!enable) {
  4244. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4245. phys_enc = sde_enc->phys_encs[i];
  4246. if (phys_enc)
  4247. phys_enc->cont_splash_enabled = false;
  4248. }
  4249. return ret;
  4250. }
  4251. if (!splash_display) {
  4252. SDE_ERROR_ENC(sde_enc, "invalid splash data\n");
  4253. return -EINVAL;
  4254. }
  4255. for (i = 0; i < priv->num_connectors; i++) {
  4256. SDE_DEBUG_ENC(sde_enc, "connector id: %d\n",
  4257. priv->connectors[i]->base.id);
  4258. sde_conn = to_sde_connector(priv->connectors[i]);
  4259. if (!sde_conn->encoder) {
  4260. SDE_DEBUG_ENC(sde_enc,
  4261. "encoder not attached to connector\n");
  4262. continue;
  4263. }
  4264. if (sde_conn->encoder->base.id
  4265. == encoder->base.id) {
  4266. conn = (priv->connectors[i]);
  4267. break;
  4268. }
  4269. }
  4270. if (!conn || !conn->state) {
  4271. SDE_ERROR_ENC(sde_enc, "connector not found\n");
  4272. return -EINVAL;
  4273. }
  4274. sde_conn_state = to_sde_connector_state(conn->state);
  4275. if (!sde_conn->ops.get_mode_info) {
  4276. SDE_ERROR_ENC(sde_enc, "conn: get_mode_info ops not found\n");
  4277. return -EINVAL;
  4278. }
  4279. ret = sde_connector_get_mode_info(&sde_conn->base,
  4280. &encoder->crtc->state->adjusted_mode,
  4281. &sde_conn_state->mode_info);
  4282. if (ret) {
  4283. SDE_ERROR_ENC(sde_enc,
  4284. "conn: ->get_mode_info failed. ret=%d\n", ret);
  4285. return ret;
  4286. }
  4287. if (sde_conn->encoder) {
  4288. conn->state->best_encoder = sde_conn->encoder;
  4289. SDE_DEBUG_ENC(sde_enc,
  4290. "configured cstate->best_encoder to ID = %d\n",
  4291. conn->state->best_encoder->base.id);
  4292. } else {
  4293. SDE_ERROR_ENC(sde_enc, "No encoder mapped to connector=%d\n",
  4294. conn->base.id);
  4295. }
  4296. ret = sde_rm_reserve(&sde_kms->rm, encoder, encoder->crtc->state,
  4297. conn->state, false);
  4298. if (ret) {
  4299. SDE_ERROR_ENC(sde_enc,
  4300. "failed to reserve hw resources, %d\n", ret);
  4301. return ret;
  4302. }
  4303. SDE_DEBUG_ENC(sde_enc, "connector topology = %llu\n",
  4304. sde_connector_get_topology_name(conn));
  4305. drm_mode = &encoder->crtc->state->adjusted_mode;
  4306. SDE_DEBUG_ENC(sde_enc, "hdisplay = %d, vdisplay = %d\n",
  4307. drm_mode->hdisplay, drm_mode->vdisplay);
  4308. drm_set_preferred_mode(conn, drm_mode->hdisplay, drm_mode->vdisplay);
  4309. if (encoder->bridge) {
  4310. SDE_DEBUG_ENC(sde_enc, "Bridge mapped to encoder\n");
  4311. /*
  4312. * For cont-splash use case, we update the mode
  4313. * configurations manually. This will skip the
  4314. * usually mode set call when actual frame is
  4315. * pushed from framework. The bridge needs to
  4316. * be updated with the current drm mode by
  4317. * calling the bridge mode set ops.
  4318. */
  4319. if (encoder->bridge->funcs) {
  4320. SDE_DEBUG_ENC(sde_enc, "calling mode_set\n");
  4321. encoder->bridge->funcs->mode_set(encoder->bridge,
  4322. drm_mode, drm_mode);
  4323. }
  4324. } else {
  4325. SDE_ERROR_ENC(sde_enc, "No bridge attached to encoder\n");
  4326. }
  4327. _sde_encoder_cache_hw_res_cont_splash(encoder, sde_kms);
  4328. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4329. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4330. if (!phys) {
  4331. SDE_ERROR_ENC(sde_enc,
  4332. "phys encoders not initialized\n");
  4333. return -EINVAL;
  4334. }
  4335. /* update connector for master and slave phys encoders */
  4336. phys->connector = conn;
  4337. phys->cont_splash_enabled = true;
  4338. phys->hw_pp = sde_enc->hw_pp[i];
  4339. if (phys->ops.cont_splash_mode_set)
  4340. phys->ops.cont_splash_mode_set(phys, drm_mode);
  4341. if (phys->ops.is_master && phys->ops.is_master(phys))
  4342. sde_enc->cur_master = phys;
  4343. }
  4344. return ret;
  4345. }
  4346. int sde_encoder_display_failure_notification(struct drm_encoder *enc,
  4347. bool skip_pre_kickoff)
  4348. {
  4349. struct msm_drm_thread *event_thread = NULL;
  4350. struct msm_drm_private *priv = NULL;
  4351. struct sde_encoder_virt *sde_enc = NULL;
  4352. if (!enc || !enc->dev || !enc->dev->dev_private) {
  4353. SDE_ERROR("invalid parameters\n");
  4354. return -EINVAL;
  4355. }
  4356. priv = enc->dev->dev_private;
  4357. sde_enc = to_sde_encoder_virt(enc);
  4358. if (!sde_enc->crtc || (sde_enc->crtc->index
  4359. >= ARRAY_SIZE(priv->event_thread))) {
  4360. SDE_DEBUG_ENC(sde_enc,
  4361. "invalid cached CRTC: %d or crtc index: %d\n",
  4362. sde_enc->crtc == NULL,
  4363. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  4364. return -EINVAL;
  4365. }
  4366. SDE_EVT32_VERBOSE(DRMID(enc));
  4367. event_thread = &priv->event_thread[sde_enc->crtc->index];
  4368. if (!skip_pre_kickoff) {
  4369. kthread_queue_work(&event_thread->worker,
  4370. &sde_enc->esd_trigger_work);
  4371. kthread_flush_work(&sde_enc->esd_trigger_work);
  4372. }
  4373. /*
  4374. * panel may stop generating te signal (vsync) during esd failure. rsc
  4375. * hardware may hang without vsync. Avoid rsc hang by generating the
  4376. * vsync from watchdog timer instead of panel.
  4377. */
  4378. sde_encoder_helper_switch_vsync(enc, true);
  4379. if (!skip_pre_kickoff)
  4380. sde_encoder_wait_for_event(enc, MSM_ENC_TX_COMPLETE);
  4381. return 0;
  4382. }
  4383. bool sde_encoder_recovery_events_enabled(struct drm_encoder *encoder)
  4384. {
  4385. struct sde_encoder_virt *sde_enc;
  4386. if (!encoder) {
  4387. SDE_ERROR("invalid drm enc\n");
  4388. return false;
  4389. }
  4390. sde_enc = to_sde_encoder_virt(encoder);
  4391. return sde_enc->recovery_events_enabled;
  4392. }
  4393. void sde_encoder_recovery_events_handler(struct drm_encoder *encoder,
  4394. bool enabled)
  4395. {
  4396. struct sde_encoder_virt *sde_enc;
  4397. if (!encoder) {
  4398. SDE_ERROR("invalid drm enc\n");
  4399. return;
  4400. }
  4401. sde_enc = to_sde_encoder_virt(encoder);
  4402. sde_enc->recovery_events_enabled = enabled;
  4403. }